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dbdma: Make little endian
[qemu.git] / hw / sun4m.c
blob4795b3f45ebc14155b72831347ecf2850b77706a
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 target_phys_addr_t ecc_base;
100 uint32_t ecc_version;
101 uint8_t nvram_machine_id;
102 uint16_t machine_id;
103 uint32_t iommu_version;
104 uint64_t max_mem;
105 const char * const default_cpu_model;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 uint8_t nvram_machine_id;
119 uint16_t machine_id;
120 uint32_t iounit_version;
121 uint64_t max_mem;
122 const char * const default_cpu_model;
123 };
124
125 struct sun4c_hwdef {
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
131 uint8_t nvram_machine_id;
132 uint16_t machine_id;
133 uint32_t iommu_version;
134 uint64_t max_mem;
135 const char * const default_cpu_model;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void pic_info(Monitor *mon)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void irq_info(Monitor *mon)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_set_irq(void *opaque, int irq, int level)
257 {
258 CPUState *env = opaque;
259
260 if (level) {
261 trace_sun4m_cpu_set_irq_raise(irq);
262 env->halted = 0;
263 env->pil_in |= 1 << irq;
264 cpu_check_irqs(env);
265 } else {
266 trace_sun4m_cpu_set_irq_lower(irq);
267 env->pil_in &= ~(1 << irq);
268 cpu_check_irqs(env);
269 }
270 }
271
272 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
273 {
274 }
275
276 static void main_cpu_reset(void *opaque)
277 {
278 CPUState *env = opaque;
279
280 cpu_reset(env);
281 env->halted = 0;
282 }
283
284 static void secondary_cpu_reset(void *opaque)
285 {
286 CPUState *env = opaque;
287
288 cpu_reset(env);
289 env->halted = 1;
290 }
291
292 static void cpu_halt_signal(void *opaque, int irq, int level)
293 {
294 if (level && cpu_single_env)
295 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
296 }
297
298 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
299 {
300 return addr - 0xf0000000ULL;
301 }
302
303 static unsigned long sun4m_load_kernel(const char *kernel_filename,
304 const char *initrd_filename,
305 ram_addr_t RAM_size)
306 {
307 int linux_boot;
308 unsigned int i;
309 long initrd_size, kernel_size;
310 uint8_t *ptr;
311
312 linux_boot = (kernel_filename != NULL);
313
314 kernel_size = 0;
315 if (linux_boot) {
316 int bswap_needed;
317
318 #ifdef BSWAP_NEEDED
319 bswap_needed = 1;
320 #else
321 bswap_needed = 0;
322 #endif
323 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
324 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
325 if (kernel_size < 0)
326 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
327 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
328 TARGET_PAGE_SIZE);
329 if (kernel_size < 0)
330 kernel_size = load_image_targphys(kernel_filename,
331 KERNEL_LOAD_ADDR,
332 RAM_size - KERNEL_LOAD_ADDR);
333 if (kernel_size < 0) {
334 fprintf(stderr, "qemu: could not load kernel '%s'\n",
335 kernel_filename);
336 exit(1);
337 }
338
339 /* load initrd */
340 initrd_size = 0;
341 if (initrd_filename) {
342 initrd_size = load_image_targphys(initrd_filename,
343 INITRD_LOAD_ADDR,
344 RAM_size - INITRD_LOAD_ADDR);
345 if (initrd_size < 0) {
346 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
347 initrd_filename);
348 exit(1);
349 }
350 }
351 if (initrd_size > 0) {
352 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
353 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
354 if (ldl_p(ptr) == 0x48647253) { // HdrS
355 stl_p(ptr + 16, INITRD_LOAD_ADDR);
356 stl_p(ptr + 20, initrd_size);
357 break;
358 }
359 }
360 }
361 }
362 return kernel_size;
363 }
364
365 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
366 {
367 DeviceState *dev;
368 SysBusDevice *s;
369
370 dev = qdev_create(NULL, "iommu");
371 qdev_prop_set_uint32(dev, "version", version);
372 qdev_init_nofail(dev);
373 s = sysbus_from_qdev(dev);
374 sysbus_connect_irq(s, 0, irq);
375 sysbus_mmio_map(s, 0, addr);
376
377 return s;
378 }
379
380 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
381 void *iommu, qemu_irq *dev_irq)
382 {
383 DeviceState *dev;
384 SysBusDevice *s;
385
386 dev = qdev_create(NULL, "sparc32_dma");
387 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
388 qdev_init_nofail(dev);
389 s = sysbus_from_qdev(dev);
390 sysbus_connect_irq(s, 0, parent_irq);
391 *dev_irq = qdev_get_gpio_in(dev, 0);
392 sysbus_mmio_map(s, 0, daddr);
393
394 return s;
395 }
396
397 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
398 void *dma_opaque, qemu_irq irq)
399 {
400 DeviceState *dev;
401 SysBusDevice *s;
402 qemu_irq reset;
403
404 qemu_check_nic_model(&nd_table[0], "lance");
405
406 dev = qdev_create(NULL, "lance");
407 qdev_set_nic_properties(dev, nd);
408 qdev_prop_set_ptr(dev, "dma", dma_opaque);
409 qdev_init_nofail(dev);
410 s = sysbus_from_qdev(dev);
411 sysbus_mmio_map(s, 0, leaddr);
412 sysbus_connect_irq(s, 0, irq);
413 reset = qdev_get_gpio_in(dev, 0);
414 qdev_connect_gpio_out(dma_opaque, 0, reset);
415 }
416
417 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
418 target_phys_addr_t addrg,
419 qemu_irq **parent_irq)
420 {
421 DeviceState *dev;
422 SysBusDevice *s;
423 unsigned int i, j;
424
425 dev = qdev_create(NULL, "slavio_intctl");
426 qdev_init_nofail(dev);
427
428 s = sysbus_from_qdev(dev);
429
430 for (i = 0; i < MAX_CPUS; i++) {
431 for (j = 0; j < MAX_PILS; j++) {
432 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
433 }
434 }
435 sysbus_mmio_map(s, 0, addrg);
436 for (i = 0; i < MAX_CPUS; i++) {
437 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
438 }
439
440 return dev;
441 }
442
443 #define SYS_TIMER_OFFSET 0x10000ULL
444 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
445
446 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
447 qemu_irq *cpu_irqs, unsigned int num_cpus)
448 {
449 DeviceState *dev;
450 SysBusDevice *s;
451 unsigned int i;
452
453 dev = qdev_create(NULL, "slavio_timer");
454 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
455 qdev_init_nofail(dev);
456 s = sysbus_from_qdev(dev);
457 sysbus_connect_irq(s, 0, master_irq);
458 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
459
460 for (i = 0; i < MAX_CPUS; i++) {
461 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
462 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
463 }
464 }
465
466 #define MISC_LEDS 0x01600000
467 #define MISC_CFG 0x01800000
468 #define MISC_DIAG 0x01a00000
469 #define MISC_MDM 0x01b00000
470 #define MISC_SYS 0x01f00000
471
472 static void slavio_misc_init(target_phys_addr_t base,
473 target_phys_addr_t aux1_base,
474 target_phys_addr_t aux2_base, qemu_irq irq,
475 qemu_irq fdc_tc)
476 {
477 DeviceState *dev;
478 SysBusDevice *s;
479
480 dev = qdev_create(NULL, "slavio_misc");
481 qdev_init_nofail(dev);
482 s = sysbus_from_qdev(dev);
483 if (base) {
484 /* 8 bit registers */
485 /* Slavio control */
486 sysbus_mmio_map(s, 0, base + MISC_CFG);
487 /* Diagnostics */
488 sysbus_mmio_map(s, 1, base + MISC_DIAG);
489 /* Modem control */
490 sysbus_mmio_map(s, 2, base + MISC_MDM);
491 /* 16 bit registers */
492 /* ss600mp diag LEDs */
493 sysbus_mmio_map(s, 3, base + MISC_LEDS);
494 /* 32 bit registers */
495 /* System control */
496 sysbus_mmio_map(s, 4, base + MISC_SYS);
497 }
498 if (aux1_base) {
499 /* AUX 1 (Misc System Functions) */
500 sysbus_mmio_map(s, 5, aux1_base);
501 }
502 if (aux2_base) {
503 /* AUX 2 (Software Powerdown Control) */
504 sysbus_mmio_map(s, 6, aux2_base);
505 }
506 sysbus_connect_irq(s, 0, irq);
507 sysbus_connect_irq(s, 1, fdc_tc);
508 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
509 }
510
511 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
512 {
513 DeviceState *dev;
514 SysBusDevice *s;
515
516 dev = qdev_create(NULL, "eccmemctl");
517 qdev_prop_set_uint32(dev, "version", version);
518 qdev_init_nofail(dev);
519 s = sysbus_from_qdev(dev);
520 sysbus_connect_irq(s, 0, irq);
521 sysbus_mmio_map(s, 0, base);
522 if (version == 0) { // SS-600MP only
523 sysbus_mmio_map(s, 1, base + 0x1000);
524 }
525 }
526
527 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
528 {
529 DeviceState *dev;
530 SysBusDevice *s;
531
532 dev = qdev_create(NULL, "apc");
533 qdev_init_nofail(dev);
534 s = sysbus_from_qdev(dev);
535 /* Power management (APC) XXX: not a Slavio device */
536 sysbus_mmio_map(s, 0, power_base);
537 sysbus_connect_irq(s, 0, cpu_halt);
538 }
539
540 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
541 int height, int depth)
542 {
543 DeviceState *dev;
544 SysBusDevice *s;
545
546 dev = qdev_create(NULL, "SUNW,tcx");
547 qdev_prop_set_taddr(dev, "addr", addr);
548 qdev_prop_set_uint32(dev, "vram_size", vram_size);
549 qdev_prop_set_uint16(dev, "width", width);
550 qdev_prop_set_uint16(dev, "height", height);
551 qdev_prop_set_uint16(dev, "depth", depth);
552 qdev_init_nofail(dev);
553 s = sysbus_from_qdev(dev);
554 /* 8-bit plane */
555 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
556 /* DAC */
557 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
558 /* TEC (dummy) */
559 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
560 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
561 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
562 if (depth == 24) {
563 /* 24-bit plane */
564 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
565 /* Control plane */
566 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
567 } else {
568 /* THC 8 bit (dummy) */
569 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
570 }
571 }
572
573 /* NCR89C100/MACIO Internal ID register */
574 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
575
576 static void idreg_init(target_phys_addr_t addr)
577 {
578 DeviceState *dev;
579 SysBusDevice *s;
580
581 dev = qdev_create(NULL, "macio_idreg");
582 qdev_init_nofail(dev);
583 s = sysbus_from_qdev(dev);
584
585 sysbus_mmio_map(s, 0, addr);
586 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
587 }
588
589 static int idreg_init1(SysBusDevice *dev)
590 {
591 ram_addr_t idreg_offset;
592
593 idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data));
594 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
595 return 0;
596 }
597
598 static SysBusDeviceInfo idreg_info = {
599 .init = idreg_init1,
600 .qdev.name = "macio_idreg",
601 .qdev.size = sizeof(SysBusDevice),
602 };
603
604 static void idreg_register_devices(void)
605 {
606 sysbus_register_withprop(&idreg_info);
607 }
608
609 device_init(idreg_register_devices);
610
611 /* SS-5 TCX AFX register */
612 static void afx_init(target_phys_addr_t addr)
613 {
614 DeviceState *dev;
615 SysBusDevice *s;
616
617 dev = qdev_create(NULL, "tcx_afx");
618 qdev_init_nofail(dev);
619 s = sysbus_from_qdev(dev);
620
621 sysbus_mmio_map(s, 0, addr);
622 }
623
624 static int afx_init1(SysBusDevice *dev)
625 {
626 ram_addr_t afx_offset;
627
628 afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4);
629 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
630 return 0;
631 }
632
633 static SysBusDeviceInfo afx_info = {
634 .init = afx_init1,
635 .qdev.name = "tcx_afx",
636 .qdev.size = sizeof(SysBusDevice),
637 };
638
639 static void afx_register_devices(void)
640 {
641 sysbus_register_withprop(&afx_info);
642 }
643
644 device_init(afx_register_devices);
645
646 /* Boot PROM (OpenBIOS) */
647 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
648 {
649 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
650 return addr + *base_addr - PROM_VADDR;
651 }
652
653 static void prom_init(target_phys_addr_t addr, const char *bios_name)
654 {
655 DeviceState *dev;
656 SysBusDevice *s;
657 char *filename;
658 int ret;
659
660 dev = qdev_create(NULL, "openprom");
661 qdev_init_nofail(dev);
662 s = sysbus_from_qdev(dev);
663
664 sysbus_mmio_map(s, 0, addr);
665
666 /* load boot prom */
667 if (bios_name == NULL) {
668 bios_name = PROM_FILENAME;
669 }
670 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
671 if (filename) {
672 ret = load_elf(filename, translate_prom_address, &addr, NULL,
673 NULL, NULL, 1, ELF_MACHINE, 0);
674 if (ret < 0 || ret > PROM_SIZE_MAX) {
675 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
676 }
677 qemu_free(filename);
678 } else {
679 ret = -1;
680 }
681 if (ret < 0 || ret > PROM_SIZE_MAX) {
682 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
683 exit(1);
684 }
685 }
686
687 static int prom_init1(SysBusDevice *dev)
688 {
689 ram_addr_t prom_offset;
690
691 prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX);
692 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
693 return 0;
694 }
695
696 static SysBusDeviceInfo prom_info = {
697 .init = prom_init1,
698 .qdev.name = "openprom",
699 .qdev.size = sizeof(SysBusDevice),
700 .qdev.props = (Property[]) {
701 {/* end of property list */}
702 }
703 };
704
705 static void prom_register_devices(void)
706 {
707 sysbus_register_withprop(&prom_info);
708 }
709
710 device_init(prom_register_devices);
711
712 typedef struct RamDevice
713 {
714 SysBusDevice busdev;
715 uint64_t size;
716 } RamDevice;
717
718 /* System RAM */
719 static int ram_init1(SysBusDevice *dev)
720 {
721 ram_addr_t RAM_size, ram_offset;
722 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
723
724 RAM_size = d->size;
725
726 ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size);
727 sysbus_init_mmio(dev, RAM_size, ram_offset);
728 return 0;
729 }
730
731 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
732 uint64_t max_mem)
733 {
734 DeviceState *dev;
735 SysBusDevice *s;
736 RamDevice *d;
737
738 /* allocate RAM */
739 if ((uint64_t)RAM_size > max_mem) {
740 fprintf(stderr,
741 "qemu: Too much memory for this machine: %d, maximum %d\n",
742 (unsigned int)(RAM_size / (1024 * 1024)),
743 (unsigned int)(max_mem / (1024 * 1024)));
744 exit(1);
745 }
746 dev = qdev_create(NULL, "memory");
747 s = sysbus_from_qdev(dev);
748
749 d = FROM_SYSBUS(RamDevice, s);
750 d->size = RAM_size;
751 qdev_init_nofail(dev);
752
753 sysbus_mmio_map(s, 0, addr);
754 }
755
756 static SysBusDeviceInfo ram_info = {
757 .init = ram_init1,
758 .qdev.name = "memory",
759 .qdev.size = sizeof(RamDevice),
760 .qdev.props = (Property[]) {
761 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
762 DEFINE_PROP_END_OF_LIST(),
763 }
764 };
765
766 static void ram_register_devices(void)
767 {
768 sysbus_register_withprop(&ram_info);
769 }
770
771 device_init(ram_register_devices);
772
773 static void cpu_devinit(const char *cpu_model, unsigned int id,
774 uint64_t prom_addr, qemu_irq **cpu_irqs)
775 {
776 CPUState *env;
777
778 env = cpu_init(cpu_model);
779 if (!env) {
780 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
781 exit(1);
782 }
783
784 cpu_sparc_set_id(env, id);
785 if (id == 0) {
786 qemu_register_reset(main_cpu_reset, env);
787 } else {
788 qemu_register_reset(secondary_cpu_reset, env);
789 env->halted = 1;
790 }
791 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
792 env->prom_addr = prom_addr;
793 }
794
795 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
796 const char *boot_device,
797 const char *kernel_filename,
798 const char *kernel_cmdline,
799 const char *initrd_filename, const char *cpu_model)
800 {
801 unsigned int i;
802 void *iommu, *espdma, *ledma, *nvram;
803 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
804 espdma_irq, ledma_irq;
805 qemu_irq esp_reset, dma_enable;
806 qemu_irq fdc_tc;
807 qemu_irq *cpu_halt;
808 unsigned long kernel_size;
809 DriveInfo *fd[MAX_FD];
810 void *fw_cfg;
811 unsigned int num_vsimms;
812
813 /* init CPUs */
814 if (!cpu_model)
815 cpu_model = hwdef->default_cpu_model;
816
817 for(i = 0; i < smp_cpus; i++) {
818 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
819 }
820
821 for (i = smp_cpus; i < MAX_CPUS; i++)
822 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
823
824
825 /* set up devices */
826 ram_init(0, RAM_size, hwdef->max_mem);
827 /* models without ECC don't trap when missing ram is accessed */
828 if (!hwdef->ecc_base) {
829 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
830 }
831
832 prom_init(hwdef->slavio_base, bios_name);
833
834 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
835 hwdef->intctl_base + 0x10000ULL,
836 cpu_irqs);
837
838 for (i = 0; i < 32; i++) {
839 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
840 }
841 for (i = 0; i < MAX_CPUS; i++) {
842 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
843 }
844
845 if (hwdef->idreg_base) {
846 idreg_init(hwdef->idreg_base);
847 }
848
849 if (hwdef->afx_base) {
850 afx_init(hwdef->afx_base);
851 }
852
853 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
854 slavio_irq[30]);
855
856 if (hwdef->iommu_pad_base) {
857 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
858 Software shouldn't use aliased addresses, neither should it crash
859 when does. Using empty_slot instead of aliasing can help with
860 debugging such accesses */
861 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
862 }
863
864 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
865 iommu, &espdma_irq);
866
867 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
868 slavio_irq[16], iommu, &ledma_irq);
869
870 if (graphic_depth != 8 && graphic_depth != 24) {
871 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
872 exit (1);
873 }
874 num_vsimms = 0;
875 if (num_vsimms == 0) {
876 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
877 graphic_depth);
878 }
879
880 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
881 /* vsimm registers probed by OBP */
882 if (hwdef->vsimm[i].reg_base) {
883 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
884 }
885 }
886
887 if (hwdef->sx_base) {
888 empty_slot_init(hwdef->sx_base, 0x2000);
889 }
890
891 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
892
893 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
894
895 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
896
897 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
898 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
899 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
900 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
901 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
902 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
903
904 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
905 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
906 slavio_irq[30], fdc_tc);
907
908 if (hwdef->apc_base) {
909 apc_init(hwdef->apc_base, cpu_halt[0]);
910 }
911
912 if (hwdef->fd_base) {
913 /* there is zero or one floppy drive */
914 memset(fd, 0, sizeof(fd));
915 fd[0] = drive_get(IF_FLOPPY, 0, 0);
916 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
917 &fdc_tc);
918 }
919
920 if (drive_get_max_bus(IF_SCSI) > 0) {
921 fprintf(stderr, "qemu: too many SCSI bus\n");
922 exit(1);
923 }
924
925 esp_init(hwdef->esp_base, 2,
926 espdma_memory_read, espdma_memory_write,
927 espdma, espdma_irq, &esp_reset, &dma_enable);
928
929 qdev_connect_gpio_out(espdma, 0, esp_reset);
930 qdev_connect_gpio_out(espdma, 1, dma_enable);
931
932 if (hwdef->cs_base) {
933 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
934 slavio_irq[5]);
935 }
936
937 if (hwdef->dbri_base) {
938 /* ISDN chip with attached CS4215 audio codec */
939 /* prom space */
940 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
941 /* reg space */
942 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
943 }
944
945 if (hwdef->bpp_base) {
946 /* parallel port */
947 empty_slot_init(hwdef->bpp_base, 0x20);
948 }
949
950 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
951 RAM_size);
952
953 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
954 boot_device, RAM_size, kernel_size, graphic_width,
955 graphic_height, graphic_depth, hwdef->nvram_machine_id,
956 "Sun4m");
957
958 if (hwdef->ecc_base)
959 ecc_init(hwdef->ecc_base, slavio_irq[28],
960 hwdef->ecc_version);
961
962 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
963 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
964 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
965 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
966 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
967 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
968 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
969 if (kernel_cmdline) {
970 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
971 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
972 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
973 (uint8_t*)strdup(kernel_cmdline),
974 strlen(kernel_cmdline) + 1);
975 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
976 strlen(kernel_cmdline) + 1);
977 } else {
978 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
979 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
980 }
981 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
982 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
983 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
984 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
985 }
986
987 enum {
988 ss2_id = 0,
989 ss5_id = 32,
990 vger_id,
991 lx_id,
992 ss4_id,
993 scls_id,
994 sbook_id,
995 ss10_id = 64,
996 ss20_id,
997 ss600mp_id,
998 ss1000_id = 96,
999 ss2000_id,
1000 };
1001
1002 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1003 /* SS-5 */
1004 {
1005 .iommu_base = 0x10000000,
1006 .iommu_pad_base = 0x10004000,
1007 .iommu_pad_len = 0x0fffb000,
1008 .tcx_base = 0x50000000,
1009 .cs_base = 0x6c000000,
1010 .slavio_base = 0x70000000,
1011 .ms_kb_base = 0x71000000,
1012 .serial_base = 0x71100000,
1013 .nvram_base = 0x71200000,
1014 .fd_base = 0x71400000,
1015 .counter_base = 0x71d00000,
1016 .intctl_base = 0x71e00000,
1017 .idreg_base = 0x78000000,
1018 .dma_base = 0x78400000,
1019 .esp_base = 0x78800000,
1020 .le_base = 0x78c00000,
1021 .apc_base = 0x6a000000,
1022 .afx_base = 0x6e000000,
1023 .aux1_base = 0x71900000,
1024 .aux2_base = 0x71910000,
1025 .nvram_machine_id = 0x80,
1026 .machine_id = ss5_id,
1027 .iommu_version = 0x05000000,
1028 .max_mem = 0x10000000,
1029 .default_cpu_model = "Fujitsu MB86904",
1030 },
1031 /* SS-10 */
1032 {
1033 .iommu_base = 0xfe0000000ULL,
1034 .tcx_base = 0xe20000000ULL,
1035 .slavio_base = 0xff0000000ULL,
1036 .ms_kb_base = 0xff1000000ULL,
1037 .serial_base = 0xff1100000ULL,
1038 .nvram_base = 0xff1200000ULL,
1039 .fd_base = 0xff1700000ULL,
1040 .counter_base = 0xff1300000ULL,
1041 .intctl_base = 0xff1400000ULL,
1042 .idreg_base = 0xef0000000ULL,
1043 .dma_base = 0xef0400000ULL,
1044 .esp_base = 0xef0800000ULL,
1045 .le_base = 0xef0c00000ULL,
1046 .apc_base = 0xefa000000ULL, // XXX should not exist
1047 .aux1_base = 0xff1800000ULL,
1048 .aux2_base = 0xff1a01000ULL,
1049 .ecc_base = 0xf00000000ULL,
1050 .ecc_version = 0x10000000, // version 0, implementation 1
1051 .nvram_machine_id = 0x72,
1052 .machine_id = ss10_id,
1053 .iommu_version = 0x03000000,
1054 .max_mem = 0xf00000000ULL,
1055 .default_cpu_model = "TI SuperSparc II",
1056 },
1057 /* SS-600MP */
1058 {
1059 .iommu_base = 0xfe0000000ULL,
1060 .tcx_base = 0xe20000000ULL,
1061 .slavio_base = 0xff0000000ULL,
1062 .ms_kb_base = 0xff1000000ULL,
1063 .serial_base = 0xff1100000ULL,
1064 .nvram_base = 0xff1200000ULL,
1065 .counter_base = 0xff1300000ULL,
1066 .intctl_base = 0xff1400000ULL,
1067 .dma_base = 0xef0081000ULL,
1068 .esp_base = 0xef0080000ULL,
1069 .le_base = 0xef0060000ULL,
1070 .apc_base = 0xefa000000ULL, // XXX should not exist
1071 .aux1_base = 0xff1800000ULL,
1072 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1073 .ecc_base = 0xf00000000ULL,
1074 .ecc_version = 0x00000000, // version 0, implementation 0
1075 .nvram_machine_id = 0x71,
1076 .machine_id = ss600mp_id,
1077 .iommu_version = 0x01000000,
1078 .max_mem = 0xf00000000ULL,
1079 .default_cpu_model = "TI SuperSparc II",
1080 },
1081 /* SS-20 */
1082 {
1083 .iommu_base = 0xfe0000000ULL,
1084 .tcx_base = 0xe20000000ULL,
1085 .slavio_base = 0xff0000000ULL,
1086 .ms_kb_base = 0xff1000000ULL,
1087 .serial_base = 0xff1100000ULL,
1088 .nvram_base = 0xff1200000ULL,
1089 .fd_base = 0xff1700000ULL,
1090 .counter_base = 0xff1300000ULL,
1091 .intctl_base = 0xff1400000ULL,
1092 .idreg_base = 0xef0000000ULL,
1093 .dma_base = 0xef0400000ULL,
1094 .esp_base = 0xef0800000ULL,
1095 .le_base = 0xef0c00000ULL,
1096 .bpp_base = 0xef4800000ULL,
1097 .apc_base = 0xefa000000ULL, // XXX should not exist
1098 .aux1_base = 0xff1800000ULL,
1099 .aux2_base = 0xff1a01000ULL,
1100 .dbri_base = 0xee0000000ULL,
1101 .sx_base = 0xf80000000ULL,
1102 .vsimm = {
1103 {
1104 .reg_base = 0x9c000000ULL,
1105 .vram_base = 0xfc000000ULL
1106 }, {
1107 .reg_base = 0x90000000ULL,
1108 .vram_base = 0xf0000000ULL
1109 }, {
1110 .reg_base = 0x94000000ULL
1111 }, {
1112 .reg_base = 0x98000000ULL
1113 }
1114 },
1115 .ecc_base = 0xf00000000ULL,
1116 .ecc_version = 0x20000000, // version 0, implementation 2
1117 .nvram_machine_id = 0x72,
1118 .machine_id = ss20_id,
1119 .iommu_version = 0x13000000,
1120 .max_mem = 0xf00000000ULL,
1121 .default_cpu_model = "TI SuperSparc II",
1122 },
1123 /* Voyager */
1124 {
1125 .iommu_base = 0x10000000,
1126 .tcx_base = 0x50000000,
1127 .slavio_base = 0x70000000,
1128 .ms_kb_base = 0x71000000,
1129 .serial_base = 0x71100000,
1130 .nvram_base = 0x71200000,
1131 .fd_base = 0x71400000,
1132 .counter_base = 0x71d00000,
1133 .intctl_base = 0x71e00000,
1134 .idreg_base = 0x78000000,
1135 .dma_base = 0x78400000,
1136 .esp_base = 0x78800000,
1137 .le_base = 0x78c00000,
1138 .apc_base = 0x71300000, // pmc
1139 .aux1_base = 0x71900000,
1140 .aux2_base = 0x71910000,
1141 .nvram_machine_id = 0x80,
1142 .machine_id = vger_id,
1143 .iommu_version = 0x05000000,
1144 .max_mem = 0x10000000,
1145 .default_cpu_model = "Fujitsu MB86904",
1146 },
1147 /* LX */
1148 {
1149 .iommu_base = 0x10000000,
1150 .iommu_pad_base = 0x10004000,
1151 .iommu_pad_len = 0x0fffb000,
1152 .tcx_base = 0x50000000,
1153 .slavio_base = 0x70000000,
1154 .ms_kb_base = 0x71000000,
1155 .serial_base = 0x71100000,
1156 .nvram_base = 0x71200000,
1157 .fd_base = 0x71400000,
1158 .counter_base = 0x71d00000,
1159 .intctl_base = 0x71e00000,
1160 .idreg_base = 0x78000000,
1161 .dma_base = 0x78400000,
1162 .esp_base = 0x78800000,
1163 .le_base = 0x78c00000,
1164 .aux1_base = 0x71900000,
1165 .aux2_base = 0x71910000,
1166 .nvram_machine_id = 0x80,
1167 .machine_id = lx_id,
1168 .iommu_version = 0x04000000,
1169 .max_mem = 0x10000000,
1170 .default_cpu_model = "TI MicroSparc I",
1171 },
1172 /* SS-4 */
1173 {
1174 .iommu_base = 0x10000000,
1175 .tcx_base = 0x50000000,
1176 .cs_base = 0x6c000000,
1177 .slavio_base = 0x70000000,
1178 .ms_kb_base = 0x71000000,
1179 .serial_base = 0x71100000,
1180 .nvram_base = 0x71200000,
1181 .fd_base = 0x71400000,
1182 .counter_base = 0x71d00000,
1183 .intctl_base = 0x71e00000,
1184 .idreg_base = 0x78000000,
1185 .dma_base = 0x78400000,
1186 .esp_base = 0x78800000,
1187 .le_base = 0x78c00000,
1188 .apc_base = 0x6a000000,
1189 .aux1_base = 0x71900000,
1190 .aux2_base = 0x71910000,
1191 .nvram_machine_id = 0x80,
1192 .machine_id = ss4_id,
1193 .iommu_version = 0x05000000,
1194 .max_mem = 0x10000000,
1195 .default_cpu_model = "Fujitsu MB86904",
1196 },
1197 /* SPARCClassic */
1198 {
1199 .iommu_base = 0x10000000,
1200 .tcx_base = 0x50000000,
1201 .slavio_base = 0x70000000,
1202 .ms_kb_base = 0x71000000,
1203 .serial_base = 0x71100000,
1204 .nvram_base = 0x71200000,
1205 .fd_base = 0x71400000,
1206 .counter_base = 0x71d00000,
1207 .intctl_base = 0x71e00000,
1208 .idreg_base = 0x78000000,
1209 .dma_base = 0x78400000,
1210 .esp_base = 0x78800000,
1211 .le_base = 0x78c00000,
1212 .apc_base = 0x6a000000,
1213 .aux1_base = 0x71900000,
1214 .aux2_base = 0x71910000,
1215 .nvram_machine_id = 0x80,
1216 .machine_id = scls_id,
1217 .iommu_version = 0x05000000,
1218 .max_mem = 0x10000000,
1219 .default_cpu_model = "TI MicroSparc I",
1220 },
1221 /* SPARCbook */
1222 {
1223 .iommu_base = 0x10000000,
1224 .tcx_base = 0x50000000, // XXX
1225 .slavio_base = 0x70000000,
1226 .ms_kb_base = 0x71000000,
1227 .serial_base = 0x71100000,
1228 .nvram_base = 0x71200000,
1229 .fd_base = 0x71400000,
1230 .counter_base = 0x71d00000,
1231 .intctl_base = 0x71e00000,
1232 .idreg_base = 0x78000000,
1233 .dma_base = 0x78400000,
1234 .esp_base = 0x78800000,
1235 .le_base = 0x78c00000,
1236 .apc_base = 0x6a000000,
1237 .aux1_base = 0x71900000,
1238 .aux2_base = 0x71910000,
1239 .nvram_machine_id = 0x80,
1240 .machine_id = sbook_id,
1241 .iommu_version = 0x05000000,
1242 .max_mem = 0x10000000,
1243 .default_cpu_model = "TI MicroSparc I",
1244 },
1245 };
1246
1247 /* SPARCstation 5 hardware initialisation */
1248 static void ss5_init(ram_addr_t RAM_size,
1249 const char *boot_device,
1250 const char *kernel_filename, const char *kernel_cmdline,
1251 const char *initrd_filename, const char *cpu_model)
1252 {
1253 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1254 kernel_cmdline, initrd_filename, cpu_model);
1255 }
1256
1257 /* SPARCstation 10 hardware initialisation */
1258 static void ss10_init(ram_addr_t RAM_size,
1259 const char *boot_device,
1260 const char *kernel_filename, const char *kernel_cmdline,
1261 const char *initrd_filename, const char *cpu_model)
1262 {
1263 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1264 kernel_cmdline, initrd_filename, cpu_model);
1265 }
1266
1267 /* SPARCserver 600MP hardware initialisation */
1268 static void ss600mp_init(ram_addr_t RAM_size,
1269 const char *boot_device,
1270 const char *kernel_filename,
1271 const char *kernel_cmdline,
1272 const char *initrd_filename, const char *cpu_model)
1273 {
1274 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1275 kernel_cmdline, initrd_filename, cpu_model);
1276 }
1277
1278 /* SPARCstation 20 hardware initialisation */
1279 static void ss20_init(ram_addr_t RAM_size,
1280 const char *boot_device,
1281 const char *kernel_filename, const char *kernel_cmdline,
1282 const char *initrd_filename, const char *cpu_model)
1283 {
1284 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1285 kernel_cmdline, initrd_filename, cpu_model);
1286 }
1287
1288 /* SPARCstation Voyager hardware initialisation */
1289 static void vger_init(ram_addr_t RAM_size,
1290 const char *boot_device,
1291 const char *kernel_filename, const char *kernel_cmdline,
1292 const char *initrd_filename, const char *cpu_model)
1293 {
1294 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1295 kernel_cmdline, initrd_filename, cpu_model);
1296 }
1297
1298 /* SPARCstation LX hardware initialisation */
1299 static void ss_lx_init(ram_addr_t RAM_size,
1300 const char *boot_device,
1301 const char *kernel_filename, const char *kernel_cmdline,
1302 const char *initrd_filename, const char *cpu_model)
1303 {
1304 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1305 kernel_cmdline, initrd_filename, cpu_model);
1306 }
1307
1308 /* SPARCstation 4 hardware initialisation */
1309 static void ss4_init(ram_addr_t RAM_size,
1310 const char *boot_device,
1311 const char *kernel_filename, const char *kernel_cmdline,
1312 const char *initrd_filename, const char *cpu_model)
1313 {
1314 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1315 kernel_cmdline, initrd_filename, cpu_model);
1316 }
1317
1318 /* SPARCClassic hardware initialisation */
1319 static void scls_init(ram_addr_t RAM_size,
1320 const char *boot_device,
1321 const char *kernel_filename, const char *kernel_cmdline,
1322 const char *initrd_filename, const char *cpu_model)
1323 {
1324 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1325 kernel_cmdline, initrd_filename, cpu_model);
1326 }
1327
1328 /* SPARCbook hardware initialisation */
1329 static void sbook_init(ram_addr_t RAM_size,
1330 const char *boot_device,
1331 const char *kernel_filename, const char *kernel_cmdline,
1332 const char *initrd_filename, const char *cpu_model)
1333 {
1334 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1335 kernel_cmdline, initrd_filename, cpu_model);
1336 }
1337
1338 static QEMUMachine ss5_machine = {
1339 .name = "SS-5",
1340 .desc = "Sun4m platform, SPARCstation 5",
1341 .init = ss5_init,
1342 .use_scsi = 1,
1343 .is_default = 1,
1344 };
1345
1346 static QEMUMachine ss10_machine = {
1347 .name = "SS-10",
1348 .desc = "Sun4m platform, SPARCstation 10",
1349 .init = ss10_init,
1350 .use_scsi = 1,
1351 .max_cpus = 4,
1352 };
1353
1354 static QEMUMachine ss600mp_machine = {
1355 .name = "SS-600MP",
1356 .desc = "Sun4m platform, SPARCserver 600MP",
1357 .init = ss600mp_init,
1358 .use_scsi = 1,
1359 .max_cpus = 4,
1360 };
1361
1362 static QEMUMachine ss20_machine = {
1363 .name = "SS-20",
1364 .desc = "Sun4m platform, SPARCstation 20",
1365 .init = ss20_init,
1366 .use_scsi = 1,
1367 .max_cpus = 4,
1368 };
1369
1370 static QEMUMachine voyager_machine = {
1371 .name = "Voyager",
1372 .desc = "Sun4m platform, SPARCstation Voyager",
1373 .init = vger_init,
1374 .use_scsi = 1,
1375 };
1376
1377 static QEMUMachine ss_lx_machine = {
1378 .name = "LX",
1379 .desc = "Sun4m platform, SPARCstation LX",
1380 .init = ss_lx_init,
1381 .use_scsi = 1,
1382 };
1383
1384 static QEMUMachine ss4_machine = {
1385 .name = "SS-4",
1386 .desc = "Sun4m platform, SPARCstation 4",
1387 .init = ss4_init,
1388 .use_scsi = 1,
1389 };
1390
1391 static QEMUMachine scls_machine = {
1392 .name = "SPARCClassic",
1393 .desc = "Sun4m platform, SPARCClassic",
1394 .init = scls_init,
1395 .use_scsi = 1,
1396 };
1397
1398 static QEMUMachine sbook_machine = {
1399 .name = "SPARCbook",
1400 .desc = "Sun4m platform, SPARCbook",
1401 .init = sbook_init,
1402 .use_scsi = 1,
1403 };
1404
1405 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1406 /* SS-1000 */
1407 {
1408 .iounit_bases = {
1409 0xfe0200000ULL,
1410 0xfe1200000ULL,
1411 0xfe2200000ULL,
1412 0xfe3200000ULL,
1413 -1,
1414 },
1415 .tcx_base = 0x820000000ULL,
1416 .slavio_base = 0xf00000000ULL,
1417 .ms_kb_base = 0xf00240000ULL,
1418 .serial_base = 0xf00200000ULL,
1419 .nvram_base = 0xf00280000ULL,
1420 .counter_base = 0xf00300000ULL,
1421 .espdma_base = 0x800081000ULL,
1422 .esp_base = 0x800080000ULL,
1423 .ledma_base = 0x800040000ULL,
1424 .le_base = 0x800060000ULL,
1425 .sbi_base = 0xf02800000ULL,
1426 .nvram_machine_id = 0x80,
1427 .machine_id = ss1000_id,
1428 .iounit_version = 0x03000000,
1429 .max_mem = 0xf00000000ULL,
1430 .default_cpu_model = "TI SuperSparc II",
1431 },
1432 /* SS-2000 */
1433 {
1434 .iounit_bases = {
1435 0xfe0200000ULL,
1436 0xfe1200000ULL,
1437 0xfe2200000ULL,
1438 0xfe3200000ULL,
1439 0xfe4200000ULL,
1440 },
1441 .tcx_base = 0x820000000ULL,
1442 .slavio_base = 0xf00000000ULL,
1443 .ms_kb_base = 0xf00240000ULL,
1444 .serial_base = 0xf00200000ULL,
1445 .nvram_base = 0xf00280000ULL,
1446 .counter_base = 0xf00300000ULL,
1447 .espdma_base = 0x800081000ULL,
1448 .esp_base = 0x800080000ULL,
1449 .ledma_base = 0x800040000ULL,
1450 .le_base = 0x800060000ULL,
1451 .sbi_base = 0xf02800000ULL,
1452 .nvram_machine_id = 0x80,
1453 .machine_id = ss2000_id,
1454 .iounit_version = 0x03000000,
1455 .max_mem = 0xf00000000ULL,
1456 .default_cpu_model = "TI SuperSparc II",
1457 },
1458 };
1459
1460 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1461 {
1462 DeviceState *dev;
1463 SysBusDevice *s;
1464 unsigned int i;
1465
1466 dev = qdev_create(NULL, "sbi");
1467 qdev_init_nofail(dev);
1468
1469 s = sysbus_from_qdev(dev);
1470
1471 for (i = 0; i < MAX_CPUS; i++) {
1472 sysbus_connect_irq(s, i, *parent_irq[i]);
1473 }
1474
1475 sysbus_mmio_map(s, 0, addr);
1476
1477 return dev;
1478 }
1479
1480 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1481 const char *boot_device,
1482 const char *kernel_filename,
1483 const char *kernel_cmdline,
1484 const char *initrd_filename, const char *cpu_model)
1485 {
1486 unsigned int i;
1487 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1488 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1489 espdma_irq, ledma_irq;
1490 qemu_irq esp_reset, dma_enable;
1491 unsigned long kernel_size;
1492 void *fw_cfg;
1493 DeviceState *dev;
1494
1495 /* init CPUs */
1496 if (!cpu_model)
1497 cpu_model = hwdef->default_cpu_model;
1498
1499 for(i = 0; i < smp_cpus; i++) {
1500 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1501 }
1502
1503 for (i = smp_cpus; i < MAX_CPUS; i++)
1504 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1505
1506 /* set up devices */
1507 ram_init(0, RAM_size, hwdef->max_mem);
1508
1509 prom_init(hwdef->slavio_base, bios_name);
1510
1511 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1512
1513 for (i = 0; i < 32; i++) {
1514 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1515 }
1516 for (i = 0; i < MAX_CPUS; i++) {
1517 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1518 }
1519
1520 for (i = 0; i < MAX_IOUNITS; i++)
1521 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1522 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1523 hwdef->iounit_version,
1524 sbi_irq[0]);
1525
1526 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1527 iounits[0], &espdma_irq);
1528
1529 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1530 iounits[0], &ledma_irq);
1531
1532 if (graphic_depth != 8 && graphic_depth != 24) {
1533 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1534 exit (1);
1535 }
1536 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1537 graphic_depth);
1538
1539 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1540
1541 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1542
1543 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1544
1545 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1546 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1547 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1548 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1549 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1550 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1551
1552 if (drive_get_max_bus(IF_SCSI) > 0) {
1553 fprintf(stderr, "qemu: too many SCSI bus\n");
1554 exit(1);
1555 }
1556
1557 esp_init(hwdef->esp_base, 2,
1558 espdma_memory_read, espdma_memory_write,
1559 espdma, espdma_irq, &esp_reset, &dma_enable);
1560
1561 qdev_connect_gpio_out(espdma, 0, esp_reset);
1562 qdev_connect_gpio_out(espdma, 1, dma_enable);
1563
1564 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1565 RAM_size);
1566
1567 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1568 boot_device, RAM_size, kernel_size, graphic_width,
1569 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1570 "Sun4d");
1571
1572 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1573 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1574 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1575 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1576 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1577 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1578 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1579 if (kernel_cmdline) {
1580 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1581 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1582 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1583 (uint8_t*)strdup(kernel_cmdline),
1584 strlen(kernel_cmdline) + 1);
1585 } else {
1586 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1587 }
1588 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1589 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1590 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1591 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1592 }
1593
1594 /* SPARCserver 1000 hardware initialisation */
1595 static void ss1000_init(ram_addr_t RAM_size,
1596 const char *boot_device,
1597 const char *kernel_filename, const char *kernel_cmdline,
1598 const char *initrd_filename, const char *cpu_model)
1599 {
1600 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1601 kernel_cmdline, initrd_filename, cpu_model);
1602 }
1603
1604 /* SPARCcenter 2000 hardware initialisation */
1605 static void ss2000_init(ram_addr_t RAM_size,
1606 const char *boot_device,
1607 const char *kernel_filename, const char *kernel_cmdline,
1608 const char *initrd_filename, const char *cpu_model)
1609 {
1610 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1611 kernel_cmdline, initrd_filename, cpu_model);
1612 }
1613
1614 static QEMUMachine ss1000_machine = {
1615 .name = "SS-1000",
1616 .desc = "Sun4d platform, SPARCserver 1000",
1617 .init = ss1000_init,
1618 .use_scsi = 1,
1619 .max_cpus = 8,
1620 };
1621
1622 static QEMUMachine ss2000_machine = {
1623 .name = "SS-2000",
1624 .desc = "Sun4d platform, SPARCcenter 2000",
1625 .init = ss2000_init,
1626 .use_scsi = 1,
1627 .max_cpus = 20,
1628 };
1629
1630 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1631 /* SS-2 */
1632 {
1633 .iommu_base = 0xf8000000,
1634 .tcx_base = 0xfe000000,
1635 .slavio_base = 0xf6000000,
1636 .intctl_base = 0xf5000000,
1637 .counter_base = 0xf3000000,
1638 .ms_kb_base = 0xf0000000,
1639 .serial_base = 0xf1000000,
1640 .nvram_base = 0xf2000000,
1641 .fd_base = 0xf7200000,
1642 .dma_base = 0xf8400000,
1643 .esp_base = 0xf8800000,
1644 .le_base = 0xf8c00000,
1645 .aux1_base = 0xf7400003,
1646 .nvram_machine_id = 0x55,
1647 .machine_id = ss2_id,
1648 .max_mem = 0x10000000,
1649 .default_cpu_model = "Cypress CY7C601",
1650 },
1651 };
1652
1653 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1654 qemu_irq *parent_irq)
1655 {
1656 DeviceState *dev;
1657 SysBusDevice *s;
1658 unsigned int i;
1659
1660 dev = qdev_create(NULL, "sun4c_intctl");
1661 qdev_init_nofail(dev);
1662
1663 s = sysbus_from_qdev(dev);
1664
1665 for (i = 0; i < MAX_PILS; i++) {
1666 sysbus_connect_irq(s, i, parent_irq[i]);
1667 }
1668 sysbus_mmio_map(s, 0, addr);
1669
1670 return dev;
1671 }
1672
1673 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1674 const char *boot_device,
1675 const char *kernel_filename,
1676 const char *kernel_cmdline,
1677 const char *initrd_filename, const char *cpu_model)
1678 {
1679 void *iommu, *espdma, *ledma, *nvram;
1680 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1681 qemu_irq esp_reset, dma_enable;
1682 qemu_irq fdc_tc;
1683 unsigned long kernel_size;
1684 DriveInfo *fd[MAX_FD];
1685 void *fw_cfg;
1686 DeviceState *dev;
1687 unsigned int i;
1688
1689 /* init CPU */
1690 if (!cpu_model)
1691 cpu_model = hwdef->default_cpu_model;
1692
1693 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1694
1695 /* set up devices */
1696 ram_init(0, RAM_size, hwdef->max_mem);
1697
1698 prom_init(hwdef->slavio_base, bios_name);
1699
1700 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1701
1702 for (i = 0; i < 8; i++) {
1703 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1704 }
1705
1706 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1707 slavio_irq[1]);
1708
1709 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1710 iommu, &espdma_irq);
1711
1712 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1713 slavio_irq[3], iommu, &ledma_irq);
1714
1715 if (graphic_depth != 8 && graphic_depth != 24) {
1716 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1717 exit (1);
1718 }
1719 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1720 graphic_depth);
1721
1722 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1723
1724 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1725
1726 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1727 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1728 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1729 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1730 escc_init(hwdef->serial_base, slavio_irq[1],
1731 slavio_irq[1], serial_hds[0], serial_hds[1],
1732 ESCC_CLOCK, 1);
1733
1734 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1735
1736 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1737 /* there is zero or one floppy drive */
1738 memset(fd, 0, sizeof(fd));
1739 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1740 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1741 &fdc_tc);
1742 }
1743
1744 if (drive_get_max_bus(IF_SCSI) > 0) {
1745 fprintf(stderr, "qemu: too many SCSI bus\n");
1746 exit(1);
1747 }
1748
1749 esp_init(hwdef->esp_base, 2,
1750 espdma_memory_read, espdma_memory_write,
1751 espdma, espdma_irq, &esp_reset, &dma_enable);
1752
1753 qdev_connect_gpio_out(espdma, 0, esp_reset);
1754 qdev_connect_gpio_out(espdma, 1, dma_enable);
1755
1756 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1757 RAM_size);
1758
1759 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1760 boot_device, RAM_size, kernel_size, graphic_width,
1761 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1762 "Sun4c");
1763
1764 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1765 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1766 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1767 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1768 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1769 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1770 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1771 if (kernel_cmdline) {
1772 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1773 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1774 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1775 (uint8_t*)strdup(kernel_cmdline),
1776 strlen(kernel_cmdline) + 1);
1777 } else {
1778 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1779 }
1780 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1781 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1782 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1783 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1784 }
1785
1786 /* SPARCstation 2 hardware initialisation */
1787 static void ss2_init(ram_addr_t RAM_size,
1788 const char *boot_device,
1789 const char *kernel_filename, const char *kernel_cmdline,
1790 const char *initrd_filename, const char *cpu_model)
1791 {
1792 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1793 kernel_cmdline, initrd_filename, cpu_model);
1794 }
1795
1796 static QEMUMachine ss2_machine = {
1797 .name = "SS-2",
1798 .desc = "Sun4c platform, SPARCstation 2",
1799 .init = ss2_init,
1800 .use_scsi = 1,
1801 };
1802
1803 static void ss2_machine_init(void)
1804 {
1805 qemu_register_machine(&ss5_machine);
1806 qemu_register_machine(&ss10_machine);
1807 qemu_register_machine(&ss600mp_machine);
1808 qemu_register_machine(&ss20_machine);
1809 qemu_register_machine(&voyager_machine);
1810 qemu_register_machine(&ss_lx_machine);
1811 qemu_register_machine(&ss4_machine);
1812 qemu_register_machine(&scls_machine);
1813 qemu_register_machine(&sbook_machine);
1814 qemu_register_machine(&ss1000_machine);
1815 qemu_register_machine(&ss2000_machine);
1816 qemu_register_machine(&ss2_machine);
1817 }
1818
1819 machine_init(ss2_machine_init);
QEmu