hw/arm/fsl-imx25.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX25 SOC emulation.
   5  *
   6  * Based on hw/arm/xlnx-zynqmp.c
   7  *
   8  * Copyright (C) 2015 Xilinx Inc
   9  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the
  13  *  Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  19  *  for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along
  22  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/arm/fsl-imx25.h"
  27 #include "sysemu/sysemu.h"
  28 #include "exec/address-spaces.h"
  29 #include "hw/boards.h"
  30 #include "sysemu/char.h"
  31
  32 static void fsl_imx25_init(Object *obj)
  33 {
  34     FslIMX25State *s = FSL_IMX25(obj);
  35     int i;
  36
  37     object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
  38
  39     object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
  40     qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
  41
  42     object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
  43     qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
  44
  45     for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
  46         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
  47         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
  48     }
  49
  50     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
  51         object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT);
  52         qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
  53     }
  54
  55     for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
  56         object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
  57         qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
  58     }
  59
  60     object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);
  61     qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());
  62
  63     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
  64         object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
  65         qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
  66     }
  67
  68     for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
  69         object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
  70         qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
  71     }
  72 }
  73
  74 static void fsl_imx25_realize(DeviceState *dev, Error **errp)
  75 {
  76     FslIMX25State *s = FSL_IMX25(dev);
  77     uint8_t i;
  78     Error *err = NULL;
  79
  80     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  81     if (err) {
  82         error_propagate(errp, err);
  83         return;
  84     }
  85
  86     object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
  87     if (err) {
  88         error_propagate(errp, err);
  89         return;
  90     }
  91     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
  92     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
  93                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
  94     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
  95                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
  96
  97     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
  98     if (err) {
  99         error_propagate(errp, err);
 100         return;
 101     }
 102     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
 103
 104     /* Initialize all UARTs */
 105     for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
 106         static const struct {
 107             hwaddr addr;
 108             unsigned int irq;
 109         } serial_table[FSL_IMX25_NUM_UARTS] = {
 110             { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
 111             { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
 112             { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
 113             { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
 114             { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
 115         };
 116
 117         if (i < MAX_SERIAL_PORTS) {
 118             CharDriverState *chr;
 119
 120             chr = serial_hds[i];
 121
 122             if (!chr) {
 123                 char label[20];
 124                 snprintf(label, sizeof(label), "imx31.uart%d", i);
 125                 chr = qemu_chr_new(label, "null", NULL);
 126             }
 127
 128             qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 129         }
 130
 131         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 132         if (err) {
 133             error_propagate(errp, err);
 134             return;
 135         }
 136         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 137         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 138                            qdev_get_gpio_in(DEVICE(&s->avic),
 139                                             serial_table[i].irq));
 140     }
 141
 142     /* Initialize all GPT timers */
 143     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
 144         static const struct {
 145             hwaddr addr;
 146             unsigned int irq;
 147         } gpt_table[FSL_IMX25_NUM_GPTS] = {
 148             { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
 149             { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
 150             { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
 151             { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
 152         };
 153
 154         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 155
 156         object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
 157         if (err) {
 158             error_propagate(errp, err);
 159             return;
 160         }
 161         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
 162         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 163                            qdev_get_gpio_in(DEVICE(&s->avic),
 164                                             gpt_table[i].irq));
 165     }
 166
 167     /* Initialize all EPIT timers */
 168     for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
 169         static const struct {
 170             hwaddr addr;
 171             unsigned int irq;
 172         } epit_table[FSL_IMX25_NUM_EPITS] = {
 173             { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
 174             { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
 175         };
 176
 177         s->epit[i].ccm = IMX_CCM(&s->ccm);
 178
 179         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
 180         if (err) {
 181             error_propagate(errp, err);
 182             return;
 183         }
 184         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 185         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 186                            qdev_get_gpio_in(DEVICE(&s->avic),
 187                                             epit_table[i].irq));
 188     }
 189
 190     qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
 191     object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
 192     if (err) {
 193         error_propagate(errp, err);
 194         return;
 195     }
 196     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
 197     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
 198                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
 199
 200
 201     /* Initialize all I2C */
 202     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
 203         static const struct {
 204             hwaddr addr;
 205             unsigned int irq;
 206         } i2c_table[FSL_IMX25_NUM_I2CS] = {
 207             { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
 208             { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
 209             { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
 210         };
 211
 212         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
 213         if (err) {
 214             error_propagate(errp, err);
 215             return;
 216         }
 217         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 218         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 219                            qdev_get_gpio_in(DEVICE(&s->avic),
 220                                             i2c_table[i].irq));
 221     }
 222
 223     /* Initialize all GPIOs */
 224     for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
 225         static const struct {
 226             hwaddr addr;
 227             unsigned int irq;
 228         } gpio_table[FSL_IMX25_NUM_GPIOS] = {
 229             { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
 230             { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
 231             { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
 232             { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
 233         };
 234
 235         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
 236         if (err) {
 237             error_propagate(errp, err);
 238             return;
 239         }
 240         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 241         /* Connect GPIO IRQ to PIC */
 242         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 243                            qdev_get_gpio_in(DEVICE(&s->avic),
 244                                             gpio_table[i].irq));
 245     }
 246
 247     /* initialize 2 x 16 KB ROM */
 248     memory_region_init_rom_device(&s->rom[0], NULL, NULL, NULL,
 249                                   "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
 250     if (err) {
 251         error_propagate(errp, err);
 252         return;
 253     }
 254     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
 255                                 &s->rom[0]);
 256     memory_region_init_rom_device(&s->rom[1], NULL, NULL, NULL,
 257                                   "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
 258     if (err) {
 259         error_propagate(errp, err);
 260         return;
 261     }
 262     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
 263                                 &s->rom[1]);
 264
 265     /* initialize internal RAM (128 KB) */
 266     memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
 267                            &err);
 268     if (err) {
 269         error_propagate(errp, err);
 270         return;
 271     }
 272     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
 273                                 &s->iram);
 274     vmstate_register_ram_global(&s->iram);
 275
 276     /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
 277     memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
 278                              &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
 279     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
 280                                 &s->iram_alias);
 281 }
 282
 283 static void fsl_imx25_class_init(ObjectClass *oc, void *data)
 284 {
 285     DeviceClass *dc = DEVICE_CLASS(oc);
 286
 287     dc->realize = fsl_imx25_realize;
 288
 289     /*
 290      * Reason: creates an ARM CPU, thus use after free(), see
 291      * arm_cpu_class_init()
 292      */
 293     dc->cannot_destroy_with_object_finalize_yet = true;
 294     dc->desc = "i.MX25 SOC";
 295 }
 296
 297 static const TypeInfo fsl_imx25_type_info = {
 298     .name = TYPE_FSL_IMX25,
 299     .parent = TYPE_DEVICE,
 300     .instance_size = sizeof(FslIMX25State),
 301     .instance_init = fsl_imx25_init,
 302     .class_init = fsl_imx25_class_init,
 303 };
 304
 305 static void fsl_imx25_register_types(void)
 306 {
 307     type_register_static(&fsl_imx25_type_info);
 308 }
 309
 310 type_init(fsl_imx25_register_types)