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ide: Convert PIO read/write commands to ide_cmd_table handler
[qemu.git] / hw / ide / core.c
blob86af4b0f66b712daa2432dd768e4ea6e4446be2e
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/isa/isa.h>
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "hw/block/block.h"
34 #include "sysemu/blockdev.h"
35
36 #include <hw/ide/internal.h>
37
38 /* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40 static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
56 };
57
58 static int ide_handle_rw_error(IDEState *s, int error, int op);
59 static void ide_dummy_transfer_stop(IDEState *s);
60
61 static void padstr(char *str, const char *src, int len)
62 {
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71 }
72
73 static void put_le16(uint16_t *p, unsigned int v)
74 {
75 *p = cpu_to_le16(v);
76 }
77
78 static void ide_identify(IDEState *s)
79 {
80 uint16_t *p;
81 unsigned int oldsize;
82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
83
84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
91 put_le16(p + 0, 0x0040);
92 put_le16(p + 1, s->cylinders);
93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
96 put_le16(p + 6, s->sectors);
97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
102 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
103 #if MAX_MULT_SECTORS > 1
104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
105 #endif
106 put_le16(p + 48, 1); /* dword I/O */
107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
114 oldsize = s->cylinders * s->heads * s->sectors;
115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
117 if (s->mult_sectors)
118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
123 put_le16(p + 64, 0x03); /* pio3-4 supported */
124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
144 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
145 if (s->wwn) {
146 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
147 } else {
148 put_le16(p + 84, (1 << 14) | 0);
149 }
150 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
151 if (bdrv_enable_write_cache(s->bs))
152 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
153 else
154 put_le16(p + 85, (1 << 14) | 1);
155 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
156 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
157 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
158 if (s->wwn) {
159 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
160 } else {
161 put_le16(p + 87, (1 << 14) | 0);
162 }
163 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
164 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
165 put_le16(p + 100, s->nb_sectors);
166 put_le16(p + 101, s->nb_sectors >> 16);
167 put_le16(p + 102, s->nb_sectors >> 32);
168 put_le16(p + 103, s->nb_sectors >> 48);
169
170 if (dev && dev->conf.physical_block_size)
171 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
172 if (s->wwn) {
173 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
174 put_le16(p + 108, s->wwn >> 48);
175 put_le16(p + 109, s->wwn >> 32);
176 put_le16(p + 110, s->wwn >> 16);
177 put_le16(p + 111, s->wwn);
178 }
179 if (dev && dev->conf.discard_granularity) {
180 put_le16(p + 169, 1); /* TRIM support */
181 }
182
183 memcpy(s->identify_data, p, sizeof(s->identify_data));
184 s->identify_set = 1;
185 }
186
187 static void ide_atapi_identify(IDEState *s)
188 {
189 uint16_t *p;
190
191 if (s->identify_set) {
192 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
193 return;
194 }
195
196 memset(s->io_buffer, 0, 512);
197 p = (uint16_t *)s->io_buffer;
198 /* Removable CDROM, 50us response, 12 byte packets */
199 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
200 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201 put_le16(p + 20, 3); /* buffer type */
202 put_le16(p + 21, 512); /* cache size in sectors */
203 put_le16(p + 22, 4); /* ecc bytes */
204 padstr((char *)(p + 23), s->version, 8); /* firmware version */
205 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
206 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
207 #ifdef USE_DMA_CDROM
208 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
209 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
210 put_le16(p + 62, 7); /* single word dma0-2 supported */
211 put_le16(p + 63, 7); /* mdma0-2 supported */
212 #else
213 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
214 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
215 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
216 #endif
217 put_le16(p + 64, 3); /* pio3-4 supported */
218 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
219 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
220 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
221 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
222
223 put_le16(p + 71, 30); /* in ns */
224 put_le16(p + 72, 30); /* in ns */
225
226 if (s->ncq_queues) {
227 put_le16(p + 75, s->ncq_queues - 1);
228 /* NCQ supported */
229 put_le16(p + 76, (1 << 8));
230 }
231
232 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
233 #ifdef USE_DMA_CDROM
234 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
235 #endif
236 memcpy(s->identify_data, p, sizeof(s->identify_data));
237 s->identify_set = 1;
238 }
239
240 static void ide_cfata_identify(IDEState *s)
241 {
242 uint16_t *p;
243 uint32_t cur_sec;
244
245 p = (uint16_t *) s->identify_data;
246 if (s->identify_set)
247 goto fill_buffer;
248
249 memset(p, 0, sizeof(s->identify_data));
250
251 cur_sec = s->cylinders * s->heads * s->sectors;
252
253 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
254 put_le16(p + 1, s->cylinders); /* Default cylinders */
255 put_le16(p + 3, s->heads); /* Default heads */
256 put_le16(p + 6, s->sectors); /* Default sectors per track */
257 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
258 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
259 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
260 put_le16(p + 22, 0x0004); /* ECC bytes */
261 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
262 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
263 #if MAX_MULT_SECTORS > 1
264 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
265 #else
266 put_le16(p + 47, 0x0000);
267 #endif
268 put_le16(p + 49, 0x0f00); /* Capabilities */
269 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
270 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
271 put_le16(p + 53, 0x0003); /* Translation params valid */
272 put_le16(p + 54, s->cylinders); /* Current cylinders */
273 put_le16(p + 55, s->heads); /* Current heads */
274 put_le16(p + 56, s->sectors); /* Current sectors */
275 put_le16(p + 57, cur_sec); /* Current capacity */
276 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
277 if (s->mult_sectors) /* Multiple sector setting */
278 put_le16(p + 59, 0x100 | s->mult_sectors);
279 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
280 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
281 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
282 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
283 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
284 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
285 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
286 put_le16(p + 82, 0x400c); /* Command Set supported */
287 put_le16(p + 83, 0x7068); /* Command Set supported */
288 put_le16(p + 84, 0x4000); /* Features supported */
289 put_le16(p + 85, 0x000c); /* Command Set enabled */
290 put_le16(p + 86, 0x7044); /* Command Set enabled */
291 put_le16(p + 87, 0x4000); /* Features enabled */
292 put_le16(p + 91, 0x4060); /* Current APM level */
293 put_le16(p + 129, 0x0002); /* Current features option */
294 put_le16(p + 130, 0x0005); /* Reassigned sectors */
295 put_le16(p + 131, 0x0001); /* Initial power mode */
296 put_le16(p + 132, 0x0000); /* User signature */
297 put_le16(p + 160, 0x8100); /* Power requirement */
298 put_le16(p + 161, 0x8001); /* CF command set */
299
300 s->identify_set = 1;
301
302 fill_buffer:
303 memcpy(s->io_buffer, p, sizeof(s->identify_data));
304 }
305
306 static void ide_set_signature(IDEState *s)
307 {
308 s->select &= 0xf0; /* clear head */
309 /* put signature */
310 s->nsector = 1;
311 s->sector = 1;
312 if (s->drive_kind == IDE_CD) {
313 s->lcyl = 0x14;
314 s->hcyl = 0xeb;
315 } else if (s->bs) {
316 s->lcyl = 0;
317 s->hcyl = 0;
318 } else {
319 s->lcyl = 0xff;
320 s->hcyl = 0xff;
321 }
322 }
323
324 typedef struct TrimAIOCB {
325 BlockDriverAIOCB common;
326 QEMUBH *bh;
327 int ret;
328 QEMUIOVector *qiov;
329 BlockDriverAIOCB *aiocb;
330 int i, j;
331 } TrimAIOCB;
332
333 static void trim_aio_cancel(BlockDriverAIOCB *acb)
334 {
335 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
336
337 /* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */
338 iocb->j = iocb->qiov->niov - 1;
339 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
340
341 /* Tell ide_issue_trim_cb not to trigger the completion, too. */
342 qemu_bh_delete(iocb->bh);
343 iocb->bh = NULL;
344
345 if (iocb->aiocb) {
346 bdrv_aio_cancel(iocb->aiocb);
347 }
348 qemu_aio_release(iocb);
349 }
350
351 static const AIOCBInfo trim_aiocb_info = {
352 .aiocb_size = sizeof(TrimAIOCB),
353 .cancel = trim_aio_cancel,
354 };
355
356 static void ide_trim_bh_cb(void *opaque)
357 {
358 TrimAIOCB *iocb = opaque;
359
360 iocb->common.cb(iocb->common.opaque, iocb->ret);
361
362 qemu_bh_delete(iocb->bh);
363 iocb->bh = NULL;
364 qemu_aio_release(iocb);
365 }
366
367 static void ide_issue_trim_cb(void *opaque, int ret)
368 {
369 TrimAIOCB *iocb = opaque;
370 if (ret >= 0) {
371 while (iocb->j < iocb->qiov->niov) {
372 int j = iocb->j;
373 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
374 int i = iocb->i;
375 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
376
377 /* 6-byte LBA + 2-byte range per entry */
378 uint64_t entry = le64_to_cpu(buffer[i]);
379 uint64_t sector = entry & 0x0000ffffffffffffULL;
380 uint16_t count = entry >> 48;
381
382 if (count == 0) {
383 continue;
384 }
385
386 /* Got an entry! Submit and exit. */
387 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
388 ide_issue_trim_cb, opaque);
389 return;
390 }
391
392 iocb->j++;
393 iocb->i = -1;
394 }
395 } else {
396 iocb->ret = ret;
397 }
398
399 iocb->aiocb = NULL;
400 if (iocb->bh) {
401 qemu_bh_schedule(iocb->bh);
402 }
403 }
404
405 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
406 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
407 BlockDriverCompletionFunc *cb, void *opaque)
408 {
409 TrimAIOCB *iocb;
410
411 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
412 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
413 iocb->ret = 0;
414 iocb->qiov = qiov;
415 iocb->i = -1;
416 iocb->j = 0;
417 ide_issue_trim_cb(iocb, 0);
418 return &iocb->common;
419 }
420
421 static inline void ide_abort_command(IDEState *s)
422 {
423 s->status = READY_STAT | ERR_STAT;
424 s->error = ABRT_ERR;
425 }
426
427 /* prepare data transfer and tell what to do after */
428 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
429 EndTransferFunc *end_transfer_func)
430 {
431 s->end_transfer_func = end_transfer_func;
432 s->data_ptr = buf;
433 s->data_end = buf + size;
434 if (!(s->status & ERR_STAT)) {
435 s->status |= DRQ_STAT;
436 }
437 s->bus->dma->ops->start_transfer(s->bus->dma);
438 }
439
440 void ide_transfer_stop(IDEState *s)
441 {
442 s->end_transfer_func = ide_transfer_stop;
443 s->data_ptr = s->io_buffer;
444 s->data_end = s->io_buffer;
445 s->status &= ~DRQ_STAT;
446 }
447
448 int64_t ide_get_sector(IDEState *s)
449 {
450 int64_t sector_num;
451 if (s->select & 0x40) {
452 /* lba */
453 if (!s->lba48) {
454 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
455 (s->lcyl << 8) | s->sector;
456 } else {
457 sector_num = ((int64_t)s->hob_hcyl << 40) |
458 ((int64_t) s->hob_lcyl << 32) |
459 ((int64_t) s->hob_sector << 24) |
460 ((int64_t) s->hcyl << 16) |
461 ((int64_t) s->lcyl << 8) | s->sector;
462 }
463 } else {
464 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
465 (s->select & 0x0f) * s->sectors + (s->sector - 1);
466 }
467 return sector_num;
468 }
469
470 void ide_set_sector(IDEState *s, int64_t sector_num)
471 {
472 unsigned int cyl, r;
473 if (s->select & 0x40) {
474 if (!s->lba48) {
475 s->select = (s->select & 0xf0) | (sector_num >> 24);
476 s->hcyl = (sector_num >> 16);
477 s->lcyl = (sector_num >> 8);
478 s->sector = (sector_num);
479 } else {
480 s->sector = sector_num;
481 s->lcyl = sector_num >> 8;
482 s->hcyl = sector_num >> 16;
483 s->hob_sector = sector_num >> 24;
484 s->hob_lcyl = sector_num >> 32;
485 s->hob_hcyl = sector_num >> 40;
486 }
487 } else {
488 cyl = sector_num / (s->heads * s->sectors);
489 r = sector_num % (s->heads * s->sectors);
490 s->hcyl = cyl >> 8;
491 s->lcyl = cyl;
492 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
493 s->sector = (r % s->sectors) + 1;
494 }
495 }
496
497 static void ide_rw_error(IDEState *s) {
498 ide_abort_command(s);
499 ide_set_irq(s->bus);
500 }
501
502 static void ide_sector_read_cb(void *opaque, int ret)
503 {
504 IDEState *s = opaque;
505 int n;
506
507 s->pio_aiocb = NULL;
508 s->status &= ~BUSY_STAT;
509
510 bdrv_acct_done(s->bs, &s->acct);
511 if (ret != 0) {
512 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
513 BM_STATUS_RETRY_READ)) {
514 return;
515 }
516 }
517
518 n = s->nsector;
519 if (n > s->req_nb_sectors) {
520 n = s->req_nb_sectors;
521 }
522
523 /* Allow the guest to read the io_buffer */
524 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
525
526 ide_set_irq(s->bus);
527
528 ide_set_sector(s, ide_get_sector(s) + n);
529 s->nsector -= n;
530 }
531
532 void ide_sector_read(IDEState *s)
533 {
534 int64_t sector_num;
535 int n;
536
537 s->status = READY_STAT | SEEK_STAT;
538 s->error = 0; /* not needed by IDE spec, but needed by Windows */
539 sector_num = ide_get_sector(s);
540 n = s->nsector;
541
542 if (n == 0) {
543 ide_transfer_stop(s);
544 return;
545 }
546
547 s->status |= BUSY_STAT;
548
549 if (n > s->req_nb_sectors) {
550 n = s->req_nb_sectors;
551 }
552
553 #if defined(DEBUG_IDE)
554 printf("sector=%" PRId64 "\n", sector_num);
555 #endif
556
557 s->iov.iov_base = s->io_buffer;
558 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
559 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
560
561 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
562 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
563 ide_sector_read_cb, s);
564 }
565
566 static void dma_buf_commit(IDEState *s)
567 {
568 qemu_sglist_destroy(&s->sg);
569 }
570
571 void ide_set_inactive(IDEState *s)
572 {
573 s->bus->dma->aiocb = NULL;
574 s->bus->dma->ops->set_inactive(s->bus->dma);
575 }
576
577 void ide_dma_error(IDEState *s)
578 {
579 ide_transfer_stop(s);
580 s->error = ABRT_ERR;
581 s->status = READY_STAT | ERR_STAT;
582 ide_set_inactive(s);
583 ide_set_irq(s->bus);
584 }
585
586 static int ide_handle_rw_error(IDEState *s, int error, int op)
587 {
588 bool is_read = (op & BM_STATUS_RETRY_READ) != 0;
589 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
590
591 if (action == BDRV_ACTION_STOP) {
592 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
593 s->bus->error_status = op;
594 } else if (action == BDRV_ACTION_REPORT) {
595 if (op & BM_STATUS_DMA_RETRY) {
596 dma_buf_commit(s);
597 ide_dma_error(s);
598 } else {
599 ide_rw_error(s);
600 }
601 }
602 bdrv_error_action(s->bs, action, is_read, error);
603 return action != BDRV_ACTION_IGNORE;
604 }
605
606 void ide_dma_cb(void *opaque, int ret)
607 {
608 IDEState *s = opaque;
609 int n;
610 int64_t sector_num;
611 bool stay_active = false;
612
613 if (ret < 0) {
614 int op = BM_STATUS_DMA_RETRY;
615
616 if (s->dma_cmd == IDE_DMA_READ)
617 op |= BM_STATUS_RETRY_READ;
618 else if (s->dma_cmd == IDE_DMA_TRIM)
619 op |= BM_STATUS_RETRY_TRIM;
620
621 if (ide_handle_rw_error(s, -ret, op)) {
622 return;
623 }
624 }
625
626 n = s->io_buffer_size >> 9;
627 if (n > s->nsector) {
628 /* The PRDs were longer than needed for this request. Shorten them so
629 * we don't get a negative remainder. The Active bit must remain set
630 * after the request completes. */
631 n = s->nsector;
632 stay_active = true;
633 }
634
635 sector_num = ide_get_sector(s);
636 if (n > 0) {
637 dma_buf_commit(s);
638 sector_num += n;
639 ide_set_sector(s, sector_num);
640 s->nsector -= n;
641 }
642
643 /* end of transfer ? */
644 if (s->nsector == 0) {
645 s->status = READY_STAT | SEEK_STAT;
646 ide_set_irq(s->bus);
647 goto eot;
648 }
649
650 /* launch next transfer */
651 n = s->nsector;
652 s->io_buffer_index = 0;
653 s->io_buffer_size = n * 512;
654 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
655 /* The PRDs were too short. Reset the Active bit, but don't raise an
656 * interrupt. */
657 s->status = READY_STAT | SEEK_STAT;
658 goto eot;
659 }
660
661 #ifdef DEBUG_AIO
662 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
663 sector_num, n, s->dma_cmd);
664 #endif
665
666 switch (s->dma_cmd) {
667 case IDE_DMA_READ:
668 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
669 ide_dma_cb, s);
670 break;
671 case IDE_DMA_WRITE:
672 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
673 ide_dma_cb, s);
674 break;
675 case IDE_DMA_TRIM:
676 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
677 ide_issue_trim, ide_dma_cb, s,
678 DMA_DIRECTION_TO_DEVICE);
679 break;
680 }
681 return;
682
683 eot:
684 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
685 bdrv_acct_done(s->bs, &s->acct);
686 }
687 ide_set_inactive(s);
688 if (stay_active) {
689 s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING);
690 }
691 }
692
693 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
694 {
695 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
696 s->io_buffer_index = 0;
697 s->io_buffer_size = 0;
698 s->dma_cmd = dma_cmd;
699
700 switch (dma_cmd) {
701 case IDE_DMA_READ:
702 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
703 BDRV_ACCT_READ);
704 break;
705 case IDE_DMA_WRITE:
706 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
707 BDRV_ACCT_WRITE);
708 break;
709 default:
710 break;
711 }
712
713 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
714 }
715
716 static void ide_sector_write_timer_cb(void *opaque)
717 {
718 IDEState *s = opaque;
719 ide_set_irq(s->bus);
720 }
721
722 static void ide_sector_write_cb(void *opaque, int ret)
723 {
724 IDEState *s = opaque;
725 int n;
726
727 bdrv_acct_done(s->bs, &s->acct);
728
729 s->pio_aiocb = NULL;
730 s->status &= ~BUSY_STAT;
731
732 if (ret != 0) {
733 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
734 return;
735 }
736 }
737
738 n = s->nsector;
739 if (n > s->req_nb_sectors) {
740 n = s->req_nb_sectors;
741 }
742 s->nsector -= n;
743 if (s->nsector == 0) {
744 /* no more sectors to write */
745 ide_transfer_stop(s);
746 } else {
747 int n1 = s->nsector;
748 if (n1 > s->req_nb_sectors) {
749 n1 = s->req_nb_sectors;
750 }
751 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
752 ide_sector_write);
753 }
754 ide_set_sector(s, ide_get_sector(s) + n);
755
756 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
757 /* It seems there is a bug in the Windows 2000 installer HDD
758 IDE driver which fills the disk with empty logs when the
759 IDE write IRQ comes too early. This hack tries to correct
760 that at the expense of slower write performances. Use this
761 option _only_ to install Windows 2000. You must disable it
762 for normal use. */
763 qemu_mod_timer(s->sector_write_timer,
764 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
765 } else {
766 ide_set_irq(s->bus);
767 }
768 }
769
770 void ide_sector_write(IDEState *s)
771 {
772 int64_t sector_num;
773 int n;
774
775 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
776 sector_num = ide_get_sector(s);
777 #if defined(DEBUG_IDE)
778 printf("sector=%" PRId64 "\n", sector_num);
779 #endif
780 n = s->nsector;
781 if (n > s->req_nb_sectors) {
782 n = s->req_nb_sectors;
783 }
784
785 s->iov.iov_base = s->io_buffer;
786 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
787 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
788
789 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
790 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
791 ide_sector_write_cb, s);
792 }
793
794 static void ide_flush_cb(void *opaque, int ret)
795 {
796 IDEState *s = opaque;
797
798 if (ret < 0) {
799 /* XXX: What sector number to set here? */
800 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
801 return;
802 }
803 }
804
805 bdrv_acct_done(s->bs, &s->acct);
806 s->status = READY_STAT | SEEK_STAT;
807 ide_set_irq(s->bus);
808 }
809
810 void ide_flush_cache(IDEState *s)
811 {
812 if (s->bs == NULL) {
813 ide_flush_cb(s, 0);
814 return;
815 }
816
817 s->status |= BUSY_STAT;
818 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
819 bdrv_aio_flush(s->bs, ide_flush_cb, s);
820 }
821
822 static void ide_cfata_metadata_inquiry(IDEState *s)
823 {
824 uint16_t *p;
825 uint32_t spd;
826
827 p = (uint16_t *) s->io_buffer;
828 memset(p, 0, 0x200);
829 spd = ((s->mdata_size - 1) >> 9) + 1;
830
831 put_le16(p + 0, 0x0001); /* Data format revision */
832 put_le16(p + 1, 0x0000); /* Media property: silicon */
833 put_le16(p + 2, s->media_changed); /* Media status */
834 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
835 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
836 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
837 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
838 }
839
840 static void ide_cfata_metadata_read(IDEState *s)
841 {
842 uint16_t *p;
843
844 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
845 s->status = ERR_STAT;
846 s->error = ABRT_ERR;
847 return;
848 }
849
850 p = (uint16_t *) s->io_buffer;
851 memset(p, 0, 0x200);
852
853 put_le16(p + 0, s->media_changed); /* Media status */
854 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
855 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
856 s->nsector << 9), 0x200 - 2));
857 }
858
859 static void ide_cfata_metadata_write(IDEState *s)
860 {
861 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
862 s->status = ERR_STAT;
863 s->error = ABRT_ERR;
864 return;
865 }
866
867 s->media_changed = 0;
868
869 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
870 s->io_buffer + 2,
871 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
872 s->nsector << 9), 0x200 - 2));
873 }
874
875 /* called when the inserted state of the media has changed */
876 static void ide_cd_change_cb(void *opaque, bool load)
877 {
878 IDEState *s = opaque;
879 uint64_t nb_sectors;
880
881 s->tray_open = !load;
882 bdrv_get_geometry(s->bs, &nb_sectors);
883 s->nb_sectors = nb_sectors;
884
885 /*
886 * First indicate to the guest that a CD has been removed. That's
887 * done on the next command the guest sends us.
888 *
889 * Then we set UNIT_ATTENTION, by which the guest will
890 * detect a new CD in the drive. See ide_atapi_cmd() for details.
891 */
892 s->cdrom_changed = 1;
893 s->events.new_media = true;
894 s->events.eject_request = false;
895 ide_set_irq(s->bus);
896 }
897
898 static void ide_cd_eject_request_cb(void *opaque, bool force)
899 {
900 IDEState *s = opaque;
901
902 s->events.eject_request = true;
903 if (force) {
904 s->tray_locked = false;
905 }
906 ide_set_irq(s->bus);
907 }
908
909 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
910 {
911 s->lba48 = lba48;
912
913 /* handle the 'magic' 0 nsector count conversion here. to avoid
914 * fiddling with the rest of the read logic, we just store the
915 * full sector count in ->nsector and ignore ->hob_nsector from now
916 */
917 if (!s->lba48) {
918 if (!s->nsector)
919 s->nsector = 256;
920 } else {
921 if (!s->nsector && !s->hob_nsector)
922 s->nsector = 65536;
923 else {
924 int lo = s->nsector;
925 int hi = s->hob_nsector;
926
927 s->nsector = (hi << 8) | lo;
928 }
929 }
930 }
931
932 static void ide_clear_hob(IDEBus *bus)
933 {
934 /* any write clears HOB high bit of device control register */
935 bus->ifs[0].select &= ~(1 << 7);
936 bus->ifs[1].select &= ~(1 << 7);
937 }
938
939 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
940 {
941 IDEBus *bus = opaque;
942
943 #ifdef DEBUG_IDE
944 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
945 #endif
946
947 addr &= 7;
948
949 /* ignore writes to command block while busy with previous command */
950 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
951 return;
952
953 switch(addr) {
954 case 0:
955 break;
956 case 1:
957 ide_clear_hob(bus);
958 /* NOTE: data is written to the two drives */
959 bus->ifs[0].hob_feature = bus->ifs[0].feature;
960 bus->ifs[1].hob_feature = bus->ifs[1].feature;
961 bus->ifs[0].feature = val;
962 bus->ifs[1].feature = val;
963 break;
964 case 2:
965 ide_clear_hob(bus);
966 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
967 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
968 bus->ifs[0].nsector = val;
969 bus->ifs[1].nsector = val;
970 break;
971 case 3:
972 ide_clear_hob(bus);
973 bus->ifs[0].hob_sector = bus->ifs[0].sector;
974 bus->ifs[1].hob_sector = bus->ifs[1].sector;
975 bus->ifs[0].sector = val;
976 bus->ifs[1].sector = val;
977 break;
978 case 4:
979 ide_clear_hob(bus);
980 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
981 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
982 bus->ifs[0].lcyl = val;
983 bus->ifs[1].lcyl = val;
984 break;
985 case 5:
986 ide_clear_hob(bus);
987 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
988 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
989 bus->ifs[0].hcyl = val;
990 bus->ifs[1].hcyl = val;
991 break;
992 case 6:
993 /* FIXME: HOB readback uses bit 7 */
994 bus->ifs[0].select = (val & ~0x10) | 0xa0;
995 bus->ifs[1].select = (val | 0x10) | 0xa0;
996 /* select drive */
997 bus->unit = (val >> 4) & 1;
998 break;
999 default:
1000 case 7:
1001 /* command */
1002 ide_exec_cmd(bus, val);
1003 break;
1004 }
1005 }
1006
1007 static bool cmd_nop(IDEState *s, uint8_t cmd)
1008 {
1009 return true;
1010 }
1011
1012 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1013 {
1014 switch (s->feature) {
1015 case DSM_TRIM:
1016 if (s->bs) {
1017 ide_sector_start_dma(s, IDE_DMA_TRIM);
1018 return false;
1019 }
1020 break;
1021 }
1022
1023 ide_abort_command(s);
1024 return true;
1025 }
1026
1027 static bool cmd_identify(IDEState *s, uint8_t cmd)
1028 {
1029 if (s->bs && s->drive_kind != IDE_CD) {
1030 if (s->drive_kind != IDE_CFATA) {
1031 ide_identify(s);
1032 } else {
1033 ide_cfata_identify(s);
1034 }
1035 s->status = READY_STAT | SEEK_STAT;
1036 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1037 ide_set_irq(s->bus);
1038 return false;
1039 } else {
1040 if (s->drive_kind == IDE_CD) {
1041 ide_set_signature(s);
1042 }
1043 ide_abort_command(s);
1044 }
1045
1046 return true;
1047 }
1048
1049 static bool cmd_verify(IDEState *s, uint8_t cmd)
1050 {
1051 bool lba48 = (cmd == WIN_VERIFY_EXT);
1052
1053 /* do sector number check ? */
1054 ide_cmd_lba48_transform(s, lba48);
1055
1056 return true;
1057 }
1058
1059 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1060 {
1061 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1062 /* Disable Read and Write Multiple */
1063 s->mult_sectors = 0;
1064 } else if ((s->nsector & 0xff) != 0 &&
1065 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1066 (s->nsector & (s->nsector - 1)) != 0)) {
1067 ide_abort_command(s);
1068 } else {
1069 s->mult_sectors = s->nsector & 0xff;
1070 }
1071
1072 return true;
1073 }
1074
1075 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1076 {
1077 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1078
1079 if (!s->bs || !s->mult_sectors) {
1080 ide_abort_command(s);
1081 return true;
1082 }
1083
1084 ide_cmd_lba48_transform(s, lba48);
1085 s->req_nb_sectors = s->mult_sectors;
1086 ide_sector_read(s);
1087 return false;
1088 }
1089
1090 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1091 {
1092 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1093 int n;
1094
1095 if (!s->bs || !s->mult_sectors) {
1096 ide_abort_command(s);
1097 return true;
1098 }
1099
1100 ide_cmd_lba48_transform(s, lba48);
1101
1102 s->req_nb_sectors = s->mult_sectors;
1103 n = MIN(s->nsector, s->req_nb_sectors);
1104
1105 s->status = SEEK_STAT | READY_STAT;
1106 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1107
1108 s->media_changed = 1;
1109
1110 return false;
1111 }
1112
1113 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1114 {
1115 bool lba48 = (cmd == WIN_READ_EXT);
1116
1117 if (s->drive_kind == IDE_CD) {
1118 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1119 ide_abort_command(s);
1120 return true;
1121 }
1122
1123 if (!s->bs) {
1124 ide_abort_command(s);
1125 return true;
1126 }
1127
1128 ide_cmd_lba48_transform(s, lba48);
1129 s->req_nb_sectors = 1;
1130 ide_sector_read(s);
1131
1132 return false;
1133 }
1134
1135 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1136 {
1137 bool lba48 = (cmd == WIN_WRITE_EXT);
1138
1139 if (!s->bs) {
1140 ide_abort_command(s);
1141 return true;
1142 }
1143
1144 ide_cmd_lba48_transform(s, lba48);
1145
1146 s->req_nb_sectors = 1;
1147 s->status = SEEK_STAT | READY_STAT;
1148 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1149
1150 s->media_changed = 1;
1151
1152 return false;
1153 }
1154
1155 #define HD_OK (1u << IDE_HD)
1156 #define CD_OK (1u << IDE_CD)
1157 #define CFA_OK (1u << IDE_CFATA)
1158 #define HD_CFA_OK (HD_OK | CFA_OK)
1159 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1160
1161 /* Set the Disk Seek Completed status bit during completion */
1162 #define SET_DSC (1u << 8)
1163
1164 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1165 static const struct {
1166 /* Returns true if the completion code should be run */
1167 bool (*handler)(IDEState *s, uint8_t cmd);
1168 int flags;
1169 } ide_cmd_table[0x100] = {
1170 /* NOP not implemented, mandatory for CD */
1171 [CFA_REQ_EXT_ERROR_CODE] = { NULL, CFA_OK },
1172 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
1173 [WIN_DEVICE_RESET] = { NULL, CD_OK },
1174 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1175 [WIN_READ] = { cmd_read_pio, ALL_OK },
1176 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1177 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1178 [WIN_READDMA_EXT] = { NULL, HD_CFA_OK },
1179 [WIN_READ_NATIVE_MAX_EXT] = { NULL, HD_CFA_OK },
1180 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1181 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1182 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1183 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1184 [WIN_WRITEDMA_EXT] = { NULL, HD_CFA_OK },
1185 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1186 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1187 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1188 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1189 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1190 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1191 [WIN_SEEK] = { NULL, HD_CFA_OK },
1192 [CFA_TRANSLATE_SECTOR] = { NULL, CFA_OK },
1193 [WIN_DIAGNOSE] = { NULL, ALL_OK },
1194 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1195 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1196 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1197 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1198 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
1199 [WIN_CHECKPOWERMODE2] = { NULL, ALL_OK },
1200 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
1201 [WIN_PACKETCMD] = { NULL, CD_OK },
1202 [WIN_PIDENTIFY] = { NULL, CD_OK },
1203 [WIN_SMART] = { NULL, HD_CFA_OK },
1204 [CFA_ACCESS_METADATA_STORAGE] = { NULL, CFA_OK },
1205 [CFA_ERASE_SECTORS] = { NULL, CFA_OK },
1206 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1207 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1208 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1209 [WIN_READDMA] = { NULL, HD_CFA_OK },
1210 [WIN_READDMA_ONCE] = { NULL, HD_CFA_OK },
1211 [WIN_WRITEDMA] = { NULL, HD_CFA_OK },
1212 [WIN_WRITEDMA_ONCE] = { NULL, HD_CFA_OK },
1213 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1214 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1215 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1216 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1217 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
1218 [WIN_CHECKPOWERMODE1] = { NULL, ALL_OK },
1219 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
1220 [WIN_FLUSH_CACHE] = { NULL, ALL_OK },
1221 [WIN_FLUSH_CACHE_EXT] = { NULL, HD_CFA_OK },
1222 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1223 [WIN_SETFEATURES] = { NULL, ALL_OK },
1224 [IBM_SENSE_CONDITION] = { NULL, CFA_OK },
1225 [CFA_WEAR_LEVEL] = { NULL, HD_CFA_OK },
1226 [WIN_READ_NATIVE_MAX] = { NULL, ALL_OK },
1227 };
1228
1229 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1230 {
1231 return cmd < ARRAY_SIZE(ide_cmd_table)
1232 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1233 }
1234
1235 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1236 {
1237 uint16_t *identify_data;
1238 IDEState *s;
1239 int n;
1240 int lba48 = 0;
1241
1242 #if defined(DEBUG_IDE)
1243 printf("ide: CMD=%02x\n", val);
1244 #endif
1245 s = idebus_active_if(bus);
1246 /* ignore commands to non existent slave */
1247 if (s != bus->ifs && !s->bs)
1248 return;
1249
1250 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1251 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1252 return;
1253
1254 if (!ide_cmd_permitted(s, val)) {
1255 goto abort_cmd;
1256 }
1257
1258 if (ide_cmd_table[val].handler != NULL) {
1259 bool complete;
1260
1261 s->status = READY_STAT | BUSY_STAT;
1262 s->error = 0;
1263
1264 complete = ide_cmd_table[val].handler(s, val);
1265 if (complete) {
1266 s->status &= ~BUSY_STAT;
1267 assert(!!s->error == !!(s->status & ERR_STAT));
1268
1269 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1270 s->status |= SEEK_STAT;
1271 }
1272
1273 ide_set_irq(s->bus);
1274 }
1275
1276 return;
1277 }
1278
1279 switch(val) {
1280 case WIN_READDMA_EXT:
1281 lba48 = 1;
1282 /* fall through */
1283 case WIN_READDMA:
1284 case WIN_READDMA_ONCE:
1285 if (!s->bs) {
1286 goto abort_cmd;
1287 }
1288 ide_cmd_lba48_transform(s, lba48);
1289 ide_sector_start_dma(s, IDE_DMA_READ);
1290 break;
1291
1292 case WIN_WRITEDMA_EXT:
1293 lba48 = 1;
1294 /* fall through */
1295 case WIN_WRITEDMA:
1296 case WIN_WRITEDMA_ONCE:
1297 if (!s->bs) {
1298 goto abort_cmd;
1299 }
1300 ide_cmd_lba48_transform(s, lba48);
1301 ide_sector_start_dma(s, IDE_DMA_WRITE);
1302 s->media_changed = 1;
1303 break;
1304
1305 case WIN_READ_NATIVE_MAX_EXT:
1306 lba48 = 1;
1307 /* fall through */
1308 case WIN_READ_NATIVE_MAX:
1309 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1310 if (s->nb_sectors == 0) {
1311 goto abort_cmd;
1312 }
1313 ide_cmd_lba48_transform(s, lba48);
1314 ide_set_sector(s, s->nb_sectors - 1);
1315 s->status = READY_STAT | SEEK_STAT;
1316 ide_set_irq(s->bus);
1317 break;
1318
1319 case WIN_CHECKPOWERMODE1:
1320 case WIN_CHECKPOWERMODE2:
1321 s->error = 0;
1322 s->nsector = 0xff; /* device active or idle */
1323 s->status = READY_STAT | SEEK_STAT;
1324 ide_set_irq(s->bus);
1325 break;
1326 case WIN_SETFEATURES:
1327 if (!s->bs)
1328 goto abort_cmd;
1329 /* XXX: valid for CDROM ? */
1330 switch(s->feature) {
1331 case 0x02: /* write cache enable */
1332 bdrv_set_enable_write_cache(s->bs, true);
1333 identify_data = (uint16_t *)s->identify_data;
1334 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1335 s->status = READY_STAT | SEEK_STAT;
1336 ide_set_irq(s->bus);
1337 break;
1338 case 0x82: /* write cache disable */
1339 bdrv_set_enable_write_cache(s->bs, false);
1340 identify_data = (uint16_t *)s->identify_data;
1341 put_le16(identify_data + 85, (1 << 14) | 1);
1342 ide_flush_cache(s);
1343 break;
1344 case 0xcc: /* reverting to power-on defaults enable */
1345 case 0x66: /* reverting to power-on defaults disable */
1346 case 0xaa: /* read look-ahead enable */
1347 case 0x55: /* read look-ahead disable */
1348 case 0x05: /* set advanced power management mode */
1349 case 0x85: /* disable advanced power management mode */
1350 case 0x69: /* NOP */
1351 case 0x67: /* NOP */
1352 case 0x96: /* NOP */
1353 case 0x9a: /* NOP */
1354 case 0x42: /* enable Automatic Acoustic Mode */
1355 case 0xc2: /* disable Automatic Acoustic Mode */
1356 s->status = READY_STAT | SEEK_STAT;
1357 ide_set_irq(s->bus);
1358 break;
1359 case 0x03: { /* set transfer mode */
1360 uint8_t val = s->nsector & 0x07;
1361 identify_data = (uint16_t *)s->identify_data;
1362
1363 switch (s->nsector >> 3) {
1364 case 0x00: /* pio default */
1365 case 0x01: /* pio mode */
1366 put_le16(identify_data + 62,0x07);
1367 put_le16(identify_data + 63,0x07);
1368 put_le16(identify_data + 88,0x3f);
1369 break;
1370 case 0x02: /* sigle word dma mode*/
1371 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1372 put_le16(identify_data + 63,0x07);
1373 put_le16(identify_data + 88,0x3f);
1374 break;
1375 case 0x04: /* mdma mode */
1376 put_le16(identify_data + 62,0x07);
1377 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1378 put_le16(identify_data + 88,0x3f);
1379 break;
1380 case 0x08: /* udma mode */
1381 put_le16(identify_data + 62,0x07);
1382 put_le16(identify_data + 63,0x07);
1383 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
1384 break;
1385 default:
1386 goto abort_cmd;
1387 }
1388 s->status = READY_STAT | SEEK_STAT;
1389 ide_set_irq(s->bus);
1390 break;
1391 }
1392 default:
1393 goto abort_cmd;
1394 }
1395 break;
1396 case WIN_FLUSH_CACHE:
1397 case WIN_FLUSH_CACHE_EXT:
1398 ide_flush_cache(s);
1399 break;
1400 case WIN_SEEK:
1401 /* XXX: Check that seek is within bounds */
1402 s->status = READY_STAT | SEEK_STAT;
1403 ide_set_irq(s->bus);
1404 break;
1405 /* ATAPI commands */
1406 case WIN_PIDENTIFY:
1407 ide_atapi_identify(s);
1408 s->status = READY_STAT | SEEK_STAT;
1409 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1410 ide_set_irq(s->bus);
1411 break;
1412 case WIN_DIAGNOSE:
1413 ide_set_signature(s);
1414 if (s->drive_kind == IDE_CD)
1415 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1416 * devices to return a clear status register
1417 * with READY_STAT *not* set. */
1418 else
1419 s->status = READY_STAT | SEEK_STAT;
1420 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1421 * present.
1422 */
1423 ide_set_irq(s->bus);
1424 break;
1425 case WIN_DEVICE_RESET:
1426 ide_set_signature(s);
1427 s->status = 0x00; /* NOTE: READY is _not_ set */
1428 s->error = 0x01;
1429 break;
1430 case WIN_PACKETCMD:
1431 /* overlapping commands not supported */
1432 if (s->feature & 0x02)
1433 goto abort_cmd;
1434 s->status = READY_STAT | SEEK_STAT;
1435 s->atapi_dma = s->feature & 1;
1436 s->nsector = 1;
1437 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1438 ide_atapi_cmd);
1439 break;
1440 /* CF-ATA commands */
1441 case CFA_REQ_EXT_ERROR_CODE:
1442 s->error = 0x09; /* miscellaneous error */
1443 s->status = READY_STAT | SEEK_STAT;
1444 ide_set_irq(s->bus);
1445 break;
1446 case CFA_ERASE_SECTORS:
1447 case CFA_WEAR_LEVEL:
1448 #if 0
1449 /* This one has the same ID as CFA_WEAR_LEVEL and is required for
1450 Windows 8 to work with AHCI */
1451 case WIN_SECURITY_FREEZE_LOCK:
1452 #endif
1453 if (val == CFA_WEAR_LEVEL)
1454 s->nsector = 0;
1455 if (val == CFA_ERASE_SECTORS)
1456 s->media_changed = 1;
1457 s->error = 0x00;
1458 s->status = READY_STAT | SEEK_STAT;
1459 ide_set_irq(s->bus);
1460 break;
1461 case CFA_TRANSLATE_SECTOR:
1462 s->error = 0x00;
1463 s->status = READY_STAT | SEEK_STAT;
1464 memset(s->io_buffer, 0, 0x200);
1465 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1466 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1467 s->io_buffer[0x02] = s->select; /* Head */
1468 s->io_buffer[0x03] = s->sector; /* Sector */
1469 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1470 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1471 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1472 s->io_buffer[0x13] = 0x00; /* Erase flag */
1473 s->io_buffer[0x18] = 0x00; /* Hot count */
1474 s->io_buffer[0x19] = 0x00; /* Hot count */
1475 s->io_buffer[0x1a] = 0x01; /* Hot count */
1476 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1477 ide_set_irq(s->bus);
1478 break;
1479 case CFA_ACCESS_METADATA_STORAGE:
1480 switch (s->feature) {
1481 case 0x02: /* Inquiry Metadata Storage */
1482 ide_cfata_metadata_inquiry(s);
1483 break;
1484 case 0x03: /* Read Metadata Storage */
1485 ide_cfata_metadata_read(s);
1486 break;
1487 case 0x04: /* Write Metadata Storage */
1488 ide_cfata_metadata_write(s);
1489 break;
1490 default:
1491 goto abort_cmd;
1492 }
1493 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1494 s->status = 0x00; /* NOTE: READY is _not_ set */
1495 ide_set_irq(s->bus);
1496 break;
1497 case IBM_SENSE_CONDITION:
1498 switch (s->feature) {
1499 case 0x01: /* sense temperature in device */
1500 s->nsector = 0x50; /* +20 C */
1501 break;
1502 default:
1503 goto abort_cmd;
1504 }
1505 s->status = READY_STAT | SEEK_STAT;
1506 ide_set_irq(s->bus);
1507 break;
1508
1509 case WIN_SMART:
1510 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
1511 goto abort_cmd;
1512 if (!s->smart_enabled && s->feature != SMART_ENABLE)
1513 goto abort_cmd;
1514 switch (s->feature) {
1515 case SMART_DISABLE:
1516 s->smart_enabled = 0;
1517 s->status = READY_STAT | SEEK_STAT;
1518 ide_set_irq(s->bus);
1519 break;
1520 case SMART_ENABLE:
1521 s->smart_enabled = 1;
1522 s->status = READY_STAT | SEEK_STAT;
1523 ide_set_irq(s->bus);
1524 break;
1525 case SMART_ATTR_AUTOSAVE:
1526 switch (s->sector) {
1527 case 0x00:
1528 s->smart_autosave = 0;
1529 break;
1530 case 0xf1:
1531 s->smart_autosave = 1;
1532 break;
1533 default:
1534 goto abort_cmd;
1535 }
1536 s->status = READY_STAT | SEEK_STAT;
1537 ide_set_irq(s->bus);
1538 break;
1539 case SMART_STATUS:
1540 if (!s->smart_errors) {
1541 s->hcyl = 0xc2;
1542 s->lcyl = 0x4f;
1543 } else {
1544 s->hcyl = 0x2c;
1545 s->lcyl = 0xf4;
1546 }
1547 s->status = READY_STAT | SEEK_STAT;
1548 ide_set_irq(s->bus);
1549 break;
1550 case SMART_READ_THRESH:
1551 memset(s->io_buffer, 0, 0x200);
1552 s->io_buffer[0] = 0x01; /* smart struct version */
1553 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1554 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
1555 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
1556 }
1557 for (n=0; n<511; n++) /* checksum */
1558 s->io_buffer[511] += s->io_buffer[n];
1559 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1560 s->status = READY_STAT | SEEK_STAT;
1561 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1562 ide_set_irq(s->bus);
1563 break;
1564 case SMART_READ_DATA:
1565 memset(s->io_buffer, 0, 0x200);
1566 s->io_buffer[0] = 0x01; /* smart struct version */
1567 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1568 int i;
1569 for(i = 0; i < 11; i++) {
1570 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1571 }
1572 }
1573 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1574 if (s->smart_selftest_count == 0) {
1575 s->io_buffer[363] = 0;
1576 } else {
1577 s->io_buffer[363] =
1578 s->smart_selftest_data[3 +
1579 (s->smart_selftest_count - 1) *
1580 24];
1581 }
1582 s->io_buffer[364] = 0x20;
1583 s->io_buffer[365] = 0x01;
1584 /* offline data collection capacity: execute + self-test*/
1585 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1586 s->io_buffer[368] = 0x03; /* smart capability (1) */
1587 s->io_buffer[369] = 0x00; /* smart capability (2) */
1588 s->io_buffer[370] = 0x01; /* error logging supported */
1589 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1590 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1591 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1592
1593 for (n=0; n<511; n++)
1594 s->io_buffer[511] += s->io_buffer[n];
1595 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1596 s->status = READY_STAT | SEEK_STAT;
1597 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1598 ide_set_irq(s->bus);
1599 break;
1600 case SMART_READ_LOG:
1601 switch (s->sector) {
1602 case 0x01: /* summary smart error log */
1603 memset(s->io_buffer, 0, 0x200);
1604 s->io_buffer[0] = 0x01;
1605 s->io_buffer[1] = 0x00; /* no error entries */
1606 s->io_buffer[452] = s->smart_errors & 0xff;
1607 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1608
1609 for (n=0; n<511; n++)
1610 s->io_buffer[511] += s->io_buffer[n];
1611 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1612 break;
1613 case 0x06: /* smart self test log */
1614 memset(s->io_buffer, 0, 0x200);
1615 s->io_buffer[0] = 0x01;
1616 if (s->smart_selftest_count == 0) {
1617 s->io_buffer[508] = 0;
1618 } else {
1619 s->io_buffer[508] = s->smart_selftest_count;
1620 for (n=2; n<506; n++)
1621 s->io_buffer[n] = s->smart_selftest_data[n];
1622 }
1623 for (n=0; n<511; n++)
1624 s->io_buffer[511] += s->io_buffer[n];
1625 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1626 break;
1627 default:
1628 goto abort_cmd;
1629 }
1630 s->status = READY_STAT | SEEK_STAT;
1631 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1632 ide_set_irq(s->bus);
1633 break;
1634 case SMART_EXECUTE_OFFLINE:
1635 switch (s->sector) {
1636 case 0: /* off-line routine */
1637 case 1: /* short self test */
1638 case 2: /* extended self test */
1639 s->smart_selftest_count++;
1640 if(s->smart_selftest_count > 21)
1641 s->smart_selftest_count = 0;
1642 n = 2 + (s->smart_selftest_count - 1) * 24;
1643 s->smart_selftest_data[n] = s->sector;
1644 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1645 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1646 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1647 s->status = READY_STAT | SEEK_STAT;
1648 ide_set_irq(s->bus);
1649 break;
1650 default:
1651 goto abort_cmd;
1652 }
1653 break;
1654 default:
1655 goto abort_cmd;
1656 }
1657 break;
1658 default:
1659 /* should not be reachable */
1660 abort_cmd:
1661 ide_abort_command(s);
1662 ide_set_irq(s->bus);
1663 break;
1664 }
1665 }
1666
1667 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1668 {
1669 IDEBus *bus = opaque;
1670 IDEState *s = idebus_active_if(bus);
1671 uint32_t addr;
1672 int ret, hob;
1673
1674 addr = addr1 & 7;
1675 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1676 //hob = s->select & (1 << 7);
1677 hob = 0;
1678 switch(addr) {
1679 case 0:
1680 ret = 0xff;
1681 break;
1682 case 1:
1683 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1684 (s != bus->ifs && !s->bs))
1685 ret = 0;
1686 else if (!hob)
1687 ret = s->error;
1688 else
1689 ret = s->hob_feature;
1690 break;
1691 case 2:
1692 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1693 ret = 0;
1694 else if (!hob)
1695 ret = s->nsector & 0xff;
1696 else
1697 ret = s->hob_nsector;
1698 break;
1699 case 3:
1700 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1701 ret = 0;
1702 else if (!hob)
1703 ret = s->sector;
1704 else
1705 ret = s->hob_sector;
1706 break;
1707 case 4:
1708 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1709 ret = 0;
1710 else if (!hob)
1711 ret = s->lcyl;
1712 else
1713 ret = s->hob_lcyl;
1714 break;
1715 case 5:
1716 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1717 ret = 0;
1718 else if (!hob)
1719 ret = s->hcyl;
1720 else
1721 ret = s->hob_hcyl;
1722 break;
1723 case 6:
1724 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1725 ret = 0;
1726 else
1727 ret = s->select;
1728 break;
1729 default:
1730 case 7:
1731 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1732 (s != bus->ifs && !s->bs))
1733 ret = 0;
1734 else
1735 ret = s->status;
1736 qemu_irq_lower(bus->irq);
1737 break;
1738 }
1739 #ifdef DEBUG_IDE
1740 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1741 #endif
1742 return ret;
1743 }
1744
1745 uint32_t ide_status_read(void *opaque, uint32_t addr)
1746 {
1747 IDEBus *bus = opaque;
1748 IDEState *s = idebus_active_if(bus);
1749 int ret;
1750
1751 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1752 (s != bus->ifs && !s->bs))
1753 ret = 0;
1754 else
1755 ret = s->status;
1756 #ifdef DEBUG_IDE
1757 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1758 #endif
1759 return ret;
1760 }
1761
1762 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1763 {
1764 IDEBus *bus = opaque;
1765 IDEState *s;
1766 int i;
1767
1768 #ifdef DEBUG_IDE
1769 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1770 #endif
1771 /* common for both drives */
1772 if (!(bus->cmd & IDE_CMD_RESET) &&
1773 (val & IDE_CMD_RESET)) {
1774 /* reset low to high */
1775 for(i = 0;i < 2; i++) {
1776 s = &bus->ifs[i];
1777 s->status = BUSY_STAT | SEEK_STAT;
1778 s->error = 0x01;
1779 }
1780 } else if ((bus->cmd & IDE_CMD_RESET) &&
1781 !(val & IDE_CMD_RESET)) {
1782 /* high to low */
1783 for(i = 0;i < 2; i++) {
1784 s = &bus->ifs[i];
1785 if (s->drive_kind == IDE_CD)
1786 s->status = 0x00; /* NOTE: READY is _not_ set */
1787 else
1788 s->status = READY_STAT | SEEK_STAT;
1789 ide_set_signature(s);
1790 }
1791 }
1792
1793 bus->cmd = val;
1794 }
1795
1796 /*
1797 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1798 * transferred from the device to the guest), false if it's a PIO in
1799 */
1800 static bool ide_is_pio_out(IDEState *s)
1801 {
1802 if (s->end_transfer_func == ide_sector_write ||
1803 s->end_transfer_func == ide_atapi_cmd) {
1804 return false;
1805 } else if (s->end_transfer_func == ide_sector_read ||
1806 s->end_transfer_func == ide_transfer_stop ||
1807 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1808 s->end_transfer_func == ide_dummy_transfer_stop) {
1809 return true;
1810 }
1811
1812 abort();
1813 }
1814
1815 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1816 {
1817 IDEBus *bus = opaque;
1818 IDEState *s = idebus_active_if(bus);
1819 uint8_t *p;
1820
1821 /* PIO data access allowed only when DRQ bit is set. The result of a write
1822 * during PIO out is indeterminate, just ignore it. */
1823 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1824 return;
1825 }
1826
1827 p = s->data_ptr;
1828 *(uint16_t *)p = le16_to_cpu(val);
1829 p += 2;
1830 s->data_ptr = p;
1831 if (p >= s->data_end)
1832 s->end_transfer_func(s);
1833 }
1834
1835 uint32_t ide_data_readw(void *opaque, uint32_t addr)
1836 {
1837 IDEBus *bus = opaque;
1838 IDEState *s = idebus_active_if(bus);
1839 uint8_t *p;
1840 int ret;
1841
1842 /* PIO data access allowed only when DRQ bit is set. The result of a read
1843 * during PIO in is indeterminate, return 0 and don't move forward. */
1844 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1845 return 0;
1846 }
1847
1848 p = s->data_ptr;
1849 ret = cpu_to_le16(*(uint16_t *)p);
1850 p += 2;
1851 s->data_ptr = p;
1852 if (p >= s->data_end)
1853 s->end_transfer_func(s);
1854 return ret;
1855 }
1856
1857 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1858 {
1859 IDEBus *bus = opaque;
1860 IDEState *s = idebus_active_if(bus);
1861 uint8_t *p;
1862
1863 /* PIO data access allowed only when DRQ bit is set. The result of a write
1864 * during PIO out is indeterminate, just ignore it. */
1865 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1866 return;
1867 }
1868
1869 p = s->data_ptr;
1870 *(uint32_t *)p = le32_to_cpu(val);
1871 p += 4;
1872 s->data_ptr = p;
1873 if (p >= s->data_end)
1874 s->end_transfer_func(s);
1875 }
1876
1877 uint32_t ide_data_readl(void *opaque, uint32_t addr)
1878 {
1879 IDEBus *bus = opaque;
1880 IDEState *s = idebus_active_if(bus);
1881 uint8_t *p;
1882 int ret;
1883
1884 /* PIO data access allowed only when DRQ bit is set. The result of a read
1885 * during PIO in is indeterminate, return 0 and don't move forward. */
1886 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1887 return 0;
1888 }
1889
1890 p = s->data_ptr;
1891 ret = cpu_to_le32(*(uint32_t *)p);
1892 p += 4;
1893 s->data_ptr = p;
1894 if (p >= s->data_end)
1895 s->end_transfer_func(s);
1896 return ret;
1897 }
1898
1899 static void ide_dummy_transfer_stop(IDEState *s)
1900 {
1901 s->data_ptr = s->io_buffer;
1902 s->data_end = s->io_buffer;
1903 s->io_buffer[0] = 0xff;
1904 s->io_buffer[1] = 0xff;
1905 s->io_buffer[2] = 0xff;
1906 s->io_buffer[3] = 0xff;
1907 }
1908
1909 static void ide_reset(IDEState *s)
1910 {
1911 #ifdef DEBUG_IDE
1912 printf("ide: reset\n");
1913 #endif
1914
1915 if (s->pio_aiocb) {
1916 bdrv_aio_cancel(s->pio_aiocb);
1917 s->pio_aiocb = NULL;
1918 }
1919
1920 if (s->drive_kind == IDE_CFATA)
1921 s->mult_sectors = 0;
1922 else
1923 s->mult_sectors = MAX_MULT_SECTORS;
1924 /* ide regs */
1925 s->feature = 0;
1926 s->error = 0;
1927 s->nsector = 0;
1928 s->sector = 0;
1929 s->lcyl = 0;
1930 s->hcyl = 0;
1931
1932 /* lba48 */
1933 s->hob_feature = 0;
1934 s->hob_sector = 0;
1935 s->hob_nsector = 0;
1936 s->hob_lcyl = 0;
1937 s->hob_hcyl = 0;
1938
1939 s->select = 0xa0;
1940 s->status = READY_STAT | SEEK_STAT;
1941
1942 s->lba48 = 0;
1943
1944 /* ATAPI specific */
1945 s->sense_key = 0;
1946 s->asc = 0;
1947 s->cdrom_changed = 0;
1948 s->packet_transfer_size = 0;
1949 s->elementary_transfer_size = 0;
1950 s->io_buffer_index = 0;
1951 s->cd_sector_size = 0;
1952 s->atapi_dma = 0;
1953 s->tray_locked = 0;
1954 s->tray_open = 0;
1955 /* ATA DMA state */
1956 s->io_buffer_size = 0;
1957 s->req_nb_sectors = 0;
1958
1959 ide_set_signature(s);
1960 /* init the transfer handler so that 0xffff is returned on data
1961 accesses */
1962 s->end_transfer_func = ide_dummy_transfer_stop;
1963 ide_dummy_transfer_stop(s);
1964 s->media_changed = 0;
1965 }
1966
1967 void ide_bus_reset(IDEBus *bus)
1968 {
1969 bus->unit = 0;
1970 bus->cmd = 0;
1971 ide_reset(&bus->ifs[0]);
1972 ide_reset(&bus->ifs[1]);
1973 ide_clear_hob(bus);
1974
1975 /* pending async DMA */
1976 if (bus->dma->aiocb) {
1977 #ifdef DEBUG_AIO
1978 printf("aio_cancel\n");
1979 #endif
1980 bdrv_aio_cancel(bus->dma->aiocb);
1981 bus->dma->aiocb = NULL;
1982 }
1983
1984 /* reset dma provider too */
1985 bus->dma->ops->reset(bus->dma);
1986 }
1987
1988 static bool ide_cd_is_tray_open(void *opaque)
1989 {
1990 return ((IDEState *)opaque)->tray_open;
1991 }
1992
1993 static bool ide_cd_is_medium_locked(void *opaque)
1994 {
1995 return ((IDEState *)opaque)->tray_locked;
1996 }
1997
1998 static const BlockDevOps ide_cd_block_ops = {
1999 .change_media_cb = ide_cd_change_cb,
2000 .eject_request_cb = ide_cd_eject_request_cb,
2001 .is_tray_open = ide_cd_is_tray_open,
2002 .is_medium_locked = ide_cd_is_medium_locked,
2003 };
2004
2005 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
2006 const char *version, const char *serial, const char *model,
2007 uint64_t wwn,
2008 uint32_t cylinders, uint32_t heads, uint32_t secs,
2009 int chs_trans)
2010 {
2011 uint64_t nb_sectors;
2012
2013 s->bs = bs;
2014 s->drive_kind = kind;
2015
2016 bdrv_get_geometry(bs, &nb_sectors);
2017 s->cylinders = cylinders;
2018 s->heads = heads;
2019 s->sectors = secs;
2020 s->chs_trans = chs_trans;
2021 s->nb_sectors = nb_sectors;
2022 s->wwn = wwn;
2023 /* The SMART values should be preserved across power cycles
2024 but they aren't. */
2025 s->smart_enabled = 1;
2026 s->smart_autosave = 1;
2027 s->smart_errors = 0;
2028 s->smart_selftest_count = 0;
2029 if (kind == IDE_CD) {
2030 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
2031 bdrv_set_buffer_alignment(bs, 2048);
2032 } else {
2033 if (!bdrv_is_inserted(s->bs)) {
2034 error_report("Device needs media, but drive is empty");
2035 return -1;
2036 }
2037 if (bdrv_is_read_only(bs)) {
2038 error_report("Can't use a read-only drive");
2039 return -1;
2040 }
2041 }
2042 if (serial) {
2043 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2044 } else {
2045 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2046 "QM%05d", s->drive_serial);
2047 }
2048 if (model) {
2049 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2050 } else {
2051 switch (kind) {
2052 case IDE_CD:
2053 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2054 break;
2055 case IDE_CFATA:
2056 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2057 break;
2058 default:
2059 strcpy(s->drive_model_str, "QEMU HARDDISK");
2060 break;
2061 }
2062 }
2063
2064 if (version) {
2065 pstrcpy(s->version, sizeof(s->version), version);
2066 } else {
2067 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
2068 }
2069
2070 ide_reset(s);
2071 bdrv_iostatus_enable(bs);
2072 return 0;
2073 }
2074
2075 static void ide_init1(IDEBus *bus, int unit)
2076 {
2077 static int drive_serial = 1;
2078 IDEState *s = &bus->ifs[unit];
2079
2080 s->bus = bus;
2081 s->unit = unit;
2082 s->drive_serial = drive_serial++;
2083 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2084 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2085 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2086 memset(s->io_buffer, 0, s->io_buffer_total_len);
2087
2088 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
2089 memset(s->smart_selftest_data, 0, 512);
2090
2091 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
2092 ide_sector_write_timer_cb, s);
2093 }
2094
2095 static void ide_nop_start(IDEDMA *dma, IDEState *s,
2096 BlockDriverCompletionFunc *cb)
2097 {
2098 }
2099
2100 static int ide_nop(IDEDMA *dma)
2101 {
2102 return 0;
2103 }
2104
2105 static int ide_nop_int(IDEDMA *dma, int x)
2106 {
2107 return 0;
2108 }
2109
2110 static void ide_nop_restart(void *opaque, int x, RunState y)
2111 {
2112 }
2113
2114 static const IDEDMAOps ide_dma_nop_ops = {
2115 .start_dma = ide_nop_start,
2116 .start_transfer = ide_nop,
2117 .prepare_buf = ide_nop_int,
2118 .rw_buf = ide_nop_int,
2119 .set_unit = ide_nop_int,
2120 .add_status = ide_nop_int,
2121 .set_inactive = ide_nop,
2122 .restart_cb = ide_nop_restart,
2123 .reset = ide_nop,
2124 };
2125
2126 static IDEDMA ide_dma_nop = {
2127 .ops = &ide_dma_nop_ops,
2128 .aiocb = NULL,
2129 };
2130
2131 void ide_init2(IDEBus *bus, qemu_irq irq)
2132 {
2133 int i;
2134
2135 for(i = 0; i < 2; i++) {
2136 ide_init1(bus, i);
2137 ide_reset(&bus->ifs[i]);
2138 }
2139 bus->irq = irq;
2140 bus->dma = &ide_dma_nop;
2141 }
2142
2143 /* TODO convert users to qdev and remove */
2144 void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
2145 DriveInfo *hd1, qemu_irq irq)
2146 {
2147 int i, trans;
2148 DriveInfo *dinfo;
2149 uint32_t cyls, heads, secs;
2150
2151 for(i = 0; i < 2; i++) {
2152 dinfo = i == 0 ? hd0 : hd1;
2153 ide_init1(bus, i);
2154 if (dinfo) {
2155 cyls = dinfo->cyls;
2156 heads = dinfo->heads;
2157 secs = dinfo->secs;
2158 trans = dinfo->trans;
2159 if (!cyls && !heads && !secs) {
2160 hd_geometry_guess(dinfo->bdrv, &cyls, &heads, &secs, &trans);
2161 } else if (trans == BIOS_ATA_TRANSLATION_AUTO) {
2162 trans = hd_bios_chs_auto_trans(cyls, heads, secs);
2163 }
2164 if (cyls < 1 || cyls > 65535) {
2165 error_report("cyls must be between 1 and 65535");
2166 exit(1);
2167 }
2168 if (heads < 1 || heads > 16) {
2169 error_report("heads must be between 1 and 16");
2170 exit(1);
2171 }
2172 if (secs < 1 || secs > 255) {
2173 error_report("secs must be between 1 and 255");
2174 exit(1);
2175 }
2176 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
2177 dinfo->media_cd ? IDE_CD : IDE_HD,
2178 NULL, dinfo->serial, NULL, 0,
2179 cyls, heads, secs, trans) < 0) {
2180 error_report("Can't set up IDE drive %s", dinfo->id);
2181 exit(1);
2182 }
2183 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
2184 } else {
2185 ide_reset(&bus->ifs[i]);
2186 }
2187 }
2188 bus->irq = irq;
2189 bus->dma = &ide_dma_nop;
2190 }
2191
2192 static const MemoryRegionPortio ide_portio_list[] = {
2193 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2194 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2195 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2196 PORTIO_END_OF_LIST(),
2197 };
2198
2199 static const MemoryRegionPortio ide_portio2_list[] = {
2200 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2201 PORTIO_END_OF_LIST(),
2202 };
2203
2204 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2205 {
2206 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2207 bridge has been setup properly to always register with ISA. */
2208 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2209
2210 if (iobase2) {
2211 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2212 }
2213 }
2214
2215 static bool is_identify_set(void *opaque, int version_id)
2216 {
2217 IDEState *s = opaque;
2218
2219 return s->identify_set != 0;
2220 }
2221
2222 static EndTransferFunc* transfer_end_table[] = {
2223 ide_sector_read,
2224 ide_sector_write,
2225 ide_transfer_stop,
2226 ide_atapi_cmd_reply_end,
2227 ide_atapi_cmd,
2228 ide_dummy_transfer_stop,
2229 };
2230
2231 static int transfer_end_table_idx(EndTransferFunc *fn)
2232 {
2233 int i;
2234
2235 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2236 if (transfer_end_table[i] == fn)
2237 return i;
2238
2239 return -1;
2240 }
2241
2242 static int ide_drive_post_load(void *opaque, int version_id)
2243 {
2244 IDEState *s = opaque;
2245
2246 if (s->identify_set) {
2247 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2248 }
2249 return 0;
2250 }
2251
2252 static int ide_drive_pio_post_load(void *opaque, int version_id)
2253 {
2254 IDEState *s = opaque;
2255
2256 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2257 return -EINVAL;
2258 }
2259 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2260 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2261 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2262
2263 return 0;
2264 }
2265
2266 static void ide_drive_pio_pre_save(void *opaque)
2267 {
2268 IDEState *s = opaque;
2269 int idx;
2270
2271 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2272 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2273
2274 idx = transfer_end_table_idx(s->end_transfer_func);
2275 if (idx == -1) {
2276 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2277 __func__);
2278 s->end_transfer_fn_idx = 2;
2279 } else {
2280 s->end_transfer_fn_idx = idx;
2281 }
2282 }
2283
2284 static bool ide_drive_pio_state_needed(void *opaque)
2285 {
2286 IDEState *s = opaque;
2287
2288 return ((s->status & DRQ_STAT) != 0)
2289 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
2290 }
2291
2292 static bool ide_tray_state_needed(void *opaque)
2293 {
2294 IDEState *s = opaque;
2295
2296 return s->tray_open || s->tray_locked;
2297 }
2298
2299 static bool ide_atapi_gesn_needed(void *opaque)
2300 {
2301 IDEState *s = opaque;
2302
2303 return s->events.new_media || s->events.eject_request;
2304 }
2305
2306 static bool ide_error_needed(void *opaque)
2307 {
2308 IDEBus *bus = opaque;
2309
2310 return (bus->error_status != 0);
2311 }
2312
2313 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2314 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2315 .name ="ide_drive/atapi/gesn_state",
2316 .version_id = 1,
2317 .minimum_version_id = 1,
2318 .minimum_version_id_old = 1,
2319 .fields = (VMStateField []) {
2320 VMSTATE_BOOL(events.new_media, IDEState),
2321 VMSTATE_BOOL(events.eject_request, IDEState),
2322 VMSTATE_END_OF_LIST()
2323 }
2324 };
2325
2326 static const VMStateDescription vmstate_ide_tray_state = {
2327 .name = "ide_drive/tray_state",
2328 .version_id = 1,
2329 .minimum_version_id = 1,
2330 .minimum_version_id_old = 1,
2331 .fields = (VMStateField[]) {
2332 VMSTATE_BOOL(tray_open, IDEState),
2333 VMSTATE_BOOL(tray_locked, IDEState),
2334 VMSTATE_END_OF_LIST()
2335 }
2336 };
2337
2338 static const VMStateDescription vmstate_ide_drive_pio_state = {
2339 .name = "ide_drive/pio_state",
2340 .version_id = 1,
2341 .minimum_version_id = 1,
2342 .minimum_version_id_old = 1,
2343 .pre_save = ide_drive_pio_pre_save,
2344 .post_load = ide_drive_pio_post_load,
2345 .fields = (VMStateField []) {
2346 VMSTATE_INT32(req_nb_sectors, IDEState),
2347 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2348 vmstate_info_uint8, uint8_t),
2349 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2350 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2351 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2352 VMSTATE_INT32(elementary_transfer_size, IDEState),
2353 VMSTATE_INT32(packet_transfer_size, IDEState),
2354 VMSTATE_END_OF_LIST()
2355 }
2356 };
2357
2358 const VMStateDescription vmstate_ide_drive = {
2359 .name = "ide_drive",
2360 .version_id = 3,
2361 .minimum_version_id = 0,
2362 .minimum_version_id_old = 0,
2363 .post_load = ide_drive_post_load,
2364 .fields = (VMStateField []) {
2365 VMSTATE_INT32(mult_sectors, IDEState),
2366 VMSTATE_INT32(identify_set, IDEState),
2367 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2368 VMSTATE_UINT8(feature, IDEState),
2369 VMSTATE_UINT8(error, IDEState),
2370 VMSTATE_UINT32(nsector, IDEState),
2371 VMSTATE_UINT8(sector, IDEState),
2372 VMSTATE_UINT8(lcyl, IDEState),
2373 VMSTATE_UINT8(hcyl, IDEState),
2374 VMSTATE_UINT8(hob_feature, IDEState),
2375 VMSTATE_UINT8(hob_sector, IDEState),
2376 VMSTATE_UINT8(hob_nsector, IDEState),
2377 VMSTATE_UINT8(hob_lcyl, IDEState),
2378 VMSTATE_UINT8(hob_hcyl, IDEState),
2379 VMSTATE_UINT8(select, IDEState),
2380 VMSTATE_UINT8(status, IDEState),
2381 VMSTATE_UINT8(lba48, IDEState),
2382 VMSTATE_UINT8(sense_key, IDEState),
2383 VMSTATE_UINT8(asc, IDEState),
2384 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2385 VMSTATE_END_OF_LIST()
2386 },
2387 .subsections = (VMStateSubsection []) {
2388 {
2389 .vmsd = &vmstate_ide_drive_pio_state,
2390 .needed = ide_drive_pio_state_needed,
2391 }, {
2392 .vmsd = &vmstate_ide_tray_state,
2393 .needed = ide_tray_state_needed,
2394 }, {
2395 .vmsd = &vmstate_ide_atapi_gesn_state,
2396 .needed = ide_atapi_gesn_needed,
2397 }, {
2398 /* empty */
2399 }
2400 }
2401 };
2402
2403 static const VMStateDescription vmstate_ide_error_status = {
2404 .name ="ide_bus/error",
2405 .version_id = 1,
2406 .minimum_version_id = 1,
2407 .minimum_version_id_old = 1,
2408 .fields = (VMStateField []) {
2409 VMSTATE_INT32(error_status, IDEBus),
2410 VMSTATE_END_OF_LIST()
2411 }
2412 };
2413
2414 const VMStateDescription vmstate_ide_bus = {
2415 .name = "ide_bus",
2416 .version_id = 1,
2417 .minimum_version_id = 1,
2418 .minimum_version_id_old = 1,
2419 .fields = (VMStateField []) {
2420 VMSTATE_UINT8(cmd, IDEBus),
2421 VMSTATE_UINT8(unit, IDEBus),
2422 VMSTATE_END_OF_LIST()
2423 },
2424 .subsections = (VMStateSubsection []) {
2425 {
2426 .vmsd = &vmstate_ide_error_status,
2427 .needed = ide_error_needed,
2428 }, {
2429 /* empty */
2430 }
2431 }
2432 };
2433
2434 void ide_drive_get(DriveInfo **hd, int max_bus)
2435 {
2436 int i;
2437
2438 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2439 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2440 exit(1);
2441 }
2442
2443 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2444 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2445 }
2446 }
QEmu