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Update version for 0.14.0-rc0
[qemu.git] / hw / pci.c
blobd5bbba975b0a04132dd10b98bf2c4943f5c749ad
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 /* Update interrupt status bit in config space on interrupt
130 * state change. */
131 static void pci_update_irq_status(PCIDevice *dev)
132 {
133 if (dev->irq_state) {
134 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
135 } else {
136 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
137 }
138 }
139
140 void pci_device_deassert_intx(PCIDevice *dev)
141 {
142 int i;
143 for (i = 0; i < PCI_NUM_PINS; ++i) {
144 qemu_set_irq(dev->irq[i], 0);
145 }
146 }
147
148 /*
149 * This function is called on #RST and FLR.
150 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
151 */
152 void pci_device_reset(PCIDevice *dev)
153 {
154 int r;
155 /* TODO: call the below unconditionally once all pci devices
156 * are qdevified */
157 if (dev->qdev.info) {
158 qdev_reset_all(&dev->qdev);
159 }
160
161 dev->irq_state = 0;
162 pci_update_irq_status(dev);
163 pci_device_deassert_intx(dev);
164 /* Clear all writeable bits */
165 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
166 pci_get_word(dev->wmask + PCI_COMMAND) |
167 pci_get_word(dev->w1cmask + PCI_COMMAND));
168 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
169 pci_get_word(dev->wmask + PCI_STATUS) |
170 pci_get_word(dev->w1cmask + PCI_STATUS));
171 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
172 dev->config[PCI_INTERRUPT_LINE] = 0x0;
173 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
174 PCIIORegion *region = &dev->io_regions[r];
175 if (!region->size) {
176 continue;
177 }
178
179 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
180 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
181 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
182 } else {
183 pci_set_long(dev->config + pci_bar(dev, r), region->type);
184 }
185 }
186 pci_update_mappings(dev);
187 }
188
189 /*
190 * Trigger pci bus reset under a given bus.
191 * To be called on RST# assert.
192 */
193 void pci_bus_reset(PCIBus *bus)
194 {
195 int i;
196
197 for (i = 0; i < bus->nirq; i++) {
198 bus->irq_count[i] = 0;
199 }
200 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
201 if (bus->devices[i]) {
202 pci_device_reset(bus->devices[i]);
203 }
204 }
205 }
206
207 static int pcibus_reset(BusState *qbus)
208 {
209 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
210
211 /* topology traverse is done by pci_bus_reset().
212 Tell qbus/qdev walker not to traverse the tree */
213 return 1;
214 }
215
216 static void pci_host_bus_register(int domain, PCIBus *bus)
217 {
218 struct PCIHostBus *host;
219 host = qemu_mallocz(sizeof(*host));
220 host->domain = domain;
221 host->bus = bus;
222 QLIST_INSERT_HEAD(&host_buses, host, next);
223 }
224
225 PCIBus *pci_find_root_bus(int domain)
226 {
227 struct PCIHostBus *host;
228
229 QLIST_FOREACH(host, &host_buses, next) {
230 if (host->domain == domain) {
231 return host->bus;
232 }
233 }
234
235 return NULL;
236 }
237
238 int pci_find_domain(const PCIBus *bus)
239 {
240 PCIDevice *d;
241 struct PCIHostBus *host;
242
243 /* obtain root bus */
244 while ((d = bus->parent_dev) != NULL) {
245 bus = d->bus;
246 }
247
248 QLIST_FOREACH(host, &host_buses, next) {
249 if (host->bus == bus) {
250 return host->domain;
251 }
252 }
253
254 abort(); /* should not be reached */
255 return -1;
256 }
257
258 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
259 const char *name, int devfn_min)
260 {
261 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
262 assert(PCI_FUNC(devfn_min) == 0);
263 bus->devfn_min = devfn_min;
264
265 /* host bridge */
266 QLIST_INIT(&bus->child);
267 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
268
269 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
270 }
271
272 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
273 {
274 PCIBus *bus;
275
276 bus = qemu_mallocz(sizeof(*bus));
277 bus->qbus.qdev_allocated = 1;
278 pci_bus_new_inplace(bus, parent, name, devfn_min);
279 return bus;
280 }
281
282 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
283 void *irq_opaque, int nirq)
284 {
285 bus->set_irq = set_irq;
286 bus->map_irq = map_irq;
287 bus->irq_opaque = irq_opaque;
288 bus->nirq = nirq;
289 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
290 }
291
292 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
293 {
294 bus->qbus.allow_hotplug = 1;
295 bus->hotplug = hotplug;
296 bus->hotplug_qdev = qdev;
297 }
298
299 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
300 {
301 bus->mem_base = base;
302 }
303
304 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
305 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
306 void *irq_opaque, int devfn_min, int nirq)
307 {
308 PCIBus *bus;
309
310 bus = pci_bus_new(parent, name, devfn_min);
311 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
312 return bus;
313 }
314
315 int pci_bus_num(PCIBus *s)
316 {
317 if (!s->parent_dev)
318 return 0; /* pci host bridge */
319 return s->parent_dev->config[PCI_SECONDARY_BUS];
320 }
321
322 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
323 {
324 PCIDevice *s = container_of(pv, PCIDevice, config);
325 uint8_t *config;
326 int i;
327
328 assert(size == pci_config_size(s));
329 config = qemu_malloc(size);
330
331 qemu_get_buffer(f, config, size);
332 for (i = 0; i < size; ++i) {
333 if ((config[i] ^ s->config[i]) &
334 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
335 qemu_free(config);
336 return -EINVAL;
337 }
338 }
339 memcpy(s->config, config, size);
340
341 pci_update_mappings(s);
342
343 qemu_free(config);
344 return 0;
345 }
346
347 /* just put buffer */
348 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
349 {
350 const uint8_t **v = pv;
351 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
352 qemu_put_buffer(f, *v, size);
353 }
354
355 static VMStateInfo vmstate_info_pci_config = {
356 .name = "pci config",
357 .get = get_pci_config_device,
358 .put = put_pci_config_device,
359 };
360
361 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
362 {
363 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
364 uint32_t irq_state[PCI_NUM_PINS];
365 int i;
366 for (i = 0; i < PCI_NUM_PINS; ++i) {
367 irq_state[i] = qemu_get_be32(f);
368 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
369 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
370 irq_state[i]);
371 return -EINVAL;
372 }
373 }
374
375 for (i = 0; i < PCI_NUM_PINS; ++i) {
376 pci_set_irq_state(s, i, irq_state[i]);
377 }
378
379 return 0;
380 }
381
382 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
383 {
384 int i;
385 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
386
387 for (i = 0; i < PCI_NUM_PINS; ++i) {
388 qemu_put_be32(f, pci_irq_state(s, i));
389 }
390 }
391
392 static VMStateInfo vmstate_info_pci_irq_state = {
393 .name = "pci irq state",
394 .get = get_pci_irq_state,
395 .put = put_pci_irq_state,
396 };
397
398 const VMStateDescription vmstate_pci_device = {
399 .name = "PCIDevice",
400 .version_id = 2,
401 .minimum_version_id = 1,
402 .minimum_version_id_old = 1,
403 .fields = (VMStateField []) {
404 VMSTATE_INT32_LE(version_id, PCIDevice),
405 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
406 vmstate_info_pci_config,
407 PCI_CONFIG_SPACE_SIZE),
408 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
409 vmstate_info_pci_irq_state,
410 PCI_NUM_PINS * sizeof(int32_t)),
411 VMSTATE_END_OF_LIST()
412 }
413 };
414
415 const VMStateDescription vmstate_pcie_device = {
416 .name = "PCIDevice",
417 .version_id = 2,
418 .minimum_version_id = 1,
419 .minimum_version_id_old = 1,
420 .fields = (VMStateField []) {
421 VMSTATE_INT32_LE(version_id, PCIDevice),
422 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
423 vmstate_info_pci_config,
424 PCIE_CONFIG_SPACE_SIZE),
425 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
426 vmstate_info_pci_irq_state,
427 PCI_NUM_PINS * sizeof(int32_t)),
428 VMSTATE_END_OF_LIST()
429 }
430 };
431
432 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
433 {
434 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
435 }
436
437 void pci_device_save(PCIDevice *s, QEMUFile *f)
438 {
439 /* Clear interrupt status bit: it is implicit
440 * in irq_state which we are saving.
441 * This makes us compatible with old devices
442 * which never set or clear this bit. */
443 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
444 vmstate_save_state(f, pci_get_vmstate(s), s);
445 /* Restore the interrupt status bit. */
446 pci_update_irq_status(s);
447 }
448
449 int pci_device_load(PCIDevice *s, QEMUFile *f)
450 {
451 int ret;
452 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
453 /* Restore the interrupt status bit. */
454 pci_update_irq_status(s);
455 return ret;
456 }
457
458 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
459 {
460 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
461 pci_default_sub_vendor_id);
462 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
463 pci_default_sub_device_id);
464 }
465
466 /*
467 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
468 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
469 */
470 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
471 unsigned int *slotp, unsigned int *funcp)
472 {
473 const char *p;
474 char *e;
475 unsigned long val;
476 unsigned long dom = 0, bus = 0;
477 unsigned int slot = 0;
478 unsigned int func = 0;
479
480 p = addr;
481 val = strtoul(p, &e, 16);
482 if (e == p)
483 return -1;
484 if (*e == ':') {
485 bus = val;
486 p = e + 1;
487 val = strtoul(p, &e, 16);
488 if (e == p)
489 return -1;
490 if (*e == ':') {
491 dom = bus;
492 bus = val;
493 p = e + 1;
494 val = strtoul(p, &e, 16);
495 if (e == p)
496 return -1;
497 }
498 }
499
500 slot = val;
501
502 if (funcp != NULL) {
503 if (*e != '.')
504 return -1;
505
506 p = e + 1;
507 val = strtoul(p, &e, 16);
508 if (e == p)
509 return -1;
510
511 func = val;
512 }
513
514 /* if funcp == NULL func is 0 */
515 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
516 return -1;
517
518 if (*e)
519 return -1;
520
521 /* Note: QEMU doesn't implement domains other than 0 */
522 if (!pci_find_bus(pci_find_root_bus(dom), bus))
523 return -1;
524
525 *domp = dom;
526 *busp = bus;
527 *slotp = slot;
528 if (funcp != NULL)
529 *funcp = func;
530 return 0;
531 }
532
533 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
534 unsigned *slotp)
535 {
536 /* strip legacy tag */
537 if (!strncmp(addr, "pci_addr=", 9)) {
538 addr += 9;
539 }
540 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
541 monitor_printf(mon, "Invalid pci address\n");
542 return -1;
543 }
544 return 0;
545 }
546
547 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
548 {
549 int dom, bus;
550 unsigned slot;
551
552 if (!devaddr) {
553 *devfnp = -1;
554 return pci_find_bus(pci_find_root_bus(0), 0);
555 }
556
557 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
558 return NULL;
559 }
560
561 *devfnp = slot << 3;
562 return pci_find_bus(pci_find_root_bus(dom), bus);
563 }
564
565 static void pci_init_cmask(PCIDevice *dev)
566 {
567 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
568 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
569 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
570 dev->cmask[PCI_REVISION_ID] = 0xff;
571 dev->cmask[PCI_CLASS_PROG] = 0xff;
572 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
573 dev->cmask[PCI_HEADER_TYPE] = 0xff;
574 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
575 }
576
577 static void pci_init_wmask(PCIDevice *dev)
578 {
579 int config_size = pci_config_size(dev);
580
581 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
582 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
583 pci_set_word(dev->wmask + PCI_COMMAND,
584 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
585 PCI_COMMAND_INTX_DISABLE);
586 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
587 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
588 }
589
590 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
591 config_size - PCI_CONFIG_HEADER_SIZE);
592 }
593
594 static void pci_init_w1cmask(PCIDevice *dev)
595 {
596 /*
597 * Note: It's okay to set w1cmask even for readonly bits as
598 * long as their value is hardwired to 0.
599 */
600 pci_set_word(dev->w1cmask + PCI_STATUS,
601 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
602 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
603 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
604 }
605
606 static void pci_init_wmask_bridge(PCIDevice *d)
607 {
608 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
609 PCI_SEC_LETENCY_TIMER */
610 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
611
612 /* base and limit */
613 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
614 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
615 pci_set_word(d->wmask + PCI_MEMORY_BASE,
616 PCI_MEMORY_RANGE_MASK & 0xffff);
617 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
618 PCI_MEMORY_RANGE_MASK & 0xffff);
619 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
620 PCI_PREF_RANGE_MASK & 0xffff);
621 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
622 PCI_PREF_RANGE_MASK & 0xffff);
623
624 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
625 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
626
627 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
628 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
629 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
630 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
631 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
632 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
633 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
634 PCI_BRIDGE_CTL_PARITY |
635 PCI_BRIDGE_CTL_SERR |
636 PCI_BRIDGE_CTL_ISA |
637 PCI_BRIDGE_CTL_VGA |
638 PCI_BRIDGE_CTL_VGA_16BIT |
639 PCI_BRIDGE_CTL_MASTER_ABORT |
640 PCI_BRIDGE_CTL_BUS_RESET |
641 PCI_BRIDGE_CTL_FAST_BACK |
642 PCI_BRIDGE_CTL_DISCARD |
643 PCI_BRIDGE_CTL_SEC_DISCARD |
644 PCI_BRIDGE_CTL_DISCARD_SERR);
645 /* Below does not do anything as we never set this bit, put here for
646 * completeness. */
647 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
648 PCI_BRIDGE_CTL_DISCARD_STATUS);
649 }
650
651 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
652 {
653 uint8_t slot = PCI_SLOT(dev->devfn);
654 uint8_t func;
655
656 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
657 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
658 }
659
660 /*
661 * multifunction bit is interpreted in two ways as follows.
662 * - all functions must set the bit to 1.
663 * Example: Intel X53
664 * - function 0 must set the bit, but the rest function (> 0)
665 * is allowed to leave the bit to 0.
666 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
667 *
668 * So OS (at least Linux) checks the bit of only function 0,
669 * and doesn't see the bit of function > 0.
670 *
671 * The below check allows both interpretation.
672 */
673 if (PCI_FUNC(dev->devfn)) {
674 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
675 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
676 /* function 0 should set multifunction bit */
677 error_report("PCI: single function device can't be populated "
678 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
679 return -1;
680 }
681 return 0;
682 }
683
684 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
685 return 0;
686 }
687 /* function 0 indicates single function, so function > 0 must be NULL */
688 for (func = 1; func < PCI_FUNC_MAX; ++func) {
689 if (bus->devices[PCI_DEVFN(slot, func)]) {
690 error_report("PCI: %x.0 indicates single function, "
691 "but %x.%x is already populated.",
692 slot, slot, func);
693 return -1;
694 }
695 }
696 return 0;
697 }
698
699 static void pci_config_alloc(PCIDevice *pci_dev)
700 {
701 int config_size = pci_config_size(pci_dev);
702
703 pci_dev->config = qemu_mallocz(config_size);
704 pci_dev->cmask = qemu_mallocz(config_size);
705 pci_dev->wmask = qemu_mallocz(config_size);
706 pci_dev->w1cmask = qemu_mallocz(config_size);
707 pci_dev->used = qemu_mallocz(config_size);
708 }
709
710 static void pci_config_free(PCIDevice *pci_dev)
711 {
712 qemu_free(pci_dev->config);
713 qemu_free(pci_dev->cmask);
714 qemu_free(pci_dev->wmask);
715 qemu_free(pci_dev->w1cmask);
716 qemu_free(pci_dev->used);
717 }
718
719 /* -1 for devfn means auto assign */
720 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
721 const char *name, int devfn,
722 PCIConfigReadFunc *config_read,
723 PCIConfigWriteFunc *config_write,
724 bool is_bridge)
725 {
726 if (devfn < 0) {
727 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
728 devfn += PCI_FUNC_MAX) {
729 if (!bus->devices[devfn])
730 goto found;
731 }
732 error_report("PCI: no slot/function available for %s, all in use", name);
733 return NULL;
734 found: ;
735 } else if (bus->devices[devfn]) {
736 error_report("PCI: slot %d function %d not available for %s, in use by %s",
737 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
738 return NULL;
739 }
740 pci_dev->bus = bus;
741 pci_dev->devfn = devfn;
742 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
743 pci_dev->irq_state = 0;
744 pci_config_alloc(pci_dev);
745
746 if (!is_bridge) {
747 pci_set_default_subsystem_id(pci_dev);
748 }
749 pci_init_cmask(pci_dev);
750 pci_init_wmask(pci_dev);
751 pci_init_w1cmask(pci_dev);
752 if (is_bridge) {
753 pci_init_wmask_bridge(pci_dev);
754 }
755 if (pci_init_multifunction(bus, pci_dev)) {
756 pci_config_free(pci_dev);
757 return NULL;
758 }
759
760 if (!config_read)
761 config_read = pci_default_read_config;
762 if (!config_write)
763 config_write = pci_default_write_config;
764 pci_dev->config_read = config_read;
765 pci_dev->config_write = config_write;
766 bus->devices[devfn] = pci_dev;
767 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
768 pci_dev->version_id = 2; /* Current pci device vmstate version */
769 return pci_dev;
770 }
771
772 static void do_pci_unregister_device(PCIDevice *pci_dev)
773 {
774 qemu_free_irqs(pci_dev->irq);
775 pci_dev->bus->devices[pci_dev->devfn] = NULL;
776 pci_config_free(pci_dev);
777 }
778
779 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
780 int instance_size, int devfn,
781 PCIConfigReadFunc *config_read,
782 PCIConfigWriteFunc *config_write)
783 {
784 PCIDevice *pci_dev;
785
786 pci_dev = qemu_mallocz(instance_size);
787 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
788 config_read, config_write,
789 PCI_HEADER_TYPE_NORMAL);
790 if (pci_dev == NULL) {
791 hw_error("PCI: can't register device\n");
792 }
793 return pci_dev;
794 }
795
796 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
797 target_phys_addr_t addr)
798 {
799 return addr + bus->mem_base;
800 }
801
802 static void pci_unregister_io_regions(PCIDevice *pci_dev)
803 {
804 PCIIORegion *r;
805 int i;
806
807 for(i = 0; i < PCI_NUM_REGIONS; i++) {
808 r = &pci_dev->io_regions[i];
809 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
810 continue;
811 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
812 isa_unassign_ioport(r->addr, r->filtered_size);
813 } else {
814 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
815 r->addr),
816 r->filtered_size,
817 IO_MEM_UNASSIGNED);
818 }
819 }
820 }
821
822 static int pci_unregister_device(DeviceState *dev)
823 {
824 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
825 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
826 int ret = 0;
827
828 if (info->exit)
829 ret = info->exit(pci_dev);
830 if (ret)
831 return ret;
832
833 pci_unregister_io_regions(pci_dev);
834 pci_del_option_rom(pci_dev);
835 qemu_free(pci_dev->romfile);
836 do_pci_unregister_device(pci_dev);
837 return 0;
838 }
839
840 void pci_register_bar(PCIDevice *pci_dev, int region_num,
841 pcibus_t size, uint8_t type,
842 PCIMapIORegionFunc *map_func)
843 {
844 PCIIORegion *r;
845 uint32_t addr;
846 uint64_t wmask;
847
848 assert(region_num >= 0);
849 assert(region_num < PCI_NUM_REGIONS);
850 if (size & (size-1)) {
851 fprintf(stderr, "ERROR: PCI region size must be pow2 "
852 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
853 exit(1);
854 }
855
856 r = &pci_dev->io_regions[region_num];
857 r->addr = PCI_BAR_UNMAPPED;
858 r->size = size;
859 r->filtered_size = size;
860 r->type = type;
861 r->map_func = map_func;
862
863 wmask = ~(size - 1);
864 addr = pci_bar(pci_dev, region_num);
865 if (region_num == PCI_ROM_SLOT) {
866 /* ROM enable bit is writeable */
867 wmask |= PCI_ROM_ADDRESS_ENABLE;
868 }
869 pci_set_long(pci_dev->config + addr, type);
870 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
871 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
872 pci_set_quad(pci_dev->wmask + addr, wmask);
873 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
874 } else {
875 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
876 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
877 }
878 }
879
880 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
881 uint8_t type)
882 {
883 pcibus_t base = *addr;
884 pcibus_t limit = *addr + *size - 1;
885 PCIDevice *br;
886
887 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
888 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
889
890 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
891 if (!(cmd & PCI_COMMAND_IO)) {
892 goto no_map;
893 }
894 } else {
895 if (!(cmd & PCI_COMMAND_MEMORY)) {
896 goto no_map;
897 }
898 }
899
900 base = MAX(base, pci_bridge_get_base(br, type));
901 limit = MIN(limit, pci_bridge_get_limit(br, type));
902 }
903
904 if (base > limit) {
905 goto no_map;
906 }
907 *addr = base;
908 *size = limit - base + 1;
909 return;
910 no_map:
911 *addr = PCI_BAR_UNMAPPED;
912 *size = 0;
913 }
914
915 static pcibus_t pci_bar_address(PCIDevice *d,
916 int reg, uint8_t type, pcibus_t size)
917 {
918 pcibus_t new_addr, last_addr;
919 int bar = pci_bar(d, reg);
920 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
921
922 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
923 if (!(cmd & PCI_COMMAND_IO)) {
924 return PCI_BAR_UNMAPPED;
925 }
926 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
927 last_addr = new_addr + size - 1;
928 /* NOTE: we have only 64K ioports on PC */
929 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
930 return PCI_BAR_UNMAPPED;
931 }
932 return new_addr;
933 }
934
935 if (!(cmd & PCI_COMMAND_MEMORY)) {
936 return PCI_BAR_UNMAPPED;
937 }
938 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
939 new_addr = pci_get_quad(d->config + bar);
940 } else {
941 new_addr = pci_get_long(d->config + bar);
942 }
943 /* the ROM slot has a specific enable bit */
944 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
945 return PCI_BAR_UNMAPPED;
946 }
947 new_addr &= ~(size - 1);
948 last_addr = new_addr + size - 1;
949 /* NOTE: we do not support wrapping */
950 /* XXX: as we cannot support really dynamic
951 mappings, we handle specific values as invalid
952 mappings. */
953 if (last_addr <= new_addr || new_addr == 0 ||
954 last_addr == PCI_BAR_UNMAPPED) {
955 return PCI_BAR_UNMAPPED;
956 }
957
958 /* Now pcibus_t is 64bit.
959 * Check if 32 bit BAR wraps around explicitly.
960 * Without this, PC ide doesn't work well.
961 * TODO: remove this work around.
962 */
963 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
964 return PCI_BAR_UNMAPPED;
965 }
966
967 /*
968 * OS is allowed to set BAR beyond its addressable
969 * bits. For example, 32 bit OS can set 64bit bar
970 * to >4G. Check it. TODO: we might need to support
971 * it in the future for e.g. PAE.
972 */
973 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
974 return PCI_BAR_UNMAPPED;
975 }
976
977 return new_addr;
978 }
979
980 static void pci_update_mappings(PCIDevice *d)
981 {
982 PCIIORegion *r;
983 int i;
984 pcibus_t new_addr, filtered_size;
985
986 for(i = 0; i < PCI_NUM_REGIONS; i++) {
987 r = &d->io_regions[i];
988
989 /* this region isn't registered */
990 if (!r->size)
991 continue;
992
993 new_addr = pci_bar_address(d, i, r->type, r->size);
994
995 /* bridge filtering */
996 filtered_size = r->size;
997 if (new_addr != PCI_BAR_UNMAPPED) {
998 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
999 }
1000
1001 /* This bar isn't changed */
1002 if (new_addr == r->addr && filtered_size == r->filtered_size)
1003 continue;
1004
1005 /* now do the real mapping */
1006 if (r->addr != PCI_BAR_UNMAPPED) {
1007 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1008 int class;
1009 /* NOTE: specific hack for IDE in PC case:
1010 only one byte must be mapped. */
1011 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1012 if (class == 0x0101 && r->size == 4) {
1013 isa_unassign_ioport(r->addr + 2, 1);
1014 } else {
1015 isa_unassign_ioport(r->addr, r->filtered_size);
1016 }
1017 } else {
1018 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1019 r->filtered_size,
1020 IO_MEM_UNASSIGNED);
1021 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1022 }
1023 }
1024 r->addr = new_addr;
1025 r->filtered_size = filtered_size;
1026 if (r->addr != PCI_BAR_UNMAPPED) {
1027 /*
1028 * TODO: currently almost all the map funcions assumes
1029 * filtered_size == size and addr & ~(size - 1) == addr.
1030 * However with bridge filtering, they aren't always true.
1031 * Teach them such cases, such that filtered_size < size and
1032 * addr & (size - 1) != 0.
1033 */
1034 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1035 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1036 } else {
1037 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1038 r->filtered_size, r->type);
1039 }
1040 }
1041 }
1042 }
1043
1044 static inline int pci_irq_disabled(PCIDevice *d)
1045 {
1046 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1047 }
1048
1049 /* Called after interrupt disabled field update in config space,
1050 * assert/deassert interrupts if necessary.
1051 * Gets original interrupt disable bit value (before update). */
1052 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1053 {
1054 int i, disabled = pci_irq_disabled(d);
1055 if (disabled == was_irq_disabled)
1056 return;
1057 for (i = 0; i < PCI_NUM_PINS; ++i) {
1058 int state = pci_irq_state(d, i);
1059 pci_change_irq_level(d, i, disabled ? -state : state);
1060 }
1061 }
1062
1063 uint32_t pci_default_read_config(PCIDevice *d,
1064 uint32_t address, int len)
1065 {
1066 uint32_t val = 0;
1067 assert(len == 1 || len == 2 || len == 4);
1068 len = MIN(len, pci_config_size(d) - address);
1069 memcpy(&val, d->config + address, len);
1070 return le32_to_cpu(val);
1071 }
1072
1073 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1074 {
1075 int i, was_irq_disabled = pci_irq_disabled(d);
1076 uint32_t config_size = pci_config_size(d);
1077
1078 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1079 uint8_t wmask = d->wmask[addr + i];
1080 uint8_t w1cmask = d->w1cmask[addr + i];
1081 assert(!(wmask & w1cmask));
1082 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1083 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1084 }
1085 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1086 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1087 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1088 range_covers_byte(addr, l, PCI_COMMAND))
1089 pci_update_mappings(d);
1090
1091 if (range_covers_byte(addr, l, PCI_COMMAND))
1092 pci_update_irq_disabled(d, was_irq_disabled);
1093 }
1094
1095 /***********************************************************/
1096 /* generic PCI irq support */
1097
1098 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1099 static void pci_set_irq(void *opaque, int irq_num, int level)
1100 {
1101 PCIDevice *pci_dev = opaque;
1102 int change;
1103
1104 change = level - pci_irq_state(pci_dev, irq_num);
1105 if (!change)
1106 return;
1107
1108 pci_set_irq_state(pci_dev, irq_num, level);
1109 pci_update_irq_status(pci_dev);
1110 if (pci_irq_disabled(pci_dev))
1111 return;
1112 pci_change_irq_level(pci_dev, irq_num, change);
1113 }
1114
1115 /***********************************************************/
1116 /* monitor info on PCI */
1117
1118 typedef struct {
1119 uint16_t class;
1120 const char *desc;
1121 const char *fw_name;
1122 uint16_t fw_ign_bits;
1123 } pci_class_desc;
1124
1125 static const pci_class_desc pci_class_descriptions[] =
1126 {
1127 { 0x0001, "VGA controller", "display"},
1128 { 0x0100, "SCSI controller", "scsi"},
1129 { 0x0101, "IDE controller", "ide"},
1130 { 0x0102, "Floppy controller", "fdc"},
1131 { 0x0103, "IPI controller", "ipi"},
1132 { 0x0104, "RAID controller", "raid"},
1133 { 0x0106, "SATA controller"},
1134 { 0x0107, "SAS controller"},
1135 { 0x0180, "Storage controller"},
1136 { 0x0200, "Ethernet controller", "ethernet"},
1137 { 0x0201, "Token Ring controller", "token-ring"},
1138 { 0x0202, "FDDI controller", "fddi"},
1139 { 0x0203, "ATM controller", "atm"},
1140 { 0x0280, "Network controller"},
1141 { 0x0300, "VGA controller", "display", 0x00ff},
1142 { 0x0301, "XGA controller"},
1143 { 0x0302, "3D controller"},
1144 { 0x0380, "Display controller"},
1145 { 0x0400, "Video controller", "video"},
1146 { 0x0401, "Audio controller", "sound"},
1147 { 0x0402, "Phone"},
1148 { 0x0480, "Multimedia controller"},
1149 { 0x0500, "RAM controller", "memory"},
1150 { 0x0501, "Flash controller", "flash"},
1151 { 0x0580, "Memory controller"},
1152 { 0x0600, "Host bridge", "host"},
1153 { 0x0601, "ISA bridge", "isa"},
1154 { 0x0602, "EISA bridge", "eisa"},
1155 { 0x0603, "MC bridge", "mca"},
1156 { 0x0604, "PCI bridge", "pci"},
1157 { 0x0605, "PCMCIA bridge", "pcmcia"},
1158 { 0x0606, "NUBUS bridge", "nubus"},
1159 { 0x0607, "CARDBUS bridge", "cardbus"},
1160 { 0x0608, "RACEWAY bridge"},
1161 { 0x0680, "Bridge"},
1162 { 0x0700, "Serial port", "serial"},
1163 { 0x0701, "Parallel port", "parallel"},
1164 { 0x0800, "Interrupt controller", "interrupt-controller"},
1165 { 0x0801, "DMA controller", "dma-controller"},
1166 { 0x0802, "Timer", "timer"},
1167 { 0x0803, "RTC", "rtc"},
1168 { 0x0900, "Keyboard", "keyboard"},
1169 { 0x0901, "Pen", "pen"},
1170 { 0x0902, "Mouse", "mouse"},
1171 { 0x0A00, "Dock station", "dock", 0x00ff},
1172 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1173 { 0x0c00, "Fireware contorller", "fireware"},
1174 { 0x0c01, "Access bus controller", "access-bus"},
1175 { 0x0c02, "SSA controller", "ssa"},
1176 { 0x0c03, "USB controller", "usb"},
1177 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1178 { 0, NULL}
1179 };
1180
1181 static void pci_for_each_device_under_bus(PCIBus *bus,
1182 void (*fn)(PCIBus *b, PCIDevice *d))
1183 {
1184 PCIDevice *d;
1185 int devfn;
1186
1187 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1188 d = bus->devices[devfn];
1189 if (d) {
1190 fn(bus, d);
1191 }
1192 }
1193 }
1194
1195 void pci_for_each_device(PCIBus *bus, int bus_num,
1196 void (*fn)(PCIBus *b, PCIDevice *d))
1197 {
1198 bus = pci_find_bus(bus, bus_num);
1199
1200 if (bus) {
1201 pci_for_each_device_under_bus(bus, fn);
1202 }
1203 }
1204
1205 static void pci_device_print(Monitor *mon, QDict *device)
1206 {
1207 QDict *qdict;
1208 QListEntry *entry;
1209 uint64_t addr, size;
1210
1211 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1212 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1213 qdict_get_int(device, "slot"),
1214 qdict_get_int(device, "function"));
1215 monitor_printf(mon, " ");
1216
1217 qdict = qdict_get_qdict(device, "class_info");
1218 if (qdict_haskey(qdict, "desc")) {
1219 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1220 } else {
1221 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1222 }
1223
1224 qdict = qdict_get_qdict(device, "id");
1225 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1226 qdict_get_int(qdict, "device"),
1227 qdict_get_int(qdict, "vendor"));
1228
1229 if (qdict_haskey(device, "irq")) {
1230 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1231 qdict_get_int(device, "irq"));
1232 }
1233
1234 if (qdict_haskey(device, "pci_bridge")) {
1235 QDict *info;
1236
1237 qdict = qdict_get_qdict(device, "pci_bridge");
1238
1239 info = qdict_get_qdict(qdict, "bus");
1240 monitor_printf(mon, " BUS %" PRId64 ".\n",
1241 qdict_get_int(info, "number"));
1242 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1243 qdict_get_int(info, "secondary"));
1244 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1245 qdict_get_int(info, "subordinate"));
1246
1247 info = qdict_get_qdict(qdict, "io_range");
1248 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1249 qdict_get_int(info, "base"),
1250 qdict_get_int(info, "limit"));
1251
1252 info = qdict_get_qdict(qdict, "memory_range");
1253 monitor_printf(mon,
1254 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1255 qdict_get_int(info, "base"),
1256 qdict_get_int(info, "limit"));
1257
1258 info = qdict_get_qdict(qdict, "prefetchable_range");
1259 monitor_printf(mon, " prefetchable memory range "
1260 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1261 qdict_get_int(info, "base"),
1262 qdict_get_int(info, "limit"));
1263 }
1264
1265 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1266 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1267 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1268
1269 addr = qdict_get_int(qdict, "address");
1270 size = qdict_get_int(qdict, "size");
1271
1272 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1273 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1274 " [0x%04"FMT_PCIBUS"].\n",
1275 addr, addr + size - 1);
1276 } else {
1277 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1278 " [0x%08"FMT_PCIBUS"].\n",
1279 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1280 qdict_get_bool(qdict, "prefetch") ?
1281 " prefetchable" : "", addr, addr + size - 1);
1282 }
1283 }
1284
1285 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1286
1287 if (qdict_haskey(device, "pci_bridge")) {
1288 qdict = qdict_get_qdict(device, "pci_bridge");
1289 if (qdict_haskey(qdict, "devices")) {
1290 QListEntry *dev;
1291 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1292 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1293 }
1294 }
1295 }
1296 }
1297
1298 void do_pci_info_print(Monitor *mon, const QObject *data)
1299 {
1300 QListEntry *bus, *dev;
1301
1302 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1303 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1304 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1305 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1306 }
1307 }
1308 }
1309
1310 static QObject *pci_get_dev_class(const PCIDevice *dev)
1311 {
1312 int class;
1313 const pci_class_desc *desc;
1314
1315 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1316 desc = pci_class_descriptions;
1317 while (desc->desc && class != desc->class)
1318 desc++;
1319
1320 if (desc->desc) {
1321 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1322 desc->desc, class);
1323 } else {
1324 return qobject_from_jsonf("{ 'class': %d }", class);
1325 }
1326 }
1327
1328 static QObject *pci_get_dev_id(const PCIDevice *dev)
1329 {
1330 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1331 pci_get_word(dev->config + PCI_VENDOR_ID),
1332 pci_get_word(dev->config + PCI_DEVICE_ID));
1333 }
1334
1335 static QObject *pci_get_regions_list(const PCIDevice *dev)
1336 {
1337 int i;
1338 QList *regions_list;
1339
1340 regions_list = qlist_new();
1341
1342 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1343 QObject *obj;
1344 const PCIIORegion *r = &dev->io_regions[i];
1345
1346 if (!r->size) {
1347 continue;
1348 }
1349
1350 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1351 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1352 "'address': %" PRId64 ", "
1353 "'size': %" PRId64 " }",
1354 i, r->addr, r->size);
1355 } else {
1356 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1357
1358 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1359 "'mem_type_64': %i, 'prefetch': %i, "
1360 "'address': %" PRId64 ", "
1361 "'size': %" PRId64 " }",
1362 i, mem_type_64,
1363 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1364 r->addr, r->size);
1365 }
1366
1367 qlist_append_obj(regions_list, obj);
1368 }
1369
1370 return QOBJECT(regions_list);
1371 }
1372
1373 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1374
1375 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1376 {
1377 uint8_t type;
1378 QObject *obj;
1379
1380 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1381 " 'qdev_id': %s }",
1382 bus_num,
1383 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1384 pci_get_dev_class(dev), pci_get_dev_id(dev),
1385 pci_get_regions_list(dev),
1386 dev->qdev.id ? dev->qdev.id : "");
1387
1388 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1389 QDict *qdict = qobject_to_qdict(obj);
1390 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1391 }
1392
1393 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1394 if (type == PCI_HEADER_TYPE_BRIDGE) {
1395 QDict *qdict;
1396 QObject *pci_bridge;
1397
1398 pci_bridge = qobject_from_jsonf("{ 'bus': "
1399 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1400 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1401 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1402 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1403 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1404 dev->config[PCI_SUBORDINATE_BUS],
1405 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1406 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1407 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1408 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1409 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1410 PCI_BASE_ADDRESS_MEM_PREFETCH),
1411 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1412 PCI_BASE_ADDRESS_MEM_PREFETCH));
1413
1414 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1415 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1416
1417 if (child_bus) {
1418 qdict = qobject_to_qdict(pci_bridge);
1419 qdict_put_obj(qdict, "devices",
1420 pci_get_devices_list(child_bus,
1421 dev->config[PCI_SECONDARY_BUS]));
1422 }
1423 }
1424 qdict = qobject_to_qdict(obj);
1425 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1426 }
1427
1428 return obj;
1429 }
1430
1431 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1432 {
1433 int devfn;
1434 PCIDevice *dev;
1435 QList *dev_list;
1436
1437 dev_list = qlist_new();
1438
1439 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1440 dev = bus->devices[devfn];
1441 if (dev) {
1442 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1443 }
1444 }
1445
1446 return QOBJECT(dev_list);
1447 }
1448
1449 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1450 {
1451 bus = pci_find_bus(bus, bus_num);
1452 if (bus) {
1453 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1454 bus_num, pci_get_devices_list(bus, bus_num));
1455 }
1456
1457 return NULL;
1458 }
1459
1460 void do_pci_info(Monitor *mon, QObject **ret_data)
1461 {
1462 QList *bus_list;
1463 struct PCIHostBus *host;
1464
1465 bus_list = qlist_new();
1466
1467 QLIST_FOREACH(host, &host_buses, next) {
1468 QObject *obj = pci_get_bus_dict(host->bus, 0);
1469 if (obj) {
1470 qlist_append_obj(bus_list, obj);
1471 }
1472 }
1473
1474 *ret_data = QOBJECT(bus_list);
1475 }
1476
1477 static const char * const pci_nic_models[] = {
1478 "ne2k_pci",
1479 "i82551",
1480 "i82557b",
1481 "i82559er",
1482 "rtl8139",
1483 "e1000",
1484 "pcnet",
1485 "virtio",
1486 NULL
1487 };
1488
1489 static const char * const pci_nic_names[] = {
1490 "ne2k_pci",
1491 "i82551",
1492 "i82557b",
1493 "i82559er",
1494 "rtl8139",
1495 "e1000",
1496 "pcnet",
1497 "virtio-net-pci",
1498 NULL
1499 };
1500
1501 /* Initialize a PCI NIC. */
1502 /* FIXME callers should check for failure, but don't */
1503 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1504 const char *default_devaddr)
1505 {
1506 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1507 PCIBus *bus;
1508 int devfn;
1509 PCIDevice *pci_dev;
1510 DeviceState *dev;
1511 int i;
1512
1513 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1514 if (i < 0)
1515 return NULL;
1516
1517 bus = pci_get_bus_devfn(&devfn, devaddr);
1518 if (!bus) {
1519 error_report("Invalid PCI device address %s for device %s",
1520 devaddr, pci_nic_names[i]);
1521 return NULL;
1522 }
1523
1524 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1525 dev = &pci_dev->qdev;
1526 qdev_set_nic_properties(dev, nd);
1527 if (qdev_init(dev) < 0)
1528 return NULL;
1529 return pci_dev;
1530 }
1531
1532 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1533 const char *default_devaddr)
1534 {
1535 PCIDevice *res;
1536
1537 if (qemu_show_nic_models(nd->model, pci_nic_models))
1538 exit(0);
1539
1540 res = pci_nic_init(nd, default_model, default_devaddr);
1541 if (!res)
1542 exit(1);
1543 return res;
1544 }
1545
1546 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1547 {
1548 pci_update_mappings(d);
1549 }
1550
1551 void pci_bridge_update_mappings(PCIBus *b)
1552 {
1553 PCIBus *child;
1554
1555 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1556
1557 QLIST_FOREACH(child, &b->child, sibling) {
1558 pci_bridge_update_mappings(child);
1559 }
1560 }
1561
1562 /* Whether a given bus number is in range of the secondary
1563 * bus of the given bridge device. */
1564 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1565 {
1566 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1567 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1568 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1569 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1570 }
1571
1572 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1573 {
1574 PCIBus *sec;
1575
1576 if (!bus) {
1577 return NULL;
1578 }
1579
1580 if (pci_bus_num(bus) == bus_num) {
1581 return bus;
1582 }
1583
1584 /* Consider all bus numbers in range for the host pci bridge. */
1585 if (bus->parent_dev &&
1586 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1587 return NULL;
1588 }
1589
1590 /* try child bus */
1591 for (; bus; bus = sec) {
1592 QLIST_FOREACH(sec, &bus->child, sibling) {
1593 assert(sec->parent_dev);
1594 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1595 return sec;
1596 }
1597 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1598 break;
1599 }
1600 }
1601 }
1602
1603 return NULL;
1604 }
1605
1606 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1607 {
1608 bus = pci_find_bus(bus, bus_num);
1609
1610 if (!bus)
1611 return NULL;
1612
1613 return bus->devices[PCI_DEVFN(slot, function)];
1614 }
1615
1616 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1617 {
1618 PCIDevice *pci_dev = (PCIDevice *)qdev;
1619 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1620 PCIBus *bus;
1621 int devfn, rc;
1622 bool is_default_rom;
1623
1624 /* initialize cap_present for pci_is_express() and pci_config_size() */
1625 if (info->is_express) {
1626 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1627 }
1628
1629 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1630 devfn = pci_dev->devfn;
1631 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1632 info->config_read, info->config_write,
1633 info->is_bridge);
1634 if (pci_dev == NULL)
1635 return -1;
1636 if (qdev->hotplugged && info->no_hotplug) {
1637 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1638 do_pci_unregister_device(pci_dev);
1639 return -1;
1640 }
1641 rc = info->init(pci_dev);
1642 if (rc != 0) {
1643 do_pci_unregister_device(pci_dev);
1644 return rc;
1645 }
1646
1647 /* rom loading */
1648 is_default_rom = false;
1649 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1650 pci_dev->romfile = qemu_strdup(info->romfile);
1651 is_default_rom = true;
1652 }
1653 pci_add_option_rom(pci_dev, is_default_rom);
1654
1655 if (bus->hotplug) {
1656 /* Let buses differentiate between hotplug and when device is
1657 * enabled during qemu machine creation. */
1658 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1659 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1660 PCI_COLDPLUG_ENABLED);
1661 if (rc != 0) {
1662 int r = pci_unregister_device(&pci_dev->qdev);
1663 assert(!r);
1664 return rc;
1665 }
1666 }
1667 return 0;
1668 }
1669
1670 static int pci_unplug_device(DeviceState *qdev)
1671 {
1672 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1673 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1674
1675 if (info->no_hotplug) {
1676 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1677 return -1;
1678 }
1679 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1680 PCI_HOTPLUG_DISABLED);
1681 }
1682
1683 void pci_qdev_register(PCIDeviceInfo *info)
1684 {
1685 info->qdev.init = pci_qdev_init;
1686 info->qdev.unplug = pci_unplug_device;
1687 info->qdev.exit = pci_unregister_device;
1688 info->qdev.bus_info = &pci_bus_info;
1689 qdev_register(&info->qdev);
1690 }
1691
1692 void pci_qdev_register_many(PCIDeviceInfo *info)
1693 {
1694 while (info->qdev.name) {
1695 pci_qdev_register(info);
1696 info++;
1697 }
1698 }
1699
1700 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1701 const char *name)
1702 {
1703 DeviceState *dev;
1704
1705 dev = qdev_create(&bus->qbus, name);
1706 qdev_prop_set_uint32(dev, "addr", devfn);
1707 qdev_prop_set_bit(dev, "multifunction", multifunction);
1708 return DO_UPCAST(PCIDevice, qdev, dev);
1709 }
1710
1711 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1712 bool multifunction,
1713 const char *name)
1714 {
1715 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1716 qdev_init_nofail(&dev->qdev);
1717 return dev;
1718 }
1719
1720 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1721 {
1722 return pci_create_multifunction(bus, devfn, false, name);
1723 }
1724
1725 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1726 {
1727 return pci_create_simple_multifunction(bus, devfn, false, name);
1728 }
1729
1730 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1731 {
1732 int config_size = pci_config_size(pdev);
1733 int offset = PCI_CONFIG_HEADER_SIZE;
1734 int i;
1735 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1736 if (pdev->used[i])
1737 offset = i + 1;
1738 else if (i - offset + 1 == size)
1739 return offset;
1740 return 0;
1741 }
1742
1743 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1744 uint8_t *prev_p)
1745 {
1746 uint8_t next, prev;
1747
1748 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1749 return 0;
1750
1751 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1752 prev = next + PCI_CAP_LIST_NEXT)
1753 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1754 break;
1755
1756 if (prev_p)
1757 *prev_p = prev;
1758 return next;
1759 }
1760
1761 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1762 {
1763 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1764 }
1765
1766 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1767 This is needed for an option rom which is used for more than one device. */
1768 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1769 {
1770 uint16_t vendor_id;
1771 uint16_t device_id;
1772 uint16_t rom_vendor_id;
1773 uint16_t rom_device_id;
1774 uint16_t rom_magic;
1775 uint16_t pcir_offset;
1776 uint8_t checksum;
1777
1778 /* Words in rom data are little endian (like in PCI configuration),
1779 so they can be read / written with pci_get_word / pci_set_word. */
1780
1781 /* Only a valid rom will be patched. */
1782 rom_magic = pci_get_word(ptr);
1783 if (rom_magic != 0xaa55) {
1784 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1785 return;
1786 }
1787 pcir_offset = pci_get_word(ptr + 0x18);
1788 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1789 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1790 return;
1791 }
1792
1793 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1794 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1795 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1796 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1797
1798 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1799 vendor_id, device_id, rom_vendor_id, rom_device_id);
1800
1801 checksum = ptr[6];
1802
1803 if (vendor_id != rom_vendor_id) {
1804 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1805 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1806 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1807 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1808 ptr[6] = checksum;
1809 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1810 }
1811
1812 if (device_id != rom_device_id) {
1813 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1814 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1815 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1816 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1817 ptr[6] = checksum;
1818 pci_set_word(ptr + pcir_offset + 6, device_id);
1819 }
1820 }
1821
1822 /* Add an option rom for the device */
1823 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1824 {
1825 int size;
1826 char *path;
1827 void *ptr;
1828 char name[32];
1829
1830 if (!pdev->romfile)
1831 return 0;
1832 if (strlen(pdev->romfile) == 0)
1833 return 0;
1834
1835 if (!pdev->rom_bar) {
1836 /*
1837 * Load rom via fw_cfg instead of creating a rom bar,
1838 * for 0.11 compatibility.
1839 */
1840 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1841 if (class == 0x0300) {
1842 rom_add_vga(pdev->romfile);
1843 } else {
1844 rom_add_option(pdev->romfile, -1);
1845 }
1846 return 0;
1847 }
1848
1849 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1850 if (path == NULL) {
1851 path = qemu_strdup(pdev->romfile);
1852 }
1853
1854 size = get_image_size(path);
1855 if (size < 0) {
1856 error_report("%s: failed to find romfile \"%s\"",
1857 __FUNCTION__, pdev->romfile);
1858 return -1;
1859 }
1860 if (size & (size - 1)) {
1861 size = 1 << qemu_fls(size);
1862 }
1863
1864 if (pdev->qdev.info->vmsd)
1865 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1866 else
1867 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1868 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1869
1870 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1871 load_image(path, ptr);
1872 qemu_free(path);
1873
1874 if (is_default_rom) {
1875 /* Only the default rom images will be patched (if needed). */
1876 pci_patch_ids(pdev, ptr, size);
1877 }
1878
1879 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1880 0, pci_map_option_rom);
1881
1882 return 0;
1883 }
1884
1885 static void pci_del_option_rom(PCIDevice *pdev)
1886 {
1887 if (!pdev->rom_offset)
1888 return;
1889
1890 qemu_ram_free(pdev->rom_offset);
1891 pdev->rom_offset = 0;
1892 }
1893
1894 /*
1895 * if !offset
1896 * Reserve space and add capability to the linked list in pci config space
1897 *
1898 * if offset = 0,
1899 * Find and reserve space and add capability to the linked list
1900 * in pci config space */
1901 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1902 uint8_t offset, uint8_t size)
1903 {
1904 uint8_t *config;
1905 if (!offset) {
1906 offset = pci_find_space(pdev, size);
1907 if (!offset) {
1908 return -ENOSPC;
1909 }
1910 }
1911
1912 config = pdev->config + offset;
1913 config[PCI_CAP_LIST_ID] = cap_id;
1914 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1915 pdev->config[PCI_CAPABILITY_LIST] = offset;
1916 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1917 memset(pdev->used + offset, 0xFF, size);
1918 /* Make capability read-only by default */
1919 memset(pdev->wmask + offset, 0, size);
1920 /* Check capability by default */
1921 memset(pdev->cmask + offset, 0xFF, size);
1922 return offset;
1923 }
1924
1925 /* Unlink capability from the pci config space. */
1926 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1927 {
1928 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1929 if (!offset)
1930 return;
1931 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1932 /* Make capability writeable again */
1933 memset(pdev->wmask + offset, 0xff, size);
1934 memset(pdev->w1cmask + offset, 0, size);
1935 /* Clear cmask as device-specific registers can't be checked */
1936 memset(pdev->cmask + offset, 0, size);
1937 memset(pdev->used + offset, 0, size);
1938
1939 if (!pdev->config[PCI_CAPABILITY_LIST])
1940 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1941 }
1942
1943 /* Reserve space for capability at a known offset (to call after load). */
1944 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1945 {
1946 memset(pdev->used + offset, 0xff, size);
1947 }
1948
1949 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1950 {
1951 return pci_find_capability_list(pdev, cap_id, NULL);
1952 }
1953
1954 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1955 {
1956 PCIDevice *d = (PCIDevice *)dev;
1957 const pci_class_desc *desc;
1958 char ctxt[64];
1959 PCIIORegion *r;
1960 int i, class;
1961
1962 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1963 desc = pci_class_descriptions;
1964 while (desc->desc && class != desc->class)
1965 desc++;
1966 if (desc->desc) {
1967 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1968 } else {
1969 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1970 }
1971
1972 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1973 "pci id %04x:%04x (sub %04x:%04x)\n",
1974 indent, "", ctxt, pci_bus_num(d->bus),
1975 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1976 pci_get_word(d->config + PCI_VENDOR_ID),
1977 pci_get_word(d->config + PCI_DEVICE_ID),
1978 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1979 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1980 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1981 r = &d->io_regions[i];
1982 if (!r->size)
1983 continue;
1984 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1985 " [0x%"FMT_PCIBUS"]\n",
1986 indent, "",
1987 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1988 r->addr, r->addr + r->size - 1);
1989 }
1990 }
1991
1992 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1993 {
1994 PCIDevice *d = (PCIDevice *)dev;
1995 const char *name = NULL;
1996 const pci_class_desc *desc = pci_class_descriptions;
1997 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1998
1999 while (desc->desc &&
2000 (class & ~desc->fw_ign_bits) !=
2001 (desc->class & ~desc->fw_ign_bits)) {
2002 desc++;
2003 }
2004
2005 if (desc->desc) {
2006 name = desc->fw_name;
2007 }
2008
2009 if (name) {
2010 pstrcpy(buf, len, name);
2011 } else {
2012 snprintf(buf, len, "pci%04x,%04x",
2013 pci_get_word(d->config + PCI_VENDOR_ID),
2014 pci_get_word(d->config + PCI_DEVICE_ID));
2015 }
2016
2017 return buf;
2018 }
2019
2020 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2021 {
2022 PCIDevice *d = (PCIDevice *)dev;
2023 char path[50], name[33];
2024 int off;
2025
2026 off = snprintf(path, sizeof(path), "%s@%x",
2027 pci_dev_fw_name(dev, name, sizeof name),
2028 PCI_SLOT(d->devfn));
2029 if (PCI_FUNC(d->devfn))
2030 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2031 return strdup(path);
2032 }
2033
2034 static char *pcibus_get_dev_path(DeviceState *dev)
2035 {
2036 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2037 PCIDevice *t;
2038 int slot_depth;
2039 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2040 * 00 is added here to make this format compatible with
2041 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2042 * Slot.Function list specifies the slot and function numbers for all
2043 * devices on the path from root to the specific device. */
2044 char domain[] = "DDDD:00";
2045 char slot[] = ":SS.F";
2046 int domain_len = sizeof domain - 1 /* For '\0' */;
2047 int slot_len = sizeof slot - 1 /* For '\0' */;
2048 int path_len;
2049 char *path, *p;
2050 int s;
2051
2052 /* Calculate # of slots on path between device and root. */;
2053 slot_depth = 0;
2054 for (t = d; t; t = t->bus->parent_dev) {
2055 ++slot_depth;
2056 }
2057
2058 path_len = domain_len + slot_len * slot_depth;
2059
2060 /* Allocate memory, fill in the terminating null byte. */
2061 path = qemu_malloc(path_len + 1 /* For '\0' */);
2062 path[path_len] = '\0';
2063
2064 /* First field is the domain. */
2065 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2066 assert(s == domain_len);
2067 memcpy(path, domain, domain_len);
2068
2069 /* Fill in slot numbers. We walk up from device to root, so need to print
2070 * them in the reverse order, last to first. */
2071 p = path + path_len;
2072 for (t = d; t; t = t->bus->parent_dev) {
2073 p -= slot_len;
2074 s = snprintf(slot, sizeof slot, ":%02x.%x",
2075 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2076 assert(s == slot_len);
2077 memcpy(p, slot, slot_len);
2078 }
2079
2080 return path;
2081 }
2082
2083 static int pci_qdev_find_recursive(PCIBus *bus,
2084 const char *id, PCIDevice **pdev)
2085 {
2086 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2087 if (!qdev) {
2088 return -ENODEV;
2089 }
2090
2091 /* roughly check if given qdev is pci device */
2092 if (qdev->info->init == &pci_qdev_init &&
2093 qdev->parent_bus->info == &pci_bus_info) {
2094 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2095 return 0;
2096 }
2097 return -EINVAL;
2098 }
2099
2100 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2101 {
2102 struct PCIHostBus *host;
2103 int rc = -ENODEV;
2104
2105 QLIST_FOREACH(host, &host_buses, next) {
2106 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2107 if (!tmp) {
2108 rc = 0;
2109 break;
2110 }
2111 if (tmp != -ENODEV) {
2112 rc = tmp;
2113 }
2114 }
2115
2116 return rc;
2117 }
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