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target/ppc: cpu_init: Reuse init_proc_604 for the 604e
[qemu.git] / target / ppc / cpu_init.c
blob28e65ba2047606d0da048868f5fc77b8b1ef6f6b
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_tcg.h"
48 #include "power8-pmu.h"
49
50 /* #define PPC_DEBUG_SPR */
51 /* #define USE_APPLE_GDB */
52
53 static inline void vscr_init(CPUPPCState *env, uint32_t val)
54 {
55 /* Altivec always uses round-to-nearest */
56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
57 ppc_store_vscr(env, val);
58 }
59
60 /**
61 * _spr_register
62 *
63 * Register an SPR with all the callbacks required for tcg,
64 * and the ID number for KVM.
65 *
66 * The reason for the conditional compilation is that the tcg functions
67 * may be compiled out, and the system kvm header may not be available
68 * for supplying the ID numbers. This is ugly, but the best we can do.
69 */
70
71 #ifdef CONFIG_TCG
72 # define USR_ARG(X) X,
73 # ifdef CONFIG_USER_ONLY
74 # define SYS_ARG(X)
75 # else
76 # define SYS_ARG(X) X,
77 # endif
78 #else
79 # define USR_ARG(X)
80 # define SYS_ARG(X)
81 #endif
82 #ifdef CONFIG_KVM
83 # define KVM_ARG(X) X,
84 #else
85 # define KVM_ARG(X)
86 #endif
87
88 typedef void spr_callback(DisasContext *, int, int);
89
90 static void _spr_register(CPUPPCState *env, int num, const char *name,
91 USR_ARG(spr_callback *uea_read)
92 USR_ARG(spr_callback *uea_write)
93 SYS_ARG(spr_callback *oea_read)
94 SYS_ARG(spr_callback *oea_write)
95 SYS_ARG(spr_callback *hea_read)
96 SYS_ARG(spr_callback *hea_write)
97 KVM_ARG(uint64_t one_reg_id)
98 target_ulong initial_value)
99 {
100 ppc_spr_t *spr = &env->spr_cb[num];
101
102 /* No SPR should be registered twice. */
103 assert(spr->name == NULL);
104 assert(name != NULL);
105
106 spr->name = name;
107 spr->default_value = initial_value;
108 env->spr[num] = initial_value;
109
110 #ifdef CONFIG_TCG
111 spr->uea_read = uea_read;
112 spr->uea_write = uea_write;
113 # ifndef CONFIG_USER_ONLY
114 spr->oea_read = oea_read;
115 spr->oea_write = oea_write;
116 spr->hea_read = hea_read;
117 spr->hea_write = hea_write;
118 # endif
119 #endif
120 #ifdef CONFIG_KVM
121 spr->one_reg_id = one_reg_id;
122 #endif
123 }
124
125 /* spr_register_kvm_hv passes all required arguments. */
126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
127 oea_read, oea_write, hea_read, hea_write, \
128 one_reg_id, initial_value) \
129 _spr_register(env, num, name, \
130 USR_ARG(uea_read) USR_ARG(uea_write) \
131 SYS_ARG(oea_read) SYS_ARG(oea_write) \
132 SYS_ARG(hea_read) SYS_ARG(hea_write) \
133 KVM_ARG(one_reg_id) initial_value)
134
135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
137 oea_read, oea_write, one_reg_id, ival) \
138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
139 oea_write, oea_read, oea_write, one_reg_id, ival)
140
141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
142 #define spr_register_hv(env, num, name, uea_read, uea_write, \
143 oea_read, oea_write, hea_read, hea_write, ival) \
144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
145 oea_write, hea_read, hea_write, 0, ival)
146
147 #define spr_register(env, num, name, uea_read, uea_write, \
148 oea_read, oea_write, ival) \
149 spr_register_kvm(env, num, name, uea_read, uea_write, \
150 oea_read, oea_write, 0, ival)
151
152 /* Generic PowerPC SPRs */
153 static void register_generic_sprs(PowerPCCPU *cpu)
154 {
155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
156 CPUPPCState *env = &cpu->env;
157
158 /* Integer processing */
159 spr_register(env, SPR_XER, "XER",
160 &spr_read_xer, &spr_write_xer,
161 &spr_read_xer, &spr_write_xer,
162 0x00000000);
163 /* Branch control */
164 spr_register(env, SPR_LR, "LR",
165 &spr_read_lr, &spr_write_lr,
166 &spr_read_lr, &spr_write_lr,
167 0x00000000);
168 spr_register(env, SPR_CTR, "CTR",
169 &spr_read_ctr, &spr_write_ctr,
170 &spr_read_ctr, &spr_write_ctr,
171 0x00000000);
172 /* Interrupt processing */
173 spr_register(env, SPR_SRR0, "SRR0",
174 SPR_NOACCESS, SPR_NOACCESS,
175 &spr_read_generic, &spr_write_generic,
176 0x00000000);
177 spr_register(env, SPR_SRR1, "SRR1",
178 SPR_NOACCESS, SPR_NOACCESS,
179 &spr_read_generic, &spr_write_generic,
180 0x00000000);
181 /* Processor control */
182 spr_register(env, SPR_SPRG0, "SPRG0",
183 SPR_NOACCESS, SPR_NOACCESS,
184 &spr_read_generic, &spr_write_generic,
185 0x00000000);
186 spr_register(env, SPR_SPRG1, "SPRG1",
187 SPR_NOACCESS, SPR_NOACCESS,
188 &spr_read_generic, &spr_write_generic,
189 0x00000000);
190 spr_register(env, SPR_SPRG2, "SPRG2",
191 SPR_NOACCESS, SPR_NOACCESS,
192 &spr_read_generic, &spr_write_generic,
193 0x00000000);
194 spr_register(env, SPR_SPRG3, "SPRG3",
195 SPR_NOACCESS, SPR_NOACCESS,
196 &spr_read_generic, &spr_write_generic,
197 0x00000000);
198
199 spr_register(env, SPR_PVR, "PVR",
200 /* Linux permits userspace to read PVR */
201 #if defined(CONFIG_LINUX_USER)
202 &spr_read_generic,
203 #else
204 SPR_NOACCESS,
205 #endif
206 SPR_NOACCESS,
207 &spr_read_generic, SPR_NOACCESS,
208 pcc->pvr);
209
210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
211 if (pcc->svr != POWERPC_SVR_NONE) {
212 if (pcc->svr & POWERPC_SVR_E500) {
213 spr_register(env, SPR_E500_SVR, "SVR",
214 SPR_NOACCESS, SPR_NOACCESS,
215 &spr_read_generic, SPR_NOACCESS,
216 pcc->svr & ~POWERPC_SVR_E500);
217 } else {
218 spr_register(env, SPR_SVR, "SVR",
219 SPR_NOACCESS, SPR_NOACCESS,
220 &spr_read_generic, SPR_NOACCESS,
221 pcc->svr);
222 }
223 }
224
225 /* Time base */
226 spr_register(env, SPR_VTBL, "TBL",
227 &spr_read_tbl, SPR_NOACCESS,
228 &spr_read_tbl, SPR_NOACCESS,
229 0x00000000);
230 spr_register(env, SPR_TBL, "TBL",
231 &spr_read_tbl, SPR_NOACCESS,
232 &spr_read_tbl, &spr_write_tbl,
233 0x00000000);
234 spr_register(env, SPR_VTBU, "TBU",
235 &spr_read_tbu, SPR_NOACCESS,
236 &spr_read_tbu, SPR_NOACCESS,
237 0x00000000);
238 spr_register(env, SPR_TBU, "TBU",
239 &spr_read_tbu, SPR_NOACCESS,
240 &spr_read_tbu, &spr_write_tbu,
241 0x00000000);
242 }
243
244 /* SPR common to all non-embedded PowerPC, including 601 */
245 static void register_ne_601_sprs(CPUPPCState *env)
246 {
247 /* Exception processing */
248 spr_register_kvm(env, SPR_DSISR, "DSISR",
249 SPR_NOACCESS, SPR_NOACCESS,
250 &spr_read_generic, &spr_write_generic,
251 KVM_REG_PPC_DSISR, 0x00000000);
252 spr_register_kvm(env, SPR_DAR, "DAR",
253 SPR_NOACCESS, SPR_NOACCESS,
254 &spr_read_generic, &spr_write_generic,
255 KVM_REG_PPC_DAR, 0x00000000);
256 /* Timer */
257 spr_register(env, SPR_DECR, "DECR",
258 SPR_NOACCESS, SPR_NOACCESS,
259 &spr_read_decr, &spr_write_decr,
260 0x00000000);
261 }
262
263 /* Storage Description Register 1 */
264 static void register_sdr1_sprs(CPUPPCState *env)
265 {
266 #ifndef CONFIG_USER_ONLY
267 if (env->has_hv_mode) {
268 /*
269 * SDR1 is a hypervisor resource on CPUs which have a
270 * hypervisor mode
271 */
272 spr_register_hv(env, SPR_SDR1, "SDR1",
273 SPR_NOACCESS, SPR_NOACCESS,
274 SPR_NOACCESS, SPR_NOACCESS,
275 &spr_read_generic, &spr_write_sdr1,
276 0x00000000);
277 } else {
278 spr_register(env, SPR_SDR1, "SDR1",
279 SPR_NOACCESS, SPR_NOACCESS,
280 &spr_read_generic, &spr_write_sdr1,
281 0x00000000);
282 }
283 #endif
284 }
285
286 /* BATs 0-3 */
287 static void register_low_BATs(CPUPPCState *env)
288 {
289 #if !defined(CONFIG_USER_ONLY)
290 spr_register(env, SPR_IBAT0U, "IBAT0U",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_ibat, &spr_write_ibatu,
293 0x00000000);
294 spr_register(env, SPR_IBAT0L, "IBAT0L",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_ibat, &spr_write_ibatl,
297 0x00000000);
298 spr_register(env, SPR_IBAT1U, "IBAT1U",
299 SPR_NOACCESS, SPR_NOACCESS,
300 &spr_read_ibat, &spr_write_ibatu,
301 0x00000000);
302 spr_register(env, SPR_IBAT1L, "IBAT1L",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_ibat, &spr_write_ibatl,
305 0x00000000);
306 spr_register(env, SPR_IBAT2U, "IBAT2U",
307 SPR_NOACCESS, SPR_NOACCESS,
308 &spr_read_ibat, &spr_write_ibatu,
309 0x00000000);
310 spr_register(env, SPR_IBAT2L, "IBAT2L",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_ibat, &spr_write_ibatl,
313 0x00000000);
314 spr_register(env, SPR_IBAT3U, "IBAT3U",
315 SPR_NOACCESS, SPR_NOACCESS,
316 &spr_read_ibat, &spr_write_ibatu,
317 0x00000000);
318 spr_register(env, SPR_IBAT3L, "IBAT3L",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_ibat, &spr_write_ibatl,
321 0x00000000);
322 spr_register(env, SPR_DBAT0U, "DBAT0U",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_dbat, &spr_write_dbatu,
325 0x00000000);
326 spr_register(env, SPR_DBAT0L, "DBAT0L",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_dbat, &spr_write_dbatl,
329 0x00000000);
330 spr_register(env, SPR_DBAT1U, "DBAT1U",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_dbat, &spr_write_dbatu,
333 0x00000000);
334 spr_register(env, SPR_DBAT1L, "DBAT1L",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_dbat, &spr_write_dbatl,
337 0x00000000);
338 spr_register(env, SPR_DBAT2U, "DBAT2U",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_dbat, &spr_write_dbatu,
341 0x00000000);
342 spr_register(env, SPR_DBAT2L, "DBAT2L",
343 SPR_NOACCESS, SPR_NOACCESS,
344 &spr_read_dbat, &spr_write_dbatl,
345 0x00000000);
346 spr_register(env, SPR_DBAT3U, "DBAT3U",
347 SPR_NOACCESS, SPR_NOACCESS,
348 &spr_read_dbat, &spr_write_dbatu,
349 0x00000000);
350 spr_register(env, SPR_DBAT3L, "DBAT3L",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_dbat, &spr_write_dbatl,
353 0x00000000);
354 env->nb_BATs += 4;
355 #endif
356 }
357
358 /* BATs 4-7 */
359 static void register_high_BATs(CPUPPCState *env)
360 {
361 #if !defined(CONFIG_USER_ONLY)
362 spr_register(env, SPR_IBAT4U, "IBAT4U",
363 SPR_NOACCESS, SPR_NOACCESS,
364 &spr_read_ibat_h, &spr_write_ibatu_h,
365 0x00000000);
366 spr_register(env, SPR_IBAT4L, "IBAT4L",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_ibat_h, &spr_write_ibatl_h,
369 0x00000000);
370 spr_register(env, SPR_IBAT5U, "IBAT5U",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_ibat_h, &spr_write_ibatu_h,
373 0x00000000);
374 spr_register(env, SPR_IBAT5L, "IBAT5L",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_ibat_h, &spr_write_ibatl_h,
377 0x00000000);
378 spr_register(env, SPR_IBAT6U, "IBAT6U",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_ibat_h, &spr_write_ibatu_h,
381 0x00000000);
382 spr_register(env, SPR_IBAT6L, "IBAT6L",
383 SPR_NOACCESS, SPR_NOACCESS,
384 &spr_read_ibat_h, &spr_write_ibatl_h,
385 0x00000000);
386 spr_register(env, SPR_IBAT7U, "IBAT7U",
387 SPR_NOACCESS, SPR_NOACCESS,
388 &spr_read_ibat_h, &spr_write_ibatu_h,
389 0x00000000);
390 spr_register(env, SPR_IBAT7L, "IBAT7L",
391 SPR_NOACCESS, SPR_NOACCESS,
392 &spr_read_ibat_h, &spr_write_ibatl_h,
393 0x00000000);
394 spr_register(env, SPR_DBAT4U, "DBAT4U",
395 SPR_NOACCESS, SPR_NOACCESS,
396 &spr_read_dbat_h, &spr_write_dbatu_h,
397 0x00000000);
398 spr_register(env, SPR_DBAT4L, "DBAT4L",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_dbat_h, &spr_write_dbatl_h,
401 0x00000000);
402 spr_register(env, SPR_DBAT5U, "DBAT5U",
403 SPR_NOACCESS, SPR_NOACCESS,
404 &spr_read_dbat_h, &spr_write_dbatu_h,
405 0x00000000);
406 spr_register(env, SPR_DBAT5L, "DBAT5L",
407 SPR_NOACCESS, SPR_NOACCESS,
408 &spr_read_dbat_h, &spr_write_dbatl_h,
409 0x00000000);
410 spr_register(env, SPR_DBAT6U, "DBAT6U",
411 SPR_NOACCESS, SPR_NOACCESS,
412 &spr_read_dbat_h, &spr_write_dbatu_h,
413 0x00000000);
414 spr_register(env, SPR_DBAT6L, "DBAT6L",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_dbat_h, &spr_write_dbatl_h,
417 0x00000000);
418 spr_register(env, SPR_DBAT7U, "DBAT7U",
419 SPR_NOACCESS, SPR_NOACCESS,
420 &spr_read_dbat_h, &spr_write_dbatu_h,
421 0x00000000);
422 spr_register(env, SPR_DBAT7L, "DBAT7L",
423 SPR_NOACCESS, SPR_NOACCESS,
424 &spr_read_dbat_h, &spr_write_dbatl_h,
425 0x00000000);
426 env->nb_BATs += 4;
427 #endif
428 }
429
430 /* Softare table search registers */
431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
432 {
433 #if !defined(CONFIG_USER_ONLY)
434 env->nb_tlb = nb_tlbs;
435 env->nb_ways = nb_ways;
436 env->id_tlbs = 1;
437 env->tlb_type = TLB_6XX;
438 spr_register(env, SPR_DMISS, "DMISS",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, SPR_NOACCESS,
441 0x00000000);
442 spr_register(env, SPR_DCMP, "DCMP",
443 SPR_NOACCESS, SPR_NOACCESS,
444 &spr_read_generic, SPR_NOACCESS,
445 0x00000000);
446 spr_register(env, SPR_HASH1, "HASH1",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, SPR_NOACCESS,
449 0x00000000);
450 spr_register(env, SPR_HASH2, "HASH2",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, SPR_NOACCESS,
453 0x00000000);
454 spr_register(env, SPR_IMISS, "IMISS",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, SPR_NOACCESS,
457 0x00000000);
458 spr_register(env, SPR_ICMP, "ICMP",
459 SPR_NOACCESS, SPR_NOACCESS,
460 &spr_read_generic, SPR_NOACCESS,
461 0x00000000);
462 spr_register(env, SPR_RPA, "RPA",
463 SPR_NOACCESS, SPR_NOACCESS,
464 &spr_read_generic, &spr_write_generic,
465 0x00000000);
466 #endif
467 }
468
469 static void register_745_sprs(CPUPPCState *env)
470 {
471 /* SGPRs */
472 spr_register(env, SPR_SPRG4, "SPRG4",
473 SPR_NOACCESS, SPR_NOACCESS,
474 &spr_read_generic, &spr_write_generic,
475 0x00000000);
476 spr_register(env, SPR_SPRG5, "SPRG5",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 spr_register(env, SPR_SPRG6, "SPRG6",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 spr_register(env, SPR_SPRG7, "SPRG7",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
487 0x00000000);
488
489 /* Hardware implementation registers */
490 spr_register(env, SPR_HID0, "HID0",
491 SPR_NOACCESS, SPR_NOACCESS,
492 &spr_read_generic, &spr_write_generic,
493 0x00000000);
494
495 spr_register(env, SPR_HID1, "HID1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499
500 spr_register(env, SPR_HID2, "HID2",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_generic, &spr_write_generic,
503 0x00000000);
504 }
505
506 static void register_755_sprs(CPUPPCState *env)
507 {
508 /* L2 cache control */
509 spr_register(env, SPR_L2CR, "L2CR",
510 SPR_NOACCESS, SPR_NOACCESS,
511 &spr_read_generic, spr_access_nop,
512 0x00000000);
513
514 spr_register(env, SPR_L2PMCR, "L2PMCR",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518 }
519
520 /* SPR common to all 7xx PowerPC implementations */
521 static void register_7xx_sprs(CPUPPCState *env)
522 {
523 /* Breakpoints */
524 spr_register_kvm(env, SPR_DABR, "DABR",
525 SPR_NOACCESS, SPR_NOACCESS,
526 &spr_read_generic, &spr_write_generic,
527 KVM_REG_PPC_DABR, 0x00000000);
528
529 spr_register(env, SPR_IABR, "IABR",
530 SPR_NOACCESS, SPR_NOACCESS,
531 &spr_read_generic, &spr_write_generic,
532 0x00000000);
533 /* Cache management */
534 spr_register(env, SPR_ICTC, "ICTC",
535 SPR_NOACCESS, SPR_NOACCESS,
536 &spr_read_generic, &spr_write_generic,
537 0x00000000);
538 /* Performance monitors */
539 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_generic, &spr_write_generic,
542 0x00000000);
543
544 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
545 SPR_NOACCESS, SPR_NOACCESS,
546 &spr_read_generic, &spr_write_generic,
547 0x00000000);
548
549 spr_register(env, SPR_7XX_PMC1, "PMC1",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_generic, &spr_write_generic,
552 0x00000000);
553
554 spr_register(env, SPR_7XX_PMC2, "PMC2",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_generic, &spr_write_generic,
557 0x00000000);
558
559 spr_register(env, SPR_7XX_PMC3, "PMC3",
560 SPR_NOACCESS, SPR_NOACCESS,
561 &spr_read_generic, &spr_write_generic,
562 0x00000000);
563
564 spr_register(env, SPR_7XX_PMC4, "PMC4",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_generic, &spr_write_generic,
567 0x00000000);
568
569 spr_register(env, SPR_7XX_SIAR, "SIAR",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_generic, SPR_NOACCESS,
572 0x00000000);
573
574 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
575 &spr_read_ureg, SPR_NOACCESS,
576 &spr_read_ureg, SPR_NOACCESS,
577 0x00000000);
578
579 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
580 &spr_read_ureg, SPR_NOACCESS,
581 &spr_read_ureg, SPR_NOACCESS,
582 0x00000000);
583
584 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
585 &spr_read_ureg, SPR_NOACCESS,
586 &spr_read_ureg, SPR_NOACCESS,
587 0x00000000);
588
589 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
590 &spr_read_ureg, SPR_NOACCESS,
591 &spr_read_ureg, SPR_NOACCESS,
592 0x00000000);
593
594 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
595 &spr_read_ureg, SPR_NOACCESS,
596 &spr_read_ureg, SPR_NOACCESS,
597 0x00000000);
598
599 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
600 &spr_read_ureg, SPR_NOACCESS,
601 &spr_read_ureg, SPR_NOACCESS,
602 0x00000000);
603
604 spr_register(env, SPR_7XX_USIAR, "USIAR",
605 &spr_read_ureg, SPR_NOACCESS,
606 &spr_read_ureg, SPR_NOACCESS,
607 0x00000000);
608 /* External access control */
609 spr_register(env, SPR_EAR, "EAR",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_generic, &spr_write_generic,
612 0x00000000);
613
614 /* Hardware implementation registers */
615 spr_register(env, SPR_HID0, "HID0",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_generic, &spr_write_generic,
618 0x00000000);
619
620 spr_register(env, SPR_HID1, "HID1",
621 SPR_NOACCESS, SPR_NOACCESS,
622 &spr_read_generic, &spr_write_generic,
623 0x00000000);
624 }
625
626 #ifdef TARGET_PPC64
627 static void register_amr_sprs(CPUPPCState *env)
628 {
629 #ifndef CONFIG_USER_ONLY
630 /*
631 * Virtual Page Class Key protection
632 *
633 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
634 * userspace accessible, 29 is privileged. So we only need to set
635 * the kvm ONE_REG id on one of them, we use 29
636 */
637 spr_register(env, SPR_UAMR, "UAMR",
638 &spr_read_generic, &spr_write_amr,
639 &spr_read_generic, &spr_write_amr,
640 0);
641 spr_register_kvm_hv(env, SPR_AMR, "AMR",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_amr,
644 &spr_read_generic, &spr_write_generic,
645 KVM_REG_PPC_AMR, 0);
646 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_uamor,
649 &spr_read_generic, &spr_write_generic,
650 KVM_REG_PPC_UAMOR, 0);
651 spr_register_hv(env, SPR_AMOR, "AMOR",
652 SPR_NOACCESS, SPR_NOACCESS,
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0);
656 #endif /* !CONFIG_USER_ONLY */
657 }
658
659 static void register_iamr_sprs(CPUPPCState *env)
660 {
661 #ifndef CONFIG_USER_ONLY
662 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_generic, &spr_write_iamr,
665 &spr_read_generic, &spr_write_generic,
666 KVM_REG_PPC_IAMR, 0);
667 #endif /* !CONFIG_USER_ONLY */
668 }
669 #endif /* TARGET_PPC64 */
670
671 static void register_thrm_sprs(CPUPPCState *env)
672 {
673 /* Thermal management */
674 spr_register(env, SPR_THRM1, "THRM1",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_thrm, &spr_write_generic,
677 0x00000000);
678
679 spr_register(env, SPR_THRM2, "THRM2",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_thrm, &spr_write_generic,
682 0x00000000);
683
684 spr_register(env, SPR_THRM3, "THRM3",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_thrm, &spr_write_generic,
687 0x00000000);
688 }
689
690 /* SPR specific to PowerPC 604 implementation */
691 static void register_604_sprs(CPUPPCState *env)
692 {
693 /* Processor identification */
694 spr_register(env, SPR_PIR, "PIR",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_generic, &spr_write_pir,
697 0x00000000);
698 /* Breakpoints */
699 spr_register(env, SPR_IABR, "IABR",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
702 0x00000000);
703
704 spr_register_kvm(env, SPR_DABR, "DABR",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, &spr_write_generic,
707 KVM_REG_PPC_DABR, 0x00000000);
708 /* Performance counters */
709 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713
714 spr_register(env, SPR_7XX_PMC1, "PMC1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718
719 spr_register(env, SPR_7XX_PMC2, "PMC2",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723
724 spr_register(env, SPR_7XX_SIAR, "SIAR",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, SPR_NOACCESS,
727 0x00000000);
728
729 spr_register(env, SPR_SDA, "SDA",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, SPR_NOACCESS,
732 0x00000000);
733 /* External access control */
734 spr_register(env, SPR_EAR, "EAR",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738
739 /* Hardware implementation registers */
740 spr_register(env, SPR_HID0, "HID0",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 }
745
746 static void register_604e_sprs(CPUPPCState *env)
747 {
748 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752
753 spr_register(env, SPR_7XX_PMC3, "PMC3",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757
758 spr_register(env, SPR_7XX_PMC4, "PMC4",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762 /* Hardware implementation registers */
763 spr_register(env, SPR_HID1, "HID1",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic,
766 0x00000000);
767 }
768
769 /* SPR specific to PowerPC 603 implementation */
770 static void register_603_sprs(CPUPPCState *env)
771 {
772 /* External access control */
773 spr_register(env, SPR_EAR, "EAR",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_generic, &spr_write_generic,
776 0x00000000);
777 /* Breakpoints */
778 spr_register(env, SPR_IABR, "IABR",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_generic,
781 0x00000000);
782
783 spr_register(env, SPR_HID0, "HID0",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, &spr_write_generic,
786 0x00000000);
787
788 spr_register(env, SPR_HID1, "HID1",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_generic, &spr_write_generic,
791 0x00000000);
792 }
793
794 static void register_e300_sprs(CPUPPCState *env)
795 {
796 /* hardware implementation registers */
797 spr_register(env, SPR_HID2, "HID2",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_generic, &spr_write_generic,
800 0x00000000);
801 /* Breakpoints */
802 spr_register(env, SPR_DABR, "DABR",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806
807 spr_register(env, SPR_DABR2, "DABR2",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
811
812 spr_register(env, SPR_IABR2, "IABR2",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816
817 spr_register(env, SPR_IBCR, "IBCR",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_generic, &spr_write_generic,
820 0x00000000);
821
822 spr_register(env, SPR_DBCR, "DBCR",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826 }
827
828 /* SPR specific to PowerPC G2 implementation */
829 static void register_G2_sprs(CPUPPCState *env)
830 {
831 /* Memory base address */
832 /* MBAR */
833 spr_register(env, SPR_MBAR, "MBAR",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_generic, &spr_write_generic,
836 0x00000000);
837 /* Exception processing */
838 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_generic, &spr_write_generic,
841 0x00000000);
842 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_generic, &spr_write_generic,
845 0x00000000);
846 /* Breakpoints */
847 spr_register(env, SPR_DABR, "DABR",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, &spr_write_generic,
850 0x00000000);
851
852 spr_register(env, SPR_DABR2, "DABR2",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, &spr_write_generic,
855 0x00000000);
856
857 spr_register(env, SPR_IABR, "IABR",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic, &spr_write_generic,
860 0x00000000);
861
862 spr_register(env, SPR_IABR2, "IABR2",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_generic,
865 0x00000000);
866
867 spr_register(env, SPR_IBCR, "IBCR",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, &spr_write_generic,
870 0x00000000);
871
872 spr_register(env, SPR_DBCR, "DBCR",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876
877 /* External access control */
878 spr_register(env, SPR_EAR, "EAR",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_generic,
881 0x00000000);
882 /* Hardware implementation register */
883 spr_register(env, SPR_HID0, "HID0",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887
888 spr_register(env, SPR_HID1, "HID1",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, &spr_write_generic,
891 0x00000000);
892
893 spr_register(env, SPR_HID2, "HID2",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_generic,
896 0x00000000);
897
898 /* SGPRs */
899 spr_register(env, SPR_SPRG4, "SPRG4",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, &spr_write_generic,
902 0x00000000);
903 spr_register(env, SPR_SPRG5, "SPRG5",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 spr_register(env, SPR_SPRG6, "SPRG6",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 spr_register(env, SPR_SPRG7, "SPRG7",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 }
916
917 static void register_74xx_sprs(CPUPPCState *env)
918 {
919 /* Breakpoints */
920 spr_register_kvm(env, SPR_DABR, "DABR",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 KVM_REG_PPC_DABR, 0x00000000);
924
925 spr_register(env, SPR_IABR, "IABR",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_generic, &spr_write_generic,
928 0x00000000);
929 /* Cache management */
930 spr_register(env, SPR_ICTC, "ICTC",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* Performance monitors */
935 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939
940 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944
945 spr_register(env, SPR_7XX_PMC1, "PMC1",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949
950 spr_register(env, SPR_7XX_PMC2, "PMC2",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954
955 spr_register(env, SPR_7XX_PMC3, "PMC3",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959
960 spr_register(env, SPR_7XX_PMC4, "PMC4",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964
965 spr_register(env, SPR_7XX_SIAR, "SIAR",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, SPR_NOACCESS,
968 0x00000000);
969
970 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
971 &spr_read_ureg, SPR_NOACCESS,
972 &spr_read_ureg, SPR_NOACCESS,
973 0x00000000);
974
975 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
976 &spr_read_ureg, SPR_NOACCESS,
977 &spr_read_ureg, SPR_NOACCESS,
978 0x00000000);
979
980 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984
985 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989
990 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994
995 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999
1000 spr_register(env, SPR_7XX_USIAR, "USIAR",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* External access control */
1005 spr_register(env, SPR_EAR, "EAR",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009
1010 /* Processor identification */
1011 spr_register(env, SPR_PIR, "PIR",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_pir,
1014 0x00000000);
1015
1016 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020
1021 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1022 &spr_read_ureg, SPR_NOACCESS,
1023 &spr_read_ureg, SPR_NOACCESS,
1024 0x00000000);
1025
1026 spr_register(env, SPR_BAMR, "BAMR",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030
1031 spr_register(env, SPR_MSSCR0, "MSSCR0",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* Hardware implementation registers */
1036 spr_register(env, SPR_HID0, "HID0",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040
1041 spr_register(env, SPR_HID1, "HID1",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* Altivec */
1046 spr_register(env, SPR_VRSAVE, "VRSAVE",
1047 &spr_read_generic, &spr_write_generic,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050
1051 spr_register(env, SPR_L2CR, "L2CR",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, spr_access_nop,
1054 0x00000000);
1055 }
1056
1057 static void register_l3_ctrl(CPUPPCState *env)
1058 {
1059 /* L3CR */
1060 spr_register(env, SPR_L3CR, "L3CR",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 /* L3ITCR0 */
1065 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1066 SPR_NOACCESS, SPR_NOACCESS,
1067 &spr_read_generic, &spr_write_generic,
1068 0x00000000);
1069 /* L3PM */
1070 spr_register(env, SPR_L3PM, "L3PM",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 &spr_read_generic, &spr_write_generic,
1073 0x00000000);
1074 }
1075
1076 static void register_usprg3_sprs(CPUPPCState *env)
1077 {
1078 spr_register(env, SPR_USPRG3, "USPRG3",
1079 &spr_read_ureg, SPR_NOACCESS,
1080 &spr_read_ureg, SPR_NOACCESS,
1081 0x00000000);
1082 }
1083
1084 static void register_usprgh_sprs(CPUPPCState *env)
1085 {
1086 spr_register(env, SPR_USPRG4, "USPRG4",
1087 &spr_read_ureg, SPR_NOACCESS,
1088 &spr_read_ureg, SPR_NOACCESS,
1089 0x00000000);
1090 spr_register(env, SPR_USPRG5, "USPRG5",
1091 &spr_read_ureg, SPR_NOACCESS,
1092 &spr_read_ureg, SPR_NOACCESS,
1093 0x00000000);
1094 spr_register(env, SPR_USPRG6, "USPRG6",
1095 &spr_read_ureg, SPR_NOACCESS,
1096 &spr_read_ureg, SPR_NOACCESS,
1097 0x00000000);
1098 spr_register(env, SPR_USPRG7, "USPRG7",
1099 &spr_read_ureg, SPR_NOACCESS,
1100 &spr_read_ureg, SPR_NOACCESS,
1101 0x00000000);
1102 }
1103
1104 /* PowerPC BookE SPR */
1105 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
1106 {
1107 const char *ivor_names[64] = {
1108 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1109 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1110 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1111 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1112 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1113 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1114 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1115 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1116 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1117 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1118 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1119 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1120 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1121 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1122 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1123 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1124 };
1125 #define SPR_BOOKE_IVORxx (-1)
1126 int ivor_sprn[64] = {
1127 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1128 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1129 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1130 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1131 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1132 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1133 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1134 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1135 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1136 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1137 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1138 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1139 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1140 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1141 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1142 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1143 };
1144 int i;
1145
1146 /* Interrupt processing */
1147 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* Debug */
1156 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160
1161 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165
1166 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_generic,
1169 0x00000000);
1170
1171 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1174 0x00000000);
1175
1176 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_40x_dbcr0,
1179 0x00000000);
1180
1181 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185
1186 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198
1199 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_clear,
1202 0x00000000);
1203 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 &spr_read_generic, &spr_write_generic,
1206 0x00000000);
1207 spr_register(env, SPR_BOOKE_ESR, "ESR",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_excp_prefix,
1214 0x00000000);
1215 /* Exception vectors */
1216 for (i = 0; i < 64; i++) {
1217 if (ivor_mask & (1ULL << i)) {
1218 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1219 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1220 exit(1);
1221 }
1222 spr_register(env, ivor_sprn[i], ivor_names[i],
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_excp_vector,
1225 0x00000000);
1226 }
1227 }
1228 spr_register(env, SPR_BOOKE_PID, "PID",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_booke_pid,
1231 0x00000000);
1232 spr_register(env, SPR_BOOKE_TCR, "TCR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_booke_tcr,
1235 0x00000000);
1236 spr_register(env, SPR_BOOKE_TSR, "TSR",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_booke_tsr,
1239 0x00000000);
1240 /* Timer */
1241 spr_register(env, SPR_DECR, "DECR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_decr, &spr_write_decr,
1244 0x00000000);
1245 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 SPR_NOACCESS, &spr_write_generic,
1248 0x00000000);
1249 /* SPRGs */
1250 spr_register(env, SPR_USPRG0, "USPRG0",
1251 &spr_read_generic, &spr_write_generic,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 spr_register(env, SPR_SPRG4, "SPRG4",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 spr_register(env, SPR_SPRG5, "SPRG5",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
1262 spr_register(env, SPR_SPRG6, "SPRG6",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 0x00000000);
1266 spr_register(env, SPR_SPRG7, "SPRG7",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
1274 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 }
1279
1280 #if !defined(CONFIG_USER_ONLY)
1281 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1282 uint32_t maxsize, uint32_t flags,
1283 uint32_t nentries)
1284 {
1285 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1286 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1287 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1288 flags | nentries;
1289 }
1290 #endif /* !CONFIG_USER_ONLY */
1291
1292 /* BookE 2.06 storage control registers */
1293 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1294 uint32_t *tlbncfg, uint32_t mmucfg)
1295 {
1296 #if !defined(CONFIG_USER_ONLY)
1297 const char *mas_names[8] = {
1298 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1299 };
1300 int mas_sprn[8] = {
1301 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1302 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1303 };
1304 int i;
1305
1306 /* TLB assist registers */
1307 for (i = 0; i < 8; i++) {
1308 if (mas_mask & (1 << i)) {
1309 spr_register(env, mas_sprn[i], mas_names[i],
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic,
1312 (i == 2 && (env->insns_flags & PPC_64B))
1313 ? &spr_write_generic : &spr_write_generic32,
1314 0x00000000);
1315 }
1316 }
1317 if (env->nb_pids > 1) {
1318 spr_register(env, SPR_BOOKE_PID1, "PID1",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_booke_pid,
1321 0x00000000);
1322 }
1323 if (env->nb_pids > 2) {
1324 spr_register(env, SPR_BOOKE_PID2, "PID2",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_booke_pid,
1327 0x00000000);
1328 }
1329
1330 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_eplc,
1333 0x00000000);
1334 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_epsc,
1337 0x00000000);
1338
1339 spr_register(env, SPR_MMUCFG, "MMUCFG",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, SPR_NOACCESS,
1342 mmucfg);
1343 switch (env->nb_ways) {
1344 case 4:
1345 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, SPR_NOACCESS,
1348 tlbncfg[3]);
1349 /* Fallthru */
1350 case 3:
1351 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, SPR_NOACCESS,
1354 tlbncfg[2]);
1355 /* Fallthru */
1356 case 2:
1357 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, SPR_NOACCESS,
1360 tlbncfg[1]);
1361 /* Fallthru */
1362 case 1:
1363 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, SPR_NOACCESS,
1366 tlbncfg[0]);
1367 /* Fallthru */
1368 case 0:
1369 default:
1370 break;
1371 }
1372 #endif
1373 }
1374
1375 /* SPR specific to PowerPC 440 implementation */
1376 static void register_440_sprs(CPUPPCState *env)
1377 {
1378 /* Cache control */
1379 spr_register(env, SPR_440_DNV0, "DNV0",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383
1384 spr_register(env, SPR_440_DNV1, "DNV1",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388
1389 spr_register(env, SPR_440_DNV2, "DNV2",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393
1394 spr_register(env, SPR_440_DNV3, "DNV3",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398
1399 spr_register(env, SPR_440_DTV0, "DTV0",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403
1404 spr_register(env, SPR_440_DTV1, "DTV1",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
1408
1409 spr_register(env, SPR_440_DTV2, "DTV2",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413
1414 spr_register(env, SPR_440_DTV3, "DTV3",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418
1419 spr_register(env, SPR_440_DVLIM, "DVLIM",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423
1424 spr_register(env, SPR_440_INV0, "INV0",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428
1429 spr_register(env, SPR_440_INV1, "INV1",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433
1434 spr_register(env, SPR_440_INV2, "INV2",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438
1439 spr_register(env, SPR_440_INV3, "INV3",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443
1444 spr_register(env, SPR_440_ITV0, "ITV0",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448
1449 spr_register(env, SPR_440_ITV1, "ITV1",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453
1454 spr_register(env, SPR_440_ITV2, "ITV2",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458
1459 spr_register(env, SPR_440_ITV3, "ITV3",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463
1464 spr_register(env, SPR_440_IVLIM, "IVLIM",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468 /* Cache debug */
1469 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, SPR_NOACCESS,
1472 0x00000000);
1473
1474 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, SPR_NOACCESS,
1477 0x00000000);
1478
1479 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, SPR_NOACCESS,
1482 0x00000000);
1483
1484 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, SPR_NOACCESS,
1487 0x00000000);
1488
1489 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, SPR_NOACCESS,
1492 0x00000000);
1493
1494 spr_register(env, SPR_440_DBDR, "DBDR",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* Processor control */
1499 spr_register(env, SPR_4xx_CCR0, "CCR0",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, SPR_NOACCESS,
1506 0x00000000);
1507 /* Storage control */
1508 spr_register(env, SPR_440_MMUCR, "MMUCR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512
1513 /* Processor identification */
1514 spr_register(env, SPR_BOOKE_PIR, "PIR",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_pir,
1517 0x00000000);
1518
1519 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523
1524 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
1528
1529 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
1533
1534 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 }
1539
1540 /* SPR shared between PowerPC 40x implementations */
1541 static void register_40x_sprs(CPUPPCState *env)
1542 {
1543 /* Cache */
1544 /* not emulated, as QEMU do not emulate caches */
1545 spr_register(env, SPR_40x_DCCR, "DCCR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 /* not emulated, as QEMU do not emulate caches */
1550 spr_register(env, SPR_40x_ICCR, "ICCR",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 /* not emulated, as QEMU do not emulate caches */
1555 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, SPR_NOACCESS,
1558 0x00000000);
1559 /* Exception */
1560 spr_register(env, SPR_40x_DEAR, "DEAR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 spr_register(env, SPR_40x_ESR, "ESR",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 spr_register(env, SPR_40x_EVPR, "EVPR",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_excp_prefix,
1571 0x00000000);
1572 spr_register(env, SPR_40x_SRR2, "SRR2",
1573 &spr_read_generic, &spr_write_generic,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 spr_register(env, SPR_40x_SRR3, "SRR3",
1577 &spr_read_generic, &spr_write_generic,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580 /* Timers */
1581 spr_register(env, SPR_40x_PIT, "PIT",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_40x_pit, &spr_write_40x_pit,
1584 0x00000000);
1585 spr_register(env, SPR_40x_TCR, "TCR",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_40x_tcr,
1588 0x00000000);
1589 spr_register(env, SPR_40x_TSR, "TSR",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_40x_tsr,
1592 0x00000000);
1593 }
1594
1595 /* SPR specific to PowerPC 405 implementation */
1596 static void register_405_sprs(CPUPPCState *env)
1597 {
1598 /* MMU */
1599 spr_register(env, SPR_40x_PID, "PID",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_40x_pid,
1602 0x00000000);
1603 spr_register(env, SPR_4xx_CCR0, "CCR0",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00700000);
1607 /* Debug interface */
1608 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_40x_dbcr0,
1611 0x00000000);
1612
1613 spr_register(env, SPR_405_DBCR1, "DBCR1",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic,
1616 0x00000000);
1617
1618 spr_register(env, SPR_40x_DBSR, "DBSR",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_clear,
1621 /* Last reset was system reset */
1622 0x00000300);
1623
1624 spr_register(env, SPR_40x_DAC1, "DAC1",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 spr_register(env, SPR_40x_DAC2, "DAC2",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1631 0x00000000);
1632
1633 spr_register(env, SPR_405_DVC1, "DVC1",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1636 0x00000000);
1637
1638 spr_register(env, SPR_405_DVC2, "DVC2",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642
1643 spr_register(env, SPR_40x_IAC1, "IAC1",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 spr_register(env, SPR_40x_IAC2, "IAC2",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651
1652 spr_register(env, SPR_405_IAC3, "IAC3",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656
1657 spr_register(env, SPR_405_IAC4, "IAC4",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* Storage control */
1662 spr_register(env, SPR_405_SLER, "SLER",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_40x_sler,
1665 0x00000000);
1666 spr_register(env, SPR_40x_ZPR, "ZPR",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1669 0x00000000);
1670
1671 spr_register(env, SPR_405_SU0R, "SU0R",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 /* SPRG */
1676 spr_register(env, SPR_USPRG0, "USPRG0",
1677 &spr_read_ureg, SPR_NOACCESS,
1678 &spr_read_ureg, SPR_NOACCESS,
1679 0x00000000);
1680 spr_register(env, SPR_SPRG4, "SPRG4",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684 spr_register(env, SPR_SPRG5, "SPRG5",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 spr_register(env, SPR_SPRG6, "SPRG6",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 spr_register(env, SPR_SPRG7, "SPRG7",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696
1697 /* Bus access control */
1698 /* not emulated, as QEMU never does speculative access */
1699 spr_register(env, SPR_40x_SGR, "SGR",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0xFFFFFFFF);
1703 /* not emulated, as QEMU do not emulate caches */
1704 spr_register(env, SPR_40x_DCWR, "DCWR",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 }
1709
1710
1711 static void register_5xx_8xx_sprs(CPUPPCState *env)
1712 {
1713 /* Exception processing */
1714 spr_register_kvm(env, SPR_DSISR, "DSISR",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 KVM_REG_PPC_DSISR, 0x00000000);
1718 spr_register_kvm(env, SPR_DAR, "DAR",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 KVM_REG_PPC_DAR, 0x00000000);
1722 /* Timer */
1723 spr_register(env, SPR_DECR, "DECR",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_decr, &spr_write_decr,
1726 0x00000000);
1727
1728 spr_register(env, SPR_MPC_EIE, "EIE",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732
1733 spr_register(env, SPR_MPC_EID, "EID",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737
1738 spr_register(env, SPR_MPC_NRI, "NRI",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742
1743 spr_register(env, SPR_MPC_CMPA, "CMPA",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747
1748 spr_register(env, SPR_MPC_CMPB, "CMPB",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752
1753 spr_register(env, SPR_MPC_CMPC, "CMPC",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757
1758 spr_register(env, SPR_MPC_CMPD, "CMPD",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762
1763 spr_register(env, SPR_MPC_ECR, "ECR",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767
1768 spr_register(env, SPR_MPC_DER, "DER",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772
1773 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777
1778 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782
1783 spr_register(env, SPR_MPC_CMPE, "CMPE",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787
1788 spr_register(env, SPR_MPC_CMPF, "CMPF",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792
1793 spr_register(env, SPR_MPC_CMPG, "CMPG",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
1797
1798 spr_register(env, SPR_MPC_CMPH, "CMPH",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802
1803 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
1807
1808 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812
1813 spr_register(env, SPR_MPC_BAR, "BAR",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817
1818 spr_register(env, SPR_MPC_DPDR, "DPDR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822
1823 spr_register(env, SPR_MPC_IMMR, "IMMR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 }
1828
1829 static void register_5xx_sprs(CPUPPCState *env)
1830 {
1831 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835
1836 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, &spr_write_generic,
1839 0x00000000);
1840
1841 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_generic,
1844 0x00000000);
1845
1846 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_generic,
1849 0x00000000);
1850
1851 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
1855
1856 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, &spr_write_generic,
1859 0x00000000);
1860
1861 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_generic, &spr_write_generic,
1864 0x00000000);
1865
1866 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870
1871 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875
1876 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880
1881 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885
1886 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890
1891 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895
1896 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900
1901 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905
1906 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910
1911 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915
1916 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1917 SPR_NOACCESS, SPR_NOACCESS,
1918 &spr_read_generic, &spr_write_generic,
1919 0x00000000);
1920
1921 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925
1926 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_generic,
1929 0x00000000);
1930
1931 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_generic,
1934 0x00000000);
1935 }
1936
1937 static void register_8xx_sprs(CPUPPCState *env)
1938 {
1939
1940 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944
1945 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 &spr_read_generic, &spr_write_generic,
1948 0x00000000);
1949
1950 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1951 SPR_NOACCESS, SPR_NOACCESS,
1952 &spr_read_generic, &spr_write_generic,
1953 0x00000000);
1954
1955 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959
1960 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
1964
1965 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_generic,
1968 0x00000000);
1969
1970 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974
1975 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979
1980 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, &spr_write_generic,
1983 0x00000000);
1984
1985 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989
1990 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994
1995 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999
2000 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004
2005 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009
2010 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014
2015 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0x00000000);
2019
2020 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024
2025 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029
2030 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034
2035 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039
2040 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
2044
2045 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2049
2050 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0x00000000);
2054
2055 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059
2060 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 }
2065
2066 /*
2067 * AMR => SPR 29 (Power 2.04)
2068 * CTRL => SPR 136 (Power 2.04)
2069 * CTRL => SPR 152 (Power 2.04)
2070 * SCOMC => SPR 276 (64 bits ?)
2071 * SCOMD => SPR 277 (64 bits ?)
2072 * TBU40 => SPR 286 (Power 2.04 hypv)
2073 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2074 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2075 * HDSISR => SPR 306 (Power 2.04 hypv)
2076 * HDAR => SPR 307 (Power 2.04 hypv)
2077 * PURR => SPR 309 (Power 2.04 hypv)
2078 * HDEC => SPR 310 (Power 2.04 hypv)
2079 * HIOR => SPR 311 (hypv)
2080 * RMOR => SPR 312 (970)
2081 * HRMOR => SPR 313 (Power 2.04 hypv)
2082 * HSRR0 => SPR 314 (Power 2.04 hypv)
2083 * HSRR1 => SPR 315 (Power 2.04 hypv)
2084 * LPIDR => SPR 317 (970)
2085 * EPR => SPR 702 (Power 2.04 emb)
2086 * perf => 768-783 (Power 2.04)
2087 * perf => 784-799 (Power 2.04)
2088 * PPR => SPR 896 (Power 2.04)
2089 * DABRX => 1015 (Power 2.04 hypv)
2090 * FPECR => SPR 1022 (?)
2091 * ... and more (thermal management, performance counters, ...)
2092 */
2093
2094 /*****************************************************************************/
2095 /* Exception vectors models */
2096 static void init_excp_4xx_softmmu(CPUPPCState *env)
2097 {
2098 #if !defined(CONFIG_USER_ONLY)
2099 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2100 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2101 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2102 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2103 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2104 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2105 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2106 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2107 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2108 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2109 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2110 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2111 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2112 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2113 env->ivor_mask = 0x0000FFF0UL;
2114 env->ivpr_mask = 0xFFFF0000UL;
2115 /* Hardware reset vector */
2116 env->hreset_vector = 0xFFFFFFFCUL;
2117 #endif
2118 }
2119
2120 static void init_excp_MPC5xx(CPUPPCState *env)
2121 {
2122 #if !defined(CONFIG_USER_ONLY)
2123 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2125 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2126 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2127 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2128 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2129 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2130 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2131 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2132 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2133 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2134 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2135 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2136 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2137 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2138 env->ivor_mask = 0x0000FFF0UL;
2139 env->ivpr_mask = 0xFFFF0000UL;
2140 /* Hardware reset vector */
2141 env->hreset_vector = 0x00000100UL;
2142 #endif
2143 }
2144
2145 static void init_excp_MPC8xx(CPUPPCState *env)
2146 {
2147 #if !defined(CONFIG_USER_ONLY)
2148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2149 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2150 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2151 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2152 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2153 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2154 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2155 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2156 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2158 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2159 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2160 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2161 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2162 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2163 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2164 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2165 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2166 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2167 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2168 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2169 env->ivor_mask = 0x0000FFF0UL;
2170 env->ivpr_mask = 0xFFFF0000UL;
2171 /* Hardware reset vector */
2172 env->hreset_vector = 0x00000100UL;
2173 #endif
2174 }
2175
2176 static void init_excp_G2(CPUPPCState *env)
2177 {
2178 #if !defined(CONFIG_USER_ONLY)
2179 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2180 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2181 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2182 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2183 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2184 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2185 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2186 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2187 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2188 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2189 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2190 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2191 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2192 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2193 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2194 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2195 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2196 /* Hardware reset vector */
2197 env->hreset_vector = 0x00000100UL;
2198 #endif
2199 }
2200
2201 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2202 {
2203 #if !defined(CONFIG_USER_ONLY)
2204 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2205 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2206 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2207 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2208 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2209 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2210 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2211 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2212 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2213 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2214 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2215 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2216 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2217 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2218 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2219 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2220 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2221 /*
2222 * These two are the same IVOR as POWERPC_EXCP_VPU and
2223 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
2224 * powerpc_excp().
2225 */
2226 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2227 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2228
2229 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2230 env->ivor_mask = 0x0000FFF7UL;
2231 env->ivpr_mask = ivpr_mask;
2232 /* Hardware reset vector */
2233 env->hreset_vector = 0xFFFFFFFCUL;
2234 #endif
2235 }
2236
2237 static void init_excp_BookE(CPUPPCState *env)
2238 {
2239 #if !defined(CONFIG_USER_ONLY)
2240 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2241 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2242 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2243 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2244 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2245 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2246 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2247 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2248 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2249 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2250 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2251 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2252 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2253 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2254 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2255 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2256 env->ivor_mask = 0x0000FFF0UL;
2257 env->ivpr_mask = 0xFFFF0000UL;
2258 /* Hardware reset vector */
2259 env->hreset_vector = 0xFFFFFFFCUL;
2260 #endif
2261 }
2262
2263 static void init_excp_603(CPUPPCState *env)
2264 {
2265 #if !defined(CONFIG_USER_ONLY)
2266 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2267 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2268 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2269 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2270 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2271 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2272 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2273 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2274 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2275 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2276 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2277 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2278 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2279 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2280 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2281 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2282 /* Hardware reset vector */
2283 env->hreset_vector = 0x00000100UL;
2284 #endif
2285 }
2286
2287 static void init_excp_604(CPUPPCState *env)
2288 {
2289 #if !defined(CONFIG_USER_ONLY)
2290 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2291 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2292 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2293 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2294 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2295 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2296 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2297 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2298 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2299 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2300 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2301 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2302 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2303 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2304 /* Hardware reset vector */
2305 env->hreset_vector = 0x00000100UL;
2306 #endif
2307 }
2308
2309 static void init_excp_7x0(CPUPPCState *env)
2310 {
2311 #if !defined(CONFIG_USER_ONLY)
2312 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2313 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2314 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2315 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2321 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2322 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2323 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2324 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2325 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2326 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2327 /* Hardware reset vector */
2328 env->hreset_vector = 0x00000100UL;
2329 #endif
2330 }
2331
2332 static void init_excp_750cl(CPUPPCState *env)
2333 {
2334 #if !defined(CONFIG_USER_ONLY)
2335 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2336 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2337 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2338 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2339 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2340 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2341 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2342 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2343 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2344 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2345 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2346 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2349 /* Hardware reset vector */
2350 env->hreset_vector = 0x00000100UL;
2351 #endif
2352 }
2353
2354 static void init_excp_750cx(CPUPPCState *env)
2355 {
2356 #if !defined(CONFIG_USER_ONLY)
2357 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2358 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2359 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2360 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2361 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2362 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2363 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2364 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2365 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2366 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2367 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2368 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2369 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2370 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2371 /* Hardware reset vector */
2372 env->hreset_vector = 0x00000100UL;
2373 #endif
2374 }
2375
2376 /* XXX: Check if this is correct */
2377 static void init_excp_7x5(CPUPPCState *env)
2378 {
2379 #if !defined(CONFIG_USER_ONLY)
2380 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2381 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2382 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2383 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2384 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2385 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2386 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2387 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2388 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2389 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2390 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2391 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2392 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2393 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2394 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2395 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2396 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2397 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2398 /* Hardware reset vector */
2399 env->hreset_vector = 0x00000100UL;
2400 #endif
2401 }
2402
2403 static void init_excp_7400(CPUPPCState *env)
2404 {
2405 #if !defined(CONFIG_USER_ONLY)
2406 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2407 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2408 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2409 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2410 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2411 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2412 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2413 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2414 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2415 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2416 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2417 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2418 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2419 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2420 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2421 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2422 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2423 /* Hardware reset vector */
2424 env->hreset_vector = 0x00000100UL;
2425 #endif
2426 }
2427
2428 static void init_excp_7450(CPUPPCState *env)
2429 {
2430 #if !defined(CONFIG_USER_ONLY)
2431 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2432 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2433 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2434 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2435 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2436 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2437 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2438 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2439 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2440 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2441 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2442 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2443 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2444 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2445 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2446 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2447 /* Hardware reset vector */
2448 env->hreset_vector = 0x00000100UL;
2449 #endif
2450 }
2451
2452 #if defined(TARGET_PPC64)
2453 static void init_excp_970(CPUPPCState *env)
2454 {
2455 #if !defined(CONFIG_USER_ONLY)
2456 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2457 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2458 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2459 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2460 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2461 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2462 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2463 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2464 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2465 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2466 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2467 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2468 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2469 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2470 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2471 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2472 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2473 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2474 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2475 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2476 /* Hardware reset vector */
2477 env->hreset_vector = 0x0000000000000100ULL;
2478 #endif
2479 }
2480
2481 static void init_excp_POWER7(CPUPPCState *env)
2482 {
2483 #if !defined(CONFIG_USER_ONLY)
2484 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2485 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2486 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2487 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2488 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2489 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2490 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2491 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2492 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2493 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2494 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2495 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2496 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2497 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2498 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2499 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2500 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2501 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2502 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2503 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2504 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2505 /* Hardware reset vector */
2506 env->hreset_vector = 0x0000000000000100ULL;
2507 #endif
2508 }
2509
2510 static void init_excp_POWER8(CPUPPCState *env)
2511 {
2512 init_excp_POWER7(env);
2513
2514 #if !defined(CONFIG_USER_ONLY)
2515 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2516 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2517 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2518 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2519 #endif
2520 }
2521
2522 static void init_excp_POWER9(CPUPPCState *env)
2523 {
2524 init_excp_POWER8(env);
2525
2526 #if !defined(CONFIG_USER_ONLY)
2527 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2528 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2529 #endif
2530 }
2531
2532 static void init_excp_POWER10(CPUPPCState *env)
2533 {
2534 init_excp_POWER9(env);
2535 }
2536
2537 #endif
2538
2539 /*****************************************************************************/
2540 /* Power management enable checks */
2541 static int check_pow_none(CPUPPCState *env)
2542 {
2543 return 0;
2544 }
2545
2546 static int check_pow_nocheck(CPUPPCState *env)
2547 {
2548 return 1;
2549 }
2550
2551 static int check_pow_hid0(CPUPPCState *env)
2552 {
2553 if (env->spr[SPR_HID0] & 0x00E00000) {
2554 return 1;
2555 }
2556
2557 return 0;
2558 }
2559
2560 static int check_pow_hid0_74xx(CPUPPCState *env)
2561 {
2562 if (env->spr[SPR_HID0] & 0x00600000) {
2563 return 1;
2564 }
2565
2566 return 0;
2567 }
2568
2569 /*****************************************************************************/
2570 /* PowerPC implementations definitions */
2571
2572 #define POWERPC_FAMILY(_name) \
2573 static void \
2574 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2575 \
2576 static const TypeInfo \
2577 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2578 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2579 .parent = TYPE_POWERPC_CPU, \
2580 .abstract = true, \
2581 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2582 }; \
2583 \
2584 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2585 { \
2586 type_register_static( \
2587 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2588 } \
2589 \
2590 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2591 \
2592 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2593
2594 static void init_proc_405(CPUPPCState *env)
2595 {
2596 register_40x_sprs(env);
2597 register_405_sprs(env);
2598 register_usprgh_sprs(env);
2599
2600 /* Memory management */
2601 #if !defined(CONFIG_USER_ONLY)
2602 env->nb_tlb = 64;
2603 env->nb_ways = 1;
2604 env->id_tlbs = 0;
2605 env->tlb_type = TLB_EMB;
2606 #endif
2607 init_excp_4xx_softmmu(env);
2608 env->dcache_line_size = 32;
2609 env->icache_line_size = 32;
2610 /* Allocate hardware IRQ controller */
2611 ppc40x_irq_init(env_archcpu(env));
2612
2613 SET_FIT_PERIOD(8, 12, 16, 20);
2614 SET_WDT_PERIOD(16, 20, 24, 28);
2615 }
2616
2617 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2618 {
2619 DeviceClass *dc = DEVICE_CLASS(oc);
2620 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2621
2622 dc->desc = "PowerPC 405";
2623 pcc->init_proc = init_proc_405;
2624 pcc->check_pow = check_pow_nocheck;
2625 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2626 PPC_DCR | PPC_WRTEE |
2627 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2628 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2629 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2630 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2631 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2632 pcc->msr_mask = (1ull << MSR_WE) |
2633 (1ull << MSR_CE) |
2634 (1ull << MSR_EE) |
2635 (1ull << MSR_PR) |
2636 (1ull << MSR_FP) |
2637 (1ull << MSR_ME) |
2638 (1ull << MSR_DWE) |
2639 (1ull << MSR_DE) |
2640 (1ull << MSR_IR) |
2641 (1ull << MSR_DR);
2642 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2643 pcc->excp_model = POWERPC_EXCP_40x;
2644 pcc->bus_model = PPC_FLAGS_INPUT_405;
2645 pcc->bfd_mach = bfd_mach_ppc_403;
2646 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2647 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2648 }
2649
2650 static void init_proc_440EP(CPUPPCState *env)
2651 {
2652 register_BookE_sprs(env, 0x000000000000FFFFULL);
2653 register_440_sprs(env);
2654 register_usprgh_sprs(env);
2655
2656 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2661 SPR_NOACCESS, SPR_NOACCESS,
2662 &spr_read_generic, &spr_write_generic,
2663 0x00000000);
2664 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2665 SPR_NOACCESS, SPR_NOACCESS,
2666 &spr_read_generic, &spr_write_generic,
2667 0x00000000);
2668
2669 spr_register(env, SPR_440_CCR1, "CCR1",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 /* Memory management */
2674 #if !defined(CONFIG_USER_ONLY)
2675 env->nb_tlb = 64;
2676 env->nb_ways = 1;
2677 env->id_tlbs = 0;
2678 env->tlb_type = TLB_EMB;
2679 #endif
2680 init_excp_BookE(env);
2681 env->dcache_line_size = 32;
2682 env->icache_line_size = 32;
2683 ppc40x_irq_init(env_archcpu(env));
2684
2685 SET_FIT_PERIOD(12, 16, 20, 24);
2686 SET_WDT_PERIOD(20, 24, 28, 32);
2687 }
2688
2689 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2690 {
2691 DeviceClass *dc = DEVICE_CLASS(oc);
2692 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2693
2694 dc->desc = "PowerPC 440 EP";
2695 pcc->init_proc = init_proc_440EP;
2696 pcc->check_pow = check_pow_nocheck;
2697 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2698 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2699 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2700 PPC_FLOAT_STFIWX |
2701 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2702 PPC_CACHE | PPC_CACHE_ICBI |
2703 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2704 PPC_MEM_TLBSYNC | PPC_MFTB |
2705 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2706 PPC_440_SPEC;
2707 pcc->msr_mask = (1ull << MSR_POW) |
2708 (1ull << MSR_CE) |
2709 (1ull << MSR_EE) |
2710 (1ull << MSR_PR) |
2711 (1ull << MSR_FP) |
2712 (1ull << MSR_ME) |
2713 (1ull << MSR_FE0) |
2714 (1ull << MSR_DWE) |
2715 (1ull << MSR_DE) |
2716 (1ull << MSR_FE1) |
2717 (1ull << MSR_IR) |
2718 (1ull << MSR_DR);
2719 pcc->mmu_model = POWERPC_MMU_BOOKE;
2720 pcc->excp_model = POWERPC_EXCP_BOOKE;
2721 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2722 pcc->bfd_mach = bfd_mach_ppc_403;
2723 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2724 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2725 }
2726
2727 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2728 {
2729 DeviceClass *dc = DEVICE_CLASS(oc);
2730 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2731
2732 dc->desc = "PowerPC 460 EX";
2733 pcc->init_proc = init_proc_440EP;
2734 pcc->check_pow = check_pow_nocheck;
2735 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2736 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2737 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2738 PPC_FLOAT_STFIWX |
2739 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2740 PPC_CACHE | PPC_CACHE_ICBI |
2741 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2742 PPC_MEM_TLBSYNC | PPC_MFTB |
2743 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2744 PPC_440_SPEC;
2745 pcc->msr_mask = (1ull << MSR_POW) |
2746 (1ull << MSR_CE) |
2747 (1ull << MSR_EE) |
2748 (1ull << MSR_PR) |
2749 (1ull << MSR_FP) |
2750 (1ull << MSR_ME) |
2751 (1ull << MSR_FE0) |
2752 (1ull << MSR_DWE) |
2753 (1ull << MSR_DE) |
2754 (1ull << MSR_FE1) |
2755 (1ull << MSR_IR) |
2756 (1ull << MSR_DR);
2757 pcc->mmu_model = POWERPC_MMU_BOOKE;
2758 pcc->excp_model = POWERPC_EXCP_BOOKE;
2759 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2760 pcc->bfd_mach = bfd_mach_ppc_403;
2761 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2762 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2763 }
2764
2765 static void init_proc_440GP(CPUPPCState *env)
2766 {
2767 register_BookE_sprs(env, 0x000000000000FFFFULL);
2768 register_440_sprs(env);
2769 register_usprgh_sprs(env);
2770
2771 /* Memory management */
2772 #if !defined(CONFIG_USER_ONLY)
2773 env->nb_tlb = 64;
2774 env->nb_ways = 1;
2775 env->id_tlbs = 0;
2776 env->tlb_type = TLB_EMB;
2777 #endif
2778 init_excp_BookE(env);
2779 env->dcache_line_size = 32;
2780 env->icache_line_size = 32;
2781 /* XXX: TODO: allocate internal IRQ controller */
2782
2783 SET_FIT_PERIOD(12, 16, 20, 24);
2784 SET_WDT_PERIOD(20, 24, 28, 32);
2785 }
2786
2787 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2788 {
2789 DeviceClass *dc = DEVICE_CLASS(oc);
2790 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2791
2792 dc->desc = "PowerPC 440 GP";
2793 pcc->init_proc = init_proc_440GP;
2794 pcc->check_pow = check_pow_nocheck;
2795 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2796 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2797 PPC_CACHE | PPC_CACHE_ICBI |
2798 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2799 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2800 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2801 PPC_440_SPEC;
2802 pcc->msr_mask = (1ull << MSR_POW) |
2803 (1ull << MSR_CE) |
2804 (1ull << MSR_EE) |
2805 (1ull << MSR_PR) |
2806 (1ull << MSR_FP) |
2807 (1ull << MSR_ME) |
2808 (1ull << MSR_FE0) |
2809 (1ull << MSR_DWE) |
2810 (1ull << MSR_DE) |
2811 (1ull << MSR_FE1) |
2812 (1ull << MSR_IR) |
2813 (1ull << MSR_DR);
2814 pcc->mmu_model = POWERPC_MMU_BOOKE;
2815 pcc->excp_model = POWERPC_EXCP_BOOKE;
2816 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2817 pcc->bfd_mach = bfd_mach_ppc_403;
2818 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2819 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2820 }
2821
2822 static void init_proc_440x5(CPUPPCState *env)
2823 {
2824 register_BookE_sprs(env, 0x000000000000FFFFULL);
2825 register_440_sprs(env);
2826 register_usprgh_sprs(env);
2827
2828 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2829 SPR_NOACCESS, SPR_NOACCESS,
2830 &spr_read_generic, &spr_write_generic,
2831 0x00000000);
2832 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2833 SPR_NOACCESS, SPR_NOACCESS,
2834 &spr_read_generic, &spr_write_generic,
2835 0x00000000);
2836 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2837 SPR_NOACCESS, SPR_NOACCESS,
2838 &spr_read_generic, &spr_write_generic,
2839 0x00000000);
2840
2841 spr_register(env, SPR_440_CCR1, "CCR1",
2842 SPR_NOACCESS, SPR_NOACCESS,
2843 &spr_read_generic, &spr_write_generic,
2844 0x00000000);
2845 /* Memory management */
2846 #if !defined(CONFIG_USER_ONLY)
2847 env->nb_tlb = 64;
2848 env->nb_ways = 1;
2849 env->id_tlbs = 0;
2850 env->tlb_type = TLB_EMB;
2851 #endif
2852 init_excp_BookE(env);
2853 env->dcache_line_size = 32;
2854 env->icache_line_size = 32;
2855 ppc40x_irq_init(env_archcpu(env));
2856
2857 SET_FIT_PERIOD(12, 16, 20, 24);
2858 SET_WDT_PERIOD(20, 24, 28, 32);
2859 }
2860
2861 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2862 {
2863 DeviceClass *dc = DEVICE_CLASS(oc);
2864 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2865
2866 dc->desc = "PowerPC 440x5";
2867 pcc->init_proc = init_proc_440x5;
2868 pcc->check_pow = check_pow_nocheck;
2869 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2870 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2871 PPC_CACHE | PPC_CACHE_ICBI |
2872 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2873 PPC_MEM_TLBSYNC | PPC_MFTB |
2874 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2875 PPC_440_SPEC;
2876 pcc->msr_mask = (1ull << MSR_POW) |
2877 (1ull << MSR_CE) |
2878 (1ull << MSR_EE) |
2879 (1ull << MSR_PR) |
2880 (1ull << MSR_FP) |
2881 (1ull << MSR_ME) |
2882 (1ull << MSR_FE0) |
2883 (1ull << MSR_DWE) |
2884 (1ull << MSR_DE) |
2885 (1ull << MSR_FE1) |
2886 (1ull << MSR_IR) |
2887 (1ull << MSR_DR);
2888 pcc->mmu_model = POWERPC_MMU_BOOKE;
2889 pcc->excp_model = POWERPC_EXCP_BOOKE;
2890 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2891 pcc->bfd_mach = bfd_mach_ppc_403;
2892 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2893 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2894 }
2895
2896 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2897 {
2898 DeviceClass *dc = DEVICE_CLASS(oc);
2899 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2900
2901 dc->desc = "PowerPC 440x5 with double precision FPU";
2902 pcc->init_proc = init_proc_440x5;
2903 pcc->check_pow = check_pow_nocheck;
2904 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2905 PPC_FLOAT | PPC_FLOAT_FSQRT |
2906 PPC_FLOAT_STFIWX |
2907 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2908 PPC_CACHE | PPC_CACHE_ICBI |
2909 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2910 PPC_MEM_TLBSYNC | PPC_MFTB |
2911 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2912 PPC_440_SPEC;
2913 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2914 pcc->msr_mask = (1ull << MSR_POW) |
2915 (1ull << MSR_CE) |
2916 (1ull << MSR_EE) |
2917 (1ull << MSR_PR) |
2918 (1ull << MSR_FP) |
2919 (1ull << MSR_ME) |
2920 (1ull << MSR_FE0) |
2921 (1ull << MSR_DWE) |
2922 (1ull << MSR_DE) |
2923 (1ull << MSR_FE1) |
2924 (1ull << MSR_IR) |
2925 (1ull << MSR_DR);
2926 pcc->mmu_model = POWERPC_MMU_BOOKE;
2927 pcc->excp_model = POWERPC_EXCP_BOOKE;
2928 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2929 pcc->bfd_mach = bfd_mach_ppc_403;
2930 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2931 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2932 }
2933
2934 static void init_proc_MPC5xx(CPUPPCState *env)
2935 {
2936 register_5xx_8xx_sprs(env);
2937 register_5xx_sprs(env);
2938 init_excp_MPC5xx(env);
2939 env->dcache_line_size = 32;
2940 env->icache_line_size = 32;
2941 /* XXX: TODO: allocate internal IRQ controller */
2942 }
2943
2944 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2945 {
2946 DeviceClass *dc = DEVICE_CLASS(oc);
2947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2948
2949 dc->desc = "Freescale 5xx cores (aka RCPU)";
2950 pcc->init_proc = init_proc_MPC5xx;
2951 pcc->check_pow = check_pow_none;
2952 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2953 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2954 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2955 PPC_MFTB;
2956 pcc->msr_mask = (1ull << MSR_ILE) |
2957 (1ull << MSR_EE) |
2958 (1ull << MSR_PR) |
2959 (1ull << MSR_FP) |
2960 (1ull << MSR_ME) |
2961 (1ull << MSR_FE0) |
2962 (1ull << MSR_SE) |
2963 (1ull << MSR_DE) |
2964 (1ull << MSR_FE1) |
2965 (1ull << MSR_EP) |
2966 (1ull << MSR_RI) |
2967 (1ull << MSR_LE);
2968 pcc->mmu_model = POWERPC_MMU_REAL;
2969 pcc->excp_model = POWERPC_EXCP_6xx;
2970 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2971 pcc->bfd_mach = bfd_mach_ppc_505;
2972 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2973 POWERPC_FLAG_BUS_CLK;
2974 }
2975
2976 static void init_proc_MPC8xx(CPUPPCState *env)
2977 {
2978 register_5xx_8xx_sprs(env);
2979 register_8xx_sprs(env);
2980 init_excp_MPC8xx(env);
2981 env->dcache_line_size = 32;
2982 env->icache_line_size = 32;
2983 /* XXX: TODO: allocate internal IRQ controller */
2984 }
2985
2986 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2987 {
2988 DeviceClass *dc = DEVICE_CLASS(oc);
2989 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2990
2991 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2992 pcc->init_proc = init_proc_MPC8xx;
2993 pcc->check_pow = check_pow_none;
2994 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2995 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2996 PPC_CACHE_ICBI | PPC_MFTB;
2997 pcc->msr_mask = (1ull << MSR_ILE) |
2998 (1ull << MSR_EE) |
2999 (1ull << MSR_PR) |
3000 (1ull << MSR_FP) |
3001 (1ull << MSR_ME) |
3002 (1ull << MSR_SE) |
3003 (1ull << MSR_DE) |
3004 (1ull << MSR_EP) |
3005 (1ull << MSR_IR) |
3006 (1ull << MSR_DR) |
3007 (1ull << MSR_RI) |
3008 (1ull << MSR_LE);
3009 pcc->mmu_model = POWERPC_MMU_MPC8xx;
3010 pcc->excp_model = POWERPC_EXCP_6xx;
3011 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3012 pcc->bfd_mach = bfd_mach_ppc_860;
3013 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3014 POWERPC_FLAG_BUS_CLK;
3015 }
3016
3017 /* Freescale 82xx cores (aka PowerQUICC-II) */
3018
3019 static void init_proc_G2(CPUPPCState *env)
3020 {
3021 register_ne_601_sprs(env);
3022 register_sdr1_sprs(env);
3023 register_G2_sprs(env);
3024
3025 /* Memory management */
3026 register_low_BATs(env);
3027 register_high_BATs(env);
3028 register_6xx_7xx_soft_tlb(env, 64, 2);
3029 init_excp_G2(env);
3030 env->dcache_line_size = 32;
3031 env->icache_line_size = 32;
3032 /* Allocate hardware IRQ controller */
3033 ppc6xx_irq_init(env_archcpu(env));
3034 }
3035
3036 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3037 {
3038 DeviceClass *dc = DEVICE_CLASS(oc);
3039 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3040
3041 dc->desc = "PowerPC G2";
3042 pcc->init_proc = init_proc_G2;
3043 pcc->check_pow = check_pow_hid0;
3044 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3045 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3046 PPC_FLOAT_STFIWX |
3047 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3048 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3049 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3050 PPC_SEGMENT | PPC_EXTERN;
3051 pcc->msr_mask = (1ull << MSR_POW) |
3052 (1ull << MSR_TGPR) |
3053 (1ull << MSR_EE) |
3054 (1ull << MSR_PR) |
3055 (1ull << MSR_FP) |
3056 (1ull << MSR_ME) |
3057 (1ull << MSR_FE0) |
3058 (1ull << MSR_SE) |
3059 (1ull << MSR_DE) |
3060 (1ull << MSR_FE1) |
3061 (1ull << MSR_AL) |
3062 (1ull << MSR_EP) |
3063 (1ull << MSR_IR) |
3064 (1ull << MSR_DR) |
3065 (1ull << MSR_RI);
3066 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3067 pcc->excp_model = POWERPC_EXCP_6xx;
3068 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3069 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3070 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3071 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3072 }
3073
3074 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3075 {
3076 DeviceClass *dc = DEVICE_CLASS(oc);
3077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3078
3079 dc->desc = "PowerPC G2LE";
3080 pcc->init_proc = init_proc_G2;
3081 pcc->check_pow = check_pow_hid0;
3082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3084 PPC_FLOAT_STFIWX |
3085 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3086 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3087 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3088 PPC_SEGMENT | PPC_EXTERN;
3089 pcc->msr_mask = (1ull << MSR_POW) |
3090 (1ull << MSR_TGPR) |
3091 (1ull << MSR_ILE) |
3092 (1ull << MSR_EE) |
3093 (1ull << MSR_PR) |
3094 (1ull << MSR_FP) |
3095 (1ull << MSR_ME) |
3096 (1ull << MSR_FE0) |
3097 (1ull << MSR_SE) |
3098 (1ull << MSR_DE) |
3099 (1ull << MSR_FE1) |
3100 (1ull << MSR_AL) |
3101 (1ull << MSR_EP) |
3102 (1ull << MSR_IR) |
3103 (1ull << MSR_DR) |
3104 (1ull << MSR_RI) |
3105 (1ull << MSR_LE);
3106 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3107 pcc->excp_model = POWERPC_EXCP_6xx;
3108 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3109 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3110 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3111 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3112 }
3113
3114 static void init_proc_e200(CPUPPCState *env)
3115 {
3116 register_BookE_sprs(env, 0x000000070000FFFFULL);
3117
3118 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3119 &spr_read_spefscr, &spr_write_spefscr,
3120 &spr_read_spefscr, &spr_write_spefscr,
3121 0x00000000);
3122 /* Memory management */
3123 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3124 register_usprgh_sprs(env);
3125
3126 spr_register(env, SPR_HID0, "HID0",
3127 SPR_NOACCESS, SPR_NOACCESS,
3128 &spr_read_generic, &spr_write_generic,
3129 0x00000000);
3130
3131 spr_register(env, SPR_HID1, "HID1",
3132 SPR_NOACCESS, SPR_NOACCESS,
3133 &spr_read_generic, &spr_write_generic,
3134 0x00000000);
3135
3136 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3137 SPR_NOACCESS, SPR_NOACCESS,
3138 &spr_read_generic, &spr_write_generic,
3139 0x00000000);
3140
3141 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3142 SPR_NOACCESS, SPR_NOACCESS,
3143 &spr_read_generic, &spr_write_generic,
3144 0x00000000);
3145
3146 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3147 SPR_NOACCESS, SPR_NOACCESS,
3148 &spr_read_generic, &spr_write_generic,
3149 0x00000000);
3150
3151 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3152 SPR_NOACCESS, SPR_NOACCESS,
3153 &spr_read_generic, &spr_write_generic,
3154 0x00000000);
3155
3156 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3157 SPR_NOACCESS, SPR_NOACCESS,
3158 &spr_read_generic, &spr_write_generic,
3159 0x00000000);
3160
3161 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3162 &spr_read_generic, SPR_NOACCESS,
3163 &spr_read_generic, SPR_NOACCESS,
3164 0x00000000);
3165
3166 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3167 SPR_NOACCESS, SPR_NOACCESS,
3168 &spr_read_generic, &spr_write_generic,
3169 0x00000000);
3170
3171 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3172 SPR_NOACCESS, SPR_NOACCESS,
3173 &spr_read_generic, &spr_write_generic,
3174 0x00000000);
3175
3176 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3177 SPR_NOACCESS, SPR_NOACCESS,
3178 &spr_read_generic, &spr_write_generic,
3179 0x00000000);
3180
3181 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3182 SPR_NOACCESS, SPR_NOACCESS,
3183 &spr_read_generic, &spr_write_generic,
3184 0x00000000);
3185
3186 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3187 SPR_NOACCESS, SPR_NOACCESS,
3188 &spr_read_generic, &spr_write_generic,
3189 0x00000000);
3190
3191 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3192 SPR_NOACCESS, SPR_NOACCESS,
3193 &spr_read_generic, &spr_write_generic,
3194 0x00000000);
3195
3196 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3197 SPR_NOACCESS, SPR_NOACCESS,
3198 &spr_read_generic, &spr_write_generic,
3199 0x00000000); /* TOFIX */
3200 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3201 SPR_NOACCESS, SPR_NOACCESS,
3202 &spr_read_generic, &spr_write_generic,
3203 0x00000000);
3204 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3205 SPR_NOACCESS, SPR_NOACCESS,
3206 &spr_read_generic, &spr_write_generic,
3207 0x00000000);
3208 #if !defined(CONFIG_USER_ONLY)
3209 env->nb_tlb = 64;
3210 env->nb_ways = 1;
3211 env->id_tlbs = 0;
3212 env->tlb_type = TLB_EMB;
3213 #endif
3214 init_excp_e200(env, 0xFFFF0000UL);
3215 env->dcache_line_size = 32;
3216 env->icache_line_size = 32;
3217 /* XXX: TODO: allocate internal IRQ controller */
3218 }
3219
3220 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3221 {
3222 DeviceClass *dc = DEVICE_CLASS(oc);
3223 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3224
3225 dc->desc = "e200 core";
3226 pcc->init_proc = init_proc_e200;
3227 pcc->check_pow = check_pow_hid0;
3228 /*
3229 * XXX: unimplemented instructions:
3230 * dcblc
3231 * dcbtlst
3232 * dcbtstls
3233 * icblc
3234 * icbtls
3235 * tlbivax
3236 * all SPE multiply-accumulate instructions
3237 */
3238 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3239 PPC_SPE | PPC_SPE_SINGLE |
3240 PPC_WRTEE | PPC_RFDI |
3241 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3242 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3243 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3244 PPC_BOOKE;
3245 pcc->msr_mask = (1ull << MSR_UCLE) |
3246 (1ull << MSR_SPE) |
3247 (1ull << MSR_POW) |
3248 (1ull << MSR_CE) |
3249 (1ull << MSR_EE) |
3250 (1ull << MSR_PR) |
3251 (1ull << MSR_FP) |
3252 (1ull << MSR_ME) |
3253 (1ull << MSR_FE0) |
3254 (1ull << MSR_DWE) |
3255 (1ull << MSR_DE) |
3256 (1ull << MSR_FE1) |
3257 (1ull << MSR_IR) |
3258 (1ull << MSR_DR);
3259 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3260 pcc->excp_model = POWERPC_EXCP_BOOKE;
3261 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3262 pcc->bfd_mach = bfd_mach_ppc_860;
3263 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3264 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3265 POWERPC_FLAG_BUS_CLK;
3266 }
3267
3268 enum fsl_e500_version {
3269 fsl_e500v1,
3270 fsl_e500v2,
3271 fsl_e500mc,
3272 fsl_e5500,
3273 fsl_e6500,
3274 };
3275
3276 static void init_proc_e500(CPUPPCState *env, int version)
3277 {
3278 uint32_t tlbncfg[2];
3279 uint64_t ivor_mask;
3280 uint64_t ivpr_mask = 0xFFFF0000ULL;
3281 uint32_t l1cfg0 = 0x3800 /* 8 ways */
3282 | 0x0020; /* 32 kb */
3283 uint32_t l1cfg1 = 0x3800 /* 8 ways */
3284 | 0x0020; /* 32 kb */
3285 uint32_t mmucfg = 0;
3286 #if !defined(CONFIG_USER_ONLY)
3287 int i;
3288 #endif
3289
3290 /*
3291 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
3292 * complain when accessing them.
3293 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
3294 */
3295 switch (version) {
3296 case fsl_e500v1:
3297 case fsl_e500v2:
3298 default:
3299 ivor_mask = 0x0000000F0000FFFFULL;
3300 break;
3301 case fsl_e500mc:
3302 case fsl_e5500:
3303 ivor_mask = 0x000003FE0000FFFFULL;
3304 break;
3305 case fsl_e6500:
3306 ivor_mask = 0x000003FF0000FFFFULL;
3307 break;
3308 }
3309 register_BookE_sprs(env, ivor_mask);
3310 register_usprg3_sprs(env);
3311 /* Processor identification */
3312 spr_register(env, SPR_BOOKE_PIR, "PIR",
3313 SPR_NOACCESS, SPR_NOACCESS,
3314 &spr_read_generic, &spr_write_pir,
3315 0x00000000);
3316
3317 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3318 &spr_read_spefscr, &spr_write_spefscr,
3319 &spr_read_spefscr, &spr_write_spefscr,
3320 0x00000000);
3321 #if !defined(CONFIG_USER_ONLY)
3322 /* Memory management */
3323 env->nb_pids = 3;
3324 env->nb_ways = 2;
3325 env->id_tlbs = 0;
3326 switch (version) {
3327 case fsl_e500v1:
3328 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
3329 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3330 break;
3331 case fsl_e500v2:
3332 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3333 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3334 break;
3335 case fsl_e500mc:
3336 case fsl_e5500:
3337 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3338 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
3339 break;
3340 case fsl_e6500:
3341 mmucfg = 0x6510B45;
3342 env->nb_pids = 1;
3343 tlbncfg[0] = 0x08052400;
3344 tlbncfg[1] = 0x40028040;
3345 break;
3346 default:
3347 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3348 env->spr[SPR_PVR]);
3349 }
3350 #endif
3351 /* Cache sizes */
3352 switch (version) {
3353 case fsl_e500v1:
3354 case fsl_e500v2:
3355 env->dcache_line_size = 32;
3356 env->icache_line_size = 32;
3357 break;
3358 case fsl_e500mc:
3359 case fsl_e5500:
3360 env->dcache_line_size = 64;
3361 env->icache_line_size = 64;
3362 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
3363 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
3364 break;
3365 case fsl_e6500:
3366 env->dcache_line_size = 32;
3367 env->icache_line_size = 32;
3368 l1cfg0 |= 0x0F83820;
3369 l1cfg1 |= 0x0B83820;
3370 break;
3371 default:
3372 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3373 env->spr[SPR_PVR]);
3374 }
3375 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
3376 register_usprgh_sprs(env);
3377
3378 spr_register(env, SPR_HID0, "HID0",
3379 SPR_NOACCESS, SPR_NOACCESS,
3380 &spr_read_generic, &spr_write_generic,
3381 0x00000000);
3382
3383 spr_register(env, SPR_HID1, "HID1",
3384 SPR_NOACCESS, SPR_NOACCESS,
3385 &spr_read_generic, &spr_write_generic,
3386 0x00000000);
3387
3388 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
3389 SPR_NOACCESS, SPR_NOACCESS,
3390 &spr_read_generic, &spr_write_generic,
3391 0x00000000);
3392
3393 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
3394 SPR_NOACCESS, SPR_NOACCESS,
3395 &spr_read_generic, &spr_write_generic,
3396 0x00000000);
3397
3398 spr_register(env, SPR_Exxx_MCAR, "MCAR",
3399 SPR_NOACCESS, SPR_NOACCESS,
3400 &spr_read_generic, &spr_write_generic,
3401 0x00000000);
3402
3403 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3404 SPR_NOACCESS, SPR_NOACCESS,
3405 &spr_read_generic, &spr_write_generic,
3406 0x00000000);
3407
3408 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
3409 SPR_NOACCESS, SPR_NOACCESS,
3410 &spr_read_generic, &spr_write_generic,
3411 0x00000000);
3412
3413 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3414 SPR_NOACCESS, SPR_NOACCESS,
3415 &spr_read_generic, &spr_write_generic,
3416 0x00000000);
3417
3418 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3419 &spr_read_generic, SPR_NOACCESS,
3420 &spr_read_generic, SPR_NOACCESS,
3421 l1cfg0);
3422 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
3423 &spr_read_generic, SPR_NOACCESS,
3424 &spr_read_generic, SPR_NOACCESS,
3425 l1cfg1);
3426 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3427 SPR_NOACCESS, SPR_NOACCESS,
3428 &spr_read_generic, &spr_write_e500_l1csr0,
3429 0x00000000);
3430 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
3431 SPR_NOACCESS, SPR_NOACCESS,
3432 &spr_read_generic, &spr_write_e500_l1csr1,
3433 0x00000000);
3434 if (version != fsl_e500v1 && version != fsl_e500v2) {
3435 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
3436 SPR_NOACCESS, SPR_NOACCESS,
3437 &spr_read_generic, &spr_write_e500_l2csr0,
3438 0x00000000);
3439 }
3440 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0x00000000);
3444 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3445 SPR_NOACCESS, SPR_NOACCESS,
3446 &spr_read_generic, &spr_write_generic,
3447 0x00000000);
3448 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3449 SPR_NOACCESS, SPR_NOACCESS,
3450 &spr_read_generic, &spr_write_booke206_mmucsr0,
3451 0x00000000);
3452 spr_register(env, SPR_BOOKE_EPR, "EPR",
3453 SPR_NOACCESS, SPR_NOACCESS,
3454 &spr_read_generic, SPR_NOACCESS,
3455 0x00000000);
3456 /* XXX better abstract into Emb.xxx features */
3457 if ((version == fsl_e5500) || (version == fsl_e6500)) {
3458 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
3459 SPR_NOACCESS, SPR_NOACCESS,
3460 &spr_read_generic, &spr_write_generic,
3461 0x00000000);
3462 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
3463 SPR_NOACCESS, SPR_NOACCESS,
3464 &spr_read_mas73, &spr_write_mas73,
3465 0x00000000);
3466 ivpr_mask = (target_ulong)~0xFFFFULL;
3467 }
3468
3469 if (version == fsl_e6500) {
3470 /* Thread identification */
3471 spr_register(env, SPR_TIR, "TIR",
3472 SPR_NOACCESS, SPR_NOACCESS,
3473 &spr_read_generic, SPR_NOACCESS,
3474 0x00000000);
3475 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3476 SPR_NOACCESS, SPR_NOACCESS,
3477 &spr_read_generic, SPR_NOACCESS,
3478 0x00000004);
3479 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3480 SPR_NOACCESS, SPR_NOACCESS,
3481 &spr_read_generic, SPR_NOACCESS,
3482 0x7FFFFFFC);
3483 }
3484
3485 #if !defined(CONFIG_USER_ONLY)
3486 env->nb_tlb = 0;
3487 env->tlb_type = TLB_MAS;
3488 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3489 env->nb_tlb += booke206_tlb_size(env, i);
3490 }
3491 #endif
3492
3493 init_excp_e200(env, ivpr_mask);
3494 /* Allocate hardware IRQ controller */
3495 ppce500_irq_init(env_archcpu(env));
3496 }
3497
3498 static void init_proc_e500v1(CPUPPCState *env)
3499 {
3500 init_proc_e500(env, fsl_e500v1);
3501 }
3502
3503 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3504 {
3505 DeviceClass *dc = DEVICE_CLASS(oc);
3506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3507
3508 dc->desc = "e500v1 core";
3509 pcc->init_proc = init_proc_e500v1;
3510 pcc->check_pow = check_pow_hid0;
3511 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3512 PPC_SPE | PPC_SPE_SINGLE |
3513 PPC_WRTEE | PPC_RFDI |
3514 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3515 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3516 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3517 pcc->insns_flags2 = PPC2_BOOKE206;
3518 pcc->msr_mask = (1ull << MSR_UCLE) |
3519 (1ull << MSR_SPE) |
3520 (1ull << MSR_POW) |
3521 (1ull << MSR_CE) |
3522 (1ull << MSR_EE) |
3523 (1ull << MSR_PR) |
3524 (1ull << MSR_FP) |
3525 (1ull << MSR_ME) |
3526 (1ull << MSR_FE0) |
3527 (1ull << MSR_DWE) |
3528 (1ull << MSR_DE) |
3529 (1ull << MSR_FE1) |
3530 (1ull << MSR_IR) |
3531 (1ull << MSR_DR);
3532 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3533 pcc->excp_model = POWERPC_EXCP_BOOKE;
3534 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3535 pcc->bfd_mach = bfd_mach_ppc_860;
3536 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3537 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3538 POWERPC_FLAG_BUS_CLK;
3539 }
3540
3541 static void init_proc_e500v2(CPUPPCState *env)
3542 {
3543 init_proc_e500(env, fsl_e500v2);
3544 }
3545
3546 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3547 {
3548 DeviceClass *dc = DEVICE_CLASS(oc);
3549 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3550
3551 dc->desc = "e500v2 core";
3552 pcc->init_proc = init_proc_e500v2;
3553 pcc->check_pow = check_pow_hid0;
3554 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3555 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3556 PPC_WRTEE | PPC_RFDI |
3557 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3558 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3559 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3560 pcc->insns_flags2 = PPC2_BOOKE206;
3561 pcc->msr_mask = (1ull << MSR_UCLE) |
3562 (1ull << MSR_SPE) |
3563 (1ull << MSR_POW) |
3564 (1ull << MSR_CE) |
3565 (1ull << MSR_EE) |
3566 (1ull << MSR_PR) |
3567 (1ull << MSR_FP) |
3568 (1ull << MSR_ME) |
3569 (1ull << MSR_FE0) |
3570 (1ull << MSR_DWE) |
3571 (1ull << MSR_DE) |
3572 (1ull << MSR_FE1) |
3573 (1ull << MSR_IR) |
3574 (1ull << MSR_DR);
3575 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3576 pcc->excp_model = POWERPC_EXCP_BOOKE;
3577 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3578 pcc->bfd_mach = bfd_mach_ppc_860;
3579 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3580 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3581 POWERPC_FLAG_BUS_CLK;
3582 }
3583
3584 static void init_proc_e500mc(CPUPPCState *env)
3585 {
3586 init_proc_e500(env, fsl_e500mc);
3587 }
3588
3589 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3590 {
3591 DeviceClass *dc = DEVICE_CLASS(oc);
3592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3593
3594 dc->desc = "e500mc core";
3595 pcc->init_proc = init_proc_e500mc;
3596 pcc->check_pow = check_pow_none;
3597 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3598 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3599 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3600 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3601 PPC_FLOAT | PPC_FLOAT_FRES |
3602 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3603 PPC_FLOAT_STFIWX | PPC_WAIT |
3604 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3605 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3606 pcc->msr_mask = (1ull << MSR_GS) |
3607 (1ull << MSR_UCLE) |
3608 (1ull << MSR_CE) |
3609 (1ull << MSR_EE) |
3610 (1ull << MSR_PR) |
3611 (1ull << MSR_FP) |
3612 (1ull << MSR_ME) |
3613 (1ull << MSR_FE0) |
3614 (1ull << MSR_DE) |
3615 (1ull << MSR_FE1) |
3616 (1ull << MSR_IR) |
3617 (1ull << MSR_DR) |
3618 (1ull << MSR_PX) |
3619 (1ull << MSR_RI);
3620 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3621 pcc->excp_model = POWERPC_EXCP_BOOKE;
3622 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3623 /* FIXME: figure out the correct flag for e500mc */
3624 pcc->bfd_mach = bfd_mach_ppc_e500;
3625 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3626 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3627 }
3628
3629 #ifdef TARGET_PPC64
3630 static void init_proc_e5500(CPUPPCState *env)
3631 {
3632 init_proc_e500(env, fsl_e5500);
3633 }
3634
3635 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3636 {
3637 DeviceClass *dc = DEVICE_CLASS(oc);
3638 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3639
3640 dc->desc = "e5500 core";
3641 pcc->init_proc = init_proc_e5500;
3642 pcc->check_pow = check_pow_none;
3643 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3644 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3645 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3646 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3647 PPC_FLOAT | PPC_FLOAT_FRES |
3648 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3649 PPC_FLOAT_STFIWX | PPC_WAIT |
3650 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3651 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3652 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3653 PPC2_FP_CVT_S64;
3654 pcc->msr_mask = (1ull << MSR_CM) |
3655 (1ull << MSR_GS) |
3656 (1ull << MSR_UCLE) |
3657 (1ull << MSR_CE) |
3658 (1ull << MSR_EE) |
3659 (1ull << MSR_PR) |
3660 (1ull << MSR_FP) |
3661 (1ull << MSR_ME) |
3662 (1ull << MSR_FE0) |
3663 (1ull << MSR_DE) |
3664 (1ull << MSR_FE1) |
3665 (1ull << MSR_IR) |
3666 (1ull << MSR_DR) |
3667 (1ull << MSR_PX) |
3668 (1ull << MSR_RI);
3669 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3670 pcc->excp_model = POWERPC_EXCP_BOOKE;
3671 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3672 /* FIXME: figure out the correct flag for e5500 */
3673 pcc->bfd_mach = bfd_mach_ppc_e500;
3674 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3675 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3676 }
3677
3678 static void init_proc_e6500(CPUPPCState *env)
3679 {
3680 init_proc_e500(env, fsl_e6500);
3681 }
3682
3683 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3684 {
3685 DeviceClass *dc = DEVICE_CLASS(oc);
3686 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3687
3688 dc->desc = "e6500 core";
3689 pcc->init_proc = init_proc_e6500;
3690 pcc->check_pow = check_pow_none;
3691 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3692 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3693 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3694 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3695 PPC_FLOAT | PPC_FLOAT_FRES |
3696 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3697 PPC_FLOAT_STFIWX | PPC_WAIT |
3698 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3699 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3700 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3701 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3702 pcc->msr_mask = (1ull << MSR_CM) |
3703 (1ull << MSR_GS) |
3704 (1ull << MSR_UCLE) |
3705 (1ull << MSR_CE) |
3706 (1ull << MSR_EE) |
3707 (1ull << MSR_PR) |
3708 (1ull << MSR_FP) |
3709 (1ull << MSR_ME) |
3710 (1ull << MSR_FE0) |
3711 (1ull << MSR_DE) |
3712 (1ull << MSR_FE1) |
3713 (1ull << MSR_IS) |
3714 (1ull << MSR_DS) |
3715 (1ull << MSR_PX) |
3716 (1ull << MSR_RI) |
3717 (1ull << MSR_VR);
3718 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3719 pcc->excp_model = POWERPC_EXCP_BOOKE;
3720 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3721 pcc->bfd_mach = bfd_mach_ppc_e500;
3722 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3723 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3724 }
3725
3726 #endif
3727
3728 /* Non-embedded PowerPC */
3729 static void init_proc_603(CPUPPCState *env)
3730 {
3731 register_ne_601_sprs(env);
3732 register_sdr1_sprs(env);
3733 register_603_sprs(env);
3734
3735 /* Memory management */
3736 register_low_BATs(env);
3737 register_6xx_7xx_soft_tlb(env, 64, 2);
3738 init_excp_603(env);
3739 env->dcache_line_size = 32;
3740 env->icache_line_size = 32;
3741 /* Allocate hardware IRQ controller */
3742 ppc6xx_irq_init(env_archcpu(env));
3743 }
3744
3745 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3746 {
3747 DeviceClass *dc = DEVICE_CLASS(oc);
3748 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3749
3750 dc->desc = "PowerPC 603";
3751 pcc->init_proc = init_proc_603;
3752 pcc->check_pow = check_pow_hid0;
3753 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3754 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3755 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3756 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3757 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3758 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3759 PPC_SEGMENT | PPC_EXTERN;
3760 pcc->msr_mask = (1ull << MSR_POW) |
3761 (1ull << MSR_TGPR) |
3762 (1ull << MSR_ILE) |
3763 (1ull << MSR_EE) |
3764 (1ull << MSR_PR) |
3765 (1ull << MSR_FP) |
3766 (1ull << MSR_ME) |
3767 (1ull << MSR_FE0) |
3768 (1ull << MSR_SE) |
3769 (1ull << MSR_DE) |
3770 (1ull << MSR_FE1) |
3771 (1ull << MSR_EP) |
3772 (1ull << MSR_IR) |
3773 (1ull << MSR_DR) |
3774 (1ull << MSR_RI) |
3775 (1ull << MSR_LE);
3776 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3777 pcc->excp_model = POWERPC_EXCP_6xx;
3778 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3779 pcc->bfd_mach = bfd_mach_ppc_603;
3780 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3781 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3782 }
3783
3784 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3785 {
3786 DeviceClass *dc = DEVICE_CLASS(oc);
3787 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3788
3789 dc->desc = "PowerPC 603e";
3790 pcc->init_proc = init_proc_603;
3791 pcc->check_pow = check_pow_hid0;
3792 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3793 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3794 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3795 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3796 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3797 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3798 PPC_SEGMENT | PPC_EXTERN;
3799 pcc->msr_mask = (1ull << MSR_POW) |
3800 (1ull << MSR_TGPR) |
3801 (1ull << MSR_ILE) |
3802 (1ull << MSR_EE) |
3803 (1ull << MSR_PR) |
3804 (1ull << MSR_FP) |
3805 (1ull << MSR_ME) |
3806 (1ull << MSR_FE0) |
3807 (1ull << MSR_SE) |
3808 (1ull << MSR_DE) |
3809 (1ull << MSR_FE1) |
3810 (1ull << MSR_EP) |
3811 (1ull << MSR_IR) |
3812 (1ull << MSR_DR) |
3813 (1ull << MSR_RI) |
3814 (1ull << MSR_LE);
3815 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3816 pcc->excp_model = POWERPC_EXCP_6xx;
3817 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3818 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3819 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3820 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3821 }
3822
3823 static void init_proc_e300(CPUPPCState *env)
3824 {
3825 init_proc_603(env);
3826 register_e300_sprs(env);
3827 }
3828
3829 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3830 {
3831 DeviceClass *dc = DEVICE_CLASS(oc);
3832 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3833
3834 dc->desc = "e300 core";
3835 pcc->init_proc = init_proc_e300;
3836 pcc->check_pow = check_pow_hid0;
3837 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3838 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3839 PPC_FLOAT_STFIWX |
3840 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3841 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3842 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3843 PPC_SEGMENT | PPC_EXTERN;
3844 pcc->msr_mask = (1ull << MSR_POW) |
3845 (1ull << MSR_TGPR) |
3846 (1ull << MSR_ILE) |
3847 (1ull << MSR_EE) |
3848 (1ull << MSR_PR) |
3849 (1ull << MSR_FP) |
3850 (1ull << MSR_ME) |
3851 (1ull << MSR_FE0) |
3852 (1ull << MSR_SE) |
3853 (1ull << MSR_DE) |
3854 (1ull << MSR_FE1) |
3855 (1ull << MSR_AL) |
3856 (1ull << MSR_EP) |
3857 (1ull << MSR_IR) |
3858 (1ull << MSR_DR) |
3859 (1ull << MSR_RI) |
3860 (1ull << MSR_LE);
3861 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3862 pcc->excp_model = POWERPC_EXCP_6xx;
3863 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3864 pcc->bfd_mach = bfd_mach_ppc_603;
3865 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3866 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3867 }
3868
3869 static void init_proc_604(CPUPPCState *env)
3870 {
3871 register_ne_601_sprs(env);
3872 register_sdr1_sprs(env);
3873 register_604_sprs(env);
3874
3875 /* Memory management */
3876 register_low_BATs(env);
3877 init_excp_604(env);
3878 env->dcache_line_size = 32;
3879 env->icache_line_size = 32;
3880 /* Allocate hardware IRQ controller */
3881 ppc6xx_irq_init(env_archcpu(env));
3882 }
3883
3884 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3885 {
3886 DeviceClass *dc = DEVICE_CLASS(oc);
3887 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3888
3889 dc->desc = "PowerPC 604";
3890 pcc->init_proc = init_proc_604;
3891 pcc->check_pow = check_pow_nocheck;
3892 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3893 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3894 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3895 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3896 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3897 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3898 PPC_SEGMENT | PPC_EXTERN;
3899 pcc->msr_mask = (1ull << MSR_POW) |
3900 (1ull << MSR_ILE) |
3901 (1ull << MSR_EE) |
3902 (1ull << MSR_PR) |
3903 (1ull << MSR_FP) |
3904 (1ull << MSR_ME) |
3905 (1ull << MSR_FE0) |
3906 (1ull << MSR_SE) |
3907 (1ull << MSR_DE) |
3908 (1ull << MSR_FE1) |
3909 (1ull << MSR_EP) |
3910 (1ull << MSR_IR) |
3911 (1ull << MSR_DR) |
3912 (1ull << MSR_PMM) |
3913 (1ull << MSR_RI) |
3914 (1ull << MSR_LE);
3915 pcc->mmu_model = POWERPC_MMU_32B;
3916 pcc->excp_model = POWERPC_EXCP_6xx;
3917 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3918 pcc->bfd_mach = bfd_mach_ppc_604;
3919 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3920 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3921 }
3922
3923 static void init_proc_604E(CPUPPCState *env)
3924 {
3925 init_proc_604(env);
3926 register_604e_sprs(env);
3927 }
3928
3929 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3930 {
3931 DeviceClass *dc = DEVICE_CLASS(oc);
3932 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3933
3934 dc->desc = "PowerPC 604E";
3935 pcc->init_proc = init_proc_604E;
3936 pcc->check_pow = check_pow_nocheck;
3937 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3938 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3939 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3940 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3941 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3942 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3943 PPC_SEGMENT | PPC_EXTERN;
3944 pcc->msr_mask = (1ull << MSR_POW) |
3945 (1ull << MSR_ILE) |
3946 (1ull << MSR_EE) |
3947 (1ull << MSR_PR) |
3948 (1ull << MSR_FP) |
3949 (1ull << MSR_ME) |
3950 (1ull << MSR_FE0) |
3951 (1ull << MSR_SE) |
3952 (1ull << MSR_DE) |
3953 (1ull << MSR_FE1) |
3954 (1ull << MSR_EP) |
3955 (1ull << MSR_IR) |
3956 (1ull << MSR_DR) |
3957 (1ull << MSR_PMM) |
3958 (1ull << MSR_RI) |
3959 (1ull << MSR_LE);
3960 pcc->mmu_model = POWERPC_MMU_32B;
3961 pcc->excp_model = POWERPC_EXCP_6xx;
3962 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3963 pcc->bfd_mach = bfd_mach_ppc_604;
3964 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3965 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3966 }
3967
3968 static void init_proc_740(CPUPPCState *env)
3969 {
3970 register_ne_601_sprs(env);
3971 register_sdr1_sprs(env);
3972 register_7xx_sprs(env);
3973 /* Thermal management */
3974 register_thrm_sprs(env);
3975
3976 /* Memory management */
3977 register_low_BATs(env);
3978 init_excp_7x0(env);
3979 env->dcache_line_size = 32;
3980 env->icache_line_size = 32;
3981 /* Allocate hardware IRQ controller */
3982 ppc6xx_irq_init(env_archcpu(env));
3983 }
3984
3985 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3986 {
3987 DeviceClass *dc = DEVICE_CLASS(oc);
3988 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3989
3990 dc->desc = "PowerPC 740";
3991 pcc->init_proc = init_proc_740;
3992 pcc->check_pow = check_pow_hid0;
3993 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3994 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3995 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3996 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3997 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3998 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3999 PPC_SEGMENT | PPC_EXTERN;
4000 pcc->msr_mask = (1ull << MSR_POW) |
4001 (1ull << MSR_ILE) |
4002 (1ull << MSR_EE) |
4003 (1ull << MSR_PR) |
4004 (1ull << MSR_FP) |
4005 (1ull << MSR_ME) |
4006 (1ull << MSR_FE0) |
4007 (1ull << MSR_SE) |
4008 (1ull << MSR_DE) |
4009 (1ull << MSR_FE1) |
4010 (1ull << MSR_EP) |
4011 (1ull << MSR_IR) |
4012 (1ull << MSR_DR) |
4013 (1ull << MSR_PMM) |
4014 (1ull << MSR_RI) |
4015 (1ull << MSR_LE);
4016 pcc->mmu_model = POWERPC_MMU_32B;
4017 pcc->excp_model = POWERPC_EXCP_7xx;
4018 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4019 pcc->bfd_mach = bfd_mach_ppc_750;
4020 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4021 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4022 }
4023
4024 static void init_proc_750(CPUPPCState *env)
4025 {
4026 register_ne_601_sprs(env);
4027 register_sdr1_sprs(env);
4028 register_7xx_sprs(env);
4029
4030 spr_register(env, SPR_L2CR, "L2CR",
4031 SPR_NOACCESS, SPR_NOACCESS,
4032 &spr_read_generic, spr_access_nop,
4033 0x00000000);
4034 /* Thermal management */
4035 register_thrm_sprs(env);
4036
4037 /* Memory management */
4038 register_low_BATs(env);
4039 /*
4040 * XXX: high BATs are also present but are known to be bugged on
4041 * die version 1.x
4042 */
4043 init_excp_7x0(env);
4044 env->dcache_line_size = 32;
4045 env->icache_line_size = 32;
4046 /* Allocate hardware IRQ controller */
4047 ppc6xx_irq_init(env_archcpu(env));
4048 }
4049
4050 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
4051 {
4052 DeviceClass *dc = DEVICE_CLASS(oc);
4053 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4054
4055 dc->desc = "PowerPC 750";
4056 pcc->init_proc = init_proc_750;
4057 pcc->check_pow = check_pow_hid0;
4058 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4059 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4060 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4061 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4062 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4063 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4064 PPC_SEGMENT | PPC_EXTERN;
4065 pcc->msr_mask = (1ull << MSR_POW) |
4066 (1ull << MSR_ILE) |
4067 (1ull << MSR_EE) |
4068 (1ull << MSR_PR) |
4069 (1ull << MSR_FP) |
4070 (1ull << MSR_ME) |
4071 (1ull << MSR_FE0) |
4072 (1ull << MSR_SE) |
4073 (1ull << MSR_DE) |
4074 (1ull << MSR_FE1) |
4075 (1ull << MSR_EP) |
4076 (1ull << MSR_IR) |
4077 (1ull << MSR_DR) |
4078 (1ull << MSR_PMM) |
4079 (1ull << MSR_RI) |
4080 (1ull << MSR_LE);
4081 pcc->mmu_model = POWERPC_MMU_32B;
4082 pcc->excp_model = POWERPC_EXCP_7xx;
4083 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4084 pcc->bfd_mach = bfd_mach_ppc_750;
4085 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4086 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4087 }
4088
4089 static void init_proc_750cl(CPUPPCState *env)
4090 {
4091 register_ne_601_sprs(env);
4092 register_sdr1_sprs(env);
4093 register_7xx_sprs(env);
4094
4095 spr_register(env, SPR_L2CR, "L2CR",
4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, spr_access_nop,
4098 0x00000000);
4099 /* Thermal management */
4100 /* Those registers are fake on 750CL */
4101 spr_register(env, SPR_THRM1, "THRM1",
4102 SPR_NOACCESS, SPR_NOACCESS,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
4105 spr_register(env, SPR_THRM2, "THRM2",
4106 SPR_NOACCESS, SPR_NOACCESS,
4107 &spr_read_generic, &spr_write_generic,
4108 0x00000000);
4109 spr_register(env, SPR_THRM3, "THRM3",
4110 SPR_NOACCESS, SPR_NOACCESS,
4111 &spr_read_generic, &spr_write_generic,
4112 0x00000000);
4113
4114 spr_register(env, SPR_750_TDCL, "TDCL",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, &spr_write_generic,
4117 0x00000000);
4118 spr_register(env, SPR_750_TDCH, "TDCH",
4119 SPR_NOACCESS, SPR_NOACCESS,
4120 &spr_read_generic, &spr_write_generic,
4121 0x00000000);
4122 /* DMA */
4123 spr_register(env, SPR_750_WPAR, "WPAR",
4124 SPR_NOACCESS, SPR_NOACCESS,
4125 &spr_read_generic, &spr_write_generic,
4126 0x00000000);
4127 spr_register(env, SPR_750_DMAL, "DMAL",
4128 SPR_NOACCESS, SPR_NOACCESS,
4129 &spr_read_generic, &spr_write_generic,
4130 0x00000000);
4131 spr_register(env, SPR_750_DMAU, "DMAU",
4132 SPR_NOACCESS, SPR_NOACCESS,
4133 &spr_read_generic, &spr_write_generic,
4134 0x00000000);
4135 /* Hardware implementation registers */
4136 spr_register(env, SPR_750CL_HID2, "HID2",
4137 SPR_NOACCESS, SPR_NOACCESS,
4138 &spr_read_generic, &spr_write_generic,
4139 0x00000000);
4140
4141 spr_register(env, SPR_750CL_HID4, "HID4",
4142 SPR_NOACCESS, SPR_NOACCESS,
4143 &spr_read_generic, &spr_write_generic,
4144 0x00000000);
4145 /* Quantization registers */
4146 spr_register(env, SPR_750_GQR0, "GQR0",
4147 SPR_NOACCESS, SPR_NOACCESS,
4148 &spr_read_generic, &spr_write_generic,
4149 0x00000000);
4150
4151 spr_register(env, SPR_750_GQR1, "GQR1",
4152 SPR_NOACCESS, SPR_NOACCESS,
4153 &spr_read_generic, &spr_write_generic,
4154 0x00000000);
4155
4156 spr_register(env, SPR_750_GQR2, "GQR2",
4157 SPR_NOACCESS, SPR_NOACCESS,
4158 &spr_read_generic, &spr_write_generic,
4159 0x00000000);
4160
4161 spr_register(env, SPR_750_GQR3, "GQR3",
4162 SPR_NOACCESS, SPR_NOACCESS,
4163 &spr_read_generic, &spr_write_generic,
4164 0x00000000);
4165
4166 spr_register(env, SPR_750_GQR4, "GQR4",
4167 SPR_NOACCESS, SPR_NOACCESS,
4168 &spr_read_generic, &spr_write_generic,
4169 0x00000000);
4170
4171 spr_register(env, SPR_750_GQR5, "GQR5",
4172 SPR_NOACCESS, SPR_NOACCESS,
4173 &spr_read_generic, &spr_write_generic,
4174 0x00000000);
4175
4176 spr_register(env, SPR_750_GQR6, "GQR6",
4177 SPR_NOACCESS, SPR_NOACCESS,
4178 &spr_read_generic, &spr_write_generic,
4179 0x00000000);
4180
4181 spr_register(env, SPR_750_GQR7, "GQR7",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, &spr_write_generic,
4184 0x00000000);
4185 /* Memory management */
4186 register_low_BATs(env);
4187 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4188 register_high_BATs(env);
4189 init_excp_750cl(env);
4190 env->dcache_line_size = 32;
4191 env->icache_line_size = 32;
4192 /* Allocate hardware IRQ controller */
4193 ppc6xx_irq_init(env_archcpu(env));
4194 }
4195
4196 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
4197 {
4198 DeviceClass *dc = DEVICE_CLASS(oc);
4199 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4200
4201 dc->desc = "PowerPC 750 CL";
4202 pcc->init_proc = init_proc_750cl;
4203 pcc->check_pow = check_pow_hid0;
4204 /*
4205 * XXX: not implemented:
4206 * cache lock instructions:
4207 * dcbz_l
4208 * floating point paired instructions
4209 * psq_lux
4210 * psq_lx
4211 * psq_stux
4212 * psq_stx
4213 * ps_abs
4214 * ps_add
4215 * ps_cmpo0
4216 * ps_cmpo1
4217 * ps_cmpu0
4218 * ps_cmpu1
4219 * ps_div
4220 * ps_madd
4221 * ps_madds0
4222 * ps_madds1
4223 * ps_merge00
4224 * ps_merge01
4225 * ps_merge10
4226 * ps_merge11
4227 * ps_mr
4228 * ps_msub
4229 * ps_mul
4230 * ps_muls0
4231 * ps_muls1
4232 * ps_nabs
4233 * ps_neg
4234 * ps_nmadd
4235 * ps_nmsub
4236 * ps_res
4237 * ps_rsqrte
4238 * ps_sel
4239 * ps_sub
4240 * ps_sum0
4241 * ps_sum1
4242 */
4243 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4244 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4245 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4246 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4247 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4248 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4249 PPC_SEGMENT | PPC_EXTERN;
4250 pcc->msr_mask = (1ull << MSR_POW) |
4251 (1ull << MSR_ILE) |
4252 (1ull << MSR_EE) |
4253 (1ull << MSR_PR) |
4254 (1ull << MSR_FP) |
4255 (1ull << MSR_ME) |
4256 (1ull << MSR_FE0) |
4257 (1ull << MSR_SE) |
4258 (1ull << MSR_DE) |
4259 (1ull << MSR_FE1) |
4260 (1ull << MSR_EP) |
4261 (1ull << MSR_IR) |
4262 (1ull << MSR_DR) |
4263 (1ull << MSR_PMM) |
4264 (1ull << MSR_RI) |
4265 (1ull << MSR_LE);
4266 pcc->mmu_model = POWERPC_MMU_32B;
4267 pcc->excp_model = POWERPC_EXCP_7xx;
4268 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4269 pcc->bfd_mach = bfd_mach_ppc_750;
4270 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4271 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4272 }
4273
4274 static void init_proc_750cx(CPUPPCState *env)
4275 {
4276 register_ne_601_sprs(env);
4277 register_sdr1_sprs(env);
4278 register_7xx_sprs(env);
4279
4280 spr_register(env, SPR_L2CR, "L2CR",
4281 SPR_NOACCESS, SPR_NOACCESS,
4282 &spr_read_generic, spr_access_nop,
4283 0x00000000);
4284 /* Thermal management */
4285 register_thrm_sprs(env);
4286
4287 spr_register(env, SPR_SDA, "SDA",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291
4292 /* Memory management */
4293 register_low_BATs(env);
4294 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4295 register_high_BATs(env);
4296 init_excp_750cx(env);
4297 env->dcache_line_size = 32;
4298 env->icache_line_size = 32;
4299 /* Allocate hardware IRQ controller */
4300 ppc6xx_irq_init(env_archcpu(env));
4301 }
4302
4303 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
4304 {
4305 DeviceClass *dc = DEVICE_CLASS(oc);
4306 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4307
4308 dc->desc = "PowerPC 750CX";
4309 pcc->init_proc = init_proc_750cx;
4310 pcc->check_pow = check_pow_hid0;
4311 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4312 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4313 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4314 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4315 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4317 PPC_SEGMENT | PPC_EXTERN;
4318 pcc->msr_mask = (1ull << MSR_POW) |
4319 (1ull << MSR_ILE) |
4320 (1ull << MSR_EE) |
4321 (1ull << MSR_PR) |
4322 (1ull << MSR_FP) |
4323 (1ull << MSR_ME) |
4324 (1ull << MSR_FE0) |
4325 (1ull << MSR_SE) |
4326 (1ull << MSR_DE) |
4327 (1ull << MSR_FE1) |
4328 (1ull << MSR_EP) |
4329 (1ull << MSR_IR) |
4330 (1ull << MSR_DR) |
4331 (1ull << MSR_PMM) |
4332 (1ull << MSR_RI) |
4333 (1ull << MSR_LE);
4334 pcc->mmu_model = POWERPC_MMU_32B;
4335 pcc->excp_model = POWERPC_EXCP_7xx;
4336 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4337 pcc->bfd_mach = bfd_mach_ppc_750;
4338 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4339 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4340 }
4341
4342 static void init_proc_750fx(CPUPPCState *env)
4343 {
4344 register_ne_601_sprs(env);
4345 register_sdr1_sprs(env);
4346 register_7xx_sprs(env);
4347
4348 spr_register(env, SPR_L2CR, "L2CR",
4349 SPR_NOACCESS, SPR_NOACCESS,
4350 &spr_read_generic, spr_access_nop,
4351 0x00000000);
4352 /* Thermal management */
4353 register_thrm_sprs(env);
4354
4355 spr_register(env, SPR_750_THRM4, "THRM4",
4356 SPR_NOACCESS, SPR_NOACCESS,
4357 &spr_read_generic, &spr_write_generic,
4358 0x00000000);
4359 /* Hardware implementation registers */
4360 spr_register(env, SPR_750FX_HID2, "HID2",
4361 SPR_NOACCESS, SPR_NOACCESS,
4362 &spr_read_generic, &spr_write_generic,
4363 0x00000000);
4364 /* Memory management */
4365 register_low_BATs(env);
4366 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4367 register_high_BATs(env);
4368 init_excp_7x0(env);
4369 env->dcache_line_size = 32;
4370 env->icache_line_size = 32;
4371 /* Allocate hardware IRQ controller */
4372 ppc6xx_irq_init(env_archcpu(env));
4373 }
4374
4375 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
4376 {
4377 DeviceClass *dc = DEVICE_CLASS(oc);
4378 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4379
4380 dc->desc = "PowerPC 750FX";
4381 pcc->init_proc = init_proc_750fx;
4382 pcc->check_pow = check_pow_hid0;
4383 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4384 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4385 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4386 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4387 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4388 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4389 PPC_SEGMENT | PPC_EXTERN;
4390 pcc->msr_mask = (1ull << MSR_POW) |
4391 (1ull << MSR_ILE) |
4392 (1ull << MSR_EE) |
4393 (1ull << MSR_PR) |
4394 (1ull << MSR_FP) |
4395 (1ull << MSR_ME) |
4396 (1ull << MSR_FE0) |
4397 (1ull << MSR_SE) |
4398 (1ull << MSR_DE) |
4399 (1ull << MSR_FE1) |
4400 (1ull << MSR_EP) |
4401 (1ull << MSR_IR) |
4402 (1ull << MSR_DR) |
4403 (1ull << MSR_PMM) |
4404 (1ull << MSR_RI) |
4405 (1ull << MSR_LE);
4406 pcc->mmu_model = POWERPC_MMU_32B;
4407 pcc->excp_model = POWERPC_EXCP_7xx;
4408 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4409 pcc->bfd_mach = bfd_mach_ppc_750;
4410 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4411 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4412 }
4413
4414 static void init_proc_750gx(CPUPPCState *env)
4415 {
4416 register_ne_601_sprs(env);
4417 register_sdr1_sprs(env);
4418 register_7xx_sprs(env);
4419
4420 spr_register(env, SPR_L2CR, "L2CR",
4421 SPR_NOACCESS, SPR_NOACCESS,
4422 &spr_read_generic, spr_access_nop,
4423 0x00000000);
4424 /* Thermal management */
4425 register_thrm_sprs(env);
4426
4427 spr_register(env, SPR_750_THRM4, "THRM4",
4428 SPR_NOACCESS, SPR_NOACCESS,
4429 &spr_read_generic, &spr_write_generic,
4430 0x00000000);
4431 /* Hardware implementation registers */
4432 spr_register(env, SPR_750FX_HID2, "HID2",
4433 SPR_NOACCESS, SPR_NOACCESS,
4434 &spr_read_generic, &spr_write_generic,
4435 0x00000000);
4436 /* Memory management */
4437 register_low_BATs(env);
4438 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4439 register_high_BATs(env);
4440 init_excp_7x0(env);
4441 env->dcache_line_size = 32;
4442 env->icache_line_size = 32;
4443 /* Allocate hardware IRQ controller */
4444 ppc6xx_irq_init(env_archcpu(env));
4445 }
4446
4447 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
4448 {
4449 DeviceClass *dc = DEVICE_CLASS(oc);
4450 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4451
4452 dc->desc = "PowerPC 750GX";
4453 pcc->init_proc = init_proc_750gx;
4454 pcc->check_pow = check_pow_hid0;
4455 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4456 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4457 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4458 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4459 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4460 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4461 PPC_SEGMENT | PPC_EXTERN;
4462 pcc->msr_mask = (1ull << MSR_POW) |
4463 (1ull << MSR_ILE) |
4464 (1ull << MSR_EE) |
4465 (1ull << MSR_PR) |
4466 (1ull << MSR_FP) |
4467 (1ull << MSR_ME) |
4468 (1ull << MSR_FE0) |
4469 (1ull << MSR_SE) |
4470 (1ull << MSR_DE) |
4471 (1ull << MSR_FE1) |
4472 (1ull << MSR_EP) |
4473 (1ull << MSR_IR) |
4474 (1ull << MSR_DR) |
4475 (1ull << MSR_PMM) |
4476 (1ull << MSR_RI) |
4477 (1ull << MSR_LE);
4478 pcc->mmu_model = POWERPC_MMU_32B;
4479 pcc->excp_model = POWERPC_EXCP_7xx;
4480 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4481 pcc->bfd_mach = bfd_mach_ppc_750;
4482 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4483 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4484 }
4485
4486 static void init_proc_745(CPUPPCState *env)
4487 {
4488 register_ne_601_sprs(env);
4489 register_sdr1_sprs(env);
4490 register_7xx_sprs(env);
4491 register_745_sprs(env);
4492 /* Thermal management */
4493 register_thrm_sprs(env);
4494
4495 /* Memory management */
4496 register_low_BATs(env);
4497 register_high_BATs(env);
4498 register_6xx_7xx_soft_tlb(env, 64, 2);
4499 init_excp_7x5(env);
4500 env->dcache_line_size = 32;
4501 env->icache_line_size = 32;
4502 /* Allocate hardware IRQ controller */
4503 ppc6xx_irq_init(env_archcpu(env));
4504 }
4505
4506 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4507 {
4508 DeviceClass *dc = DEVICE_CLASS(oc);
4509 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4510
4511 dc->desc = "PowerPC 745";
4512 pcc->init_proc = init_proc_745;
4513 pcc->check_pow = check_pow_hid0;
4514 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4515 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4516 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4517 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4518 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4519 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4520 PPC_SEGMENT | PPC_EXTERN;
4521 pcc->msr_mask = (1ull << MSR_POW) |
4522 (1ull << MSR_ILE) |
4523 (1ull << MSR_EE) |
4524 (1ull << MSR_PR) |
4525 (1ull << MSR_FP) |
4526 (1ull << MSR_ME) |
4527 (1ull << MSR_FE0) |
4528 (1ull << MSR_SE) |
4529 (1ull << MSR_DE) |
4530 (1ull << MSR_FE1) |
4531 (1ull << MSR_EP) |
4532 (1ull << MSR_IR) |
4533 (1ull << MSR_DR) |
4534 (1ull << MSR_PMM) |
4535 (1ull << MSR_RI) |
4536 (1ull << MSR_LE);
4537 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4538 pcc->excp_model = POWERPC_EXCP_7xx;
4539 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4540 pcc->bfd_mach = bfd_mach_ppc_750;
4541 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4542 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4543 }
4544
4545 static void init_proc_755(CPUPPCState *env)
4546 {
4547 register_ne_601_sprs(env);
4548 register_sdr1_sprs(env);
4549 register_7xx_sprs(env);
4550 register_745_sprs(env);
4551 register_755_sprs(env);
4552
4553 /* Thermal management */
4554 register_thrm_sprs(env);
4555
4556 /* Memory management */
4557 register_low_BATs(env);
4558 register_high_BATs(env);
4559 register_6xx_7xx_soft_tlb(env, 64, 2);
4560 init_excp_7x5(env);
4561 env->dcache_line_size = 32;
4562 env->icache_line_size = 32;
4563 /* Allocate hardware IRQ controller */
4564 ppc6xx_irq_init(env_archcpu(env));
4565 }
4566
4567 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4568 {
4569 DeviceClass *dc = DEVICE_CLASS(oc);
4570 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4571
4572 dc->desc = "PowerPC 755";
4573 pcc->init_proc = init_proc_755;
4574 pcc->check_pow = check_pow_hid0;
4575 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4576 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4577 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4578 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4579 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4580 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4581 PPC_SEGMENT | PPC_EXTERN;
4582 pcc->msr_mask = (1ull << MSR_POW) |
4583 (1ull << MSR_ILE) |
4584 (1ull << MSR_EE) |
4585 (1ull << MSR_PR) |
4586 (1ull << MSR_FP) |
4587 (1ull << MSR_ME) |
4588 (1ull << MSR_FE0) |
4589 (1ull << MSR_SE) |
4590 (1ull << MSR_DE) |
4591 (1ull << MSR_FE1) |
4592 (1ull << MSR_EP) |
4593 (1ull << MSR_IR) |
4594 (1ull << MSR_DR) |
4595 (1ull << MSR_PMM) |
4596 (1ull << MSR_RI) |
4597 (1ull << MSR_LE);
4598 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4599 pcc->excp_model = POWERPC_EXCP_7xx;
4600 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4601 pcc->bfd_mach = bfd_mach_ppc_750;
4602 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4603 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4604 }
4605
4606 static void init_proc_7400(CPUPPCState *env)
4607 {
4608 register_ne_601_sprs(env);
4609 register_sdr1_sprs(env);
4610 register_74xx_sprs(env);
4611 vscr_init(env, 0x00010000);
4612
4613 spr_register(env, SPR_UBAMR, "UBAMR",
4614 &spr_read_ureg, SPR_NOACCESS,
4615 &spr_read_ureg, SPR_NOACCESS,
4616 0x00000000);
4617
4618 spr_register(env, SPR_MSSCR1, "MSSCR1",
4619 SPR_NOACCESS, SPR_NOACCESS,
4620 &spr_read_generic, &spr_write_generic,
4621 0x00000000);
4622 /* Thermal management */
4623 register_thrm_sprs(env);
4624 /* Memory management */
4625 register_low_BATs(env);
4626 init_excp_7400(env);
4627 env->dcache_line_size = 32;
4628 env->icache_line_size = 32;
4629 /* Allocate hardware IRQ controller */
4630 ppc6xx_irq_init(env_archcpu(env));
4631 }
4632
4633 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4634 {
4635 DeviceClass *dc = DEVICE_CLASS(oc);
4636 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4637
4638 dc->desc = "PowerPC 7400 (aka G4)";
4639 pcc->init_proc = init_proc_7400;
4640 pcc->check_pow = check_pow_hid0;
4641 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4642 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4643 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4644 PPC_FLOAT_STFIWX |
4645 PPC_CACHE | PPC_CACHE_ICBI |
4646 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4647 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4648 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4649 PPC_MEM_TLBIA |
4650 PPC_SEGMENT | PPC_EXTERN |
4651 PPC_ALTIVEC;
4652 pcc->msr_mask = (1ull << MSR_VR) |
4653 (1ull << MSR_POW) |
4654 (1ull << MSR_ILE) |
4655 (1ull << MSR_EE) |
4656 (1ull << MSR_PR) |
4657 (1ull << MSR_FP) |
4658 (1ull << MSR_ME) |
4659 (1ull << MSR_FE0) |
4660 (1ull << MSR_SE) |
4661 (1ull << MSR_DE) |
4662 (1ull << MSR_FE1) |
4663 (1ull << MSR_EP) |
4664 (1ull << MSR_IR) |
4665 (1ull << MSR_DR) |
4666 (1ull << MSR_PMM) |
4667 (1ull << MSR_RI) |
4668 (1ull << MSR_LE);
4669 pcc->mmu_model = POWERPC_MMU_32B;
4670 pcc->excp_model = POWERPC_EXCP_74xx;
4671 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4672 pcc->bfd_mach = bfd_mach_ppc_7400;
4673 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4674 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4675 POWERPC_FLAG_BUS_CLK;
4676 }
4677
4678 static void init_proc_7410(CPUPPCState *env)
4679 {
4680 register_ne_601_sprs(env);
4681 register_sdr1_sprs(env);
4682 register_74xx_sprs(env);
4683 vscr_init(env, 0x00010000);
4684
4685 spr_register(env, SPR_UBAMR, "UBAMR",
4686 &spr_read_ureg, SPR_NOACCESS,
4687 &spr_read_ureg, SPR_NOACCESS,
4688 0x00000000);
4689 /* Thermal management */
4690 register_thrm_sprs(env);
4691 /* L2PMCR */
4692
4693 spr_register(env, SPR_L2PMCR, "L2PMCR",
4694 SPR_NOACCESS, SPR_NOACCESS,
4695 &spr_read_generic, &spr_write_generic,
4696 0x00000000);
4697 /* LDSTDB */
4698
4699 spr_register(env, SPR_LDSTDB, "LDSTDB",
4700 SPR_NOACCESS, SPR_NOACCESS,
4701 &spr_read_generic, &spr_write_generic,
4702 0x00000000);
4703 /* Memory management */
4704 register_low_BATs(env);
4705 init_excp_7400(env);
4706 env->dcache_line_size = 32;
4707 env->icache_line_size = 32;
4708 /* Allocate hardware IRQ controller */
4709 ppc6xx_irq_init(env_archcpu(env));
4710 }
4711
4712 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4713 {
4714 DeviceClass *dc = DEVICE_CLASS(oc);
4715 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4716
4717 dc->desc = "PowerPC 7410 (aka G4)";
4718 pcc->init_proc = init_proc_7410;
4719 pcc->check_pow = check_pow_hid0;
4720 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4721 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4722 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4723 PPC_FLOAT_STFIWX |
4724 PPC_CACHE | PPC_CACHE_ICBI |
4725 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4726 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4727 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4728 PPC_MEM_TLBIA |
4729 PPC_SEGMENT | PPC_EXTERN |
4730 PPC_ALTIVEC;
4731 pcc->msr_mask = (1ull << MSR_VR) |
4732 (1ull << MSR_POW) |
4733 (1ull << MSR_ILE) |
4734 (1ull << MSR_EE) |
4735 (1ull << MSR_PR) |
4736 (1ull << MSR_FP) |
4737 (1ull << MSR_ME) |
4738 (1ull << MSR_FE0) |
4739 (1ull << MSR_SE) |
4740 (1ull << MSR_DE) |
4741 (1ull << MSR_FE1) |
4742 (1ull << MSR_EP) |
4743 (1ull << MSR_IR) |
4744 (1ull << MSR_DR) |
4745 (1ull << MSR_PMM) |
4746 (1ull << MSR_RI) |
4747 (1ull << MSR_LE);
4748 pcc->mmu_model = POWERPC_MMU_32B;
4749 pcc->excp_model = POWERPC_EXCP_74xx;
4750 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4751 pcc->bfd_mach = bfd_mach_ppc_7400;
4752 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4753 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4754 POWERPC_FLAG_BUS_CLK;
4755 }
4756
4757 static void init_proc_7440(CPUPPCState *env)
4758 {
4759 register_ne_601_sprs(env);
4760 register_sdr1_sprs(env);
4761 register_74xx_sprs(env);
4762 vscr_init(env, 0x00010000);
4763
4764 spr_register(env, SPR_UBAMR, "UBAMR",
4765 &spr_read_ureg, SPR_NOACCESS,
4766 &spr_read_ureg, SPR_NOACCESS,
4767 0x00000000);
4768 /* LDSTCR */
4769 spr_register(env, SPR_LDSTCR, "LDSTCR",
4770 SPR_NOACCESS, SPR_NOACCESS,
4771 &spr_read_generic, &spr_write_generic,
4772 0x00000000);
4773 /* ICTRL */
4774 spr_register(env, SPR_ICTRL, "ICTRL",
4775 SPR_NOACCESS, SPR_NOACCESS,
4776 &spr_read_generic, &spr_write_generic,
4777 0x00000000);
4778 /* MSSSR0 */
4779 spr_register(env, SPR_MSSSR0, "MSSSR0",
4780 SPR_NOACCESS, SPR_NOACCESS,
4781 &spr_read_generic, &spr_write_generic,
4782 0x00000000);
4783 /* PMC */
4784 spr_register(env, SPR_7XX_PMC5, "PMC5",
4785 SPR_NOACCESS, SPR_NOACCESS,
4786 &spr_read_generic, &spr_write_generic,
4787 0x00000000);
4788
4789 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4790 &spr_read_ureg, SPR_NOACCESS,
4791 &spr_read_ureg, SPR_NOACCESS,
4792 0x00000000);
4793
4794 spr_register(env, SPR_7XX_PMC6, "PMC6",
4795 SPR_NOACCESS, SPR_NOACCESS,
4796 &spr_read_generic, &spr_write_generic,
4797 0x00000000);
4798
4799 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4800 &spr_read_ureg, SPR_NOACCESS,
4801 &spr_read_ureg, SPR_NOACCESS,
4802 0x00000000);
4803 /* Memory management */
4804 register_low_BATs(env);
4805 init_excp_7450(env);
4806 env->dcache_line_size = 32;
4807 env->icache_line_size = 32;
4808 /* Allocate hardware IRQ controller */
4809 ppc6xx_irq_init(env_archcpu(env));
4810 }
4811
4812 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4813 {
4814 DeviceClass *dc = DEVICE_CLASS(oc);
4815 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4816
4817 dc->desc = "PowerPC 7440 (aka G4)";
4818 pcc->init_proc = init_proc_7440;
4819 pcc->check_pow = check_pow_hid0_74xx;
4820 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4821 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4822 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4823 PPC_FLOAT_STFIWX |
4824 PPC_CACHE | PPC_CACHE_ICBI |
4825 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4826 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4827 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4828 PPC_MEM_TLBIA |
4829 PPC_SEGMENT | PPC_EXTERN |
4830 PPC_ALTIVEC;
4831 pcc->msr_mask = (1ull << MSR_VR) |
4832 (1ull << MSR_POW) |
4833 (1ull << MSR_ILE) |
4834 (1ull << MSR_EE) |
4835 (1ull << MSR_PR) |
4836 (1ull << MSR_FP) |
4837 (1ull << MSR_ME) |
4838 (1ull << MSR_FE0) |
4839 (1ull << MSR_SE) |
4840 (1ull << MSR_DE) |
4841 (1ull << MSR_FE1) |
4842 (1ull << MSR_EP) |
4843 (1ull << MSR_IR) |
4844 (1ull << MSR_DR) |
4845 (1ull << MSR_PMM) |
4846 (1ull << MSR_RI) |
4847 (1ull << MSR_LE);
4848 pcc->mmu_model = POWERPC_MMU_32B;
4849 pcc->excp_model = POWERPC_EXCP_74xx;
4850 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4851 pcc->bfd_mach = bfd_mach_ppc_7400;
4852 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4853 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4854 POWERPC_FLAG_BUS_CLK;
4855 }
4856
4857 static void init_proc_7450(CPUPPCState *env)
4858 {
4859 register_ne_601_sprs(env);
4860 register_sdr1_sprs(env);
4861 register_74xx_sprs(env);
4862 vscr_init(env, 0x00010000);
4863 /* Level 3 cache control */
4864 register_l3_ctrl(env);
4865 /* L3ITCR1 */
4866 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4867 SPR_NOACCESS, SPR_NOACCESS,
4868 &spr_read_generic, &spr_write_generic,
4869 0x00000000);
4870 /* L3ITCR2 */
4871 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 /* L3ITCR3 */
4876 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 /* L3OHCR */
4881 spr_register(env, SPR_L3OHCR, "L3OHCR",
4882 SPR_NOACCESS, SPR_NOACCESS,
4883 &spr_read_generic, &spr_write_generic,
4884 0x00000000);
4885
4886 spr_register(env, SPR_UBAMR, "UBAMR",
4887 &spr_read_ureg, SPR_NOACCESS,
4888 &spr_read_ureg, SPR_NOACCESS,
4889 0x00000000);
4890 /* LDSTCR */
4891 spr_register(env, SPR_LDSTCR, "LDSTCR",
4892 SPR_NOACCESS, SPR_NOACCESS,
4893 &spr_read_generic, &spr_write_generic,
4894 0x00000000);
4895 /* ICTRL */
4896 spr_register(env, SPR_ICTRL, "ICTRL",
4897 SPR_NOACCESS, SPR_NOACCESS,
4898 &spr_read_generic, &spr_write_generic,
4899 0x00000000);
4900 /* MSSSR0 */
4901 spr_register(env, SPR_MSSSR0, "MSSSR0",
4902 SPR_NOACCESS, SPR_NOACCESS,
4903 &spr_read_generic, &spr_write_generic,
4904 0x00000000);
4905 /* PMC */
4906 spr_register(env, SPR_7XX_PMC5, "PMC5",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910
4911 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4912 &spr_read_ureg, SPR_NOACCESS,
4913 &spr_read_ureg, SPR_NOACCESS,
4914 0x00000000);
4915
4916 spr_register(env, SPR_7XX_PMC6, "PMC6",
4917 SPR_NOACCESS, SPR_NOACCESS,
4918 &spr_read_generic, &spr_write_generic,
4919 0x00000000);
4920
4921 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4922 &spr_read_ureg, SPR_NOACCESS,
4923 &spr_read_ureg, SPR_NOACCESS,
4924 0x00000000);
4925 /* Memory management */
4926 register_low_BATs(env);
4927 init_excp_7450(env);
4928 env->dcache_line_size = 32;
4929 env->icache_line_size = 32;
4930 /* Allocate hardware IRQ controller */
4931 ppc6xx_irq_init(env_archcpu(env));
4932 }
4933
4934 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4935 {
4936 DeviceClass *dc = DEVICE_CLASS(oc);
4937 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4938
4939 dc->desc = "PowerPC 7450 (aka G4)";
4940 pcc->init_proc = init_proc_7450;
4941 pcc->check_pow = check_pow_hid0_74xx;
4942 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4943 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4944 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4945 PPC_FLOAT_STFIWX |
4946 PPC_CACHE | PPC_CACHE_ICBI |
4947 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4948 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4949 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4950 PPC_MEM_TLBIA |
4951 PPC_SEGMENT | PPC_EXTERN |
4952 PPC_ALTIVEC;
4953 pcc->msr_mask = (1ull << MSR_VR) |
4954 (1ull << MSR_POW) |
4955 (1ull << MSR_ILE) |
4956 (1ull << MSR_EE) |
4957 (1ull << MSR_PR) |
4958 (1ull << MSR_FP) |
4959 (1ull << MSR_ME) |
4960 (1ull << MSR_FE0) |
4961 (1ull << MSR_SE) |
4962 (1ull << MSR_DE) |
4963 (1ull << MSR_FE1) |
4964 (1ull << MSR_EP) |
4965 (1ull << MSR_IR) |
4966 (1ull << MSR_DR) |
4967 (1ull << MSR_PMM) |
4968 (1ull << MSR_RI) |
4969 (1ull << MSR_LE);
4970 pcc->mmu_model = POWERPC_MMU_32B;
4971 pcc->excp_model = POWERPC_EXCP_74xx;
4972 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4973 pcc->bfd_mach = bfd_mach_ppc_7400;
4974 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4975 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4976 POWERPC_FLAG_BUS_CLK;
4977 }
4978
4979 static void init_proc_7445(CPUPPCState *env)
4980 {
4981 register_ne_601_sprs(env);
4982 register_sdr1_sprs(env);
4983 register_74xx_sprs(env);
4984 vscr_init(env, 0x00010000);
4985 /* LDSTCR */
4986 spr_register(env, SPR_LDSTCR, "LDSTCR",
4987 SPR_NOACCESS, SPR_NOACCESS,
4988 &spr_read_generic, &spr_write_generic,
4989 0x00000000);
4990 /* ICTRL */
4991 spr_register(env, SPR_ICTRL, "ICTRL",
4992 SPR_NOACCESS, SPR_NOACCESS,
4993 &spr_read_generic, &spr_write_generic,
4994 0x00000000);
4995 /* MSSSR0 */
4996 spr_register(env, SPR_MSSSR0, "MSSSR0",
4997 SPR_NOACCESS, SPR_NOACCESS,
4998 &spr_read_generic, &spr_write_generic,
4999 0x00000000);
5000 /* PMC */
5001 spr_register(env, SPR_7XX_PMC5, "PMC5",
5002 SPR_NOACCESS, SPR_NOACCESS,
5003 &spr_read_generic, &spr_write_generic,
5004 0x00000000);
5005
5006 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5007 &spr_read_ureg, SPR_NOACCESS,
5008 &spr_read_ureg, SPR_NOACCESS,
5009 0x00000000);
5010
5011 spr_register(env, SPR_7XX_PMC6, "PMC6",
5012 SPR_NOACCESS, SPR_NOACCESS,
5013 &spr_read_generic, &spr_write_generic,
5014 0x00000000);
5015
5016 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5017 &spr_read_ureg, SPR_NOACCESS,
5018 &spr_read_ureg, SPR_NOACCESS,
5019 0x00000000);
5020 /* SPRGs */
5021 spr_register(env, SPR_SPRG4, "SPRG4",
5022 SPR_NOACCESS, SPR_NOACCESS,
5023 &spr_read_generic, &spr_write_generic,
5024 0x00000000);
5025 spr_register(env, SPR_USPRG4, "USPRG4",
5026 &spr_read_ureg, SPR_NOACCESS,
5027 &spr_read_ureg, SPR_NOACCESS,
5028 0x00000000);
5029 spr_register(env, SPR_SPRG5, "SPRG5",
5030 SPR_NOACCESS, SPR_NOACCESS,
5031 &spr_read_generic, &spr_write_generic,
5032 0x00000000);
5033 spr_register(env, SPR_USPRG5, "USPRG5",
5034 &spr_read_ureg, SPR_NOACCESS,
5035 &spr_read_ureg, SPR_NOACCESS,
5036 0x00000000);
5037 spr_register(env, SPR_SPRG6, "SPRG6",
5038 SPR_NOACCESS, SPR_NOACCESS,
5039 &spr_read_generic, &spr_write_generic,
5040 0x00000000);
5041 spr_register(env, SPR_USPRG6, "USPRG6",
5042 &spr_read_ureg, SPR_NOACCESS,
5043 &spr_read_ureg, SPR_NOACCESS,
5044 0x00000000);
5045 spr_register(env, SPR_SPRG7, "SPRG7",
5046 SPR_NOACCESS, SPR_NOACCESS,
5047 &spr_read_generic, &spr_write_generic,
5048 0x00000000);
5049 spr_register(env, SPR_USPRG7, "USPRG7",
5050 &spr_read_ureg, SPR_NOACCESS,
5051 &spr_read_ureg, SPR_NOACCESS,
5052 0x00000000);
5053 /* Memory management */
5054 register_low_BATs(env);
5055 register_high_BATs(env);
5056 init_excp_7450(env);
5057 env->dcache_line_size = 32;
5058 env->icache_line_size = 32;
5059 /* Allocate hardware IRQ controller */
5060 ppc6xx_irq_init(env_archcpu(env));
5061 }
5062
5063 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
5064 {
5065 DeviceClass *dc = DEVICE_CLASS(oc);
5066 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5067
5068 dc->desc = "PowerPC 7445 (aka G4)";
5069 pcc->init_proc = init_proc_7445;
5070 pcc->check_pow = check_pow_hid0_74xx;
5071 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5072 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5073 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5074 PPC_FLOAT_STFIWX |
5075 PPC_CACHE | PPC_CACHE_ICBI |
5076 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5077 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5078 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5079 PPC_MEM_TLBIA |
5080 PPC_SEGMENT | PPC_EXTERN |
5081 PPC_ALTIVEC;
5082 pcc->msr_mask = (1ull << MSR_VR) |
5083 (1ull << MSR_POW) |
5084 (1ull << MSR_ILE) |
5085 (1ull << MSR_EE) |
5086 (1ull << MSR_PR) |
5087 (1ull << MSR_FP) |
5088 (1ull << MSR_ME) |
5089 (1ull << MSR_FE0) |
5090 (1ull << MSR_SE) |
5091 (1ull << MSR_DE) |
5092 (1ull << MSR_FE1) |
5093 (1ull << MSR_EP) |
5094 (1ull << MSR_IR) |
5095 (1ull << MSR_DR) |
5096 (1ull << MSR_PMM) |
5097 (1ull << MSR_RI) |
5098 (1ull << MSR_LE);
5099 pcc->mmu_model = POWERPC_MMU_32B;
5100 pcc->excp_model = POWERPC_EXCP_74xx;
5101 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5102 pcc->bfd_mach = bfd_mach_ppc_7400;
5103 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5104 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5105 POWERPC_FLAG_BUS_CLK;
5106 }
5107
5108 static void init_proc_7455(CPUPPCState *env)
5109 {
5110 register_ne_601_sprs(env);
5111 register_sdr1_sprs(env);
5112 register_74xx_sprs(env);
5113 vscr_init(env, 0x00010000);
5114 /* Level 3 cache control */
5115 register_l3_ctrl(env);
5116 /* LDSTCR */
5117 spr_register(env, SPR_LDSTCR, "LDSTCR",
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 0x00000000);
5121 /* ICTRL */
5122 spr_register(env, SPR_ICTRL, "ICTRL",
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 &spr_read_generic, &spr_write_generic,
5125 0x00000000);
5126 /* MSSSR0 */
5127 spr_register(env, SPR_MSSSR0, "MSSSR0",
5128 SPR_NOACCESS, SPR_NOACCESS,
5129 &spr_read_generic, &spr_write_generic,
5130 0x00000000);
5131 /* PMC */
5132 spr_register(env, SPR_7XX_PMC5, "PMC5",
5133 SPR_NOACCESS, SPR_NOACCESS,
5134 &spr_read_generic, &spr_write_generic,
5135 0x00000000);
5136
5137 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5138 &spr_read_ureg, SPR_NOACCESS,
5139 &spr_read_ureg, SPR_NOACCESS,
5140 0x00000000);
5141
5142 spr_register(env, SPR_7XX_PMC6, "PMC6",
5143 SPR_NOACCESS, SPR_NOACCESS,
5144 &spr_read_generic, &spr_write_generic,
5145 0x00000000);
5146
5147 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5148 &spr_read_ureg, SPR_NOACCESS,
5149 &spr_read_ureg, SPR_NOACCESS,
5150 0x00000000);
5151 /* SPRGs */
5152 spr_register(env, SPR_SPRG4, "SPRG4",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 0x00000000);
5156 spr_register(env, SPR_USPRG4, "USPRG4",
5157 &spr_read_ureg, SPR_NOACCESS,
5158 &spr_read_ureg, SPR_NOACCESS,
5159 0x00000000);
5160 spr_register(env, SPR_SPRG5, "SPRG5",
5161 SPR_NOACCESS, SPR_NOACCESS,
5162 &spr_read_generic, &spr_write_generic,
5163 0x00000000);
5164 spr_register(env, SPR_USPRG5, "USPRG5",
5165 &spr_read_ureg, SPR_NOACCESS,
5166 &spr_read_ureg, SPR_NOACCESS,
5167 0x00000000);
5168 spr_register(env, SPR_SPRG6, "SPRG6",
5169 SPR_NOACCESS, SPR_NOACCESS,
5170 &spr_read_generic, &spr_write_generic,
5171 0x00000000);
5172 spr_register(env, SPR_USPRG6, "USPRG6",
5173 &spr_read_ureg, SPR_NOACCESS,
5174 &spr_read_ureg, SPR_NOACCESS,
5175 0x00000000);
5176 spr_register(env, SPR_SPRG7, "SPRG7",
5177 SPR_NOACCESS, SPR_NOACCESS,
5178 &spr_read_generic, &spr_write_generic,
5179 0x00000000);
5180 spr_register(env, SPR_USPRG7, "USPRG7",
5181 &spr_read_ureg, SPR_NOACCESS,
5182 &spr_read_ureg, SPR_NOACCESS,
5183 0x00000000);
5184 /* Memory management */
5185 register_low_BATs(env);
5186 register_high_BATs(env);
5187 init_excp_7450(env);
5188 env->dcache_line_size = 32;
5189 env->icache_line_size = 32;
5190 /* Allocate hardware IRQ controller */
5191 ppc6xx_irq_init(env_archcpu(env));
5192 }
5193
5194 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
5195 {
5196 DeviceClass *dc = DEVICE_CLASS(oc);
5197 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5198
5199 dc->desc = "PowerPC 7455 (aka G4)";
5200 pcc->init_proc = init_proc_7455;
5201 pcc->check_pow = check_pow_hid0_74xx;
5202 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5203 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5204 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5205 PPC_FLOAT_STFIWX |
5206 PPC_CACHE | PPC_CACHE_ICBI |
5207 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5208 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5209 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5210 PPC_MEM_TLBIA |
5211 PPC_SEGMENT | PPC_EXTERN |
5212 PPC_ALTIVEC;
5213 pcc->msr_mask = (1ull << MSR_VR) |
5214 (1ull << MSR_POW) |
5215 (1ull << MSR_ILE) |
5216 (1ull << MSR_EE) |
5217 (1ull << MSR_PR) |
5218 (1ull << MSR_FP) |
5219 (1ull << MSR_ME) |
5220 (1ull << MSR_FE0) |
5221 (1ull << MSR_SE) |
5222 (1ull << MSR_DE) |
5223 (1ull << MSR_FE1) |
5224 (1ull << MSR_EP) |
5225 (1ull << MSR_IR) |
5226 (1ull << MSR_DR) |
5227 (1ull << MSR_PMM) |
5228 (1ull << MSR_RI) |
5229 (1ull << MSR_LE);
5230 pcc->mmu_model = POWERPC_MMU_32B;
5231 pcc->excp_model = POWERPC_EXCP_74xx;
5232 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5233 pcc->bfd_mach = bfd_mach_ppc_7400;
5234 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5235 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5236 POWERPC_FLAG_BUS_CLK;
5237 }
5238
5239 static void init_proc_7457(CPUPPCState *env)
5240 {
5241 register_ne_601_sprs(env);
5242 register_sdr1_sprs(env);
5243 register_74xx_sprs(env);
5244 vscr_init(env, 0x00010000);
5245 /* Level 3 cache control */
5246 register_l3_ctrl(env);
5247 /* L3ITCR1 */
5248 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5249 SPR_NOACCESS, SPR_NOACCESS,
5250 &spr_read_generic, &spr_write_generic,
5251 0x00000000);
5252 /* L3ITCR2 */
5253 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5254 SPR_NOACCESS, SPR_NOACCESS,
5255 &spr_read_generic, &spr_write_generic,
5256 0x00000000);
5257 /* L3ITCR3 */
5258 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5259 SPR_NOACCESS, SPR_NOACCESS,
5260 &spr_read_generic, &spr_write_generic,
5261 0x00000000);
5262 /* L3OHCR */
5263 spr_register(env, SPR_L3OHCR, "L3OHCR",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 /* LDSTCR */
5268 spr_register(env, SPR_LDSTCR, "LDSTCR",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 0x00000000);
5272 /* ICTRL */
5273 spr_register(env, SPR_ICTRL, "ICTRL",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 0x00000000);
5277 /* MSSSR0 */
5278 spr_register(env, SPR_MSSSR0, "MSSSR0",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 /* PMC */
5283 spr_register(env, SPR_7XX_PMC5, "PMC5",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287
5288 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5289 &spr_read_ureg, SPR_NOACCESS,
5290 &spr_read_ureg, SPR_NOACCESS,
5291 0x00000000);
5292
5293 spr_register(env, SPR_7XX_PMC6, "PMC6",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297
5298 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5299 &spr_read_ureg, SPR_NOACCESS,
5300 &spr_read_ureg, SPR_NOACCESS,
5301 0x00000000);
5302 /* SPRGs */
5303 spr_register(env, SPR_SPRG4, "SPRG4",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 spr_register(env, SPR_USPRG4, "USPRG4",
5308 &spr_read_ureg, SPR_NOACCESS,
5309 &spr_read_ureg, SPR_NOACCESS,
5310 0x00000000);
5311 spr_register(env, SPR_SPRG5, "SPRG5",
5312 SPR_NOACCESS, SPR_NOACCESS,
5313 &spr_read_generic, &spr_write_generic,
5314 0x00000000);
5315 spr_register(env, SPR_USPRG5, "USPRG5",
5316 &spr_read_ureg, SPR_NOACCESS,
5317 &spr_read_ureg, SPR_NOACCESS,
5318 0x00000000);
5319 spr_register(env, SPR_SPRG6, "SPRG6",
5320 SPR_NOACCESS, SPR_NOACCESS,
5321 &spr_read_generic, &spr_write_generic,
5322 0x00000000);
5323 spr_register(env, SPR_USPRG6, "USPRG6",
5324 &spr_read_ureg, SPR_NOACCESS,
5325 &spr_read_ureg, SPR_NOACCESS,
5326 0x00000000);
5327 spr_register(env, SPR_SPRG7, "SPRG7",
5328 SPR_NOACCESS, SPR_NOACCESS,
5329 &spr_read_generic, &spr_write_generic,
5330 0x00000000);
5331 spr_register(env, SPR_USPRG7, "USPRG7",
5332 &spr_read_ureg, SPR_NOACCESS,
5333 &spr_read_ureg, SPR_NOACCESS,
5334 0x00000000);
5335 /* Memory management */
5336 register_low_BATs(env);
5337 register_high_BATs(env);
5338 init_excp_7450(env);
5339 env->dcache_line_size = 32;
5340 env->icache_line_size = 32;
5341 /* Allocate hardware IRQ controller */
5342 ppc6xx_irq_init(env_archcpu(env));
5343 }
5344
5345 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
5346 {
5347 DeviceClass *dc = DEVICE_CLASS(oc);
5348 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5349
5350 dc->desc = "PowerPC 7457 (aka G4)";
5351 pcc->init_proc = init_proc_7457;
5352 pcc->check_pow = check_pow_hid0_74xx;
5353 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5354 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5355 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5356 PPC_FLOAT_STFIWX |
5357 PPC_CACHE | PPC_CACHE_ICBI |
5358 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5359 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5360 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5361 PPC_MEM_TLBIA |
5362 PPC_SEGMENT | PPC_EXTERN |
5363 PPC_ALTIVEC;
5364 pcc->msr_mask = (1ull << MSR_VR) |
5365 (1ull << MSR_POW) |
5366 (1ull << MSR_ILE) |
5367 (1ull << MSR_EE) |
5368 (1ull << MSR_PR) |
5369 (1ull << MSR_FP) |
5370 (1ull << MSR_ME) |
5371 (1ull << MSR_FE0) |
5372 (1ull << MSR_SE) |
5373 (1ull << MSR_DE) |
5374 (1ull << MSR_FE1) |
5375 (1ull << MSR_EP) |
5376 (1ull << MSR_IR) |
5377 (1ull << MSR_DR) |
5378 (1ull << MSR_PMM) |
5379 (1ull << MSR_RI) |
5380 (1ull << MSR_LE);
5381 pcc->mmu_model = POWERPC_MMU_32B;
5382 pcc->excp_model = POWERPC_EXCP_74xx;
5383 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5384 pcc->bfd_mach = bfd_mach_ppc_7400;
5385 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5386 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5387 POWERPC_FLAG_BUS_CLK;
5388 }
5389
5390 static void init_proc_e600(CPUPPCState *env)
5391 {
5392 register_ne_601_sprs(env);
5393 register_sdr1_sprs(env);
5394 register_74xx_sprs(env);
5395 vscr_init(env, 0x00010000);
5396
5397 spr_register(env, SPR_UBAMR, "UBAMR",
5398 &spr_read_ureg, SPR_NOACCESS,
5399 &spr_read_ureg, SPR_NOACCESS,
5400 0x00000000);
5401
5402 spr_register(env, SPR_LDSTCR, "LDSTCR",
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 &spr_read_generic, &spr_write_generic,
5405 0x00000000);
5406
5407 spr_register(env, SPR_ICTRL, "ICTRL",
5408 SPR_NOACCESS, SPR_NOACCESS,
5409 &spr_read_generic, &spr_write_generic,
5410 0x00000000);
5411
5412 spr_register(env, SPR_MSSSR0, "MSSSR0",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 &spr_read_generic, &spr_write_generic,
5415 0x00000000);
5416
5417 spr_register(env, SPR_7XX_PMC5, "PMC5",
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 &spr_read_generic, &spr_write_generic,
5420 0x00000000);
5421
5422 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5423 &spr_read_ureg, SPR_NOACCESS,
5424 &spr_read_ureg, SPR_NOACCESS,
5425 0x00000000);
5426
5427 spr_register(env, SPR_7XX_PMC6, "PMC6",
5428 SPR_NOACCESS, SPR_NOACCESS,
5429 &spr_read_generic, &spr_write_generic,
5430 0x00000000);
5431
5432 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5433 &spr_read_ureg, SPR_NOACCESS,
5434 &spr_read_ureg, SPR_NOACCESS,
5435 0x00000000);
5436 /* SPRGs */
5437 spr_register(env, SPR_SPRG4, "SPRG4",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 spr_register(env, SPR_USPRG4, "USPRG4",
5442 &spr_read_ureg, SPR_NOACCESS,
5443 &spr_read_ureg, SPR_NOACCESS,
5444 0x00000000);
5445 spr_register(env, SPR_SPRG5, "SPRG5",
5446 SPR_NOACCESS, SPR_NOACCESS,
5447 &spr_read_generic, &spr_write_generic,
5448 0x00000000);
5449 spr_register(env, SPR_USPRG5, "USPRG5",
5450 &spr_read_ureg, SPR_NOACCESS,
5451 &spr_read_ureg, SPR_NOACCESS,
5452 0x00000000);
5453 spr_register(env, SPR_SPRG6, "SPRG6",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 spr_register(env, SPR_USPRG6, "USPRG6",
5458 &spr_read_ureg, SPR_NOACCESS,
5459 &spr_read_ureg, SPR_NOACCESS,
5460 0x00000000);
5461 spr_register(env, SPR_SPRG7, "SPRG7",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465 spr_register(env, SPR_USPRG7, "USPRG7",
5466 &spr_read_ureg, SPR_NOACCESS,
5467 &spr_read_ureg, SPR_NOACCESS,
5468 0x00000000);
5469 /* Memory management */
5470 register_low_BATs(env);
5471 register_high_BATs(env);
5472 init_excp_7450(env);
5473 env->dcache_line_size = 32;
5474 env->icache_line_size = 32;
5475 /* Allocate hardware IRQ controller */
5476 ppc6xx_irq_init(env_archcpu(env));
5477 }
5478
5479 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
5480 {
5481 DeviceClass *dc = DEVICE_CLASS(oc);
5482 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5483
5484 dc->desc = "PowerPC e600";
5485 pcc->init_proc = init_proc_e600;
5486 pcc->check_pow = check_pow_hid0_74xx;
5487 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5488 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5489 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5490 PPC_FLOAT_STFIWX |
5491 PPC_CACHE | PPC_CACHE_ICBI |
5492 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5493 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5494 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5495 PPC_MEM_TLBIA |
5496 PPC_SEGMENT | PPC_EXTERN |
5497 PPC_ALTIVEC;
5498 pcc->insns_flags2 = PPC_NONE;
5499 pcc->msr_mask = (1ull << MSR_VR) |
5500 (1ull << MSR_POW) |
5501 (1ull << MSR_ILE) |
5502 (1ull << MSR_EE) |
5503 (1ull << MSR_PR) |
5504 (1ull << MSR_FP) |
5505 (1ull << MSR_ME) |
5506 (1ull << MSR_FE0) |
5507 (1ull << MSR_SE) |
5508 (1ull << MSR_DE) |
5509 (1ull << MSR_FE1) |
5510 (1ull << MSR_EP) |
5511 (1ull << MSR_IR) |
5512 (1ull << MSR_DR) |
5513 (1ull << MSR_PMM) |
5514 (1ull << MSR_RI) |
5515 (1ull << MSR_LE);
5516 pcc->mmu_model = POWERPC_MMU_32B;
5517 pcc->excp_model = POWERPC_EXCP_74xx;
5518 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5519 pcc->bfd_mach = bfd_mach_ppc_7400;
5520 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5521 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5522 POWERPC_FLAG_BUS_CLK;
5523 }
5524
5525 #if defined(TARGET_PPC64)
5526 #if defined(CONFIG_USER_ONLY)
5527 #define POWERPC970_HID5_INIT 0x00000080
5528 #else
5529 #define POWERPC970_HID5_INIT 0x00000000
5530 #endif
5531
5532 static int check_pow_970(CPUPPCState *env)
5533 {
5534 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5535 return 1;
5536 }
5537
5538 return 0;
5539 }
5540
5541 static void register_970_hid_sprs(CPUPPCState *env)
5542 {
5543 /* Hardware implementation registers */
5544 spr_register(env, SPR_HID0, "HID0",
5545 SPR_NOACCESS, SPR_NOACCESS,
5546 &spr_read_generic, &spr_write_clear,
5547 0x60000000);
5548 spr_register(env, SPR_HID1, "HID1",
5549 SPR_NOACCESS, SPR_NOACCESS,
5550 &spr_read_generic, &spr_write_generic,
5551 0x00000000);
5552 spr_register(env, SPR_970_HID5, "HID5",
5553 SPR_NOACCESS, SPR_NOACCESS,
5554 &spr_read_generic, &spr_write_generic,
5555 POWERPC970_HID5_INIT);
5556 }
5557
5558 static void register_970_hior_sprs(CPUPPCState *env)
5559 {
5560 spr_register(env, SPR_HIOR, "SPR_HIOR",
5561 SPR_NOACCESS, SPR_NOACCESS,
5562 &spr_read_hior, &spr_write_hior,
5563 0x00000000);
5564 }
5565
5566 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5567 {
5568 spr_register(env, SPR_CTRL, "SPR_CTRL",
5569 SPR_NOACCESS, SPR_NOACCESS,
5570 SPR_NOACCESS, &spr_write_CTRL,
5571 0x00000000);
5572 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5573 &spr_read_ureg, SPR_NOACCESS,
5574 &spr_read_ureg, SPR_NOACCESS,
5575 0x00000000);
5576 }
5577
5578 static void register_book3s_altivec_sprs(CPUPPCState *env)
5579 {
5580 if (!(env->insns_flags & PPC_ALTIVEC)) {
5581 return;
5582 }
5583
5584 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5585 &spr_read_generic, &spr_write_generic,
5586 &spr_read_generic, &spr_write_generic,
5587 KVM_REG_PPC_VRSAVE, 0x00000000);
5588
5589 }
5590
5591 static void register_book3s_dbg_sprs(CPUPPCState *env)
5592 {
5593 /*
5594 * TODO: different specs define different scopes for these,
5595 * will have to address this:
5596 * 970: super/write and super/read
5597 * powerisa 2.03..2.04: hypv/write and super/read.
5598 * powerisa 2.05 and newer: hypv/write and hypv/read.
5599 */
5600 spr_register_kvm(env, SPR_DABR, "DABR",
5601 SPR_NOACCESS, SPR_NOACCESS,
5602 &spr_read_generic, &spr_write_generic,
5603 KVM_REG_PPC_DABR, 0x00000000);
5604 spr_register_kvm(env, SPR_DABRX, "DABRX",
5605 SPR_NOACCESS, SPR_NOACCESS,
5606 &spr_read_generic, &spr_write_generic,
5607 KVM_REG_PPC_DABRX, 0x00000000);
5608 }
5609
5610 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5611 {
5612 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5613 SPR_NOACCESS, SPR_NOACCESS,
5614 SPR_NOACCESS, SPR_NOACCESS,
5615 &spr_read_generic, &spr_write_generic,
5616 KVM_REG_PPC_DAWR, 0x00000000);
5617 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5618 SPR_NOACCESS, SPR_NOACCESS,
5619 SPR_NOACCESS, SPR_NOACCESS,
5620 &spr_read_generic, &spr_write_generic,
5621 KVM_REG_PPC_DAWRX, 0x00000000);
5622 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5623 SPR_NOACCESS, SPR_NOACCESS,
5624 SPR_NOACCESS, SPR_NOACCESS,
5625 &spr_read_generic, &spr_write_generic,
5626 KVM_REG_PPC_CIABR, 0x00000000);
5627 }
5628
5629 static void register_970_dbg_sprs(CPUPPCState *env)
5630 {
5631 /* Breakpoints */
5632 spr_register(env, SPR_IABR, "IABR",
5633 SPR_NOACCESS, SPR_NOACCESS,
5634 &spr_read_generic, &spr_write_generic,
5635 0x00000000);
5636 }
5637
5638 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5639 {
5640 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5641 SPR_NOACCESS, SPR_NOACCESS,
5642 &spr_read_generic, &spr_write_MMCR0,
5643 KVM_REG_PPC_MMCR0, 0x80000000);
5644 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5645 SPR_NOACCESS, SPR_NOACCESS,
5646 &spr_read_generic, &spr_write_MMCR1,
5647 KVM_REG_PPC_MMCR1, 0x00000000);
5648 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5649 SPR_NOACCESS, SPR_NOACCESS,
5650 &spr_read_generic, &spr_write_generic,
5651 KVM_REG_PPC_MMCRA, 0x00000000);
5652 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5653 SPR_NOACCESS, SPR_NOACCESS,
5654 &spr_read_PMC, &spr_write_PMC,
5655 KVM_REG_PPC_PMC1, 0x00000000);
5656 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_PMC, &spr_write_PMC,
5659 KVM_REG_PPC_PMC2, 0x00000000);
5660 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5661 SPR_NOACCESS, SPR_NOACCESS,
5662 &spr_read_PMC, &spr_write_PMC,
5663 KVM_REG_PPC_PMC3, 0x00000000);
5664 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5665 SPR_NOACCESS, SPR_NOACCESS,
5666 &spr_read_PMC, &spr_write_PMC,
5667 KVM_REG_PPC_PMC4, 0x00000000);
5668 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5669 SPR_NOACCESS, SPR_NOACCESS,
5670 &spr_read_PMC, &spr_write_PMC,
5671 KVM_REG_PPC_PMC5, 0x00000000);
5672 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5673 SPR_NOACCESS, SPR_NOACCESS,
5674 &spr_read_PMC, &spr_write_PMC,
5675 KVM_REG_PPC_PMC6, 0x00000000);
5676 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5677 SPR_NOACCESS, SPR_NOACCESS,
5678 &spr_read_generic, &spr_write_generic,
5679 KVM_REG_PPC_SIAR, 0x00000000);
5680 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5681 SPR_NOACCESS, SPR_NOACCESS,
5682 &spr_read_generic, &spr_write_generic,
5683 KVM_REG_PPC_SDAR, 0x00000000);
5684 }
5685
5686 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5687 {
5688 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5689 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5690 &spr_read_ureg, &spr_write_ureg,
5691 0x80000000);
5692 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5693 &spr_read_ureg, SPR_NOACCESS,
5694 &spr_read_ureg, &spr_write_ureg,
5695 0x00000000);
5696 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5697 &spr_read_ureg, SPR_NOACCESS,
5698 &spr_read_ureg, &spr_write_ureg,
5699 0x00000000);
5700 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5701 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5702 &spr_read_ureg, &spr_write_ureg,
5703 0x00000000);
5704 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5705 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5706 &spr_read_ureg, &spr_write_ureg,
5707 0x00000000);
5708 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5709 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5710 &spr_read_ureg, &spr_write_ureg,
5711 0x00000000);
5712 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5713 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5714 &spr_read_ureg, &spr_write_ureg,
5715 0x00000000);
5716 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5717 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5718 &spr_read_ureg, &spr_write_ureg,
5719 0x00000000);
5720 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5721 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5722 &spr_read_ureg, &spr_write_ureg,
5723 0x00000000);
5724 spr_register(env, SPR_POWER_USIAR, "USIAR",
5725 &spr_read_ureg, SPR_NOACCESS,
5726 &spr_read_ureg, &spr_write_ureg,
5727 0x00000000);
5728 spr_register(env, SPR_POWER_USDAR, "USDAR",
5729 &spr_read_ureg, SPR_NOACCESS,
5730 &spr_read_ureg, &spr_write_ureg,
5731 0x00000000);
5732 }
5733
5734 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5735 {
5736 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_read_generic, &spr_write_generic,
5739 KVM_REG_PPC_PMC7, 0x00000000);
5740 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5741 SPR_NOACCESS, SPR_NOACCESS,
5742 &spr_read_generic, &spr_write_generic,
5743 KVM_REG_PPC_PMC8, 0x00000000);
5744 }
5745
5746 static void register_970_pmu_user_sprs(CPUPPCState *env)
5747 {
5748 spr_register(env, SPR_970_UPMC7, "UPMC7",
5749 &spr_read_ureg, SPR_NOACCESS,
5750 &spr_read_ureg, &spr_write_ureg,
5751 0x00000000);
5752 spr_register(env, SPR_970_UPMC8, "UPMC8",
5753 &spr_read_ureg, SPR_NOACCESS,
5754 &spr_read_ureg, &spr_write_ureg,
5755 0x00000000);
5756 }
5757
5758 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5759 {
5760 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5761 SPR_NOACCESS, SPR_NOACCESS,
5762 &spr_read_generic, &spr_write_generic,
5763 KVM_REG_PPC_MMCR2, 0x00000000);
5764 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_write_generic,
5767 KVM_REG_PPC_MMCRS, 0x00000000);
5768 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5769 SPR_NOACCESS, SPR_NOACCESS,
5770 &spr_read_generic, &spr_write_generic,
5771 KVM_REG_PPC_SIER, 0x00000000);
5772 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5773 SPR_NOACCESS, SPR_NOACCESS,
5774 &spr_read_generic, &spr_write_generic,
5775 KVM_REG_PPC_SPMC1, 0x00000000);
5776 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5777 SPR_NOACCESS, SPR_NOACCESS,
5778 &spr_read_generic, &spr_write_generic,
5779 KVM_REG_PPC_SPMC2, 0x00000000);
5780 spr_register_kvm(env, SPR_TACR, "TACR",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 KVM_REG_PPC_TACR, 0x00000000);
5784 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5785 SPR_NOACCESS, SPR_NOACCESS,
5786 &spr_read_generic, &spr_write_generic,
5787 KVM_REG_PPC_TCSCR, 0x00000000);
5788 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5789 SPR_NOACCESS, SPR_NOACCESS,
5790 &spr_read_generic, &spr_write_generic,
5791 KVM_REG_PPC_CSIGR, 0x00000000);
5792 }
5793
5794 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5795 {
5796 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5797 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5798 &spr_read_ureg, &spr_write_ureg,
5799 0x00000000);
5800 spr_register(env, SPR_POWER_USIER, "USIER",
5801 &spr_read_generic, SPR_NOACCESS,
5802 &spr_read_generic, &spr_write_generic,
5803 0x00000000);
5804 }
5805
5806 static void register_power5p_ear_sprs(CPUPPCState *env)
5807 {
5808 /* External access control */
5809 spr_register(env, SPR_EAR, "EAR",
5810 SPR_NOACCESS, SPR_NOACCESS,
5811 &spr_read_generic, &spr_write_generic,
5812 0x00000000);
5813 }
5814
5815 static void register_power5p_tb_sprs(CPUPPCState *env)
5816 {
5817 /* TBU40 (High 40 bits of the Timebase register */
5818 spr_register_hv(env, SPR_TBU40, "TBU40",
5819 SPR_NOACCESS, SPR_NOACCESS,
5820 SPR_NOACCESS, SPR_NOACCESS,
5821 SPR_NOACCESS, &spr_write_tbu40,
5822 0x00000000);
5823 }
5824
5825 static void register_970_lpar_sprs(CPUPPCState *env)
5826 {
5827 #if !defined(CONFIG_USER_ONLY)
5828 /*
5829 * PPC970: HID4 covers things later controlled by the LPCR and
5830 * RMOR in later CPUs, but with a different encoding. We only
5831 * support the 970 in "Apple mode" which has all hypervisor
5832 * facilities disabled by strapping, so we can basically just
5833 * ignore it
5834 */
5835 spr_register(env, SPR_970_HID4, "HID4",
5836 SPR_NOACCESS, SPR_NOACCESS,
5837 &spr_read_generic, &spr_write_generic,
5838 0x00000000);
5839 #endif
5840 }
5841
5842 static void register_power5p_lpar_sprs(CPUPPCState *env)
5843 {
5844 #if !defined(CONFIG_USER_ONLY)
5845 /* Logical partitionning */
5846 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_write_lpcr,
5850 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5851 spr_register_hv(env, SPR_HDEC, "HDEC",
5852 SPR_NOACCESS, SPR_NOACCESS,
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_hdecr, &spr_write_hdecr, 0);
5855 #endif
5856 }
5857
5858 static void register_book3s_ids_sprs(CPUPPCState *env)
5859 {
5860 /* FIXME: Will need to deal with thread vs core only SPRs */
5861
5862 /* Processor identification */
5863 spr_register_hv(env, SPR_PIR, "PIR",
5864 SPR_NOACCESS, SPR_NOACCESS,
5865 &spr_read_generic, SPR_NOACCESS,
5866 &spr_read_generic, NULL,
5867 0x00000000);
5868 spr_register_hv(env, SPR_HID0, "HID0",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 SPR_NOACCESS, SPR_NOACCESS,
5871 &spr_read_generic, &spr_write_generic,
5872 0x00000000);
5873 spr_register_hv(env, SPR_TSCR, "TSCR",
5874 SPR_NOACCESS, SPR_NOACCESS,
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 &spr_read_generic, &spr_write_generic,
5877 0x00000000);
5878 spr_register_hv(env, SPR_HMER, "HMER",
5879 SPR_NOACCESS, SPR_NOACCESS,
5880 SPR_NOACCESS, SPR_NOACCESS,
5881 &spr_read_generic, &spr_write_hmer,
5882 0x00000000);
5883 spr_register_hv(env, SPR_HMEER, "HMEER",
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 SPR_NOACCESS, SPR_NOACCESS,
5886 &spr_read_generic, &spr_write_generic,
5887 0x00000000);
5888 spr_register_hv(env, SPR_TFMR, "TFMR",
5889 SPR_NOACCESS, SPR_NOACCESS,
5890 SPR_NOACCESS, SPR_NOACCESS,
5891 &spr_read_generic, &spr_write_generic,
5892 0x00000000);
5893 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 SPR_NOACCESS, SPR_NOACCESS,
5896 &spr_read_generic, &spr_write_lpidr,
5897 0x00000000);
5898 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5899 SPR_NOACCESS, SPR_NOACCESS,
5900 SPR_NOACCESS, SPR_NOACCESS,
5901 &spr_read_generic, &spr_write_generic,
5902 0x00000000);
5903 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5904 SPR_NOACCESS, SPR_NOACCESS,
5905 SPR_NOACCESS, SPR_NOACCESS,
5906 &spr_read_generic, &spr_write_generic,
5907 0x00000000);
5908 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 SPR_NOACCESS, SPR_NOACCESS,
5911 &spr_read_generic, &spr_write_generic,
5912 0x00000000);
5913 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5914 SPR_NOACCESS, SPR_NOACCESS,
5915 SPR_NOACCESS, SPR_NOACCESS,
5916 &spr_read_generic, &spr_write_generic,
5917 0x00000000);
5918 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 SPR_NOACCESS, SPR_NOACCESS,
5921 &spr_read_generic, &spr_write_generic,
5922 0x00000000);
5923 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5924 SPR_NOACCESS, SPR_NOACCESS,
5925 SPR_NOACCESS, SPR_NOACCESS,
5926 &spr_read_generic, &spr_write_generic,
5927 0x00000000);
5928 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5929 SPR_NOACCESS, SPR_NOACCESS,
5930 SPR_NOACCESS, SPR_NOACCESS,
5931 &spr_read_generic, &spr_write_generic,
5932 0x00000000);
5933 spr_register_hv(env, SPR_HDAR, "HDAR",
5934 SPR_NOACCESS, SPR_NOACCESS,
5935 SPR_NOACCESS, SPR_NOACCESS,
5936 &spr_read_generic, &spr_write_generic,
5937 0x00000000);
5938 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5939 SPR_NOACCESS, SPR_NOACCESS,
5940 SPR_NOACCESS, SPR_NOACCESS,
5941 &spr_read_generic, &spr_write_generic,
5942 0x00000000);
5943 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5944 SPR_NOACCESS, SPR_NOACCESS,
5945 SPR_NOACCESS, SPR_NOACCESS,
5946 &spr_read_generic, &spr_write_generic,
5947 0x00000000);
5948 }
5949
5950 static void register_rmor_sprs(CPUPPCState *env)
5951 {
5952 spr_register_hv(env, SPR_RMOR, "RMOR",
5953 SPR_NOACCESS, SPR_NOACCESS,
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 0x00000000);
5957 }
5958
5959 static void register_power8_ids_sprs(CPUPPCState *env)
5960 {
5961 /* Thread identification */
5962 spr_register(env, SPR_TIR, "TIR",
5963 SPR_NOACCESS, SPR_NOACCESS,
5964 &spr_read_generic, SPR_NOACCESS,
5965 0x00000000);
5966 }
5967
5968 static void register_book3s_purr_sprs(CPUPPCState *env)
5969 {
5970 #if !defined(CONFIG_USER_ONLY)
5971 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5972 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5973 &spr_read_purr, SPR_NOACCESS,
5974 &spr_read_purr, SPR_NOACCESS,
5975 &spr_read_purr, &spr_write_purr,
5976 KVM_REG_PPC_PURR, 0x00000000);
5977 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5978 &spr_read_purr, SPR_NOACCESS,
5979 &spr_read_purr, SPR_NOACCESS,
5980 &spr_read_purr, &spr_write_purr,
5981 KVM_REG_PPC_SPURR, 0x00000000);
5982 #endif
5983 }
5984
5985 static void register_power6_dbg_sprs(CPUPPCState *env)
5986 {
5987 #if !defined(CONFIG_USER_ONLY)
5988 spr_register(env, SPR_CFAR, "SPR_CFAR",
5989 SPR_NOACCESS, SPR_NOACCESS,
5990 &spr_read_cfar, &spr_write_cfar,
5991 0x00000000);
5992 #endif
5993 }
5994
5995 static void register_power5p_common_sprs(CPUPPCState *env)
5996 {
5997 spr_register_kvm(env, SPR_PPR, "PPR",
5998 &spr_read_generic, &spr_write_generic,
5999 &spr_read_generic, &spr_write_generic,
6000 KVM_REG_PPC_PPR, 0x00000000);
6001 }
6002
6003 static void register_power6_common_sprs(CPUPPCState *env)
6004 {
6005 #if !defined(CONFIG_USER_ONLY)
6006 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6007 SPR_NOACCESS, SPR_NOACCESS,
6008 &spr_read_generic, &spr_write_generic,
6009 KVM_REG_PPC_DSCR, 0x00000000);
6010 #endif
6011 /*
6012 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
6013 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
6014 */
6015 spr_register_hv(env, SPR_PCR, "PCR",
6016 SPR_NOACCESS, SPR_NOACCESS,
6017 SPR_NOACCESS, SPR_NOACCESS,
6018 &spr_read_generic, &spr_write_pcr,
6019 0x00000000);
6020 }
6021
6022 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
6023 {
6024 spr_register_kvm(env, SPR_TAR, "TAR",
6025 &spr_read_tar, &spr_write_tar,
6026 &spr_read_generic, &spr_write_generic,
6027 KVM_REG_PPC_TAR, 0x00000000);
6028 }
6029
6030 static void register_power8_tm_sprs(CPUPPCState *env)
6031 {
6032 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
6033 &spr_read_tm, &spr_write_tm,
6034 &spr_read_tm, &spr_write_tm,
6035 KVM_REG_PPC_TFHAR, 0x00000000);
6036 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
6037 &spr_read_tm, &spr_write_tm,
6038 &spr_read_tm, &spr_write_tm,
6039 KVM_REG_PPC_TFIAR, 0x00000000);
6040 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
6041 &spr_read_tm, &spr_write_tm,
6042 &spr_read_tm, &spr_write_tm,
6043 KVM_REG_PPC_TEXASR, 0x00000000);
6044 spr_register(env, SPR_TEXASRU, "TEXASRU",
6045 &spr_read_tm_upper32, &spr_write_tm_upper32,
6046 &spr_read_tm_upper32, &spr_write_tm_upper32,
6047 0x00000000);
6048 }
6049
6050 static void register_power8_ebb_sprs(CPUPPCState *env)
6051 {
6052 spr_register(env, SPR_BESCRS, "BESCRS",
6053 &spr_read_ebb, &spr_write_ebb,
6054 &spr_read_generic, &spr_write_generic,
6055 0x00000000);
6056 spr_register(env, SPR_BESCRSU, "BESCRSU",
6057 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6058 &spr_read_prev_upper32, &spr_write_prev_upper32,
6059 0x00000000);
6060 spr_register(env, SPR_BESCRR, "BESCRR",
6061 &spr_read_ebb, &spr_write_ebb,
6062 &spr_read_generic, &spr_write_generic,
6063 0x00000000);
6064 spr_register(env, SPR_BESCRRU, "BESCRRU",
6065 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6066 &spr_read_prev_upper32, &spr_write_prev_upper32,
6067 0x00000000);
6068 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
6069 &spr_read_ebb, &spr_write_ebb,
6070 &spr_read_generic, &spr_write_generic,
6071 KVM_REG_PPC_EBBHR, 0x00000000);
6072 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
6073 &spr_read_ebb, &spr_write_ebb,
6074 &spr_read_generic, &spr_write_generic,
6075 KVM_REG_PPC_EBBRR, 0x00000000);
6076 spr_register_kvm(env, SPR_BESCR, "BESCR",
6077 &spr_read_ebb, &spr_write_ebb,
6078 &spr_read_generic, &spr_write_generic,
6079 KVM_REG_PPC_BESCR, 0x00000000);
6080 }
6081
6082 /* Virtual Time Base */
6083 static void register_vtb_sprs(CPUPPCState *env)
6084 {
6085 spr_register_kvm_hv(env, SPR_VTB, "VTB",
6086 SPR_NOACCESS, SPR_NOACCESS,
6087 &spr_read_vtb, SPR_NOACCESS,
6088 &spr_read_vtb, &spr_write_vtb,
6089 KVM_REG_PPC_VTB, 0x00000000);
6090 }
6091
6092 static void register_power8_fscr_sprs(CPUPPCState *env)
6093 {
6094 #if defined(CONFIG_USER_ONLY)
6095 target_ulong initval = 1ULL << FSCR_TAR;
6096 #else
6097 target_ulong initval = 0;
6098 #endif
6099 spr_register_kvm(env, SPR_FSCR, "FSCR",
6100 SPR_NOACCESS, SPR_NOACCESS,
6101 &spr_read_generic, &spr_write_generic,
6102 KVM_REG_PPC_FSCR, initval);
6103 }
6104
6105 static void register_power8_pspb_sprs(CPUPPCState *env)
6106 {
6107 spr_register_kvm(env, SPR_PSPB, "PSPB",
6108 SPR_NOACCESS, SPR_NOACCESS,
6109 &spr_read_generic, &spr_write_generic32,
6110 KVM_REG_PPC_PSPB, 0);
6111 }
6112
6113 static void register_power8_dpdes_sprs(CPUPPCState *env)
6114 {
6115 #if !defined(CONFIG_USER_ONLY)
6116 /* Directed Privileged Door-bell Exception State, used for IPI */
6117 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
6118 SPR_NOACCESS, SPR_NOACCESS,
6119 &spr_read_dpdes, SPR_NOACCESS,
6120 &spr_read_dpdes, &spr_write_dpdes,
6121 KVM_REG_PPC_DPDES, 0x00000000);
6122 #endif
6123 }
6124
6125 static void register_power8_ic_sprs(CPUPPCState *env)
6126 {
6127 #if !defined(CONFIG_USER_ONLY)
6128 spr_register_hv(env, SPR_IC, "IC",
6129 SPR_NOACCESS, SPR_NOACCESS,
6130 &spr_read_generic, SPR_NOACCESS,
6131 &spr_read_generic, &spr_write_generic,
6132 0);
6133 #endif
6134 }
6135
6136 static void register_power8_book4_sprs(CPUPPCState *env)
6137 {
6138 /* Add a number of P8 book4 registers */
6139 #if !defined(CONFIG_USER_ONLY)
6140 spr_register_kvm(env, SPR_ACOP, "ACOP",
6141 SPR_NOACCESS, SPR_NOACCESS,
6142 &spr_read_generic, &spr_write_generic,
6143 KVM_REG_PPC_ACOP, 0);
6144 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6145 SPR_NOACCESS, SPR_NOACCESS,
6146 &spr_read_generic, &spr_write_pidr,
6147 KVM_REG_PPC_PID, 0);
6148 spr_register_kvm(env, SPR_WORT, "WORT",
6149 SPR_NOACCESS, SPR_NOACCESS,
6150 &spr_read_generic, &spr_write_generic,
6151 KVM_REG_PPC_WORT, 0);
6152 #endif
6153 }
6154
6155 static void register_power7_book4_sprs(CPUPPCState *env)
6156 {
6157 /* Add a number of P7 book4 registers */
6158 #if !defined(CONFIG_USER_ONLY)
6159 spr_register_kvm(env, SPR_ACOP, "ACOP",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, &spr_write_generic,
6162 KVM_REG_PPC_ACOP, 0);
6163 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6164 SPR_NOACCESS, SPR_NOACCESS,
6165 &spr_read_generic, &spr_write_generic,
6166 KVM_REG_PPC_PID, 0);
6167 #endif
6168 }
6169
6170 static void register_power8_rpr_sprs(CPUPPCState *env)
6171 {
6172 #if !defined(CONFIG_USER_ONLY)
6173 spr_register_hv(env, SPR_RPR, "RPR",
6174 SPR_NOACCESS, SPR_NOACCESS,
6175 SPR_NOACCESS, SPR_NOACCESS,
6176 &spr_read_generic, &spr_write_generic,
6177 0x00000103070F1F3F);
6178 #endif
6179 }
6180
6181 static void register_power9_mmu_sprs(CPUPPCState *env)
6182 {
6183 #if !defined(CONFIG_USER_ONLY)
6184 /* Partition Table Control */
6185 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
6186 SPR_NOACCESS, SPR_NOACCESS,
6187 SPR_NOACCESS, SPR_NOACCESS,
6188 &spr_read_generic, &spr_write_ptcr,
6189 KVM_REG_PPC_PTCR, 0x00000000);
6190 /* Address Segment Descriptor Register */
6191 spr_register_hv(env, SPR_ASDR, "ASDR",
6192 SPR_NOACCESS, SPR_NOACCESS,
6193 SPR_NOACCESS, SPR_NOACCESS,
6194 &spr_read_generic, &spr_write_generic,
6195 0x0000000000000000);
6196 #endif
6197 }
6198
6199 /*
6200 * Initialize PMU counter overflow timers for Power8 and
6201 * newer Power chips when using TCG.
6202 */
6203 static void init_tcg_pmu_power8(CPUPPCState *env)
6204 {
6205 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
6206 /* Init PMU overflow timers */
6207 if (!kvm_enabled()) {
6208 cpu_ppc_pmu_init(env);
6209 }
6210 #endif
6211 }
6212
6213 static void init_proc_book3s_common(CPUPPCState *env)
6214 {
6215 register_ne_601_sprs(env);
6216 register_usprg3_sprs(env);
6217 register_book3s_altivec_sprs(env);
6218 register_book3s_pmu_sup_sprs(env);
6219 register_book3s_pmu_user_sprs(env);
6220 register_book3s_ctrl_sprs(env);
6221 /*
6222 * Can't find information on what this should be on reset. This
6223 * value is the one used by 74xx processors.
6224 */
6225 vscr_init(env, 0x00010000);
6226 }
6227
6228 static void init_proc_970(CPUPPCState *env)
6229 {
6230 /* Common Registers */
6231 init_proc_book3s_common(env);
6232 register_sdr1_sprs(env);
6233 register_book3s_dbg_sprs(env);
6234
6235 /* 970 Specific Registers */
6236 register_970_hid_sprs(env);
6237 register_970_hior_sprs(env);
6238 register_low_BATs(env);
6239 register_970_pmu_sup_sprs(env);
6240 register_970_pmu_user_sprs(env);
6241 register_970_lpar_sprs(env);
6242 register_970_dbg_sprs(env);
6243
6244 /* env variables */
6245 env->dcache_line_size = 128;
6246 env->icache_line_size = 128;
6247
6248 /* Allocate hardware IRQ controller */
6249 init_excp_970(env);
6250 ppc970_irq_init(env_archcpu(env));
6251 }
6252
6253 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6254 {
6255 DeviceClass *dc = DEVICE_CLASS(oc);
6256 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6257
6258 dc->desc = "PowerPC 970";
6259 pcc->init_proc = init_proc_970;
6260 pcc->check_pow = check_pow_970;
6261 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6262 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6263 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6264 PPC_FLOAT_STFIWX |
6265 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6266 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6267 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6268 PPC_64B | PPC_ALTIVEC |
6269 PPC_SEGMENT_64B | PPC_SLBI;
6270 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6271 pcc->msr_mask = (1ull << MSR_SF) |
6272 (1ull << MSR_VR) |
6273 (1ull << MSR_POW) |
6274 (1ull << MSR_EE) |
6275 (1ull << MSR_PR) |
6276 (1ull << MSR_FP) |
6277 (1ull << MSR_ME) |
6278 (1ull << MSR_FE0) |
6279 (1ull << MSR_SE) |
6280 (1ull << MSR_DE) |
6281 (1ull << MSR_FE1) |
6282 (1ull << MSR_IR) |
6283 (1ull << MSR_DR) |
6284 (1ull << MSR_PMM) |
6285 (1ull << MSR_RI);
6286 pcc->mmu_model = POWERPC_MMU_64B;
6287 #if defined(CONFIG_SOFTMMU)
6288 pcc->hash64_opts = &ppc_hash64_opts_basic;
6289 #endif
6290 pcc->excp_model = POWERPC_EXCP_970;
6291 pcc->bus_model = PPC_FLAGS_INPUT_970;
6292 pcc->bfd_mach = bfd_mach_ppc64;
6293 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6294 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6295 POWERPC_FLAG_BUS_CLK;
6296 pcc->l1_dcache_size = 0x8000;
6297 pcc->l1_icache_size = 0x10000;
6298 }
6299
6300 static void init_proc_power5plus(CPUPPCState *env)
6301 {
6302 /* Common Registers */
6303 init_proc_book3s_common(env);
6304 register_sdr1_sprs(env);
6305 register_book3s_dbg_sprs(env);
6306
6307 /* POWER5+ Specific Registers */
6308 register_970_hid_sprs(env);
6309 register_970_hior_sprs(env);
6310 register_low_BATs(env);
6311 register_970_pmu_sup_sprs(env);
6312 register_970_pmu_user_sprs(env);
6313 register_power5p_common_sprs(env);
6314 register_power5p_lpar_sprs(env);
6315 register_power5p_ear_sprs(env);
6316 register_power5p_tb_sprs(env);
6317
6318 /* env variables */
6319 env->dcache_line_size = 128;
6320 env->icache_line_size = 128;
6321
6322 /* Allocate hardware IRQ controller */
6323 init_excp_970(env);
6324 ppc970_irq_init(env_archcpu(env));
6325 }
6326
6327 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6328 {
6329 DeviceClass *dc = DEVICE_CLASS(oc);
6330 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6331
6332 dc->fw_name = "PowerPC,POWER5";
6333 dc->desc = "POWER5+";
6334 pcc->init_proc = init_proc_power5plus;
6335 pcc->check_pow = check_pow_970;
6336 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6337 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6338 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6339 PPC_FLOAT_STFIWX |
6340 PPC_FLOAT_EXT |
6341 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6342 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6343 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6344 PPC_64B |
6345 PPC_POPCNTB |
6346 PPC_SEGMENT_64B | PPC_SLBI;
6347 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6348 pcc->msr_mask = (1ull << MSR_SF) |
6349 (1ull << MSR_VR) |
6350 (1ull << MSR_POW) |
6351 (1ull << MSR_EE) |
6352 (1ull << MSR_PR) |
6353 (1ull << MSR_FP) |
6354 (1ull << MSR_ME) |
6355 (1ull << MSR_FE0) |
6356 (1ull << MSR_SE) |
6357 (1ull << MSR_DE) |
6358 (1ull << MSR_FE1) |
6359 (1ull << MSR_IR) |
6360 (1ull << MSR_DR) |
6361 (1ull << MSR_PMM) |
6362 (1ull << MSR_RI);
6363 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6364 LPCR_RMI | LPCR_HDICE;
6365 pcc->mmu_model = POWERPC_MMU_2_03;
6366 #if defined(CONFIG_SOFTMMU)
6367 pcc->hash64_opts = &ppc_hash64_opts_basic;
6368 pcc->lrg_decr_bits = 32;
6369 #endif
6370 pcc->excp_model = POWERPC_EXCP_970;
6371 pcc->bus_model = PPC_FLAGS_INPUT_970;
6372 pcc->bfd_mach = bfd_mach_ppc64;
6373 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6374 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6375 POWERPC_FLAG_BUS_CLK;
6376 pcc->l1_dcache_size = 0x8000;
6377 pcc->l1_icache_size = 0x10000;
6378 }
6379
6380 static void init_proc_POWER7(CPUPPCState *env)
6381 {
6382 /* Common Registers */
6383 init_proc_book3s_common(env);
6384 register_sdr1_sprs(env);
6385 register_book3s_dbg_sprs(env);
6386
6387 /* POWER7 Specific Registers */
6388 register_book3s_ids_sprs(env);
6389 register_rmor_sprs(env);
6390 register_amr_sprs(env);
6391 register_book3s_purr_sprs(env);
6392 register_power5p_common_sprs(env);
6393 register_power5p_lpar_sprs(env);
6394 register_power5p_ear_sprs(env);
6395 register_power5p_tb_sprs(env);
6396 register_power6_common_sprs(env);
6397 register_power6_dbg_sprs(env);
6398 register_power7_book4_sprs(env);
6399
6400 /* env variables */
6401 env->dcache_line_size = 128;
6402 env->icache_line_size = 128;
6403
6404 /* Allocate hardware IRQ controller */
6405 init_excp_POWER7(env);
6406 ppcPOWER7_irq_init(env_archcpu(env));
6407 }
6408
6409 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
6410 {
6411 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
6412 return true;
6413 }
6414 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
6415 return true;
6416 }
6417 return false;
6418 }
6419
6420 static bool cpu_has_work_POWER7(CPUState *cs)
6421 {
6422 PowerPCCPU *cpu = POWERPC_CPU(cs);
6423 CPUPPCState *env = &cpu->env;
6424
6425 if (cs->halted) {
6426 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6427 return false;
6428 }
6429 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6430 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
6431 return true;
6432 }
6433 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6434 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
6435 return true;
6436 }
6437 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6438 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6439 return true;
6440 }
6441 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6442 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6443 return true;
6444 }
6445 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6446 return true;
6447 }
6448 return false;
6449 } else {
6450 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6451 }
6452 }
6453
6454 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6455 {
6456 DeviceClass *dc = DEVICE_CLASS(oc);
6457 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6458 CPUClass *cc = CPU_CLASS(oc);
6459
6460 dc->fw_name = "PowerPC,POWER7";
6461 dc->desc = "POWER7";
6462 pcc->pvr_match = ppc_pvr_match_power7;
6463 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6464 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6465 pcc->init_proc = init_proc_POWER7;
6466 pcc->check_pow = check_pow_nocheck;
6467 cc->has_work = cpu_has_work_POWER7;
6468 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6469 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6470 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6471 PPC_FLOAT_FRSQRTES |
6472 PPC_FLOAT_STFIWX |
6473 PPC_FLOAT_EXT |
6474 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6475 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6476 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6477 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6478 PPC_SEGMENT_64B | PPC_SLBI |
6479 PPC_POPCNTB | PPC_POPCNTWD |
6480 PPC_CILDST;
6481 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6482 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6483 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6484 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6485 PPC2_PM_ISA206;
6486 pcc->msr_mask = (1ull << MSR_SF) |
6487 (1ull << MSR_VR) |
6488 (1ull << MSR_VSX) |
6489 (1ull << MSR_EE) |
6490 (1ull << MSR_PR) |
6491 (1ull << MSR_FP) |
6492 (1ull << MSR_ME) |
6493 (1ull << MSR_FE0) |
6494 (1ull << MSR_SE) |
6495 (1ull << MSR_DE) |
6496 (1ull << MSR_FE1) |
6497 (1ull << MSR_IR) |
6498 (1ull << MSR_DR) |
6499 (1ull << MSR_PMM) |
6500 (1ull << MSR_RI) |
6501 (1ull << MSR_LE);
6502 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6503 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6504 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6505 LPCR_MER | LPCR_TC |
6506 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6507 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6508 pcc->mmu_model = POWERPC_MMU_2_06;
6509 #if defined(CONFIG_SOFTMMU)
6510 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6511 pcc->lrg_decr_bits = 32;
6512 #endif
6513 pcc->excp_model = POWERPC_EXCP_POWER7;
6514 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6515 pcc->bfd_mach = bfd_mach_ppc64;
6516 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6517 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6518 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6519 POWERPC_FLAG_VSX;
6520 pcc->l1_dcache_size = 0x8000;
6521 pcc->l1_icache_size = 0x8000;
6522 }
6523
6524 static void init_proc_POWER8(CPUPPCState *env)
6525 {
6526 /* Common Registers */
6527 init_proc_book3s_common(env);
6528 register_sdr1_sprs(env);
6529 register_book3s_207_dbg_sprs(env);
6530
6531 /* Common TCG PMU */
6532 init_tcg_pmu_power8(env);
6533
6534 /* POWER8 Specific Registers */
6535 register_book3s_ids_sprs(env);
6536 register_rmor_sprs(env);
6537 register_amr_sprs(env);
6538 register_iamr_sprs(env);
6539 register_book3s_purr_sprs(env);
6540 register_power5p_common_sprs(env);
6541 register_power5p_lpar_sprs(env);
6542 register_power5p_ear_sprs(env);
6543 register_power5p_tb_sprs(env);
6544 register_power6_common_sprs(env);
6545 register_power6_dbg_sprs(env);
6546 register_power8_tce_address_control_sprs(env);
6547 register_power8_ids_sprs(env);
6548 register_power8_ebb_sprs(env);
6549 register_power8_fscr_sprs(env);
6550 register_power8_pmu_sup_sprs(env);
6551 register_power8_pmu_user_sprs(env);
6552 register_power8_tm_sprs(env);
6553 register_power8_pspb_sprs(env);
6554 register_power8_dpdes_sprs(env);
6555 register_vtb_sprs(env);
6556 register_power8_ic_sprs(env);
6557 register_power8_book4_sprs(env);
6558 register_power8_rpr_sprs(env);
6559
6560 /* env variables */
6561 env->dcache_line_size = 128;
6562 env->icache_line_size = 128;
6563
6564 /* Allocate hardware IRQ controller */
6565 init_excp_POWER8(env);
6566 ppcPOWER7_irq_init(env_archcpu(env));
6567 }
6568
6569 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
6570 {
6571 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
6572 return true;
6573 }
6574 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
6575 return true;
6576 }
6577 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
6578 return true;
6579 }
6580 return false;
6581 }
6582
6583 static bool cpu_has_work_POWER8(CPUState *cs)
6584 {
6585 PowerPCCPU *cpu = POWERPC_CPU(cs);
6586 CPUPPCState *env = &cpu->env;
6587
6588 if (cs->halted) {
6589 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6590 return false;
6591 }
6592 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6593 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6594 return true;
6595 }
6596 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6597 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6598 return true;
6599 }
6600 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6601 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6602 return true;
6603 }
6604 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6605 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6606 return true;
6607 }
6608 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6609 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6610 return true;
6611 }
6612 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6613 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6614 return true;
6615 }
6616 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6617 return true;
6618 }
6619 return false;
6620 } else {
6621 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6622 }
6623 }
6624
6625 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6626 {
6627 DeviceClass *dc = DEVICE_CLASS(oc);
6628 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6629 CPUClass *cc = CPU_CLASS(oc);
6630
6631 dc->fw_name = "PowerPC,POWER8";
6632 dc->desc = "POWER8";
6633 pcc->pvr_match = ppc_pvr_match_power8;
6634 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6635 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6636 pcc->init_proc = init_proc_POWER8;
6637 pcc->check_pow = check_pow_nocheck;
6638 cc->has_work = cpu_has_work_POWER8;
6639 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6640 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6641 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6642 PPC_FLOAT_FRSQRTES |
6643 PPC_FLOAT_STFIWX |
6644 PPC_FLOAT_EXT |
6645 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6646 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6647 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6648 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6649 PPC_SEGMENT_64B | PPC_SLBI |
6650 PPC_POPCNTB | PPC_POPCNTWD |
6651 PPC_CILDST;
6652 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6653 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6654 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6655 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6656 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6657 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6658 PPC2_TM | PPC2_PM_ISA206;
6659 pcc->msr_mask = (1ull << MSR_SF) |
6660 (1ull << MSR_HV) |
6661 (1ull << MSR_TM) |
6662 (1ull << MSR_VR) |
6663 (1ull << MSR_VSX) |
6664 (1ull << MSR_EE) |
6665 (1ull << MSR_PR) |
6666 (1ull << MSR_FP) |
6667 (1ull << MSR_ME) |
6668 (1ull << MSR_FE0) |
6669 (1ull << MSR_SE) |
6670 (1ull << MSR_DE) |
6671 (1ull << MSR_FE1) |
6672 (1ull << MSR_IR) |
6673 (1ull << MSR_DR) |
6674 (1ull << MSR_PMM) |
6675 (1ull << MSR_RI) |
6676 (1ull << MSR_TS0) |
6677 (1ull << MSR_TS1) |
6678 (1ull << MSR_LE);
6679 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6680 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6681 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6682 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6683 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6684 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6685 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6686 pcc->mmu_model = POWERPC_MMU_2_07;
6687 #if defined(CONFIG_SOFTMMU)
6688 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6689 pcc->lrg_decr_bits = 32;
6690 pcc->n_host_threads = 8;
6691 #endif
6692 pcc->excp_model = POWERPC_EXCP_POWER8;
6693 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6694 pcc->bfd_mach = bfd_mach_ppc64;
6695 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6696 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6697 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6698 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6699 pcc->l1_dcache_size = 0x8000;
6700 pcc->l1_icache_size = 0x8000;
6701 }
6702
6703 #ifdef CONFIG_SOFTMMU
6704 /*
6705 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6706 * Encoded as array of int_32s in the form:
6707 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6708 * x -> AP encoding
6709 * y -> radix mode supported page size (encoded as a shift)
6710 */
6711 static struct ppc_radix_page_info POWER9_radix_page_info = {
6712 .count = 4,
6713 .entries = {
6714 0x0000000c, /* 4K - enc: 0x0 */
6715 0xa0000010, /* 64K - enc: 0x5 */
6716 0x20000015, /* 2M - enc: 0x1 */
6717 0x4000001e /* 1G - enc: 0x2 */
6718 }
6719 };
6720 #endif /* CONFIG_SOFTMMU */
6721
6722 static void init_proc_POWER9(CPUPPCState *env)
6723 {
6724 /* Common Registers */
6725 init_proc_book3s_common(env);
6726 register_book3s_207_dbg_sprs(env);
6727
6728 /* Common TCG PMU */
6729 init_tcg_pmu_power8(env);
6730
6731 /* POWER8 Specific Registers */
6732 register_book3s_ids_sprs(env);
6733 register_amr_sprs(env);
6734 register_iamr_sprs(env);
6735 register_book3s_purr_sprs(env);
6736 register_power5p_common_sprs(env);
6737 register_power5p_lpar_sprs(env);
6738 register_power5p_ear_sprs(env);
6739 register_power5p_tb_sprs(env);
6740 register_power6_common_sprs(env);
6741 register_power6_dbg_sprs(env);
6742 register_power8_tce_address_control_sprs(env);
6743 register_power8_ids_sprs(env);
6744 register_power8_ebb_sprs(env);
6745 register_power8_fscr_sprs(env);
6746 register_power8_pmu_sup_sprs(env);
6747 register_power8_pmu_user_sprs(env);
6748 register_power8_tm_sprs(env);
6749 register_power8_pspb_sprs(env);
6750 register_power8_dpdes_sprs(env);
6751 register_vtb_sprs(env);
6752 register_power8_ic_sprs(env);
6753 register_power8_book4_sprs(env);
6754 register_power8_rpr_sprs(env);
6755 register_power9_mmu_sprs(env);
6756
6757 /* POWER9 Specific registers */
6758 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6759 spr_read_generic, spr_write_generic,
6760 KVM_REG_PPC_TIDR, 0);
6761
6762 /* FIXME: Filter fields properly based on privilege level */
6763 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6764 spr_read_generic, spr_write_generic,
6765 KVM_REG_PPC_PSSCR, 0);
6766
6767 /* env variables */
6768 env->dcache_line_size = 128;
6769 env->icache_line_size = 128;
6770
6771 /* Allocate hardware IRQ controller */
6772 init_excp_POWER9(env);
6773 ppcPOWER9_irq_init(env_archcpu(env));
6774 }
6775
6776 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
6777 {
6778 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
6779 return true;
6780 }
6781 return false;
6782 }
6783
6784 static bool cpu_has_work_POWER9(CPUState *cs)
6785 {
6786 PowerPCCPU *cpu = POWERPC_CPU(cs);
6787 CPUPPCState *env = &cpu->env;
6788
6789 if (cs->halted) {
6790 uint64_t psscr = env->spr[SPR_PSSCR];
6791
6792 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6793 return false;
6794 }
6795
6796 /* If EC is clear, just return true on any pending interrupt */
6797 if (!(psscr & PSSCR_EC)) {
6798 return true;
6799 }
6800 /* External Exception */
6801 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6802 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6803 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6804 if (heic == 0 || !msr_hv || msr_pr) {
6805 return true;
6806 }
6807 }
6808 /* Decrementer Exception */
6809 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6810 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6811 return true;
6812 }
6813 /* Machine Check or Hypervisor Maintenance Exception */
6814 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6815 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6816 return true;
6817 }
6818 /* Privileged Doorbell Exception */
6819 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6820 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6821 return true;
6822 }
6823 /* Hypervisor Doorbell Exception */
6824 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6825 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6826 return true;
6827 }
6828 /* Hypervisor virtualization exception */
6829 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6830 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6831 return true;
6832 }
6833 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6834 return true;
6835 }
6836 return false;
6837 } else {
6838 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6839 }
6840 }
6841
6842 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6843 {
6844 DeviceClass *dc = DEVICE_CLASS(oc);
6845 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6846 CPUClass *cc = CPU_CLASS(oc);
6847
6848 dc->fw_name = "PowerPC,POWER9";
6849 dc->desc = "POWER9";
6850 pcc->pvr_match = ppc_pvr_match_power9;
6851 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6852 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6853 PCR_COMPAT_2_05;
6854 pcc->init_proc = init_proc_POWER9;
6855 pcc->check_pow = check_pow_nocheck;
6856 cc->has_work = cpu_has_work_POWER9;
6857 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6858 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6859 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6860 PPC_FLOAT_FRSQRTES |
6861 PPC_FLOAT_STFIWX |
6862 PPC_FLOAT_EXT |
6863 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6864 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6865 PPC_MEM_TLBSYNC |
6866 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6867 PPC_SEGMENT_64B | PPC_SLBI |
6868 PPC_POPCNTB | PPC_POPCNTWD |
6869 PPC_CILDST;
6870 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6871 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6872 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6873 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6874 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6875 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6876 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
6877 pcc->msr_mask = (1ull << MSR_SF) |
6878 (1ull << MSR_HV) |
6879 (1ull << MSR_TM) |
6880 (1ull << MSR_VR) |
6881 (1ull << MSR_VSX) |
6882 (1ull << MSR_EE) |
6883 (1ull << MSR_PR) |
6884 (1ull << MSR_FP) |
6885 (1ull << MSR_ME) |
6886 (1ull << MSR_FE0) |
6887 (1ull << MSR_SE) |
6888 (1ull << MSR_DE) |
6889 (1ull << MSR_FE1) |
6890 (1ull << MSR_IR) |
6891 (1ull << MSR_DR) |
6892 (1ull << MSR_PMM) |
6893 (1ull << MSR_RI) |
6894 (1ull << MSR_LE);
6895 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6896 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6897 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6898 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6899 LPCR_DEE | LPCR_OEE))
6900 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6901 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6902 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6903 pcc->mmu_model = POWERPC_MMU_3_00;
6904 #if defined(CONFIG_SOFTMMU)
6905 /* segment page size remain the same */
6906 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6907 pcc->radix_page_info = &POWER9_radix_page_info;
6908 pcc->lrg_decr_bits = 56;
6909 pcc->n_host_threads = 4;
6910 #endif
6911 pcc->excp_model = POWERPC_EXCP_POWER9;
6912 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6913 pcc->bfd_mach = bfd_mach_ppc64;
6914 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6915 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6916 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6917 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6918 pcc->l1_dcache_size = 0x8000;
6919 pcc->l1_icache_size = 0x8000;
6920 }
6921
6922 #ifdef CONFIG_SOFTMMU
6923 /*
6924 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6925 * Encoded as array of int_32s in the form:
6926 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6927 * x -> AP encoding
6928 * y -> radix mode supported page size (encoded as a shift)
6929 */
6930 static struct ppc_radix_page_info POWER10_radix_page_info = {
6931 .count = 4,
6932 .entries = {
6933 0x0000000c, /* 4K - enc: 0x0 */
6934 0xa0000010, /* 64K - enc: 0x5 */
6935 0x20000015, /* 2M - enc: 0x1 */
6936 0x4000001e /* 1G - enc: 0x2 */
6937 }
6938 };
6939 #endif /* CONFIG_SOFTMMU */
6940
6941 static void init_proc_POWER10(CPUPPCState *env)
6942 {
6943 /* Common Registers */
6944 init_proc_book3s_common(env);
6945 register_book3s_207_dbg_sprs(env);
6946
6947 /* Common TCG PMU */
6948 init_tcg_pmu_power8(env);
6949
6950 /* POWER8 Specific Registers */
6951 register_book3s_ids_sprs(env);
6952 register_amr_sprs(env);
6953 register_iamr_sprs(env);
6954 register_book3s_purr_sprs(env);
6955 register_power5p_common_sprs(env);
6956 register_power5p_lpar_sprs(env);
6957 register_power5p_ear_sprs(env);
6958 register_power6_common_sprs(env);
6959 register_power6_dbg_sprs(env);
6960 register_power8_tce_address_control_sprs(env);
6961 register_power8_ids_sprs(env);
6962 register_power8_ebb_sprs(env);
6963 register_power8_fscr_sprs(env);
6964 register_power8_pmu_sup_sprs(env);
6965 register_power8_pmu_user_sprs(env);
6966 register_power8_tm_sprs(env);
6967 register_power8_pspb_sprs(env);
6968 register_vtb_sprs(env);
6969 register_power8_ic_sprs(env);
6970 register_power8_book4_sprs(env);
6971 register_power8_rpr_sprs(env);
6972 register_power9_mmu_sprs(env);
6973
6974 /* FIXME: Filter fields properly based on privilege level */
6975 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6976 spr_read_generic, spr_write_generic,
6977 KVM_REG_PPC_PSSCR, 0);
6978
6979 /* env variables */
6980 env->dcache_line_size = 128;
6981 env->icache_line_size = 128;
6982
6983 /* Allocate hardware IRQ controller */
6984 init_excp_POWER10(env);
6985 ppcPOWER9_irq_init(env_archcpu(env));
6986 }
6987
6988 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
6989 {
6990 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
6991 return true;
6992 }
6993 return false;
6994 }
6995
6996 static bool cpu_has_work_POWER10(CPUState *cs)
6997 {
6998 PowerPCCPU *cpu = POWERPC_CPU(cs);
6999 CPUPPCState *env = &cpu->env;
7000
7001 if (cs->halted) {
7002 uint64_t psscr = env->spr[SPR_PSSCR];
7003
7004 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7005 return false;
7006 }
7007
7008 /* If EC is clear, just return true on any pending interrupt */
7009 if (!(psscr & PSSCR_EC)) {
7010 return true;
7011 }
7012 /* External Exception */
7013 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7014 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7015 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7016 if (heic == 0 || !msr_hv || msr_pr) {
7017 return true;
7018 }
7019 }
7020 /* Decrementer Exception */
7021 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7022 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7023 return true;
7024 }
7025 /* Machine Check or Hypervisor Maintenance Exception */
7026 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7027 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7028 return true;
7029 }
7030 /* Privileged Doorbell Exception */
7031 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7032 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7033 return true;
7034 }
7035 /* Hypervisor Doorbell Exception */
7036 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7037 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7038 return true;
7039 }
7040 /* Hypervisor virtualization exception */
7041 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7042 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7043 return true;
7044 }
7045 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7046 return true;
7047 }
7048 return false;
7049 } else {
7050 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7051 }
7052 }
7053
7054 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
7055 {
7056 DeviceClass *dc = DEVICE_CLASS(oc);
7057 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7058 CPUClass *cc = CPU_CLASS(oc);
7059
7060 dc->fw_name = "PowerPC,POWER10";
7061 dc->desc = "POWER10";
7062 pcc->pvr_match = ppc_pvr_match_power10;
7063 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
7064 PCR_COMPAT_3_00;
7065 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
7066 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7067 pcc->init_proc = init_proc_POWER10;
7068 pcc->check_pow = check_pow_nocheck;
7069 cc->has_work = cpu_has_work_POWER10;
7070 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7071 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7072 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7073 PPC_FLOAT_FRSQRTES |
7074 PPC_FLOAT_STFIWX |
7075 PPC_FLOAT_EXT |
7076 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7077 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7078 PPC_MEM_TLBSYNC |
7079 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7080 PPC_SEGMENT_64B | PPC_SLBI |
7081 PPC_POPCNTB | PPC_POPCNTWD |
7082 PPC_CILDST;
7083 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7084 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7085 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7086 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7087 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7088 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7089 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
7090 pcc->msr_mask = (1ull << MSR_SF) |
7091 (1ull << MSR_HV) |
7092 (1ull << MSR_TM) |
7093 (1ull << MSR_VR) |
7094 (1ull << MSR_VSX) |
7095 (1ull << MSR_EE) |
7096 (1ull << MSR_PR) |
7097 (1ull << MSR_FP) |
7098 (1ull << MSR_ME) |
7099 (1ull << MSR_FE0) |
7100 (1ull << MSR_SE) |
7101 (1ull << MSR_DE) |
7102 (1ull << MSR_FE1) |
7103 (1ull << MSR_IR) |
7104 (1ull << MSR_DR) |
7105 (1ull << MSR_PMM) |
7106 (1ull << MSR_RI) |
7107 (1ull << MSR_LE);
7108 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7109 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7110 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7111 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7112 LPCR_DEE | LPCR_OEE))
7113 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7114 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7115 /* DD2 adds an extra HAIL bit */
7116 pcc->lpcr_mask |= LPCR_HAIL;
7117
7118 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7119 pcc->mmu_model = POWERPC_MMU_3_00;
7120 #if defined(CONFIG_SOFTMMU)
7121 /* segment page size remain the same */
7122 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7123 pcc->radix_page_info = &POWER10_radix_page_info;
7124 pcc->lrg_decr_bits = 56;
7125 #endif
7126 pcc->excp_model = POWERPC_EXCP_POWER10;
7127 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7128 pcc->bfd_mach = bfd_mach_ppc64;
7129 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7130 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7131 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7132 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7133 pcc->l1_dcache_size = 0x8000;
7134 pcc->l1_icache_size = 0x8000;
7135 }
7136
7137 #if !defined(CONFIG_USER_ONLY)
7138 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
7139 {
7140 CPUPPCState *env = &cpu->env;
7141
7142 cpu->vhyp = vhyp;
7143
7144 /*
7145 * With a virtual hypervisor mode we never allow the CPU to go
7146 * hypervisor mode itself
7147 */
7148 env->msr_mask &= ~MSR_HVB;
7149 }
7150
7151 #endif /* !defined(CONFIG_USER_ONLY) */
7152
7153 #endif /* defined(TARGET_PPC64) */
7154
7155 /*****************************************************************************/
7156 /* Generic CPU instantiation routine */
7157 static void init_ppc_proc(PowerPCCPU *cpu)
7158 {
7159 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7160 CPUPPCState *env = &cpu->env;
7161 #if !defined(CONFIG_USER_ONLY)
7162 int i;
7163
7164 env->irq_inputs = NULL;
7165 /* Set all exception vectors to an invalid address */
7166 for (i = 0; i < POWERPC_EXCP_NB; i++) {
7167 env->excp_vectors[i] = (target_ulong)(-1ULL);
7168 }
7169 env->ivor_mask = 0x00000000;
7170 env->ivpr_mask = 0x00000000;
7171 /* Default MMU definitions */
7172 env->nb_BATs = 0;
7173 env->nb_tlb = 0;
7174 env->nb_ways = 0;
7175 env->tlb_type = TLB_NONE;
7176 #endif
7177 /* Register SPR common to all PowerPC implementations */
7178 register_generic_sprs(cpu);
7179
7180 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7181 (*pcc->init_proc)(env);
7182
7183 #if !defined(CONFIG_USER_ONLY)
7184 ppc_gdb_gen_spr_xml(cpu);
7185 #endif
7186
7187 /* MSR bits & flags consistency checks */
7188 if (env->msr_mask & (1 << 25)) {
7189 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7190 case POWERPC_FLAG_SPE:
7191 case POWERPC_FLAG_VRE:
7192 break;
7193 default:
7194 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7195 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7196 exit(1);
7197 }
7198 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7199 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7200 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7201 exit(1);
7202 }
7203 if (env->msr_mask & (1 << 17)) {
7204 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7205 case POWERPC_FLAG_TGPR:
7206 case POWERPC_FLAG_CE:
7207 break;
7208 default:
7209 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7210 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7211 exit(1);
7212 }
7213 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7214 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7215 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7216 exit(1);
7217 }
7218 if (env->msr_mask & (1 << 10)) {
7219 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7220 POWERPC_FLAG_UBLE)) {
7221 case POWERPC_FLAG_SE:
7222 case POWERPC_FLAG_DWE:
7223 case POWERPC_FLAG_UBLE:
7224 break;
7225 default:
7226 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7227 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7228 "POWERPC_FLAG_UBLE\n");
7229 exit(1);
7230 }
7231 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7232 POWERPC_FLAG_UBLE)) {
7233 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7234 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7235 "POWERPC_FLAG_UBLE\n");
7236 exit(1);
7237 }
7238 if (env->msr_mask & (1 << 9)) {
7239 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7240 case POWERPC_FLAG_BE:
7241 case POWERPC_FLAG_DE:
7242 break;
7243 default:
7244 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7245 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7246 exit(1);
7247 }
7248 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7249 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7250 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7251 exit(1);
7252 }
7253 if (env->msr_mask & (1 << 2)) {
7254 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7255 case POWERPC_FLAG_PX:
7256 case POWERPC_FLAG_PMM:
7257 break;
7258 default:
7259 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7260 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7261 exit(1);
7262 }
7263 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7264 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7265 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7266 exit(1);
7267 }
7268 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
7269 fprintf(stderr, "PowerPC flags inconsistency\n"
7270 "Should define the time-base and decrementer clock source\n");
7271 exit(1);
7272 }
7273 /* Allocate TLBs buffer when needed */
7274 #if !defined(CONFIG_USER_ONLY)
7275 if (env->nb_tlb != 0) {
7276 int nb_tlb = env->nb_tlb;
7277 if (env->id_tlbs != 0) {
7278 nb_tlb *= 2;
7279 }
7280 switch (env->tlb_type) {
7281 case TLB_6XX:
7282 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
7283 break;
7284 case TLB_EMB:
7285 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
7286 break;
7287 case TLB_MAS:
7288 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
7289 break;
7290 }
7291 /* Pre-compute some useful values */
7292 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7293 }
7294 if (env->irq_inputs == NULL) {
7295 warn_report("no internal IRQ controller registered."
7296 " Attempt QEMU to crash very soon !");
7297 }
7298 #endif
7299 if (env->check_pow == NULL) {
7300 warn_report("no power management check handler registered."
7301 " Attempt QEMU to crash very soon !");
7302 }
7303 }
7304
7305
7306 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
7307 {
7308 CPUState *cs = CPU(dev);
7309 PowerPCCPU *cpu = POWERPC_CPU(dev);
7310 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7311 Error *local_err = NULL;
7312
7313 cpu_exec_realizefn(cs, &local_err);
7314 if (local_err != NULL) {
7315 error_propagate(errp, local_err);
7316 return;
7317 }
7318 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
7319 cpu->vcpu_id = cs->cpu_index;
7320 }
7321
7322 if (tcg_enabled()) {
7323 if (ppc_fixup_cpu(cpu) != 0) {
7324 error_setg(errp, "Unable to emulate selected CPU with TCG");
7325 goto unrealize;
7326 }
7327 }
7328
7329 create_ppc_opcodes(cpu, &local_err);
7330 if (local_err != NULL) {
7331 error_propagate(errp, local_err);
7332 goto unrealize;
7333 }
7334 init_ppc_proc(cpu);
7335
7336 ppc_gdb_init(cs, pcc);
7337 qemu_init_vcpu(cs);
7338
7339 pcc->parent_realize(dev, errp);
7340
7341 return;
7342
7343 unrealize:
7344 cpu_exec_unrealizefn(cs);
7345 }
7346
7347 static void ppc_cpu_unrealize(DeviceState *dev)
7348 {
7349 PowerPCCPU *cpu = POWERPC_CPU(dev);
7350 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7351
7352 pcc->parent_unrealize(dev);
7353
7354 cpu_remove_sync(CPU(cpu));
7355
7356 destroy_ppc_opcodes(cpu);
7357 }
7358
7359 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7360 {
7361 ObjectClass *oc = (ObjectClass *)a;
7362 uint32_t pvr = *(uint32_t *)b;
7363 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7364
7365 /* -cpu host does a PVR lookup during construction */
7366 if (unlikely(strcmp(object_class_get_name(oc),
7367 TYPE_HOST_POWERPC_CPU) == 0)) {
7368 return -1;
7369 }
7370
7371 return pcc->pvr == pvr ? 0 : -1;
7372 }
7373
7374 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7375 {
7376 GSList *list, *item;
7377 PowerPCCPUClass *pcc = NULL;
7378
7379 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7380 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7381 if (item != NULL) {
7382 pcc = POWERPC_CPU_CLASS(item->data);
7383 }
7384 g_slist_free(list);
7385
7386 return pcc;
7387 }
7388
7389 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7390 {
7391 ObjectClass *oc = (ObjectClass *)a;
7392 uint32_t pvr = *(uint32_t *)b;
7393 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7394
7395 /* -cpu host does a PVR lookup during construction */
7396 if (unlikely(strcmp(object_class_get_name(oc),
7397 TYPE_HOST_POWERPC_CPU) == 0)) {
7398 return -1;
7399 }
7400
7401 if (pcc->pvr_match(pcc, pvr)) {
7402 return 0;
7403 }
7404
7405 return -1;
7406 }
7407
7408 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
7409 {
7410 GSList *list, *item;
7411 PowerPCCPUClass *pcc = NULL;
7412
7413 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7414 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7415 if (item != NULL) {
7416 pcc = POWERPC_CPU_CLASS(item->data);
7417 }
7418 g_slist_free(list);
7419
7420 return pcc;
7421 }
7422
7423 static const char *ppc_cpu_lookup_alias(const char *alias)
7424 {
7425 int ai;
7426
7427 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7428 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7429 return ppc_cpu_aliases[ai].model;
7430 }
7431 }
7432
7433 return NULL;
7434 }
7435
7436 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7437 {
7438 char *cpu_model, *typename;
7439 ObjectClass *oc;
7440 const char *p;
7441 unsigned long pvr;
7442
7443 /*
7444 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7445 * 0x prefix if present)
7446 */
7447 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7448 int len = p - name;
7449 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7450 if ((len == 8) && (*p == '\0')) {
7451 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7452 }
7453 }
7454
7455 cpu_model = g_ascii_strdown(name, -1);
7456 p = ppc_cpu_lookup_alias(cpu_model);
7457 if (p) {
7458 g_free(cpu_model);
7459 cpu_model = g_strdup(p);
7460 }
7461
7462 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7463 oc = object_class_by_name(typename);
7464 g_free(typename);
7465 g_free(cpu_model);
7466
7467 return oc;
7468 }
7469
7470 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7471 {
7472 ObjectClass *oc = OBJECT_CLASS(pcc);
7473
7474 while (oc && !object_class_is_abstract(oc)) {
7475 oc = object_class_get_parent(oc);
7476 }
7477 assert(oc);
7478
7479 return POWERPC_CPU_CLASS(oc);
7480 }
7481
7482 /* Sort by PVR, ordering special case "host" last. */
7483 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7484 {
7485 ObjectClass *oc_a = (ObjectClass *)a;
7486 ObjectClass *oc_b = (ObjectClass *)b;
7487 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7488 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7489 const char *name_a = object_class_get_name(oc_a);
7490 const char *name_b = object_class_get_name(oc_b);
7491
7492 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7493 return 1;
7494 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7495 return -1;
7496 } else {
7497 /* Avoid an integer overflow during subtraction */
7498 if (pcc_a->pvr < pcc_b->pvr) {
7499 return -1;
7500 } else if (pcc_a->pvr > pcc_b->pvr) {
7501 return 1;
7502 } else {
7503 return 0;
7504 }
7505 }
7506 }
7507
7508 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7509 {
7510 ObjectClass *oc = data;
7511 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7512 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7513 const char *typename = object_class_get_name(oc);
7514 char *name;
7515 int i;
7516
7517 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7518 return;
7519 }
7520
7521 name = g_strndup(typename,
7522 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7523 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7524 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7525 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7526 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7527
7528 if (alias_oc != oc) {
7529 continue;
7530 }
7531 /*
7532 * If running with KVM, we might update the family alias later, so
7533 * avoid printing the wrong alias here and use "preferred" instead
7534 */
7535 if (strcmp(alias->alias, family->desc) == 0) {
7536 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7537 alias->alias, family->desc);
7538 } else {
7539 qemu_printf("PowerPC %-16s (alias for %s)\n",
7540 alias->alias, name);
7541 }
7542 }
7543 g_free(name);
7544 }
7545
7546 void ppc_cpu_list(void)
7547 {
7548 GSList *list;
7549
7550 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7551 list = g_slist_sort(list, ppc_cpu_list_compare);
7552 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7553 g_slist_free(list);
7554
7555 #ifdef CONFIG_KVM
7556 qemu_printf("\n");
7557 qemu_printf("PowerPC %s\n", "host");
7558 #endif
7559 }
7560
7561 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7562 {
7563 ObjectClass *oc = data;
7564 CpuDefinitionInfoList **first = user_data;
7565 const char *typename;
7566 CpuDefinitionInfo *info;
7567
7568 typename = object_class_get_name(oc);
7569 info = g_malloc0(sizeof(*info));
7570 info->name = g_strndup(typename,
7571 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7572
7573 QAPI_LIST_PREPEND(*first, info);
7574 }
7575
7576 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7577 {
7578 CpuDefinitionInfoList *cpu_list = NULL;
7579 GSList *list;
7580 int i;
7581
7582 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7583 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7584 g_slist_free(list);
7585
7586 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7587 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7588 ObjectClass *oc;
7589 CpuDefinitionInfo *info;
7590
7591 oc = ppc_cpu_class_by_name(alias->model);
7592 if (oc == NULL) {
7593 continue;
7594 }
7595
7596 info = g_malloc0(sizeof(*info));
7597 info->name = g_strdup(alias->alias);
7598 info->q_typename = g_strdup(object_class_get_name(oc));
7599
7600 QAPI_LIST_PREPEND(cpu_list, info);
7601 }
7602
7603 return cpu_list;
7604 }
7605
7606 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7607 {
7608 PowerPCCPU *cpu = POWERPC_CPU(cs);
7609
7610 cpu->env.nip = value;
7611 }
7612
7613 static bool ppc_cpu_has_work(CPUState *cs)
7614 {
7615 PowerPCCPU *cpu = POWERPC_CPU(cs);
7616 CPUPPCState *env = &cpu->env;
7617
7618 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7619 }
7620
7621 static void ppc_cpu_reset(DeviceState *dev)
7622 {
7623 CPUState *s = CPU(dev);
7624 PowerPCCPU *cpu = POWERPC_CPU(s);
7625 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7626 CPUPPCState *env = &cpu->env;
7627 target_ulong msr;
7628 int i;
7629
7630 pcc->parent_reset(dev);
7631
7632 msr = (target_ulong)0;
7633 msr |= (target_ulong)MSR_HVB;
7634 msr |= (target_ulong)1 << MSR_EP;
7635 #if defined(DO_SINGLE_STEP) && 0
7636 /* Single step trace mode */
7637 msr |= (target_ulong)1 << MSR_SE;
7638 msr |= (target_ulong)1 << MSR_BE;
7639 #endif
7640 #if defined(CONFIG_USER_ONLY)
7641 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7642 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7643 msr |= (target_ulong)1 << MSR_FE1;
7644 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7645 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7646 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7647 msr |= (target_ulong)1 << MSR_PR;
7648 #if defined(TARGET_PPC64)
7649 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7650 #endif
7651 #if !defined(TARGET_WORDS_BIGENDIAN)
7652 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7653 if (!((env->msr_mask >> MSR_LE) & 1)) {
7654 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7655 exit(1);
7656 }
7657 #endif
7658 #endif
7659
7660 #if defined(TARGET_PPC64)
7661 if (mmu_is_64bit(env->mmu_model)) {
7662 msr |= (1ULL << MSR_SF);
7663 }
7664 #endif
7665
7666 hreg_store_msr(env, msr, 1);
7667
7668 #if !defined(CONFIG_USER_ONLY)
7669 env->nip = env->hreset_vector | env->excp_prefix;
7670 #if defined(CONFIG_TCG)
7671 if (env->mmu_model != POWERPC_MMU_REAL) {
7672 ppc_tlb_invalidate_all(env);
7673 }
7674 #endif /* CONFIG_TCG */
7675 #endif
7676
7677 pmu_update_summaries(env);
7678 hreg_compute_hflags(env);
7679 env->reserve_addr = (target_ulong)-1ULL;
7680 /* Be sure no exception or interrupt is pending */
7681 env->pending_interrupts = 0;
7682 s->exception_index = POWERPC_EXCP_NONE;
7683 env->error_code = 0;
7684 ppc_irq_reset(cpu);
7685
7686 /* tininess for underflow is detected before rounding */
7687 set_float_detect_tininess(float_tininess_before_rounding,
7688 &env->fp_status);
7689
7690 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7691 ppc_spr_t *spr = &env->spr_cb[i];
7692
7693 if (!spr->name) {
7694 continue;
7695 }
7696 env->spr[i] = spr->default_value;
7697 }
7698 }
7699
7700 #ifndef CONFIG_USER_ONLY
7701
7702 static bool ppc_cpu_is_big_endian(CPUState *cs)
7703 {
7704 PowerPCCPU *cpu = POWERPC_CPU(cs);
7705 CPUPPCState *env = &cpu->env;
7706
7707 cpu_synchronize_state(cs);
7708
7709 return !msr_le;
7710 }
7711
7712 #ifdef CONFIG_TCG
7713 static void ppc_cpu_exec_enter(CPUState *cs)
7714 {
7715 PowerPCCPU *cpu = POWERPC_CPU(cs);
7716
7717 if (cpu->vhyp) {
7718 PPCVirtualHypervisorClass *vhc =
7719 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7720 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7721 }
7722 }
7723
7724 static void ppc_cpu_exec_exit(CPUState *cs)
7725 {
7726 PowerPCCPU *cpu = POWERPC_CPU(cs);
7727
7728 if (cpu->vhyp) {
7729 PPCVirtualHypervisorClass *vhc =
7730 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7731 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7732 }
7733 }
7734 #endif /* CONFIG_TCG */
7735
7736 #endif /* !CONFIG_USER_ONLY */
7737
7738 static void ppc_cpu_instance_init(Object *obj)
7739 {
7740 PowerPCCPU *cpu = POWERPC_CPU(obj);
7741 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7742 CPUPPCState *env = &cpu->env;
7743
7744 cpu_set_cpustate_pointers(cpu);
7745 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7746
7747 env->msr_mask = pcc->msr_mask;
7748 env->mmu_model = pcc->mmu_model;
7749 env->excp_model = pcc->excp_model;
7750 env->bus_model = pcc->bus_model;
7751 env->insns_flags = pcc->insns_flags;
7752 env->insns_flags2 = pcc->insns_flags2;
7753 env->flags = pcc->flags;
7754 env->bfd_mach = pcc->bfd_mach;
7755 env->check_pow = pcc->check_pow;
7756
7757 /*
7758 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7759 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7760 * mode support will remain, thus enforcing that we cannot use
7761 * priv. instructions in guest in PAPR mode. For 970 we currently
7762 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7763 * 970. If we ever want to support 970 HV mode, we'll have to add
7764 * a processor attribute of some sort.
7765 */
7766 #if !defined(CONFIG_USER_ONLY)
7767 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7768 #endif
7769
7770 ppc_hash64_init(cpu);
7771 }
7772
7773 static void ppc_cpu_instance_finalize(Object *obj)
7774 {
7775 PowerPCCPU *cpu = POWERPC_CPU(obj);
7776
7777 ppc_hash64_finalize(cpu);
7778 }
7779
7780 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
7781 {
7782 return pcc->pvr == pvr;
7783 }
7784
7785 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7786 {
7787 PowerPCCPU *cpu = POWERPC_CPU(cs);
7788 CPUPPCState *env = &cpu->env;
7789
7790 if ((env->hflags >> MSR_LE) & 1) {
7791 info->endian = BFD_ENDIAN_LITTLE;
7792 }
7793 info->mach = env->bfd_mach;
7794 if (!env->bfd_mach) {
7795 #ifdef TARGET_PPC64
7796 info->mach = bfd_mach_ppc64;
7797 #else
7798 info->mach = bfd_mach_ppc;
7799 #endif
7800 }
7801 info->disassembler_options = (char *)"any";
7802 info->print_insn = print_insn_ppc;
7803
7804 info->cap_arch = CS_ARCH_PPC;
7805 #ifdef TARGET_PPC64
7806 info->cap_mode = CS_MODE_64;
7807 #endif
7808 }
7809
7810 static Property ppc_cpu_properties[] = {
7811 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7812 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7813 false),
7814 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7815 false),
7816 DEFINE_PROP_END_OF_LIST(),
7817 };
7818
7819 #ifndef CONFIG_USER_ONLY
7820 #include "hw/core/sysemu-cpu-ops.h"
7821
7822 static const struct SysemuCPUOps ppc_sysemu_ops = {
7823 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7824 .write_elf32_note = ppc32_cpu_write_elf32_note,
7825 .write_elf64_note = ppc64_cpu_write_elf64_note,
7826 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7827 .legacy_vmsd = &vmstate_ppc_cpu,
7828 };
7829 #endif
7830
7831 #ifdef CONFIG_TCG
7832 #include "hw/core/tcg-cpu-ops.h"
7833
7834 static const struct TCGCPUOps ppc_tcg_ops = {
7835 .initialize = ppc_translate_init,
7836
7837 #ifdef CONFIG_USER_ONLY
7838 .record_sigsegv = ppc_cpu_record_sigsegv,
7839 #else
7840 .tlb_fill = ppc_cpu_tlb_fill,
7841 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7842 .do_interrupt = ppc_cpu_do_interrupt,
7843 .cpu_exec_enter = ppc_cpu_exec_enter,
7844 .cpu_exec_exit = ppc_cpu_exec_exit,
7845 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7846 #endif /* !CONFIG_USER_ONLY */
7847 };
7848 #endif /* CONFIG_TCG */
7849
7850 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7851 {
7852 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7853 CPUClass *cc = CPU_CLASS(oc);
7854 DeviceClass *dc = DEVICE_CLASS(oc);
7855
7856 device_class_set_parent_realize(dc, ppc_cpu_realize,
7857 &pcc->parent_realize);
7858 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7859 &pcc->parent_unrealize);
7860 pcc->pvr_match = ppc_pvr_match_default;
7861 device_class_set_props(dc, ppc_cpu_properties);
7862
7863 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
7864
7865 cc->class_by_name = ppc_cpu_class_by_name;
7866 cc->has_work = ppc_cpu_has_work;
7867 cc->dump_state = ppc_cpu_dump_state;
7868 cc->set_pc = ppc_cpu_set_pc;
7869 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7870 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7871 #ifndef CONFIG_USER_ONLY
7872 cc->sysemu_ops = &ppc_sysemu_ops;
7873 #endif
7874
7875 cc->gdb_num_core_regs = 71;
7876 #ifndef CONFIG_USER_ONLY
7877 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7878 #endif
7879 #ifdef USE_APPLE_GDB
7880 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7881 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7882 cc->gdb_num_core_regs = 71 + 32;
7883 #endif
7884
7885 cc->gdb_arch_name = ppc_gdb_arch_name;
7886 #if defined(TARGET_PPC64)
7887 cc->gdb_core_xml_file = "power64-core.xml";
7888 #else
7889 cc->gdb_core_xml_file = "power-core.xml";
7890 #endif
7891 cc->disas_set_info = ppc_disas_set_info;
7892
7893 dc->fw_name = "PowerPC,UNKNOWN";
7894
7895 #ifdef CONFIG_TCG
7896 cc->tcg_ops = &ppc_tcg_ops;
7897 #endif /* CONFIG_TCG */
7898 }
7899
7900 static const TypeInfo ppc_cpu_type_info = {
7901 .name = TYPE_POWERPC_CPU,
7902 .parent = TYPE_CPU,
7903 .instance_size = sizeof(PowerPCCPU),
7904 .instance_align = __alignof__(PowerPCCPU),
7905 .instance_init = ppc_cpu_instance_init,
7906 .instance_finalize = ppc_cpu_instance_finalize,
7907 .abstract = true,
7908 .class_size = sizeof(PowerPCCPUClass),
7909 .class_init = ppc_cpu_class_init,
7910 };
7911
7912 #ifndef CONFIG_USER_ONLY
7913 static const TypeInfo ppc_vhyp_type_info = {
7914 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7915 .parent = TYPE_INTERFACE,
7916 .class_size = sizeof(PPCVirtualHypervisorClass),
7917 };
7918 #endif
7919
7920 static void ppc_cpu_register_types(void)
7921 {
7922 type_register_static(&ppc_cpu_type_info);
7923 #ifndef CONFIG_USER_ONLY
7924 type_register_static(&ppc_vhyp_type_info);
7925 #endif
7926 }
7927
7928 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7929 {
7930 #define RGPL 4
7931 #define RFPL 4
7932
7933 PowerPCCPU *cpu = POWERPC_CPU(cs);
7934 CPUPPCState *env = &cpu->env;
7935 int i;
7936
7937 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7938 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7939 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7940 cs->cpu_index);
7941 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7942 "%08x iidx %d didx %d\n",
7943 env->msr, env->spr[SPR_HID0], env->hflags,
7944 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
7945 #if !defined(NO_TIMER_DUMP)
7946 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7947 #if !defined(CONFIG_USER_ONLY)
7948 " DECR " TARGET_FMT_lu
7949 #endif
7950 "\n",
7951 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7952 #if !defined(CONFIG_USER_ONLY)
7953 , cpu_ppc_load_decr(env)
7954 #endif
7955 );
7956 #endif
7957 for (i = 0; i < 32; i++) {
7958 if ((i & (RGPL - 1)) == 0) {
7959 qemu_fprintf(f, "GPR%02d", i);
7960 }
7961 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7962 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7963 qemu_fprintf(f, "\n");
7964 }
7965 }
7966 qemu_fprintf(f, "CR ");
7967 for (i = 0; i < 8; i++)
7968 qemu_fprintf(f, "%01x", env->crf[i]);
7969 qemu_fprintf(f, " [");
7970 for (i = 0; i < 8; i++) {
7971 char a = '-';
7972 if (env->crf[i] & 0x08) {
7973 a = 'L';
7974 } else if (env->crf[i] & 0x04) {
7975 a = 'G';
7976 } else if (env->crf[i] & 0x02) {
7977 a = 'E';
7978 }
7979 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7980 }
7981 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7982 env->reserve_addr);
7983
7984 if (flags & CPU_DUMP_FPU) {
7985 for (i = 0; i < 32; i++) {
7986 if ((i & (RFPL - 1)) == 0) {
7987 qemu_fprintf(f, "FPR%02d", i);
7988 }
7989 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7990 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7991 qemu_fprintf(f, "\n");
7992 }
7993 }
7994 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7995 }
7996
7997 #if !defined(CONFIG_USER_ONLY)
7998 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7999 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
8000 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
8001 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
8002
8003 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
8004 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
8005 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
8006 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
8007
8008 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
8009 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
8010 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
8011 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
8012
8013 switch (env->excp_model) {
8014 #if defined(TARGET_PPC64)
8015 case POWERPC_EXCP_POWER7:
8016 case POWERPC_EXCP_POWER8:
8017 case POWERPC_EXCP_POWER9:
8018 case POWERPC_EXCP_POWER10:
8019 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
8020 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
8021 break;
8022 #endif
8023 case POWERPC_EXCP_BOOKE:
8024 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
8025 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
8026 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
8027 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
8028
8029 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8030 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8031 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
8032 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
8033
8034 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
8035 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
8036 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
8037 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
8038
8039 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
8040 " EPR " TARGET_FMT_lx "\n",
8041 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
8042 env->spr[SPR_BOOKE_EPR]);
8043
8044 /* FSL-specific */
8045 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
8046 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
8047 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
8048 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
8049
8050 /*
8051 * IVORs are left out as they are large and do not change often --
8052 * they can be read with "p $ivor0", "p $ivor1", etc.
8053 */
8054 break;
8055 case POWERPC_EXCP_40x:
8056 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8057 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8058 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
8059 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
8060
8061 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
8062 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8063 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
8064 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
8065 break;
8066 default:
8067 break;
8068 }
8069
8070 #if defined(TARGET_PPC64)
8071 if (env->flags & POWERPC_FLAG_CFAR) {
8072 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
8073 }
8074 #endif
8075
8076 if (env->spr_cb[SPR_LPCR].name) {
8077 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
8078 }
8079
8080 switch (env->mmu_model) {
8081 case POWERPC_MMU_32B:
8082 case POWERPC_MMU_SOFT_6xx:
8083 #if defined(TARGET_PPC64)
8084 case POWERPC_MMU_64B:
8085 case POWERPC_MMU_2_03:
8086 case POWERPC_MMU_2_06:
8087 case POWERPC_MMU_2_07:
8088 case POWERPC_MMU_3_00:
8089 #endif
8090 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
8091 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
8092 }
8093 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
8094 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
8095 }
8096 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
8097 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
8098 break;
8099 case POWERPC_MMU_BOOKE206:
8100 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
8101 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
8102 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
8103 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
8104
8105 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
8106 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8107 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
8108 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
8109
8110 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
8111 " TLB1CFG " TARGET_FMT_lx "\n",
8112 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
8113 env->spr[SPR_BOOKE_TLB1CFG]);
8114 break;
8115 default:
8116 break;
8117 }
8118 #endif
8119
8120 #undef RGPL
8121 #undef RFPL
8122 }
8123 type_init(ppc_cpu_register_types)
QEmu