4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "internals.h"
23 #include "exec/gdbstub.h"
25 typedef struct RegisterSysregXmlParam
{
29 } RegisterSysregXmlParam
;
31 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
32 whatever the target description contains. Due to a historical mishap
33 the FPA registers appear in between core integer regs and the CPSR.
34 We hack round this by giving the FPA regs zero size when talking to a
37 int arm_cpu_gdb_read_register(CPUState
*cs
, GByteArray
*mem_buf
, int n
)
39 ARMCPU
*cpu
= ARM_CPU(cs
);
40 CPUARMState
*env
= &cpu
->env
;
43 /* Core integer register. */
44 return gdb_get_reg32(mem_buf
, env
->regs
[n
]);
51 return gdb_get_zeroes(mem_buf
, 12);
55 /* FPA status register. */
59 return gdb_get_reg32(mem_buf
, 0);
61 /* CPSR, or XPSR for M-profile */
62 if (arm_feature(env
, ARM_FEATURE_M
)) {
63 return gdb_get_reg32(mem_buf
, xpsr_read(env
));
65 return gdb_get_reg32(mem_buf
, cpsr_read(env
));
68 /* Unknown register. */
72 int arm_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
74 ARMCPU
*cpu
= ARM_CPU(cs
);
75 CPUARMState
*env
= &cpu
->env
;
81 * Mask out low bits of PC to workaround gdb bugs.
82 * This avoids an assert in thumb_tr_translate_insn, because it is
83 * architecturally impossible to misalign the pc.
84 * This will probably cause problems if we ever implement the
85 * Jazelle DBX extensions.
92 /* Core integer register. */
93 if (n
== 13 && arm_feature(env
, ARM_FEATURE_M
)) {
94 /* M profile SP low bits are always 0 */
100 if (n
< 24) { /* 16-23 */
101 /* FPA registers (ignored). */
109 /* FPA status register (ignored). */
115 /* CPSR, or XPSR for M-profile */
116 if (arm_feature(env
, ARM_FEATURE_M
)) {
118 * Don't allow writing to XPSR.Exception as it can cause
119 * a transition into or out of handler mode (it's not
120 * writeable via the MSR insn so this is a reasonable
121 * restriction). Other fields are safe to update.
123 xpsr_write(env
, tmp
, ~XPSR_EXCP
);
125 cpsr_write(env
, tmp
, 0xffffffff, CPSRWriteByGDBStub
);
129 /* Unknown register. */
133 static int vfp_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
135 ARMCPU
*cpu
= env_archcpu(env
);
136 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
138 /* VFP data registers are always little-endian. */
140 return gdb_get_reg64(buf
, *aa32_vfp_dreg(env
, reg
));
142 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
143 /* Aliases for Q regs. */
146 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
147 return gdb_get_reg128(buf
, q
[0], q
[1]);
150 switch (reg
- nregs
) {
152 return gdb_get_reg32(buf
, vfp_get_fpscr(env
));
157 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
159 ARMCPU
*cpu
= env_archcpu(env
);
160 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
163 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
166 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
169 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
170 q
[0] = ldq_le_p(buf
);
171 q
[1] = ldq_le_p(buf
+ 8);
175 switch (reg
- nregs
) {
177 vfp_set_fpscr(env
, ldl_p(buf
));
183 static int vfp_gdb_get_sysreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
187 return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]);
189 return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]);
194 static int vfp_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
198 env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
);
201 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30);
207 static int mve_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
211 return gdb_get_reg32(buf
, env
->v7m
.vpr
);
217 static int mve_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
221 env
->v7m
.vpr
= ldl_p(buf
);
229 * arm_get/set_gdb_*: get/set a gdb register
230 * @env: the CPU state
231 * @buf: a buffer to copy to/from
232 * @reg: register number (offset from start of group)
234 * We return the number of bytes copied
237 static int arm_gdb_get_sysreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
239 ARMCPU
*cpu
= env_archcpu(env
);
240 const ARMCPRegInfo
*ri
;
243 key
= cpu
->dyn_sysreg_xml
.data
.cpregs
.keys
[reg
];
244 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
246 if (cpreg_field_is_64bit(ri
)) {
247 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
249 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
255 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
260 static void arm_gen_one_xml_sysreg_tag(GString
*s
, DynamicGDBXMLInfo
*dyn_xml
,
261 ARMCPRegInfo
*ri
, uint32_t ri_key
,
262 int bitsize
, int regnum
)
264 g_string_append_printf(s
, "<reg name=\"%s\"", ri
->name
);
265 g_string_append_printf(s
, " bitsize=\"%d\"", bitsize
);
266 g_string_append_printf(s
, " regnum=\"%d\"", regnum
);
267 g_string_append_printf(s
, " group=\"cp_regs\"/>");
268 dyn_xml
->data
.cpregs
.keys
[dyn_xml
->num
] = ri_key
;
272 static void arm_register_sysreg_for_xml(gpointer key
, gpointer value
,
275 uint32_t ri_key
= *(uint32_t *)key
;
276 ARMCPRegInfo
*ri
= value
;
277 RegisterSysregXmlParam
*param
= (RegisterSysregXmlParam
*)p
;
278 GString
*s
= param
->s
;
279 ARMCPU
*cpu
= ARM_CPU(param
->cs
);
280 CPUARMState
*env
= &cpu
->env
;
281 DynamicGDBXMLInfo
*dyn_xml
= &cpu
->dyn_sysreg_xml
;
283 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_NO_GDB
))) {
284 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
285 if (ri
->state
== ARM_CP_STATE_AA64
) {
286 arm_gen_one_xml_sysreg_tag(s
, dyn_xml
, ri
, ri_key
, 64,
290 if (ri
->state
== ARM_CP_STATE_AA32
) {
291 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
292 (ri
->secure
& ARM_CP_SECSTATE_S
)) {
295 if (ri
->type
& ARM_CP_64BIT
) {
296 arm_gen_one_xml_sysreg_tag(s
, dyn_xml
, ri
, ri_key
, 64,
299 arm_gen_one_xml_sysreg_tag(s
, dyn_xml
, ri
, ri_key
, 32,
307 int arm_gen_dynamic_sysreg_xml(CPUState
*cs
, int base_reg
)
309 ARMCPU
*cpu
= ARM_CPU(cs
);
310 GString
*s
= g_string_new(NULL
);
311 RegisterSysregXmlParam param
= {cs
, s
, base_reg
};
313 cpu
->dyn_sysreg_xml
.num
= 0;
314 cpu
->dyn_sysreg_xml
.data
.cpregs
.keys
= g_new(uint32_t, g_hash_table_size(cpu
->cp_regs
));
315 g_string_printf(s
, "<?xml version=\"1.0\"?>");
316 g_string_append_printf(s
, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
317 g_string_append_printf(s
, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
318 g_hash_table_foreach(cpu
->cp_regs
, arm_register_sysreg_for_xml
, ¶m
);
319 g_string_append_printf(s
, "</feature>");
320 cpu
->dyn_sysreg_xml
.desc
= g_string_free(s
, false);
321 return cpu
->dyn_sysreg_xml
.num
;
325 const char *gdb_type
;
327 const char sz
, suffix
;
330 static const struct TypeSize vec_lanes
[] = {
332 { "uint128", 128, 'q', 'u' },
333 { "int128", 128, 'q', 's' },
335 { "ieee_double", 64, 'd', 'f' },
336 { "uint64", 64, 'd', 'u' },
337 { "int64", 64, 'd', 's' },
339 { "ieee_single", 32, 's', 'f' },
340 { "uint32", 32, 's', 'u' },
341 { "int32", 32, 's', 's' },
343 { "ieee_half", 16, 'h', 'f' },
344 { "uint16", 16, 'h', 'u' },
345 { "int16", 16, 'h', 's' },
347 { "uint8", 8, 'b', 'u' },
348 { "int8", 8, 'b', 's' },
352 int arm_gen_dynamic_svereg_xml(CPUState
*cs
, int base_reg
)
354 ARMCPU
*cpu
= ARM_CPU(cs
);
355 GString
*s
= g_string_new(NULL
);
356 DynamicGDBXMLInfo
*info
= &cpu
->dyn_svereg_xml
;
357 g_autoptr(GString
) ts
= g_string_new("");
358 int i
, j
, bits
, reg_width
= (cpu
->sve_max_vq
* 128);
360 g_string_printf(s
, "<?xml version=\"1.0\"?>");
361 g_string_append_printf(s
, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
362 g_string_append_printf(s
, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
364 /* First define types and totals in a whole VL */
365 for (i
= 0; i
< ARRAY_SIZE(vec_lanes
); i
++) {
366 int count
= reg_width
/ vec_lanes
[i
].size
;
367 g_string_printf(ts
, "svev%c%c", vec_lanes
[i
].sz
, vec_lanes
[i
].suffix
);
368 g_string_append_printf(s
,
369 "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
370 ts
->str
, vec_lanes
[i
].gdb_type
, count
);
373 * Now define a union for each size group containing unsigned and
374 * signed and potentially float versions of each size from 128 to
377 for (bits
= 128, i
= 0; bits
>= 8; bits
/= 2, i
++) {
378 const char suf
[] = { 'q', 'd', 's', 'h', 'b' };
379 g_string_append_printf(s
, "<union id=\"svevn%c\">", suf
[i
]);
380 for (j
= 0; j
< ARRAY_SIZE(vec_lanes
); j
++) {
381 if (vec_lanes
[j
].size
== bits
) {
382 g_string_append_printf(s
, "<field name=\"%c\" type=\"svev%c%c\"/>",
384 vec_lanes
[j
].sz
, vec_lanes
[j
].suffix
);
387 g_string_append(s
, "</union>");
389 /* And now the final union of unions */
390 g_string_append(s
, "<union id=\"svev\">");
391 for (bits
= 128, i
= 0; bits
>= 8; bits
/= 2, i
++) {
392 const char suf
[] = { 'q', 'd', 's', 'h', 'b' };
393 g_string_append_printf(s
, "<field name=\"%c\" type=\"svevn%c\"/>",
396 g_string_append(s
, "</union>");
398 /* Finally the sve prefix type */
399 g_string_append_printf(s
,
400 "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
403 /* Then define each register in parts for each vq */
404 for (i
= 0; i
< 32; i
++) {
405 g_string_append_printf(s
,
406 "<reg name=\"z%d\" bitsize=\"%d\""
407 " regnum=\"%d\" type=\"svev\"/>",
408 i
, reg_width
, base_reg
++);
411 /* fpscr & status registers */
412 g_string_append_printf(s
, "<reg name=\"fpsr\" bitsize=\"32\""
413 " regnum=\"%d\" group=\"float\""
414 " type=\"int\"/>", base_reg
++);
415 g_string_append_printf(s
, "<reg name=\"fpcr\" bitsize=\"32\""
416 " regnum=\"%d\" group=\"float\""
417 " type=\"int\"/>", base_reg
++);
420 for (i
= 0; i
< 16; i
++) {
421 g_string_append_printf(s
,
422 "<reg name=\"p%d\" bitsize=\"%d\""
423 " regnum=\"%d\" type=\"svep\"/>",
424 i
, cpu
->sve_max_vq
* 16, base_reg
++);
427 g_string_append_printf(s
,
428 "<reg name=\"ffr\" bitsize=\"%d\""
429 " regnum=\"%d\" group=\"vector\""
431 cpu
->sve_max_vq
* 16, base_reg
++);
432 g_string_append_printf(s
,
433 "<reg name=\"vg\" bitsize=\"64\""
434 " regnum=\"%d\" type=\"int\"/>",
437 g_string_append_printf(s
, "</feature>");
438 cpu
->dyn_svereg_xml
.desc
= g_string_free(s
, false);
440 return cpu
->dyn_svereg_xml
.num
;
444 const char *arm_gdb_get_dynamic_xml(CPUState
*cs
, const char *xmlname
)
446 ARMCPU
*cpu
= ARM_CPU(cs
);
448 if (strcmp(xmlname
, "system-registers.xml") == 0) {
449 return cpu
->dyn_sysreg_xml
.desc
;
450 } else if (strcmp(xmlname
, "sve-registers.xml") == 0) {
451 return cpu
->dyn_svereg_xml
.desc
;
456 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
458 CPUState
*cs
= CPU(cpu
);
459 CPUARMState
*env
= &cpu
->env
;
461 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
463 * The lower part of each SVE register aliases to the FPU
464 * registers so we don't need to include both.
466 #ifdef TARGET_AARCH64
467 if (isar_feature_aa64_sve(&cpu
->isar
)) {
468 gdb_register_coprocessor(cs
, arm_gdb_get_svereg
, arm_gdb_set_svereg
,
469 arm_gen_dynamic_svereg_xml(cs
, cs
->gdb_num_regs
),
470 "sve-registers.xml", 0);
472 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
473 aarch64_fpu_gdb_set_reg
,
474 34, "aarch64-fpu.xml", 0);
478 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
479 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
480 49, "arm-neon.xml", 0);
481 } else if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
482 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
483 33, "arm-vfp3.xml", 0);
484 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
485 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
486 17, "arm-vfp.xml", 0);
488 if (!arm_feature(env
, ARM_FEATURE_M
)) {
490 * A and R profile have FP sysregs FPEXC and FPSID that we
493 gdb_register_coprocessor(cs
, vfp_gdb_get_sysreg
, vfp_gdb_set_sysreg
,
494 2, "arm-vfp-sysregs.xml", 0);
497 if (cpu_isar_feature(aa32_mve
, cpu
)) {
498 gdb_register_coprocessor(cs
, mve_gdb_get_reg
, mve_gdb_set_reg
,
499 1, "arm-m-profile-mve.xml", 0);
501 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
502 arm_gen_dynamic_sysreg_xml(cs
, cs
->gdb_num_regs
),
503 "system-registers.xml", 0);