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ppc/pnv: turn chip8->phbs[] into a PnvPHB* array
[qemu.git] / hw / ppc / pnv.c
blob0208517f1ab175fe798538654094b4e69fb85d13
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
39 #include "hw/nmi.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci-host/pnv_phb.h"
47
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
52
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
56
57 #include <libfdt.h>
58
59 #define FDT_MAX_SIZE (1 * MiB)
60
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
64
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
69
70 static const char *pnv_chip_core_typename(const PnvChip *o)
71 {
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78 }
79
80 /*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85 #define MAX_CPUS 2048
86
87 /*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93 {
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109 }
110
111 static int get_cpus_node(void *fdt)
112 {
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124 }
125
126 /*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134 {
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208 /*
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
212 * 2 == VSX available
213 */
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220 /*
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
223 * 1 == DFP available
224 */
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249 {
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282 }
283
284 /*
285 * Adds a PnvPHB to the chip. Returns the parent obj of the
286 * PHB which varies with each version (phb version 3 is parented
287 * by the chip, version 4 and 5 are parented by the PEC
288 * device).
289 *
290 * TODO: for version 3 we're still parenting the PHB with the
291 * chip. We should parent with a (so far not implemented)
292 * PHB3 PEC device.
293 */
294 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
295 {
296 if (phb->version == 3) {
297 Pnv8Chip *chip8 = PNV8_CHIP(chip);
298
299 phb->chip = chip;
300
301 chip8->phbs[chip8->num_phbs] = phb;
302 chip8->num_phbs++;
303
304 return OBJECT(chip);
305 } else {
306 /* phb4 support will be added later */
307 return NULL;
308 }
309 }
310
311 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
312 {
313 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
314 int i;
315
316 pnv_dt_xscom(chip, fdt, 0,
317 cpu_to_be64(PNV_XSCOM_BASE(chip)),
318 cpu_to_be64(PNV_XSCOM_SIZE),
319 compat, sizeof(compat));
320
321 for (i = 0; i < chip->nr_cores; i++) {
322 PnvCore *pnv_core = chip->cores[i];
323
324 pnv_dt_core(chip, pnv_core, fdt);
325
326 /* Interrupt Control Presenters (ICP). One per core. */
327 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
328 }
329
330 if (chip->ram_size) {
331 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
332 }
333 }
334
335 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
336 {
337 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
338 int i;
339
340 pnv_dt_xscom(chip, fdt, 0,
341 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
342 cpu_to_be64(PNV9_XSCOM_SIZE),
343 compat, sizeof(compat));
344
345 for (i = 0; i < chip->nr_cores; i++) {
346 PnvCore *pnv_core = chip->cores[i];
347
348 pnv_dt_core(chip, pnv_core, fdt);
349 }
350
351 if (chip->ram_size) {
352 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
353 }
354
355 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
356 }
357
358 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
359 {
360 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
361 int i;
362
363 pnv_dt_xscom(chip, fdt, 0,
364 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
365 cpu_to_be64(PNV10_XSCOM_SIZE),
366 compat, sizeof(compat));
367
368 for (i = 0; i < chip->nr_cores; i++) {
369 PnvCore *pnv_core = chip->cores[i];
370
371 pnv_dt_core(chip, pnv_core, fdt);
372 }
373
374 if (chip->ram_size) {
375 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
376 }
377
378 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
379 }
380
381 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
382 {
383 uint32_t io_base = d->ioport_id;
384 uint32_t io_regs[] = {
385 cpu_to_be32(1),
386 cpu_to_be32(io_base),
387 cpu_to_be32(2)
388 };
389 char *name;
390 int node;
391
392 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
393 node = fdt_add_subnode(fdt, lpc_off, name);
394 _FDT(node);
395 g_free(name);
396
397 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
398 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
399 }
400
401 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
402 {
403 const char compatible[] = "ns16550\0pnpPNP,501";
404 uint32_t io_base = d->ioport_id;
405 uint32_t io_regs[] = {
406 cpu_to_be32(1),
407 cpu_to_be32(io_base),
408 cpu_to_be32(8)
409 };
410 uint32_t irq;
411 char *name;
412 int node;
413
414 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
415
416 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
417 node = fdt_add_subnode(fdt, lpc_off, name);
418 _FDT(node);
419 g_free(name);
420
421 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
422 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
423 sizeof(compatible))));
424
425 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
426 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
427 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
428 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
429 fdt_get_phandle(fdt, lpc_off))));
430
431 /* This is needed by Linux */
432 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
433 }
434
435 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
436 {
437 const char compatible[] = "bt\0ipmi-bt";
438 uint32_t io_base;
439 uint32_t io_regs[] = {
440 cpu_to_be32(1),
441 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
442 cpu_to_be32(3)
443 };
444 uint32_t irq;
445 char *name;
446 int node;
447
448 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
449 io_regs[1] = cpu_to_be32(io_base);
450
451 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
452
453 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
454 node = fdt_add_subnode(fdt, lpc_off, name);
455 _FDT(node);
456 g_free(name);
457
458 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
459 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
460 sizeof(compatible))));
461
462 /* Mark it as reserved to avoid Linux trying to claim it */
463 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
464 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
465 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
466 fdt_get_phandle(fdt, lpc_off))));
467 }
468
469 typedef struct ForeachPopulateArgs {
470 void *fdt;
471 int offset;
472 } ForeachPopulateArgs;
473
474 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
475 {
476 ForeachPopulateArgs *args = opaque;
477 ISADevice *d = ISA_DEVICE(dev);
478
479 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
480 pnv_dt_rtc(d, args->fdt, args->offset);
481 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
482 pnv_dt_serial(d, args->fdt, args->offset);
483 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
484 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
485 } else {
486 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
487 d->ioport_id);
488 }
489
490 return 0;
491 }
492
493 /*
494 * The default LPC bus of a multichip system is on chip 0. It's
495 * recognized by the firmware (skiboot) using a "primary" property.
496 */
497 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
498 {
499 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
500 ForeachPopulateArgs args = {
501 .fdt = fdt,
502 .offset = isa_offset,
503 };
504 uint32_t phandle;
505
506 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
507
508 phandle = qemu_fdt_alloc_phandle(fdt);
509 assert(phandle > 0);
510 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
511
512 /*
513 * ISA devices are not necessarily parented to the ISA bus so we
514 * can not use object_child_foreach()
515 */
516 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
517 &args);
518 }
519
520 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
521 {
522 int off;
523
524 off = fdt_add_subnode(fdt, 0, "ibm,opal");
525 off = fdt_add_subnode(fdt, off, "power-mgt");
526
527 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
528 }
529
530 static void *pnv_dt_create(MachineState *machine)
531 {
532 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
533 PnvMachineState *pnv = PNV_MACHINE(machine);
534 void *fdt;
535 char *buf;
536 int off;
537 int i;
538
539 fdt = g_malloc0(FDT_MAX_SIZE);
540 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
541
542 /* /qemu node */
543 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
544
545 /* Root node */
546 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
547 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
548 _FDT((fdt_setprop_string(fdt, 0, "model",
549 "IBM PowerNV (emulated by qemu)")));
550 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
551
552 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
553 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
554 if (qemu_uuid_set) {
555 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
556 }
557 g_free(buf);
558
559 off = fdt_add_subnode(fdt, 0, "chosen");
560 if (machine->kernel_cmdline) {
561 _FDT((fdt_setprop_string(fdt, off, "bootargs",
562 machine->kernel_cmdline)));
563 }
564
565 if (pnv->initrd_size) {
566 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
567 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
568
569 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
570 &start_prop, sizeof(start_prop))));
571 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
572 &end_prop, sizeof(end_prop))));
573 }
574
575 /* Populate device tree for each chip */
576 for (i = 0; i < pnv->num_chips; i++) {
577 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
578 }
579
580 /* Populate ISA devices on chip 0 */
581 pnv_dt_isa(pnv, fdt);
582
583 if (pnv->bmc) {
584 pnv_dt_bmc_sensors(pnv->bmc, fdt);
585 }
586
587 /* Create an extra node for power management on machines that support it */
588 if (pmc->dt_power_mgt) {
589 pmc->dt_power_mgt(pnv, fdt);
590 }
591
592 return fdt;
593 }
594
595 static void pnv_powerdown_notify(Notifier *n, void *opaque)
596 {
597 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
598
599 if (pnv->bmc) {
600 pnv_bmc_powerdown(pnv->bmc);
601 }
602 }
603
604 static void pnv_reset(MachineState *machine)
605 {
606 PnvMachineState *pnv = PNV_MACHINE(machine);
607 IPMIBmc *bmc;
608 void *fdt;
609
610 qemu_devices_reset();
611
612 /*
613 * The machine should provide by default an internal BMC simulator.
614 * If not, try to use the BMC device that was provided on the command
615 * line.
616 */
617 bmc = pnv_bmc_find(&error_fatal);
618 if (!pnv->bmc) {
619 if (!bmc) {
620 if (!qtest_enabled()) {
621 warn_report("machine has no BMC device. Use '-device "
622 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
623 "to define one");
624 }
625 } else {
626 pnv_bmc_set_pnor(bmc, pnv->pnor);
627 pnv->bmc = bmc;
628 }
629 }
630
631 fdt = pnv_dt_create(machine);
632
633 /* Pack resulting tree */
634 _FDT((fdt_pack(fdt)));
635
636 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
637 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
638
639 g_free(fdt);
640 }
641
642 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
643 {
644 Pnv8Chip *chip8 = PNV8_CHIP(chip);
645 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
646
647 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
648 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
649 }
650
651 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
652 {
653 Pnv8Chip *chip8 = PNV8_CHIP(chip);
654 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
655
656 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
657 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
658 }
659
660 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
661 {
662 Pnv9Chip *chip9 = PNV9_CHIP(chip);
663 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
664
665 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
666 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
667 }
668
669 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
670 {
671 Pnv10Chip *chip10 = PNV10_CHIP(chip);
672 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
673
674 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
675 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
676 }
677
678 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
679 {
680 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
681 }
682
683 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
684 {
685 Pnv8Chip *chip8 = PNV8_CHIP(chip);
686 int i;
687
688 ics_pic_print_info(&chip8->psi.ics, mon);
689
690 for (i = 0; i < chip8->num_phbs; i++) {
691 PnvPHB *phb = chip8->phbs[i];
692 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
693
694 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
695 ics_pic_print_info(&phb3->lsis, mon);
696 }
697 }
698
699 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
700 {
701 Monitor *mon = opaque;
702 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
703
704 if (!phb) {
705 return 0;
706 }
707
708 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
709
710 return 0;
711 }
712
713 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
714 {
715 Pnv9Chip *chip9 = PNV9_CHIP(chip);
716
717 pnv_xive_pic_print_info(&chip9->xive, mon);
718 pnv_psi_pic_print_info(&chip9->psi, mon);
719
720 object_child_foreach_recursive(OBJECT(chip),
721 pnv_chip_power9_pic_print_info_child, mon);
722 }
723
724 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
725 uint32_t core_id)
726 {
727 return PNV_XSCOM_EX_BASE(core_id);
728 }
729
730 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
731 uint32_t core_id)
732 {
733 return PNV9_XSCOM_EC_BASE(core_id);
734 }
735
736 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
737 uint32_t core_id)
738 {
739 return PNV10_XSCOM_EC_BASE(core_id);
740 }
741
742 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
743 {
744 PowerPCCPUClass *ppc_default =
745 POWERPC_CPU_CLASS(object_class_by_name(default_type));
746 PowerPCCPUClass *ppc =
747 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
748
749 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
750 }
751
752 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
753 {
754 ISADevice *dev = isa_new("isa-ipmi-bt");
755
756 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
757 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
758 isa_realize_and_unref(dev, bus, &error_fatal);
759 }
760
761 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
762 {
763 Pnv10Chip *chip10 = PNV10_CHIP(chip);
764
765 pnv_xive2_pic_print_info(&chip10->xive, mon);
766 pnv_psi_pic_print_info(&chip10->psi, mon);
767
768 object_child_foreach_recursive(OBJECT(chip),
769 pnv_chip_power9_pic_print_info_child, mon);
770 }
771
772 /* Always give the first 1GB to chip 0 else we won't boot */
773 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
774 {
775 MachineState *machine = MACHINE(pnv);
776 uint64_t ram_per_chip;
777
778 assert(machine->ram_size >= 1 * GiB);
779
780 ram_per_chip = machine->ram_size / pnv->num_chips;
781 if (ram_per_chip >= 1 * GiB) {
782 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
783 }
784
785 assert(pnv->num_chips > 1);
786
787 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
788 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
789 }
790
791 static void pnv_init(MachineState *machine)
792 {
793 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
794 PnvMachineState *pnv = PNV_MACHINE(machine);
795 MachineClass *mc = MACHINE_GET_CLASS(machine);
796 char *fw_filename;
797 long fw_size;
798 uint64_t chip_ram_start = 0;
799 int i;
800 char *chip_typename;
801 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
802 DeviceState *dev;
803
804 if (kvm_enabled()) {
805 error_report("The powernv machine does not work with KVM acceleration");
806 exit(EXIT_FAILURE);
807 }
808
809 /* allocate RAM */
810 if (machine->ram_size < mc->default_ram_size) {
811 char *sz = size_to_str(mc->default_ram_size);
812 error_report("Invalid RAM size, should be bigger than %s", sz);
813 g_free(sz);
814 exit(EXIT_FAILURE);
815 }
816 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
817
818 /*
819 * Create our simple PNOR device
820 */
821 dev = qdev_new(TYPE_PNV_PNOR);
822 if (pnor) {
823 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
824 }
825 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
826 pnv->pnor = PNV_PNOR(dev);
827
828 /* load skiboot firmware */
829 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
830 if (!fw_filename) {
831 error_report("Could not find OPAL firmware '%s'", bios_name);
832 exit(1);
833 }
834
835 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
836 if (fw_size < 0) {
837 error_report("Could not load OPAL firmware '%s'", fw_filename);
838 exit(1);
839 }
840 g_free(fw_filename);
841
842 /* load kernel */
843 if (machine->kernel_filename) {
844 long kernel_size;
845
846 kernel_size = load_image_targphys(machine->kernel_filename,
847 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
848 if (kernel_size < 0) {
849 error_report("Could not load kernel '%s'",
850 machine->kernel_filename);
851 exit(1);
852 }
853 }
854
855 /* load initrd */
856 if (machine->initrd_filename) {
857 pnv->initrd_base = INITRD_LOAD_ADDR;
858 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
859 pnv->initrd_base, INITRD_MAX_SIZE);
860 if (pnv->initrd_size < 0) {
861 error_report("Could not load initial ram disk '%s'",
862 machine->initrd_filename);
863 exit(1);
864 }
865 }
866
867 /* MSIs are supported on this platform */
868 msi_nonbroken = true;
869
870 /*
871 * Check compatibility of the specified CPU with the machine
872 * default.
873 */
874 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
875 error_report("invalid CPU model '%s' for %s machine",
876 machine->cpu_type, mc->name);
877 exit(1);
878 }
879
880 /* Create the processor chips */
881 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
882 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
883 i, machine->cpu_type);
884 if (!object_class_by_name(chip_typename)) {
885 error_report("invalid chip model '%.*s' for %s machine",
886 i, machine->cpu_type, mc->name);
887 exit(1);
888 }
889
890 pnv->num_chips =
891 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
892 /*
893 * TODO: should we decide on how many chips we can create based
894 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
895 */
896 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
897 error_report("invalid number of chips: '%d'", pnv->num_chips);
898 error_printf(
899 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
900 exit(1);
901 }
902
903 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
904 for (i = 0; i < pnv->num_chips; i++) {
905 char chip_name[32];
906 Object *chip = OBJECT(qdev_new(chip_typename));
907 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
908
909 pnv->chips[i] = PNV_CHIP(chip);
910
911 /* Distribute RAM among the chips */
912 object_property_set_int(chip, "ram-start", chip_ram_start,
913 &error_fatal);
914 object_property_set_int(chip, "ram-size", chip_ram_size,
915 &error_fatal);
916 chip_ram_start += chip_ram_size;
917
918 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
919 object_property_add_child(OBJECT(pnv), chip_name, chip);
920 object_property_set_int(chip, "chip-id", i, &error_fatal);
921 object_property_set_int(chip, "nr-cores", machine->smp.cores,
922 &error_fatal);
923 object_property_set_int(chip, "nr-threads", machine->smp.threads,
924 &error_fatal);
925 /*
926 * The POWER8 machine use the XICS interrupt interface.
927 * Propagate the XICS fabric to the chip and its controllers.
928 */
929 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
930 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
931 }
932 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
933 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
934 &error_abort);
935 }
936 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
937 }
938 g_free(chip_typename);
939
940 /* Instantiate ISA bus on chip 0 */
941 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
942
943 /* Create serial port */
944 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
945
946 /* Create an RTC ISA device too */
947 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
948
949 /*
950 * Create the machine BMC simulator and the IPMI BT device for
951 * communication with the BMC
952 */
953 if (defaults_enabled()) {
954 pnv->bmc = pnv_bmc_create(pnv->pnor);
955 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
956 }
957
958 /*
959 * The PNOR is mapped on the LPC FW address space by the BMC.
960 * Since we can not reach the remote BMC machine with LPC memops,
961 * map it always for now.
962 */
963 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
964 &pnv->pnor->mmio);
965
966 /*
967 * OpenPOWER systems use a IPMI SEL Event message to notify the
968 * host to powerdown
969 */
970 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
971 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
972 }
973
974 /*
975 * 0:21 Reserved - Read as zeros
976 * 22:24 Chip ID
977 * 25:28 Core number
978 * 29:31 Thread ID
979 */
980 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
981 {
982 return (chip->chip_id << 7) | (core_id << 3);
983 }
984
985 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
986 Error **errp)
987 {
988 Pnv8Chip *chip8 = PNV8_CHIP(chip);
989 Error *local_err = NULL;
990 Object *obj;
991 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
992
993 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
994 if (local_err) {
995 error_propagate(errp, local_err);
996 return;
997 }
998
999 pnv_cpu->intc = obj;
1000 }
1001
1002
1003 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1004 {
1005 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1006
1007 icp_reset(ICP(pnv_cpu->intc));
1008 }
1009
1010 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1011 {
1012 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1013
1014 icp_destroy(ICP(pnv_cpu->intc));
1015 pnv_cpu->intc = NULL;
1016 }
1017
1018 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1019 Monitor *mon)
1020 {
1021 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1022 }
1023
1024 /*
1025 * 0:48 Reserved - Read as zeroes
1026 * 49:52 Node ID
1027 * 53:55 Chip ID
1028 * 56 Reserved - Read as zero
1029 * 57:61 Core number
1030 * 62:63 Thread ID
1031 *
1032 * We only care about the lower bits. uint32_t is fine for the moment.
1033 */
1034 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
1035 {
1036 return (chip->chip_id << 8) | (core_id << 2);
1037 }
1038
1039 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1040 {
1041 return (chip->chip_id << 8) | (core_id << 2);
1042 }
1043
1044 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1045 Error **errp)
1046 {
1047 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1048 Error *local_err = NULL;
1049 Object *obj;
1050 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1051
1052 /*
1053 * The core creates its interrupt presenter but the XIVE interrupt
1054 * controller object is initialized afterwards. Hopefully, it's
1055 * only used at runtime.
1056 */
1057 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1058 &local_err);
1059 if (local_err) {
1060 error_propagate(errp, local_err);
1061 return;
1062 }
1063
1064 pnv_cpu->intc = obj;
1065 }
1066
1067 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1068 {
1069 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1070
1071 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1072 }
1073
1074 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1075 {
1076 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1077
1078 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1079 pnv_cpu->intc = NULL;
1080 }
1081
1082 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1083 Monitor *mon)
1084 {
1085 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1086 }
1087
1088 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1089 Error **errp)
1090 {
1091 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1092 Error *local_err = NULL;
1093 Object *obj;
1094 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1095
1096 /*
1097 * The core creates its interrupt presenter but the XIVE2 interrupt
1098 * controller object is initialized afterwards. Hopefully, it's
1099 * only used at runtime.
1100 */
1101 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1102 &local_err);
1103 if (local_err) {
1104 error_propagate(errp, local_err);
1105 return;
1106 }
1107
1108 pnv_cpu->intc = obj;
1109 }
1110
1111 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1112 {
1113 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1114
1115 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1116 }
1117
1118 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1119 {
1120 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1121
1122 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1123 pnv_cpu->intc = NULL;
1124 }
1125
1126 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1127 Monitor *mon)
1128 {
1129 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1130 }
1131
1132 /*
1133 * Allowed core identifiers on a POWER8 Processor Chip :
1134 *
1135 * <EX0 reserved>
1136 * EX1 - Venice only
1137 * EX2 - Venice only
1138 * EX3 - Venice only
1139 * EX4
1140 * EX5
1141 * EX6
1142 * <EX7,8 reserved> <reserved>
1143 * EX9 - Venice only
1144 * EX10 - Venice only
1145 * EX11 - Venice only
1146 * EX12
1147 * EX13
1148 * EX14
1149 * <EX15 reserved>
1150 */
1151 #define POWER8E_CORE_MASK (0x7070ull)
1152 #define POWER8_CORE_MASK (0x7e7eull)
1153
1154 /*
1155 * POWER9 has 24 cores, ids starting at 0x0
1156 */
1157 #define POWER9_CORE_MASK (0xffffffffffffffull)
1158
1159
1160 #define POWER10_CORE_MASK (0xffffffffffffffull)
1161
1162 static void pnv_chip_power8_instance_init(Object *obj)
1163 {
1164 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1165 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1166 int i;
1167
1168 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1169 (Object **)&chip8->xics,
1170 object_property_allow_set_link,
1171 OBJ_PROP_LINK_STRONG);
1172
1173 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1174
1175 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1176
1177 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1178
1179 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1180
1181 chip8->num_phbs = pcc->num_phbs;
1182
1183 for (i = 0; i < chip8->num_phbs; i++) {
1184 Object *phb = object_new(TYPE_PNV_PHB);
1185
1186 /*
1187 * We need the chip to parent the PHB to allow the DT
1188 * to build correctly (via pnv_xscom_dt()).
1189 *
1190 * TODO: the PHB should be parented by a PEC device that, at
1191 * this moment, is not modelled powernv8/phb3.
1192 */
1193 object_property_add_child(obj, "phb[*]", phb);
1194 chip8->phbs[i] = PNV_PHB(phb);
1195 }
1196
1197 }
1198
1199 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1200 {
1201 PnvChip *chip = PNV_CHIP(chip8);
1202 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1203 int i, j;
1204 char *name;
1205
1206 name = g_strdup_printf("icp-%x", chip->chip_id);
1207 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1208 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1209 g_free(name);
1210
1211 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1212
1213 /* Map the ICP registers for each thread */
1214 for (i = 0; i < chip->nr_cores; i++) {
1215 PnvCore *pnv_core = chip->cores[i];
1216 int core_hwid = CPU_CORE(pnv_core)->core_id;
1217
1218 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1219 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1220 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1221
1222 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1223 &icp->mmio);
1224 }
1225 }
1226 }
1227
1228 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1229 {
1230 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1231 PnvChip *chip = PNV_CHIP(dev);
1232 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1233 Pnv8Psi *psi8 = &chip8->psi;
1234 Error *local_err = NULL;
1235 int i;
1236
1237 assert(chip8->xics);
1238
1239 /* XSCOM bridge is first */
1240 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1241 if (local_err) {
1242 error_propagate(errp, local_err);
1243 return;
1244 }
1245 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1246
1247 pcc->parent_realize(dev, &local_err);
1248 if (local_err) {
1249 error_propagate(errp, local_err);
1250 return;
1251 }
1252
1253 /* Processor Service Interface (PSI) Host Bridge */
1254 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1255 &error_fatal);
1256 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1257 OBJECT(chip8->xics), &error_abort);
1258 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1259 return;
1260 }
1261 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1262 &PNV_PSI(psi8)->xscom_regs);
1263
1264 /* Create LPC controller */
1265 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1266 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1267
1268 chip->fw_mr = &chip8->lpc.isa_fw;
1269 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1270 (uint64_t) PNV_XSCOM_BASE(chip),
1271 PNV_XSCOM_LPC_BASE);
1272
1273 /*
1274 * Interrupt Management Area. This is the memory region holding
1275 * all the Interrupt Control Presenter (ICP) registers
1276 */
1277 pnv_chip_icp_realize(chip8, &local_err);
1278 if (local_err) {
1279 error_propagate(errp, local_err);
1280 return;
1281 }
1282
1283 /* Create the simplified OCC model */
1284 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1285 return;
1286 }
1287 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1288 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1289 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
1290
1291 /* OCC SRAM model */
1292 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1293 &chip8->occ.sram_regs);
1294
1295 /* HOMER */
1296 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1297 &error_abort);
1298 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1299 return;
1300 }
1301 /* Homer Xscom region */
1302 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1303
1304 /* Homer mmio region */
1305 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1306 &chip8->homer.regs);
1307
1308 /* PHB controllers */
1309 for (i = 0; i < chip8->num_phbs; i++) {
1310 PnvPHB *phb = chip8->phbs[i];
1311
1312 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1313 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1314 &error_fatal);
1315 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1316 &error_fatal);
1317 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1318 return;
1319 }
1320 }
1321 }
1322
1323 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1324 {
1325 addr &= (PNV_XSCOM_SIZE - 1);
1326 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1327 }
1328
1329 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1330 {
1331 DeviceClass *dc = DEVICE_CLASS(klass);
1332 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1333
1334 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1335 k->cores_mask = POWER8E_CORE_MASK;
1336 k->num_phbs = 3;
1337 k->core_pir = pnv_chip_core_pir_p8;
1338 k->intc_create = pnv_chip_power8_intc_create;
1339 k->intc_reset = pnv_chip_power8_intc_reset;
1340 k->intc_destroy = pnv_chip_power8_intc_destroy;
1341 k->intc_print_info = pnv_chip_power8_intc_print_info;
1342 k->isa_create = pnv_chip_power8_isa_create;
1343 k->dt_populate = pnv_chip_power8_dt_populate;
1344 k->pic_print_info = pnv_chip_power8_pic_print_info;
1345 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1346 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1347 dc->desc = "PowerNV Chip POWER8E";
1348
1349 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1350 &k->parent_realize);
1351 }
1352
1353 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1354 {
1355 DeviceClass *dc = DEVICE_CLASS(klass);
1356 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1357
1358 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1359 k->cores_mask = POWER8_CORE_MASK;
1360 k->num_phbs = 3;
1361 k->core_pir = pnv_chip_core_pir_p8;
1362 k->intc_create = pnv_chip_power8_intc_create;
1363 k->intc_reset = pnv_chip_power8_intc_reset;
1364 k->intc_destroy = pnv_chip_power8_intc_destroy;
1365 k->intc_print_info = pnv_chip_power8_intc_print_info;
1366 k->isa_create = pnv_chip_power8_isa_create;
1367 k->dt_populate = pnv_chip_power8_dt_populate;
1368 k->pic_print_info = pnv_chip_power8_pic_print_info;
1369 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1370 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1371 dc->desc = "PowerNV Chip POWER8";
1372
1373 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1374 &k->parent_realize);
1375 }
1376
1377 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1378 {
1379 DeviceClass *dc = DEVICE_CLASS(klass);
1380 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1381
1382 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1383 k->cores_mask = POWER8_CORE_MASK;
1384 k->num_phbs = 4;
1385 k->core_pir = pnv_chip_core_pir_p8;
1386 k->intc_create = pnv_chip_power8_intc_create;
1387 k->intc_reset = pnv_chip_power8_intc_reset;
1388 k->intc_destroy = pnv_chip_power8_intc_destroy;
1389 k->intc_print_info = pnv_chip_power8_intc_print_info;
1390 k->isa_create = pnv_chip_power8nvl_isa_create;
1391 k->dt_populate = pnv_chip_power8_dt_populate;
1392 k->pic_print_info = pnv_chip_power8_pic_print_info;
1393 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1394 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1395 dc->desc = "PowerNV Chip POWER8NVL";
1396
1397 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1398 &k->parent_realize);
1399 }
1400
1401 static void pnv_chip_power9_instance_init(Object *obj)
1402 {
1403 PnvChip *chip = PNV_CHIP(obj);
1404 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1405 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1406 int i;
1407
1408 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1409 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1410 "xive-fabric");
1411
1412 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1413
1414 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1415
1416 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1417
1418 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1419
1420 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1421
1422 /* Number of PECs is the chip default */
1423 chip->num_pecs = pcc->num_pecs;
1424
1425 for (i = 0; i < chip->num_pecs; i++) {
1426 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1427 TYPE_PNV_PHB4_PEC);
1428 }
1429 }
1430
1431 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1432 PnvCore *pnv_core)
1433 {
1434 char eq_name[32];
1435 int core_id = CPU_CORE(pnv_core)->core_id;
1436
1437 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1438 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1439 sizeof(*eq), TYPE_PNV_QUAD,
1440 &error_fatal, NULL);
1441
1442 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1443 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1444 }
1445
1446 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1447 {
1448 PnvChip *chip = PNV_CHIP(chip9);
1449 int i;
1450
1451 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1452 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1453
1454 for (i = 0; i < chip9->nr_quads; i++) {
1455 PnvQuad *eq = &chip9->quads[i];
1456
1457 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1458
1459 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1460 &eq->xscom_regs);
1461 }
1462 }
1463
1464 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1465 {
1466 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1467 int i;
1468
1469 for (i = 0; i < chip->num_pecs; i++) {
1470 PnvPhb4PecState *pec = &chip9->pecs[i];
1471 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1472 uint32_t pec_nest_base;
1473 uint32_t pec_pci_base;
1474
1475 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1476 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1477 &error_fatal);
1478 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1479 &error_fatal);
1480 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1481 return;
1482 }
1483
1484 pec_nest_base = pecc->xscom_nest_base(pec);
1485 pec_pci_base = pecc->xscom_pci_base(pec);
1486
1487 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1488 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1489 }
1490 }
1491
1492 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1493 {
1494 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1495 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1496 PnvChip *chip = PNV_CHIP(dev);
1497 Pnv9Psi *psi9 = &chip9->psi;
1498 Error *local_err = NULL;
1499
1500 /* XSCOM bridge is first */
1501 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1502 if (local_err) {
1503 error_propagate(errp, local_err);
1504 return;
1505 }
1506 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1507
1508 pcc->parent_realize(dev, &local_err);
1509 if (local_err) {
1510 error_propagate(errp, local_err);
1511 return;
1512 }
1513
1514 pnv_chip_quad_realize(chip9, &local_err);
1515 if (local_err) {
1516 error_propagate(errp, local_err);
1517 return;
1518 }
1519
1520 /* XIVE interrupt controller (POWER9) */
1521 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1522 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1523 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1524 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1525 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1526 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1527 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1528 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1529 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1530 &error_abort);
1531 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1532 return;
1533 }
1534 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1535 &chip9->xive.xscom_regs);
1536
1537 /* Processor Service Interface (PSI) Host Bridge */
1538 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1539 &error_fatal);
1540 /* This is the only device with 4k ESB pages */
1541 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
1542 &error_fatal);
1543 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1544 return;
1545 }
1546 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1547 &PNV_PSI(psi9)->xscom_regs);
1548
1549 /* LPC */
1550 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1551 return;
1552 }
1553 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1554 &chip9->lpc.xscom_regs);
1555
1556 chip->fw_mr = &chip9->lpc.isa_fw;
1557 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1558 (uint64_t) PNV9_LPCM_BASE(chip));
1559
1560 /* Create the simplified OCC model */
1561 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1562 return;
1563 }
1564 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1565 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1566 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
1567
1568 /* OCC SRAM model */
1569 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1570 &chip9->occ.sram_regs);
1571
1572 /* SBE */
1573 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1574 return;
1575 }
1576 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1577 &chip9->sbe.xscom_ctrl_regs);
1578 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1579 &chip9->sbe.xscom_mbox_regs);
1580 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1581 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
1582
1583 /* HOMER */
1584 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1585 &error_abort);
1586 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1587 return;
1588 }
1589 /* Homer Xscom region */
1590 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1591
1592 /* Homer mmio region */
1593 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1594 &chip9->homer.regs);
1595
1596 /* PEC PHBs */
1597 pnv_chip_power9_pec_realize(chip, &local_err);
1598 if (local_err) {
1599 error_propagate(errp, local_err);
1600 return;
1601 }
1602 }
1603
1604 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1605 {
1606 addr &= (PNV9_XSCOM_SIZE - 1);
1607 return addr >> 3;
1608 }
1609
1610 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1611 {
1612 DeviceClass *dc = DEVICE_CLASS(klass);
1613 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1614
1615 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1616 k->cores_mask = POWER9_CORE_MASK;
1617 k->core_pir = pnv_chip_core_pir_p9;
1618 k->intc_create = pnv_chip_power9_intc_create;
1619 k->intc_reset = pnv_chip_power9_intc_reset;
1620 k->intc_destroy = pnv_chip_power9_intc_destroy;
1621 k->intc_print_info = pnv_chip_power9_intc_print_info;
1622 k->isa_create = pnv_chip_power9_isa_create;
1623 k->dt_populate = pnv_chip_power9_dt_populate;
1624 k->pic_print_info = pnv_chip_power9_pic_print_info;
1625 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1626 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1627 dc->desc = "PowerNV Chip POWER9";
1628 k->num_pecs = PNV9_CHIP_MAX_PEC;
1629
1630 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1631 &k->parent_realize);
1632 }
1633
1634 static void pnv_chip_power10_instance_init(Object *obj)
1635 {
1636 PnvChip *chip = PNV_CHIP(obj);
1637 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1638 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1639 int i;
1640
1641 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1642 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1643 "xive-fabric");
1644 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1645 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1646 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1647 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
1648 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1649
1650 chip->num_pecs = pcc->num_pecs;
1651
1652 for (i = 0; i < chip->num_pecs; i++) {
1653 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1654 TYPE_PNV_PHB5_PEC);
1655 }
1656 }
1657
1658 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1659 {
1660 PnvChip *chip = PNV_CHIP(chip10);
1661 int i;
1662
1663 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1664 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1665
1666 for (i = 0; i < chip10->nr_quads; i++) {
1667 PnvQuad *eq = &chip10->quads[i];
1668
1669 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1670
1671 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1672 &eq->xscom_regs);
1673 }
1674 }
1675
1676 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1677 {
1678 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1679 int i;
1680
1681 for (i = 0; i < chip->num_pecs; i++) {
1682 PnvPhb4PecState *pec = &chip10->pecs[i];
1683 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1684 uint32_t pec_nest_base;
1685 uint32_t pec_pci_base;
1686
1687 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1688 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1689 &error_fatal);
1690 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1691 &error_fatal);
1692 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1693 return;
1694 }
1695
1696 pec_nest_base = pecc->xscom_nest_base(pec);
1697 pec_pci_base = pecc->xscom_pci_base(pec);
1698
1699 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1700 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1701 }
1702 }
1703
1704 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1705 {
1706 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1707 PnvChip *chip = PNV_CHIP(dev);
1708 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1709 Error *local_err = NULL;
1710
1711 /* XSCOM bridge is first */
1712 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1713 if (local_err) {
1714 error_propagate(errp, local_err);
1715 return;
1716 }
1717 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1718
1719 pcc->parent_realize(dev, &local_err);
1720 if (local_err) {
1721 error_propagate(errp, local_err);
1722 return;
1723 }
1724
1725 pnv_chip_power10_quad_realize(chip10, &local_err);
1726 if (local_err) {
1727 error_propagate(errp, local_err);
1728 return;
1729 }
1730
1731 /* XIVE2 interrupt controller (POWER10) */
1732 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1733 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1734 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1735 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1736 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1737 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1738 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1739 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1740 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1741 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1742 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1743 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1744 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1745 &error_abort);
1746 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1747 return;
1748 }
1749 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1750 &chip10->xive.xscom_regs);
1751
1752 /* Processor Service Interface (PSI) Host Bridge */
1753 object_property_set_int(OBJECT(&chip10->psi), "bar",
1754 PNV10_PSIHB_BASE(chip), &error_fatal);
1755 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1756 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1757 &error_fatal);
1758 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1759 return;
1760 }
1761 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1762 &PNV_PSI(&chip10->psi)->xscom_regs);
1763
1764 /* LPC */
1765 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1766 return;
1767 }
1768 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1769 &chip10->lpc.xscom_regs);
1770
1771 chip->fw_mr = &chip10->lpc.isa_fw;
1772 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1773 (uint64_t) PNV10_LPCM_BASE(chip));
1774
1775 /* Create the simplified OCC model */
1776 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1777 return;
1778 }
1779 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1780 &chip10->occ.xscom_regs);
1781 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
1782 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
1783
1784 /* OCC SRAM model */
1785 memory_region_add_subregion(get_system_memory(),
1786 PNV10_OCC_SENSOR_BASE(chip),
1787 &chip10->occ.sram_regs);
1788
1789 /* SBE */
1790 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
1791 return;
1792 }
1793 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
1794 &chip10->sbe.xscom_ctrl_regs);
1795 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
1796 &chip10->sbe.xscom_mbox_regs);
1797 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
1798 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
1799
1800 /* HOMER */
1801 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1802 &error_abort);
1803 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1804 return;
1805 }
1806 /* Homer Xscom region */
1807 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1808 &chip10->homer.pba_regs);
1809
1810 /* Homer mmio region */
1811 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1812 &chip10->homer.regs);
1813
1814 /* PHBs */
1815 pnv_chip_power10_phb_realize(chip, &local_err);
1816 if (local_err) {
1817 error_propagate(errp, local_err);
1818 return;
1819 }
1820 }
1821
1822 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1823 {
1824 addr &= (PNV10_XSCOM_SIZE - 1);
1825 return addr >> 3;
1826 }
1827
1828 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1829 {
1830 DeviceClass *dc = DEVICE_CLASS(klass);
1831 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1832
1833 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1834 k->cores_mask = POWER10_CORE_MASK;
1835 k->core_pir = pnv_chip_core_pir_p10;
1836 k->intc_create = pnv_chip_power10_intc_create;
1837 k->intc_reset = pnv_chip_power10_intc_reset;
1838 k->intc_destroy = pnv_chip_power10_intc_destroy;
1839 k->intc_print_info = pnv_chip_power10_intc_print_info;
1840 k->isa_create = pnv_chip_power10_isa_create;
1841 k->dt_populate = pnv_chip_power10_dt_populate;
1842 k->pic_print_info = pnv_chip_power10_pic_print_info;
1843 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1844 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1845 dc->desc = "PowerNV Chip POWER10";
1846 k->num_pecs = PNV10_CHIP_MAX_PEC;
1847
1848 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1849 &k->parent_realize);
1850 }
1851
1852 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1853 {
1854 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1855 int cores_max;
1856
1857 /*
1858 * No custom mask for this chip, let's use the default one from *
1859 * the chip class
1860 */
1861 if (!chip->cores_mask) {
1862 chip->cores_mask = pcc->cores_mask;
1863 }
1864
1865 /* filter alien core ids ! some are reserved */
1866 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1867 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1868 chip->cores_mask);
1869 return;
1870 }
1871 chip->cores_mask &= pcc->cores_mask;
1872
1873 /* now that we have a sane layout, let check the number of cores */
1874 cores_max = ctpop64(chip->cores_mask);
1875 if (chip->nr_cores > cores_max) {
1876 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1877 cores_max);
1878 return;
1879 }
1880 }
1881
1882 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1883 {
1884 Error *error = NULL;
1885 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1886 const char *typename = pnv_chip_core_typename(chip);
1887 int i, core_hwid;
1888 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1889
1890 if (!object_class_by_name(typename)) {
1891 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1892 return;
1893 }
1894
1895 /* Cores */
1896 pnv_chip_core_sanitize(chip, &error);
1897 if (error) {
1898 error_propagate(errp, error);
1899 return;
1900 }
1901
1902 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1903
1904 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1905 && (i < chip->nr_cores); core_hwid++) {
1906 char core_name[32];
1907 PnvCore *pnv_core;
1908 uint64_t xscom_core_base;
1909
1910 if (!(chip->cores_mask & (1ull << core_hwid))) {
1911 continue;
1912 }
1913
1914 pnv_core = PNV_CORE(object_new(typename));
1915
1916 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1917 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1918 chip->cores[i] = pnv_core;
1919 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1920 chip->nr_threads, &error_fatal);
1921 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1922 core_hwid, &error_fatal);
1923 object_property_set_int(OBJECT(pnv_core), "pir",
1924 pcc->core_pir(chip, core_hwid), &error_fatal);
1925 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1926 &error_fatal);
1927 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1928 &error_abort);
1929 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1930
1931 /* Each core has an XSCOM MMIO region */
1932 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1933
1934 pnv_xscom_add_subregion(chip, xscom_core_base,
1935 &pnv_core->xscom_regs);
1936 i++;
1937 }
1938 }
1939
1940 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1941 {
1942 PnvChip *chip = PNV_CHIP(dev);
1943 Error *error = NULL;
1944
1945 /* Cores */
1946 pnv_chip_core_realize(chip, &error);
1947 if (error) {
1948 error_propagate(errp, error);
1949 return;
1950 }
1951 }
1952
1953 static Property pnv_chip_properties[] = {
1954 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1955 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1956 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1957 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1958 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1959 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1960 DEFINE_PROP_END_OF_LIST(),
1961 };
1962
1963 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1964 {
1965 DeviceClass *dc = DEVICE_CLASS(klass);
1966
1967 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1968 dc->realize = pnv_chip_realize;
1969 device_class_set_props(dc, pnv_chip_properties);
1970 dc->desc = "PowerNV Chip";
1971 }
1972
1973 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1974 {
1975 int i, j;
1976
1977 for (i = 0; i < chip->nr_cores; i++) {
1978 PnvCore *pc = chip->cores[i];
1979 CPUCore *cc = CPU_CORE(pc);
1980
1981 for (j = 0; j < cc->nr_threads; j++) {
1982 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1983 return pc->threads[j];
1984 }
1985 }
1986 }
1987 return NULL;
1988 }
1989
1990 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1991 {
1992 PnvMachineState *pnv = PNV_MACHINE(xi);
1993 int i, j;
1994
1995 for (i = 0; i < pnv->num_chips; i++) {
1996 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1997
1998 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1999 return &chip8->psi.ics;
2000 }
2001
2002 for (j = 0; j < chip8->num_phbs; j++) {
2003 PnvPHB *phb = chip8->phbs[j];
2004 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2005
2006 if (ics_valid_irq(&phb3->lsis, irq)) {
2007 return &phb3->lsis;
2008 }
2009
2010 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2011 return ICS(&phb3->msis);
2012 }
2013 }
2014 }
2015 return NULL;
2016 }
2017
2018 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2019 {
2020 int i;
2021
2022 for (i = 0; i < pnv->num_chips; i++) {
2023 PnvChip *chip = pnv->chips[i];
2024 if (chip->chip_id == chip_id) {
2025 return chip;
2026 }
2027 }
2028 return NULL;
2029 }
2030
2031 static void pnv_ics_resend(XICSFabric *xi)
2032 {
2033 PnvMachineState *pnv = PNV_MACHINE(xi);
2034 int i, j;
2035
2036 for (i = 0; i < pnv->num_chips; i++) {
2037 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2038
2039 ics_resend(&chip8->psi.ics);
2040
2041 for (j = 0; j < chip8->num_phbs; j++) {
2042 PnvPHB *phb = chip8->phbs[j];
2043 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2044
2045 ics_resend(&phb3->lsis);
2046 ics_resend(ICS(&phb3->msis));
2047 }
2048 }
2049 }
2050
2051 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2052 {
2053 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2054
2055 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2056 }
2057
2058 static void pnv_pic_print_info(InterruptStatsProvider *obj,
2059 Monitor *mon)
2060 {
2061 PnvMachineState *pnv = PNV_MACHINE(obj);
2062 int i;
2063 CPUState *cs;
2064
2065 CPU_FOREACH(cs) {
2066 PowerPCCPU *cpu = POWERPC_CPU(cs);
2067
2068 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2069 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
2070 mon);
2071 }
2072
2073 for (i = 0; i < pnv->num_chips; i++) {
2074 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
2075 }
2076 }
2077
2078 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2079 uint8_t nvt_blk, uint32_t nvt_idx,
2080 bool cam_ignore, uint8_t priority,
2081 uint32_t logic_serv,
2082 XiveTCTXMatch *match)
2083 {
2084 PnvMachineState *pnv = PNV_MACHINE(xfb);
2085 int total_count = 0;
2086 int i;
2087
2088 for (i = 0; i < pnv->num_chips; i++) {
2089 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2090 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2091 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2092 int count;
2093
2094 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2095 priority, logic_serv, match);
2096
2097 if (count < 0) {
2098 return count;
2099 }
2100
2101 total_count += count;
2102 }
2103
2104 return total_count;
2105 }
2106
2107 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2108 uint8_t nvt_blk, uint32_t nvt_idx,
2109 bool cam_ignore, uint8_t priority,
2110 uint32_t logic_serv,
2111 XiveTCTXMatch *match)
2112 {
2113 PnvMachineState *pnv = PNV_MACHINE(xfb);
2114 int total_count = 0;
2115 int i;
2116
2117 for (i = 0; i < pnv->num_chips; i++) {
2118 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2119 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2120 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2121 int count;
2122
2123 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2124 priority, logic_serv, match);
2125
2126 if (count < 0) {
2127 return count;
2128 }
2129
2130 total_count += count;
2131 }
2132
2133 return total_count;
2134 }
2135
2136 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2137 {
2138 MachineClass *mc = MACHINE_CLASS(oc);
2139 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2140 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2141 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2142
2143 static GlobalProperty phb_compat[] = {
2144 { TYPE_PNV_PHB, "version", "3" },
2145 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2146 };
2147
2148 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2149 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2150 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2151
2152 xic->icp_get = pnv_icp_get;
2153 xic->ics_get = pnv_ics_get;
2154 xic->ics_resend = pnv_ics_resend;
2155
2156 pmc->compat = compat;
2157 pmc->compat_size = sizeof(compat);
2158 }
2159
2160 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2161 {
2162 MachineClass *mc = MACHINE_CLASS(oc);
2163 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2164 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2165 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2166
2167 static GlobalProperty phb_compat[] = {
2168 { TYPE_PNV_PHB, "version", "4" },
2169 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2170 };
2171
2172 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2173 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
2174 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2175
2176 xfc->match_nvt = pnv_match_nvt;
2177
2178 mc->alias = "powernv";
2179
2180 pmc->compat = compat;
2181 pmc->compat_size = sizeof(compat);
2182 pmc->dt_power_mgt = pnv_dt_power_mgt;
2183 }
2184
2185 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2186 {
2187 MachineClass *mc = MACHINE_CLASS(oc);
2188 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2189 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2190 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2191
2192 static GlobalProperty phb_compat[] = {
2193 { TYPE_PNV_PHB, "version", "5" },
2194 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2195 };
2196
2197 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2198 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2199 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2200
2201 pmc->compat = compat;
2202 pmc->compat_size = sizeof(compat);
2203 pmc->dt_power_mgt = pnv_dt_power_mgt;
2204
2205 xfc->match_nvt = pnv10_xive_match_nvt;
2206 }
2207
2208 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2209 {
2210 PnvMachineState *pnv = PNV_MACHINE(obj);
2211
2212 return !!pnv->fw_load_addr;
2213 }
2214
2215 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2216 {
2217 PnvMachineState *pnv = PNV_MACHINE(obj);
2218
2219 if (value) {
2220 pnv->fw_load_addr = 0x8000000;
2221 }
2222 }
2223
2224 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2225 {
2226 PowerPCCPU *cpu = POWERPC_CPU(cs);
2227 CPUPPCState *env = &cpu->env;
2228
2229 cpu_synchronize_state(cs);
2230 ppc_cpu_do_system_reset(cs);
2231 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2232 /*
2233 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2234 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2235 * (PPC_BIT(43)).
2236 */
2237 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2238 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2239 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2240 }
2241 } else {
2242 /*
2243 * For non-powersave system resets, SRR1[42:45] are defined to be
2244 * implementation-dependent. The POWER9 User Manual specifies that
2245 * an external (SCOM driven, which may come from a BMC nmi command or
2246 * another CPU requesting a NMI IPI) system reset exception should be
2247 * 0b0010 (PPC_BIT(44)).
2248 */
2249 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2250 }
2251 }
2252
2253 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2254 {
2255 CPUState *cs;
2256
2257 CPU_FOREACH(cs) {
2258 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2259 }
2260 }
2261
2262 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2263 {
2264 MachineClass *mc = MACHINE_CLASS(oc);
2265 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2266 NMIClass *nc = NMI_CLASS(oc);
2267
2268 mc->desc = "IBM PowerNV (Non-Virtualized)";
2269 mc->init = pnv_init;
2270 mc->reset = pnv_reset;
2271 mc->max_cpus = MAX_CPUS;
2272 /* Pnv provides a AHCI device for storage */
2273 mc->block_default_type = IF_IDE;
2274 mc->no_parallel = 1;
2275 mc->default_boot_order = NULL;
2276 /*
2277 * RAM defaults to less than 2048 for 32-bit hosts, and large
2278 * enough to fit the maximum initrd size at it's load address
2279 */
2280 mc->default_ram_size = 1 * GiB;
2281 mc->default_ram_id = "pnv.ram";
2282 ispc->print_info = pnv_pic_print_info;
2283 nc->nmi_monitor_handler = pnv_nmi;
2284
2285 object_class_property_add_bool(oc, "hb-mode",
2286 pnv_machine_get_hb, pnv_machine_set_hb);
2287 object_class_property_set_description(oc, "hb-mode",
2288 "Use a hostboot like boot loader");
2289 }
2290
2291 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2292 { \
2293 .name = type, \
2294 .class_init = class_initfn, \
2295 .parent = TYPE_PNV8_CHIP, \
2296 }
2297
2298 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2299 { \
2300 .name = type, \
2301 .class_init = class_initfn, \
2302 .parent = TYPE_PNV9_CHIP, \
2303 }
2304
2305 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2306 { \
2307 .name = type, \
2308 .class_init = class_initfn, \
2309 .parent = TYPE_PNV10_CHIP, \
2310 }
2311
2312 static const TypeInfo types[] = {
2313 {
2314 .name = MACHINE_TYPE_NAME("powernv10"),
2315 .parent = TYPE_PNV_MACHINE,
2316 .class_init = pnv_machine_power10_class_init,
2317 .interfaces = (InterfaceInfo[]) {
2318 { TYPE_XIVE_FABRIC },
2319 { },
2320 },
2321 },
2322 {
2323 .name = MACHINE_TYPE_NAME("powernv9"),
2324 .parent = TYPE_PNV_MACHINE,
2325 .class_init = pnv_machine_power9_class_init,
2326 .interfaces = (InterfaceInfo[]) {
2327 { TYPE_XIVE_FABRIC },
2328 { },
2329 },
2330 },
2331 {
2332 .name = MACHINE_TYPE_NAME("powernv8"),
2333 .parent = TYPE_PNV_MACHINE,
2334 .class_init = pnv_machine_power8_class_init,
2335 .interfaces = (InterfaceInfo[]) {
2336 { TYPE_XICS_FABRIC },
2337 { },
2338 },
2339 },
2340 {
2341 .name = TYPE_PNV_MACHINE,
2342 .parent = TYPE_MACHINE,
2343 .abstract = true,
2344 .instance_size = sizeof(PnvMachineState),
2345 .class_init = pnv_machine_class_init,
2346 .class_size = sizeof(PnvMachineClass),
2347 .interfaces = (InterfaceInfo[]) {
2348 { TYPE_INTERRUPT_STATS_PROVIDER },
2349 { TYPE_NMI },
2350 { },
2351 },
2352 },
2353 {
2354 .name = TYPE_PNV_CHIP,
2355 .parent = TYPE_SYS_BUS_DEVICE,
2356 .class_init = pnv_chip_class_init,
2357 .instance_size = sizeof(PnvChip),
2358 .class_size = sizeof(PnvChipClass),
2359 .abstract = true,
2360 },
2361
2362 /*
2363 * P10 chip and variants
2364 */
2365 {
2366 .name = TYPE_PNV10_CHIP,
2367 .parent = TYPE_PNV_CHIP,
2368 .instance_init = pnv_chip_power10_instance_init,
2369 .instance_size = sizeof(Pnv10Chip),
2370 },
2371 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2372
2373 /*
2374 * P9 chip and variants
2375 */
2376 {
2377 .name = TYPE_PNV9_CHIP,
2378 .parent = TYPE_PNV_CHIP,
2379 .instance_init = pnv_chip_power9_instance_init,
2380 .instance_size = sizeof(Pnv9Chip),
2381 },
2382 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2383
2384 /*
2385 * P8 chip and variants
2386 */
2387 {
2388 .name = TYPE_PNV8_CHIP,
2389 .parent = TYPE_PNV_CHIP,
2390 .instance_init = pnv_chip_power8_instance_init,
2391 .instance_size = sizeof(Pnv8Chip),
2392 },
2393 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2394 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2395 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2396 pnv_chip_power8nvl_class_init),
2397 };
2398
2399 DEFINE_TYPES(types)
QEmu