2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX31 SOC emulation.
6 * Based on hw/arm/fsl-imx31.c
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "hw/arm/fsl-imx31.h"
23 #include "sysemu/sysemu.h"
24 #include "exec/address-spaces.h"
25 #include "hw/boards.h"
26 #include "sysemu/char.h"
28 static void fsl_imx31_init(Object
*obj
)
30 FslIMX31State
*s
= FSL_IMX31(obj
);
33 object_initialize(&s
->cpu
, sizeof(s
->cpu
), "arm1136-" TYPE_ARM_CPU
);
35 object_initialize(&s
->avic
, sizeof(s
->avic
), TYPE_IMX_AVIC
);
36 qdev_set_parent_bus(DEVICE(&s
->avic
), sysbus_get_default());
38 object_initialize(&s
->ccm
, sizeof(s
->ccm
), TYPE_IMX_CCM
);
39 qdev_set_parent_bus(DEVICE(&s
->ccm
), sysbus_get_default());
41 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
42 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_IMX_SERIAL
);
43 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
46 object_initialize(&s
->gpt
, sizeof(s
->gpt
), TYPE_IMX_GPT
);
47 qdev_set_parent_bus(DEVICE(&s
->gpt
), sysbus_get_default());
49 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
50 object_initialize(&s
->epit
[i
], sizeof(s
->epit
[i
]), TYPE_IMX_EPIT
);
51 qdev_set_parent_bus(DEVICE(&s
->epit
[i
]), sysbus_get_default());
54 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
55 object_initialize(&s
->i2c
[i
], sizeof(s
->i2c
[i
]), TYPE_IMX_I2C
);
56 qdev_set_parent_bus(DEVICE(&s
->i2c
[i
]), sysbus_get_default());
59 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
60 object_initialize(&s
->gpio
[i
], sizeof(s
->gpio
[i
]), TYPE_IMX_GPIO
);
61 qdev_set_parent_bus(DEVICE(&s
->gpio
[i
]), sysbus_get_default());
65 static void fsl_imx31_realize(DeviceState
*dev
, Error
**errp
)
67 FslIMX31State
*s
= FSL_IMX31(dev
);
71 object_property_set_bool(OBJECT(&s
->cpu
), true, "realized", &err
);
73 error_propagate(errp
, err
);
77 object_property_set_bool(OBJECT(&s
->avic
), true, "realized", &err
);
79 error_propagate(errp
, err
);
82 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->avic
), 0, FSL_IMX31_AVIC_ADDR
);
83 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 0,
84 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
85 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 1,
86 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
88 object_property_set_bool(OBJECT(&s
->ccm
), true, "realized", &err
);
90 error_propagate(errp
, err
);
93 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX31_CCM_ADDR
);
95 /* Initialize all UARTS */
96 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
100 } serial_table
[FSL_IMX31_NUM_UARTS
] = {
101 { FSL_IMX31_UART1_ADDR
, FSL_IMX31_UART1_IRQ
},
102 { FSL_IMX31_UART2_ADDR
, FSL_IMX31_UART2_IRQ
},
105 if (i
< MAX_SERIAL_PORTS
) {
106 CharDriverState
*chr
;
112 snprintf(label
, sizeof(label
), "imx31.uart%d", i
);
113 chr
= qemu_chr_new(label
, "null", NULL
);
116 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", chr
);
119 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
121 error_propagate(errp
, err
);
125 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, serial_table
[i
].addr
);
126 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
127 qdev_get_gpio_in(DEVICE(&s
->avic
),
128 serial_table
[i
].irq
));
131 s
->gpt
.ccm
= DEVICE(&s
->ccm
);
133 object_property_set_bool(OBJECT(&s
->gpt
), true, "realized", &err
);
135 error_propagate(errp
, err
);
139 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
), 0, FSL_IMX31_GPT_ADDR
);
140 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
), 0,
141 qdev_get_gpio_in(DEVICE(&s
->avic
), FSL_IMX31_GPT_IRQ
));
143 /* Initialize all EPIT timers */
144 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
145 static const struct {
148 } epit_table
[FSL_IMX31_NUM_EPITS
] = {
149 { FSL_IMX31_EPIT1_ADDR
, FSL_IMX31_EPIT1_IRQ
},
150 { FSL_IMX31_EPIT2_ADDR
, FSL_IMX31_EPIT2_IRQ
},
153 s
->epit
[i
].ccm
= DEVICE(&s
->ccm
);
155 object_property_set_bool(OBJECT(&s
->epit
[i
]), true, "realized", &err
);
157 error_propagate(errp
, err
);
161 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->epit
[i
]), 0, epit_table
[i
].addr
);
162 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
163 qdev_get_gpio_in(DEVICE(&s
->avic
),
167 /* Initialize all I2C */
168 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
169 static const struct {
172 } i2c_table
[FSL_IMX31_NUM_I2CS
] = {
173 { FSL_IMX31_I2C1_ADDR
, FSL_IMX31_I2C1_IRQ
},
174 { FSL_IMX31_I2C2_ADDR
, FSL_IMX31_I2C2_IRQ
},
175 { FSL_IMX31_I2C3_ADDR
, FSL_IMX31_I2C3_IRQ
}
178 /* Initialize the I2C */
179 object_property_set_bool(OBJECT(&s
->i2c
[i
]), true, "realized", &err
);
181 error_propagate(errp
, err
);
185 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, i2c_table
[i
].addr
);
186 /* Connect I2C IRQ to PIC */
187 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
188 qdev_get_gpio_in(DEVICE(&s
->avic
),
192 /* Initialize all GPIOs */
193 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
194 static const struct {
197 } gpio_table
[FSL_IMX31_NUM_GPIOS
] = {
198 { FSL_IMX31_GPIO1_ADDR
, FSL_IMX31_GPIO1_IRQ
},
199 { FSL_IMX31_GPIO2_ADDR
, FSL_IMX31_GPIO2_IRQ
},
200 { FSL_IMX31_GPIO3_ADDR
, FSL_IMX31_GPIO3_IRQ
}
203 object_property_set_bool(OBJECT(&s
->gpio
[i
]), false, "has-edge-sel",
205 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "realized", &err
);
207 error_propagate(errp
, err
);
210 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, gpio_table
[i
].addr
);
211 /* Connect GPIO IRQ to PIC */
212 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
213 qdev_get_gpio_in(DEVICE(&s
->avic
),
217 /* On a real system, the first 16k is a `secure boot rom' */
218 memory_region_init_rom_device(&s
->secure_rom
, NULL
, NULL
, NULL
,
220 FSL_IMX31_SECURE_ROM_SIZE
, &err
);
222 error_propagate(errp
, err
);
225 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR
,
228 /* There is also a 16k ROM */
229 memory_region_init_rom_device(&s
->rom
, NULL
, NULL
, NULL
, "imx31.rom",
230 FSL_IMX31_ROM_SIZE
, &err
);
232 error_propagate(errp
, err
);
235 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR
,
238 /* initialize internal RAM (16 KB) */
239 memory_region_init_ram(&s
->iram
, NULL
, "imx31.iram", FSL_IMX31_IRAM_SIZE
,
242 error_propagate(errp
, err
);
245 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR
,
247 vmstate_register_ram_global(&s
->iram
);
249 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
250 memory_region_init_alias(&s
->iram_alias
, NULL
, "imx31.iram_alias",
251 &s
->iram
, 0, FSL_IMX31_IRAM_ALIAS_SIZE
);
252 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR
,
256 static void fsl_imx31_class_init(ObjectClass
*oc
, void *data
)
258 DeviceClass
*dc
= DEVICE_CLASS(oc
);
260 dc
->realize
= fsl_imx31_realize
;
263 static const TypeInfo fsl_imx31_type_info
= {
264 .name
= TYPE_FSL_IMX31
,
265 .parent
= TYPE_DEVICE
,
266 .instance_size
= sizeof(FslIMX31State
),
267 .instance_init
= fsl_imx31_init
,
268 .class_init
= fsl_imx31_class_init
,
271 static void fsl_imx31_register_types(void)
273 type_register_static(&fsl_imx31_type_info
);
276 type_init(fsl_imx31_register_types
)