hw/intc/spapr_xive_kvm.c

   1 /*
   2  * QEMU PowerPC sPAPR XIVE interrupt controller model
   3  *
   4  * Copyright (c) 2017-2019, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/error-report.h"
  13 #include "qapi/error.h"
  14 #include "target/ppc/cpu.h"
  15 #include "sysemu/cpus.h"
  16 #include "sysemu/kvm.h"
  17 #include "hw/ppc/spapr.h"
  18 #include "hw/ppc/spapr_xive.h"
  19 #include "hw/ppc/xive.h"
  20 #include "kvm_ppc.h"
  21
  22 #include <sys/ioctl.h>
  23
  24 /*
  25  * Helpers for CPU hotplug
  26  *
  27  * TODO: make a common KVMEnabledCPU layer for XICS and XIVE
  28  */
  29 typedef struct KVMEnabledCPU {
  30     unsigned long vcpu_id;
  31     QLIST_ENTRY(KVMEnabledCPU) node;
  32 } KVMEnabledCPU;
  33
  34 static QLIST_HEAD(, KVMEnabledCPU)
  35     kvm_enabled_cpus = QLIST_HEAD_INITIALIZER(&kvm_enabled_cpus);
  36
  37 static bool kvm_cpu_is_enabled(CPUState *cs)
  38 {
  39     KVMEnabledCPU *enabled_cpu;
  40     unsigned long vcpu_id = kvm_arch_vcpu_id(cs);
  41
  42     QLIST_FOREACH(enabled_cpu, &kvm_enabled_cpus, node) {
  43         if (enabled_cpu->vcpu_id == vcpu_id) {
  44             return true;
  45         }
  46     }
  47     return false;
  48 }
  49
  50 static void kvm_cpu_enable(CPUState *cs)
  51 {
  52     KVMEnabledCPU *enabled_cpu;
  53     unsigned long vcpu_id = kvm_arch_vcpu_id(cs);
  54
  55     enabled_cpu = g_malloc(sizeof(*enabled_cpu));
  56     enabled_cpu->vcpu_id = vcpu_id;
  57     QLIST_INSERT_HEAD(&kvm_enabled_cpus, enabled_cpu, node);
  58 }
  59
  60 /*
  61  * XIVE Thread Interrupt Management context (KVM)
  62  */
  63
  64 void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
  65 {
  66     SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;
  67     unsigned long vcpu_id;
  68     int ret;
  69
  70     /* Check if CPU was hot unplugged and replugged. */
  71     if (kvm_cpu_is_enabled(tctx->cs)) {
  72         return;
  73     }
  74
  75     vcpu_id = kvm_arch_vcpu_id(tctx->cs);
  76
  77     ret = kvm_vcpu_enable_cap(tctx->cs, KVM_CAP_PPC_IRQ_XIVE, 0, xive->fd,
  78                               vcpu_id, 0);
  79     if (ret < 0) {
  80         error_setg(errp, "XIVE: unable to connect CPU%ld to KVM device: %s",
  81                    vcpu_id, strerror(errno));
  82         return;
  83     }
  84
  85     kvm_cpu_enable(tctx->cs);
  86 }
  87
  88 /*
  89  * XIVE Interrupt Source (KVM)
  90  */
  91
  92 void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,
  93                                    Error **errp)
  94 {
  95     uint32_t end_idx;
  96     uint32_t end_blk;
  97     uint8_t priority;
  98     uint32_t server;
  99     bool masked;
 100     uint32_t eisn;
 101     uint64_t kvm_src;
 102     Error *local_err = NULL;
 103
 104     assert(xive_eas_is_valid(eas));
 105
 106     end_idx = xive_get_field64(EAS_END_INDEX, eas->w);
 107     end_blk = xive_get_field64(EAS_END_BLOCK, eas->w);
 108     eisn = xive_get_field64(EAS_END_DATA, eas->w);
 109     masked = xive_eas_is_masked(eas);
 110
 111     spapr_xive_end_to_target(end_blk, end_idx, &server, &priority);
 112
 113     kvm_src = priority << KVM_XIVE_SOURCE_PRIORITY_SHIFT &
 114         KVM_XIVE_SOURCE_PRIORITY_MASK;
 115     kvm_src |= server << KVM_XIVE_SOURCE_SERVER_SHIFT &
 116         KVM_XIVE_SOURCE_SERVER_MASK;
 117     kvm_src |= ((uint64_t) masked << KVM_XIVE_SOURCE_MASKED_SHIFT) &
 118         KVM_XIVE_SOURCE_MASKED_MASK;
 119     kvm_src |= ((uint64_t)eisn << KVM_XIVE_SOURCE_EISN_SHIFT) &
 120         KVM_XIVE_SOURCE_EISN_MASK;
 121
 122     kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_SOURCE_CONFIG, lisn,
 123                       &kvm_src, true, &local_err);
 124     if (local_err) {
 125         error_propagate(errp, local_err);
 126         return;
 127     }
 128 }
 129
 130 void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp)
 131 {
 132     kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_SOURCE_SYNC, lisn,
 133                       NULL, true, errp);
 134 }
 135
 136 /*
 137  * At reset, the interrupt sources are simply created and MASKED. We
 138  * only need to inform the KVM XIVE device about their type: LSI or
 139  * MSI.
 140  */
 141 void kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp)
 142 {
 143     SpaprXive *xive = SPAPR_XIVE(xsrc->xive);
 144     uint64_t state = 0;
 145
 146     if (xive_source_irq_is_lsi(xsrc, srcno)) {
 147         state |= KVM_XIVE_LEVEL_SENSITIVE;
 148         if (xsrc->status[srcno] & XIVE_STATUS_ASSERTED) {
 149             state |= KVM_XIVE_LEVEL_ASSERTED;
 150         }
 151     }
 152
 153     kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_SOURCE, srcno, &state,
 154                       true, errp);
 155 }
 156
 157 void kvmppc_xive_source_reset(XiveSource *xsrc, Error **errp)
 158 {
 159     int i;
 160
 161     for (i = 0; i < xsrc->nr_irqs; i++) {
 162         Error *local_err = NULL;
 163
 164         kvmppc_xive_source_reset_one(xsrc, i, &local_err);
 165         if (local_err) {
 166             error_propagate(errp, local_err);
 167             return;
 168         }
 169     }
 170 }
 171
 172 /*
 173  * This is used to perform the magic loads on the ESB pages, described
 174  * in xive.h.
 175  *
 176  * Memory barriers should not be needed for loads (no store for now).
 177  */
 178 static uint64_t xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,
 179                             uint64_t data, bool write)
 180 {
 181     uint64_t *addr = xsrc->esb_mmap + xive_source_esb_mgmt(xsrc, srcno) +
 182         offset;
 183
 184     if (write) {
 185         *addr = cpu_to_be64(data);
 186         return -1;
 187     } else {
 188         /* Prevent the compiler from optimizing away the load */
 189         volatile uint64_t value = be64_to_cpu(*addr);
 190         return value;
 191     }
 192 }
 193
 194 static uint8_t xive_esb_read(XiveSource *xsrc, int srcno, uint32_t offset)
 195 {
 196     return xive_esb_rw(xsrc, srcno, offset, 0, 0) & 0x3;
 197 }
 198
 199 static void xive_esb_trigger(XiveSource *xsrc, int srcno)
 200 {
 201     uint64_t *addr = xsrc->esb_mmap + xive_source_esb_page(xsrc, srcno);
 202
 203     *addr = 0x0;
 204 }
 205
 206 uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,
 207                             uint64_t data, bool write)
 208 {
 209     if (write) {
 210         return xive_esb_rw(xsrc, srcno, offset, data, 1);
 211     }
 212
 213     /*
 214      * Special Load EOI handling for LSI sources. Q bit is never set
 215      * and the interrupt should be re-triggered if the level is still
 216      * asserted.
 217      */
 218     if (xive_source_irq_is_lsi(xsrc, srcno) &&
 219         offset == XIVE_ESB_LOAD_EOI) {
 220         xive_esb_read(xsrc, srcno, XIVE_ESB_SET_PQ_00);
 221         if (xsrc->status[srcno] & XIVE_STATUS_ASSERTED) {
 222             xive_esb_trigger(xsrc, srcno);
 223         }
 224         return 0;
 225     } else {
 226         return xive_esb_rw(xsrc, srcno, offset, 0, 0);
 227     }
 228 }
 229
 230 void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val)
 231 {
 232     XiveSource *xsrc = opaque;
 233     struct kvm_irq_level args;
 234     int rc;
 235
 236     args.irq = srcno;
 237     if (!xive_source_irq_is_lsi(xsrc, srcno)) {
 238         if (!val) {
 239             return;
 240         }
 241         args.level = KVM_INTERRUPT_SET;
 242     } else {
 243         if (val) {
 244             xsrc->status[srcno] |= XIVE_STATUS_ASSERTED;
 245             args.level = KVM_INTERRUPT_SET_LEVEL;
 246         } else {
 247             xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED;
 248             args.level = KVM_INTERRUPT_UNSET;
 249         }
 250     }
 251     rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args);
 252     if (rc < 0) {
 253         error_report("XIVE: kvm_irq_line() failed : %s", strerror(errno));
 254     }
 255 }
 256
 257 /*
 258  * sPAPR XIVE interrupt controller (KVM)
 259  */
 260 void kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk,
 261                                   uint32_t end_idx, XiveEND *end,
 262                                   Error **errp)
 263 {
 264     struct kvm_ppc_xive_eq kvm_eq = { 0 };
 265     uint64_t kvm_eq_idx;
 266     uint8_t priority;
 267     uint32_t server;
 268     Error *local_err = NULL;
 269
 270     assert(xive_end_is_valid(end));
 271
 272     /* Encode the tuple (server, prio) as a KVM EQ index */
 273     spapr_xive_end_to_target(end_blk, end_idx, &server, &priority);
 274
 275     kvm_eq_idx = priority << KVM_XIVE_EQ_PRIORITY_SHIFT &
 276             KVM_XIVE_EQ_PRIORITY_MASK;
 277     kvm_eq_idx |= server << KVM_XIVE_EQ_SERVER_SHIFT &
 278         KVM_XIVE_EQ_SERVER_MASK;
 279
 280     kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_EQ_CONFIG, kvm_eq_idx,
 281                       &kvm_eq, false, &local_err);
 282     if (local_err) {
 283         error_propagate(errp, local_err);
 284         return;
 285     }
 286
 287     /*
 288      * The EQ index and toggle bit are updated by HW. These are the
 289      * only fields from KVM we want to update QEMU with. The other END
 290      * fields should already be in the QEMU END table.
 291      */
 292     end->w1 = xive_set_field32(END_W1_GENERATION, 0ul, kvm_eq.qtoggle) |
 293         xive_set_field32(END_W1_PAGE_OFF, 0ul, kvm_eq.qindex);
 294 }
 295
 296 void kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk,
 297                                   uint32_t end_idx, XiveEND *end,
 298                                   Error **errp)
 299 {
 300     struct kvm_ppc_xive_eq kvm_eq = { 0 };
 301     uint64_t kvm_eq_idx;
 302     uint8_t priority;
 303     uint32_t server;
 304     Error *local_err = NULL;
 305
 306     /*
 307      * Build the KVM state from the local END structure.
 308      */
 309
 310     kvm_eq.flags = 0;
 311     if (xive_get_field32(END_W0_UCOND_NOTIFY, end->w0)) {
 312         kvm_eq.flags |= KVM_XIVE_EQ_ALWAYS_NOTIFY;
 313     }
 314
 315     /*
 316      * If the hcall is disabling the EQ, set the size and page address
 317      * to zero. When migrating, only valid ENDs are taken into
 318      * account.
 319      */
 320     if (xive_end_is_valid(end)) {
 321         kvm_eq.qshift = xive_get_field32(END_W0_QSIZE, end->w0) + 12;
 322         kvm_eq.qaddr  = xive_end_qaddr(end);
 323         /*
 324          * The EQ toggle bit and index should only be relevant when
 325          * restoring the EQ state
 326          */
 327         kvm_eq.qtoggle = xive_get_field32(END_W1_GENERATION, end->w1);
 328         kvm_eq.qindex  = xive_get_field32(END_W1_PAGE_OFF, end->w1);
 329     } else {
 330         kvm_eq.qshift = 0;
 331         kvm_eq.qaddr  = 0;
 332     }
 333
 334     /* Encode the tuple (server, prio) as a KVM EQ index */
 335     spapr_xive_end_to_target(end_blk, end_idx, &server, &priority);
 336
 337     kvm_eq_idx = priority << KVM_XIVE_EQ_PRIORITY_SHIFT &
 338             KVM_XIVE_EQ_PRIORITY_MASK;
 339     kvm_eq_idx |= server << KVM_XIVE_EQ_SERVER_SHIFT &
 340         KVM_XIVE_EQ_SERVER_MASK;
 341
 342     kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_EQ_CONFIG, kvm_eq_idx,
 343                       &kvm_eq, true, &local_err);
 344     if (local_err) {
 345         error_propagate(errp, local_err);
 346         return;
 347     }
 348 }
 349
 350 void kvmppc_xive_reset(SpaprXive *xive, Error **errp)
 351 {
 352     kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_CTRL, KVM_DEV_XIVE_RESET,
 353                       NULL, true, errp);
 354 }
 355
 356 static void *kvmppc_xive_mmap(SpaprXive *xive, int pgoff, size_t len,
 357                               Error **errp)
 358 {
 359     void *addr;
 360     uint32_t page_shift = 16; /* TODO: fix page_shift */
 361
 362     addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, xive->fd,
 363                 pgoff << page_shift);
 364     if (addr == MAP_FAILED) {
 365         error_setg_errno(errp, errno, "XIVE: unable to set memory mapping");
 366         return NULL;
 367     }
 368
 369     return addr;
 370 }
 371
 372 /*
 373  * All the XIVE memory regions are now backed by mappings from the KVM
 374  * XIVE device.
 375  */
 376 void kvmppc_xive_connect(SpaprXive *xive, Error **errp)
 377 {
 378     XiveSource *xsrc = &xive->source;
 379     XiveENDSource *end_xsrc = &xive->end_source;
 380     Error *local_err = NULL;
 381     size_t esb_len = (1ull << xsrc->esb_shift) * xsrc->nr_irqs;
 382     size_t tima_len = 4ull << TM_SHIFT;
 383
 384     if (!kvmppc_has_cap_xive()) {
 385         error_setg(errp, "IRQ_XIVE capability must be present for KVM");
 386         return;
 387     }
 388
 389     /* First, create the KVM XIVE device */
 390     xive->fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_XIVE, false);
 391     if (xive->fd < 0) {
 392         error_setg_errno(errp, -xive->fd, "XIVE: error creating KVM device");
 393         return;
 394     }
 395
 396     /*
 397      * 1. Source ESB pages - KVM mapping
 398      */
 399     xsrc->esb_mmap = kvmppc_xive_mmap(xive, KVM_XIVE_ESB_PAGE_OFFSET, esb_len,
 400                                       &local_err);
 401     if (local_err) {
 402         error_propagate(errp, local_err);
 403         return;
 404     }
 405
 406     memory_region_init_ram_device_ptr(&xsrc->esb_mmio, OBJECT(xsrc),
 407                                       "xive.esb", esb_len, xsrc->esb_mmap);
 408     sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio);
 409
 410     /*
 411      * 2. END ESB pages (No KVM support yet)
 412      */
 413     sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio);
 414
 415     /*
 416      * 3. TIMA pages - KVM mapping
 417      */
 418     xive->tm_mmap = kvmppc_xive_mmap(xive, KVM_XIVE_TIMA_PAGE_OFFSET, tima_len,
 419                                      &local_err);
 420     if (local_err) {
 421         error_propagate(errp, local_err);
 422         return;
 423     }
 424     memory_region_init_ram_device_ptr(&xive->tm_mmio, OBJECT(xive),
 425                                       "xive.tima", tima_len, xive->tm_mmap);
 426     sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio);
 427
 428     kvm_kernel_irqchip = true;
 429     kvm_msi_via_irqfd_allowed = true;
 430     kvm_gsi_direct_mapping = true;
 431
 432     /* Map all regions */
 433     spapr_xive_map_mmio(xive);
 434 }