target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010-2014 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "sysemu/sysemu.h"
  23 #include "exec/semihost.h"
  24
  25 int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  26                               int mmu_idx)
  27 {
  28     LM32CPU *cpu = LM32_CPU(cs);
  29     CPULM32State *env = &cpu->env;
  30     int prot;
  31
  32     address &= TARGET_PAGE_MASK;
  33     prot = PAGE_BITS;
  34     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  35         tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
  36                      TARGET_PAGE_SIZE);
  37     } else {
  38         tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  39     }
  40
  41     return 0;
  42 }
  43
  44 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
  45 {
  46     LM32CPU *cpu = LM32_CPU(cs);
  47
  48     addr &= TARGET_PAGE_MASK;
  49     if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
  50         return addr & 0x7fffffff;
  51     } else {
  52         return addr;
  53     }
  54 }
  55
  56 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
  57 {
  58     LM32CPU *cpu = lm32_env_get_cpu(env);
  59
  60     cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
  61                           &env->cpu_breakpoint[idx]);
  62 }
  63
  64 void lm32_breakpoint_remove(CPULM32State *env, int idx)
  65 {
  66     LM32CPU *cpu = lm32_env_get_cpu(env);
  67
  68     if (!env->cpu_breakpoint[idx]) {
  69         return;
  70     }
  71
  72     cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
  73     env->cpu_breakpoint[idx] = NULL;
  74 }
  75
  76 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
  77                             lm32_wp_t wp_type)
  78 {
  79     LM32CPU *cpu = lm32_env_get_cpu(env);
  80     int flags = 0;
  81
  82     switch (wp_type) {
  83     case LM32_WP_DISABLED:
  84         /* nothing to to */
  85         break;
  86     case LM32_WP_READ:
  87         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
  88         break;
  89     case LM32_WP_WRITE:
  90         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
  91         break;
  92     case LM32_WP_READ_WRITE:
  93         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
  94         break;
  95     }
  96
  97     if (flags != 0) {
  98         cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
  99                 &env->cpu_watchpoint[idx]);
 100     }
 101 }
 102
 103 void lm32_watchpoint_remove(CPULM32State *env, int idx)
 104 {
 105     LM32CPU *cpu = lm32_env_get_cpu(env);
 106
 107     if (!env->cpu_watchpoint[idx]) {
 108         return;
 109     }
 110
 111     cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
 112     env->cpu_watchpoint[idx] = NULL;
 113 }
 114
 115 static bool check_watchpoints(CPULM32State *env)
 116 {
 117     LM32CPU *cpu = lm32_env_get_cpu(env);
 118     int i;
 119
 120     for (i = 0; i < cpu->num_watchpoints; i++) {
 121         if (env->cpu_watchpoint[i] &&
 122                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
 123             return true;
 124         }
 125     }
 126     return false;
 127 }
 128
 129 void lm32_debug_excp_handler(CPUState *cs)
 130 {
 131     LM32CPU *cpu = LM32_CPU(cs);
 132     CPULM32State *env = &cpu->env;
 133     CPUBreakpoint *bp;
 134
 135     if (cs->watchpoint_hit) {
 136         if (cs->watchpoint_hit->flags & BP_CPU) {
 137             cs->watchpoint_hit = NULL;
 138             if (check_watchpoints(env)) {
 139                 raise_exception(env, EXCP_WATCHPOINT);
 140             } else {
 141                 cpu_resume_from_signal(cs, NULL);
 142             }
 143         }
 144     } else {
 145         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 146             if (bp->pc == env->pc) {
 147                 if (bp->flags & BP_CPU) {
 148                     raise_exception(env, EXCP_BREAKPOINT);
 149                 }
 150                 break;
 151             }
 152         }
 153     }
 154 }
 155
 156 void lm32_cpu_do_interrupt(CPUState *cs)
 157 {
 158     LM32CPU *cpu = LM32_CPU(cs);
 159     CPULM32State *env = &cpu->env;
 160
 161     qemu_log_mask(CPU_LOG_INT,
 162             "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
 163
 164     switch (cs->exception_index) {
 165     case EXCP_SYSTEMCALL:
 166         if (unlikely(semihosting_enabled())) {
 167             /* do_semicall() returns true if call was handled. Otherwise
 168              * do the normal exception handling. */
 169             if (lm32_cpu_do_semihosting(cs)) {
 170                 env->pc += 4;
 171                 break;
 172             }
 173         }
 174         /* fall through */
 175     case EXCP_INSN_BUS_ERROR:
 176     case EXCP_DATA_BUS_ERROR:
 177     case EXCP_DIVIDE_BY_ZERO:
 178     case EXCP_IRQ:
 179         /* non-debug exceptions */
 180         env->regs[R_EA] = env->pc;
 181         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
 182         env->ie &= ~IE_IE;
 183         if (env->dc & DC_RE) {
 184             env->pc = env->deba + (cs->exception_index * 32);
 185         } else {
 186             env->pc = env->eba + (cs->exception_index * 32);
 187         }
 188         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 189         break;
 190     case EXCP_BREAKPOINT:
 191     case EXCP_WATCHPOINT:
 192         /* debug exceptions */
 193         env->regs[R_BA] = env->pc;
 194         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
 195         env->ie &= ~IE_IE;
 196         env->pc = env->deba + (cs->exception_index * 32);
 197         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 198         break;
 199     default:
 200         cpu_abort(cs, "unhandled exception type=%d\n",
 201                   cs->exception_index);
 202         break;
 203     }
 204 }
 205
 206 bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 207 {
 208     LM32CPU *cpu = LM32_CPU(cs);
 209     CPULM32State *env = &cpu->env;
 210
 211     if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) {
 212         cs->exception_index = EXCP_IRQ;
 213         lm32_cpu_do_interrupt(cs);
 214         return true;
 215     }
 216     return false;
 217 }
 218
 219 LM32CPU *cpu_lm32_init(const char *cpu_model)
 220 {
 221     return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
 222 }
 223
 224 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 225  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 226  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 227 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
 228 {
 229     if (value) {
 230         env->flags |= LM32_FLAG_IGNORE_MSB;
 231     } else {
 232         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 233     }
 234 }