target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #include "config.h"
  23
  24 #include "kvm-consts.h"
  25
  26 #if defined(TARGET_AARCH64)
  27   /* AArch64 definitions */
  28 #  define TARGET_LONG_BITS 64
  29 #  define ELF_MACHINE EM_AARCH64
  30 #else
  31 #  define TARGET_LONG_BITS 32
  32 #  define ELF_MACHINE EM_ARM
  33 #endif
  34
  35 #define CPUArchState struct CPUARMState
  36
  37 #include "qemu-common.h"
  38 #include "exec/cpu-defs.h"
  39
  40 #include "fpu/softfloat.h"
  41
  42 #define TARGET_HAS_ICE 1
  43
  44 #define EXCP_UDEF            1   /* undefined instruction */
  45 #define EXCP_SWI             2   /* software interrupt */
  46 #define EXCP_PREFETCH_ABORT  3
  47 #define EXCP_DATA_ABORT      4
  48 #define EXCP_IRQ             5
  49 #define EXCP_FIQ             6
  50 #define EXCP_BKPT            7
  51 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  52 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  53 #define EXCP_STREX          10
  54
  55 #define ARMV7M_EXCP_RESET   1
  56 #define ARMV7M_EXCP_NMI     2
  57 #define ARMV7M_EXCP_HARD    3
  58 #define ARMV7M_EXCP_MEM     4
  59 #define ARMV7M_EXCP_BUS     5
  60 #define ARMV7M_EXCP_USAGE   6
  61 #define ARMV7M_EXCP_SVC     11
  62 #define ARMV7M_EXCP_DEBUG   12
  63 #define ARMV7M_EXCP_PENDSV  14
  64 #define ARMV7M_EXCP_SYSTICK 15
  65
  66 /* ARM-specific interrupt pending bits.  */
  67 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  68
  69 /* Meanings of the ARMCPU object's two inbound GPIO lines */
  70 #define ARM_CPU_IRQ 0
  71 #define ARM_CPU_FIQ 1
  72
  73 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  74                             int srcreg, int operand, uint32_t value);
  75 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  76                                int dstreg, int operand);
  77
  78 struct arm_boot_info;
  79
  80 #define NB_MMU_MODES 2
  81
  82 /* We currently assume float and double are IEEE single and double
  83    precision respectively.
  84    Doing runtime conversions is tricky because VFP registers may contain
  85    integer values (eg. as the result of a FTOSI instruction).
  86    s<2n> maps to the least significant half of d<n>
  87    s<2n+1> maps to the most significant half of d<n>
  88  */
  89
  90 /* CPU state for each instance of a generic timer (in cp15 c14) */
  91 typedef struct ARMGenericTimer {
  92     uint64_t cval; /* Timer CompareValue register */
  93     uint32_t ctl; /* Timer Control register */
  94 } ARMGenericTimer;
  95
  96 #define GTIMER_PHYS 0
  97 #define GTIMER_VIRT 1
  98 #define NUM_GTIMERS 2
  99
 100 /* Scale factor for generic timers, ie number of ns per tick.
 101  * This gives a 62.5MHz timer.
 102  */
 103 #define GTIMER_SCALE 16
 104
 105 typedef struct CPUARMState {
 106     /* Regs for current mode.  */
 107     uint32_t regs[16];
 108
 109     /* 32/64 switch only happens when taking and returning from
 110      * exceptions so the overlap semantics are taken care of then
 111      * instead of having a complicated union.
 112      */
 113     /* Regs for A64 mode.  */
 114     uint64_t xregs[32];
 115     uint64_t pc;
 116     /* PSTATE isn't an architectural register for ARMv8. However, it is
 117      * convenient for us to assemble the underlying state into a 32 bit format
 118      * identical to the architectural format used for the SPSR. (This is also
 119      * what the Linux kernel's 'pstate' field in signal handlers and KVM's
 120      * 'pstate' register are.) Of the PSTATE bits:
 121      *  NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
 122      *    semantics as for AArch32, as described in the comments on each field)
 123      *  nRW (also known as M[4]) is kept, inverted, in env->aarch64
 124      *  all other bits are stored in their correct places in env->pstate
 125      */
 126     uint32_t pstate;
 127     uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
 128
 129     /* Frequently accessed CPSR bits are stored separately for efficiency.
 130        This contains all the other bits.  Use cpsr_{read,write} to access
 131        the whole CPSR.  */
 132     uint32_t uncached_cpsr;
 133     uint32_t spsr;
 134
 135     /* Banked registers.  */
 136     uint32_t banked_spsr[6];
 137     uint32_t banked_r13[6];
 138     uint32_t banked_r14[6];
 139
 140     /* These hold r8-r12.  */
 141     uint32_t usr_regs[5];
 142     uint32_t fiq_regs[5];
 143
 144     /* cpsr flag cache for faster execution */
 145     uint32_t CF; /* 0 or 1 */
 146     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 147     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 148     uint32_t ZF; /* Z set if zero.  */
 149     uint32_t QF; /* 0 or 1 */
 150     uint32_t GE; /* cpsr[19:16] */
 151     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 152     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 153
 154     /* System control coprocessor (cp15) */
 155     struct {
 156         uint32_t c0_cpuid;
 157         uint32_t c0_cssel; /* Cache size selection.  */
 158         uint32_t c1_sys; /* System control register.  */
 159         uint32_t c1_coproc; /* Coprocessor access register.  */
 160         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 161         uint32_t c1_scr; /* secure config register.  */
 162         uint32_t c2_base0; /* MMU translation table base 0.  */
 163         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 164         uint32_t c2_base1; /* MMU translation table base 0.  */
 165         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 166         uint32_t c2_control; /* MMU translation table base control.  */
 167         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 168         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 169         uint32_t c2_data; /* MPU data cachable bits.  */
 170         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 171         uint32_t c3; /* MMU domain access control register
 172                         MPU write buffer control.  */
 173         uint32_t c5_insn; /* Fault status registers.  */
 174         uint32_t c5_data;
 175         uint32_t c6_region[8]; /* MPU base/size registers.  */
 176         uint32_t c6_insn; /* Fault address registers.  */
 177         uint32_t c6_data;
 178         uint32_t c7_par;  /* Translation result. */
 179         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 180         uint32_t c9_insn; /* Cache lockdown registers.  */
 181         uint32_t c9_data;
 182         uint32_t c9_pmcr; /* performance monitor control register */
 183         uint32_t c9_pmcnten; /* perf monitor counter enables */
 184         uint32_t c9_pmovsr; /* perf monitor overflow status */
 185         uint32_t c9_pmxevtyper; /* perf monitor event type */
 186         uint32_t c9_pmuserenr; /* perf monitor user enable */
 187         uint32_t c9_pminten; /* perf monitor interrupt enables */
 188         uint32_t c12_vbar; /* vector base address register */
 189         uint32_t c13_fcse; /* FCSE PID.  */
 190         uint32_t c13_context; /* Context ID.  */
 191         uint32_t c13_tls1; /* User RW Thread register.  */
 192         uint32_t c13_tls2; /* User RO Thread register.  */
 193         uint32_t c13_tls3; /* Privileged Thread register.  */
 194         uint32_t c14_cntfrq; /* Counter Frequency register */
 195         uint32_t c14_cntkctl; /* Timer Control register */
 196         ARMGenericTimer c14_timer[NUM_GTIMERS];
 197         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 198         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 199         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 200         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 201         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 202         uint32_t c15_config_base_address; /* SCU base address.  */
 203         uint32_t c15_diagnostic; /* diagnostic register */
 204         uint32_t c15_power_diagnostic;
 205         uint32_t c15_power_control; /* power control */
 206     } cp15;
 207
 208     /* System registers (AArch64) */
 209     struct {
 210         uint64_t tpidr_el0;
 211     } sr;
 212
 213     struct {
 214         uint32_t other_sp;
 215         uint32_t vecbase;
 216         uint32_t basepri;
 217         uint32_t control;
 218         int current_sp;
 219         int exception;
 220         int pending_exception;
 221     } v7m;
 222
 223     /* Thumb-2 EE state.  */
 224     uint32_t teecr;
 225     uint32_t teehbr;
 226
 227     /* VFP coprocessor state.  */
 228     struct {
 229         /* VFP/Neon register state. Note that the mapping between S, D and Q
 230          * views of the register bank differs between AArch64 and AArch32:
 231          * In AArch32:
 232          *  Qn = regs[2n+1]:regs[2n]
 233          *  Dn = regs[n]
 234          *  Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
 235          * (and regs[32] to regs[63] are inaccessible)
 236          * In AArch64:
 237          *  Qn = regs[2n+1]:regs[2n]
 238          *  Dn = regs[2n]
 239          *  Sn = regs[2n] bits 31..0
 240          * This corresponds to the architecturally defined mapping between
 241          * the two execution states, and means we do not need to explicitly
 242          * map these registers when changing states.
 243          */
 244         float64 regs[64];
 245
 246         uint32_t xregs[16];
 247         /* We store these fpcsr fields separately for convenience.  */
 248         int vec_len;
 249         int vec_stride;
 250
 251         /* scratch space when Tn are not sufficient.  */
 252         uint32_t scratch[8];
 253
 254         /* fp_status is the "normal" fp status. standard_fp_status retains
 255          * values corresponding to the ARM "Standard FPSCR Value", ie
 256          * default-NaN, flush-to-zero, round-to-nearest and is used by
 257          * any operations (generally Neon) which the architecture defines
 258          * as controlled by the standard FPSCR value rather than the FPSCR.
 259          *
 260          * To avoid having to transfer exception bits around, we simply
 261          * say that the FPSCR cumulative exception flags are the logical
 262          * OR of the flags in the two fp statuses. This relies on the
 263          * only thing which needs to read the exception flags being
 264          * an explicit FPSCR read.
 265          */
 266         float_status fp_status;
 267         float_status standard_fp_status;
 268     } vfp;
 269     uint32_t exclusive_addr;
 270     uint32_t exclusive_val;
 271     uint32_t exclusive_high;
 272 #if defined(CONFIG_USER_ONLY)
 273     uint32_t exclusive_test;
 274     uint32_t exclusive_info;
 275 #endif
 276
 277     /* iwMMXt coprocessor state.  */
 278     struct {
 279         uint64_t regs[16];
 280         uint64_t val;
 281
 282         uint32_t cregs[16];
 283     } iwmmxt;
 284
 285     /* For mixed endian mode.  */
 286     bool bswap_code;
 287
 288 #if defined(CONFIG_USER_ONLY)
 289     /* For usermode syscall translation.  */
 290     int eabi;
 291 #endif
 292
 293     CPU_COMMON
 294
 295     /* These fields after the common ones so they are preserved on reset.  */
 296
 297     /* Internal CPU feature flags.  */
 298     uint64_t features;
 299
 300     void *nvic;
 301     const struct arm_boot_info *boot_info;
 302 } CPUARMState;
 303
 304 #include "cpu-qom.h"
 305
 306 ARMCPU *cpu_arm_init(const char *cpu_model);
 307 void arm_translate_init(void);
 308 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 309 int cpu_arm_exec(CPUARMState *s);
 310 int bank_number(int mode);
 311 void switch_mode(CPUARMState *, int);
 312 uint32_t do_arm_semihosting(CPUARMState *env);
 313
 314 static inline bool is_a64(CPUARMState *env)
 315 {
 316     return env->aarch64;
 317 }
 318
 319 /* you can call this signal handler from your SIGBUS and SIGSEGV
 320    signal handlers to inform the virtual CPU of exceptions. non zero
 321    is returned if the signal was handled by the virtual CPU.  */
 322 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 323                            void *puc);
 324 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 325                               int mmu_idx);
 326 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 327
 328 #define CPSR_M (0x1fU)
 329 #define CPSR_T (1U << 5)
 330 #define CPSR_F (1U << 6)
 331 #define CPSR_I (1U << 7)
 332 #define CPSR_A (1U << 8)
 333 #define CPSR_E (1U << 9)
 334 #define CPSR_IT_2_7 (0xfc00U)
 335 #define CPSR_GE (0xfU << 16)
 336 #define CPSR_RESERVED (0xfU << 20)
 337 #define CPSR_J (1U << 24)
 338 #define CPSR_IT_0_1 (3U << 25)
 339 #define CPSR_Q (1U << 27)
 340 #define CPSR_V (1U << 28)
 341 #define CPSR_C (1U << 29)
 342 #define CPSR_Z (1U << 30)
 343 #define CPSR_N (1U << 31)
 344 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 345
 346 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 347 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 348 /* Bits writable in user mode.  */
 349 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 350 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 351 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 352
 353 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
 354  * Only these are valid when in AArch64 mode; in
 355  * AArch32 mode SPSRs are basically CPSR-format.
 356  */
 357 #define PSTATE_M (0xFU)
 358 #define PSTATE_nRW (1U << 4)
 359 #define PSTATE_F (1U << 6)
 360 #define PSTATE_I (1U << 7)
 361 #define PSTATE_A (1U << 8)
 362 #define PSTATE_D (1U << 9)
 363 #define PSTATE_IL (1U << 20)
 364 #define PSTATE_SS (1U << 21)
 365 #define PSTATE_V (1U << 28)
 366 #define PSTATE_C (1U << 29)
 367 #define PSTATE_Z (1U << 30)
 368 #define PSTATE_N (1U << 31)
 369 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
 370 #define CACHED_PSTATE_BITS (PSTATE_NZCV)
 371 /* Mode values for AArch64 */
 372 #define PSTATE_MODE_EL3h 13
 373 #define PSTATE_MODE_EL3t 12
 374 #define PSTATE_MODE_EL2h 9
 375 #define PSTATE_MODE_EL2t 8
 376 #define PSTATE_MODE_EL1h 5
 377 #define PSTATE_MODE_EL1t 4
 378 #define PSTATE_MODE_EL0t 0
 379
 380 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
 381  * interprocessing, so we don't attempt to sync with the cpsr state used by
 382  * the 32 bit decoder.
 383  */
 384 static inline uint32_t pstate_read(CPUARMState *env)
 385 {
 386     int ZF;
 387
 388     ZF = (env->ZF == 0);
 389     return (env->NF & 0x80000000) | (ZF << 30)
 390         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
 391         | env->pstate;
 392 }
 393
 394 static inline void pstate_write(CPUARMState *env, uint32_t val)
 395 {
 396     env->ZF = (~val) & PSTATE_Z;
 397     env->NF = val;
 398     env->CF = (val >> 29) & 1;
 399     env->VF = (val << 3) & 0x80000000;
 400     env->pstate = val & ~CACHED_PSTATE_BITS;
 401 }
 402
 403 /* Return the current CPSR value.  */
 404 uint32_t cpsr_read(CPUARMState *env);
 405 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 406 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 407
 408 /* Return the current xPSR value.  */
 409 static inline uint32_t xpsr_read(CPUARMState *env)
 410 {
 411     int ZF;
 412     ZF = (env->ZF == 0);
 413     return (env->NF & 0x80000000) | (ZF << 30)
 414         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 415         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 416         | ((env->condexec_bits & 0xfc) << 8)
 417         | env->v7m.exception;
 418 }
 419
 420 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 421 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 422 {
 423     if (mask & CPSR_NZCV) {
 424         env->ZF = (~val) & CPSR_Z;
 425         env->NF = val;
 426         env->CF = (val >> 29) & 1;
 427         env->VF = (val << 3) & 0x80000000;
 428     }
 429     if (mask & CPSR_Q)
 430         env->QF = ((val & CPSR_Q) != 0);
 431     if (mask & (1 << 24))
 432         env->thumb = ((val & (1 << 24)) != 0);
 433     if (mask & CPSR_IT_0_1) {
 434         env->condexec_bits &= ~3;
 435         env->condexec_bits |= (val >> 25) & 3;
 436     }
 437     if (mask & CPSR_IT_2_7) {
 438         env->condexec_bits &= 3;
 439         env->condexec_bits |= (val >> 8) & 0xfc;
 440     }
 441     if (mask & 0x1ff) {
 442         env->v7m.exception = val & 0x1ff;
 443     }
 444 }
 445
 446 /* Return the current FPSCR value.  */
 447 uint32_t vfp_get_fpscr(CPUARMState *env);
 448 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 449
 450 /* For A64 the FPSCR is split into two logically distinct registers,
 451  * FPCR and FPSR. However since they still use non-overlapping bits
 452  * we store the underlying state in fpscr and just mask on read/write.
 453  */
 454 #define FPSR_MASK 0xf800009f
 455 #define FPCR_MASK 0x07f79f00
 456 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
 457 {
 458     return vfp_get_fpscr(env) & FPSR_MASK;
 459 }
 460
 461 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
 462 {
 463     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
 464     vfp_set_fpscr(env, new_fpscr);
 465 }
 466
 467 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
 468 {
 469     return vfp_get_fpscr(env) & FPCR_MASK;
 470 }
 471
 472 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
 473 {
 474     uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
 475     vfp_set_fpscr(env, new_fpscr);
 476 }
 477
 478 enum arm_cpu_mode {
 479   ARM_CPU_MODE_USR = 0x10,
 480   ARM_CPU_MODE_FIQ = 0x11,
 481   ARM_CPU_MODE_IRQ = 0x12,
 482   ARM_CPU_MODE_SVC = 0x13,
 483   ARM_CPU_MODE_ABT = 0x17,
 484   ARM_CPU_MODE_UND = 0x1b,
 485   ARM_CPU_MODE_SYS = 0x1f
 486 };
 487
 488 /* VFP system registers.  */
 489 #define ARM_VFP_FPSID   0
 490 #define ARM_VFP_FPSCR   1
 491 #define ARM_VFP_MVFR1   6
 492 #define ARM_VFP_MVFR0   7
 493 #define ARM_VFP_FPEXC   8
 494 #define ARM_VFP_FPINST  9
 495 #define ARM_VFP_FPINST2 10
 496
 497 /* iwMMXt coprocessor control registers.  */
 498 #define ARM_IWMMXT_wCID         0
 499 #define ARM_IWMMXT_wCon         1
 500 #define ARM_IWMMXT_wCSSF        2
 501 #define ARM_IWMMXT_wCASF        3
 502 #define ARM_IWMMXT_wCGR0        8
 503 #define ARM_IWMMXT_wCGR1        9
 504 #define ARM_IWMMXT_wCGR2        10
 505 #define ARM_IWMMXT_wCGR3        11
 506
 507 /* If adding a feature bit which corresponds to a Linux ELF
 508  * HWCAP bit, remember to update the feature-bit-to-hwcap
 509  * mapping in linux-user/elfload.c:get_elf_hwcap().
 510  */
 511 enum arm_features {
 512     ARM_FEATURE_VFP,
 513     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 514     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 515     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 516     ARM_FEATURE_V6,
 517     ARM_FEATURE_V6K,
 518     ARM_FEATURE_V7,
 519     ARM_FEATURE_THUMB2,
 520     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 521     ARM_FEATURE_VFP3,
 522     ARM_FEATURE_VFP_FP16,
 523     ARM_FEATURE_NEON,
 524     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 525     ARM_FEATURE_M, /* Microcontroller profile.  */
 526     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 527     ARM_FEATURE_THUMB2EE,
 528     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 529     ARM_FEATURE_V4T,
 530     ARM_FEATURE_V5,
 531     ARM_FEATURE_STRONGARM,
 532     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 533     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 534     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 535     ARM_FEATURE_GENERIC_TIMER,
 536     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 537     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 538     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 539     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 540     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 541     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 542     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 543     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 544     ARM_FEATURE_V8,
 545     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
 546     ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
 547     ARM_FEATURE_CBAR, /* has cp15 CBAR */
 548 };
 549
 550 static inline int arm_feature(CPUARMState *env, int feature)
 551 {
 552     return (env->features & (1ULL << feature)) != 0;
 553 }
 554
 555 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 556
 557 /* Interface between CPU and Interrupt controller.  */
 558 void armv7m_nvic_set_pending(void *opaque, int irq);
 559 int armv7m_nvic_acknowledge_irq(void *opaque);
 560 void armv7m_nvic_complete_irq(void *opaque, int irq);
 561
 562 /* Interface for defining coprocessor registers.
 563  * Registers are defined in tables of arm_cp_reginfo structs
 564  * which are passed to define_arm_cp_regs().
 565  */
 566
 567 /* When looking up a coprocessor register we look for it
 568  * via an integer which encodes all of:
 569  *  coprocessor number
 570  *  Crn, Crm, opc1, opc2 fields
 571  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 572  *    or via MRRC/MCRR?)
 573  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 574  * (In this case crn and opc2 should be zero.)
 575  */
 576 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 577     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 578      ((crm) << 7) | ((opc1) << 3) | (opc2))
 579
 580 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
 581  * version used as a key for the coprocessor register hashtable
 582  */
 583 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 584 {
 585     uint32_t cpregid = kvmid;
 586     if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 587         cpregid |= (1 << 15);
 588     }
 589     return cpregid;
 590 }
 591
 592 /* Convert a truncated 32 bit hashtable key into the full
 593  * 64 bit KVM register ID.
 594  */
 595 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 596 {
 597     uint64_t kvmid = cpregid & ~(1 << 15);
 598     if (cpregid & (1 << 15)) {
 599         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 600     } else {
 601         kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 602     }
 603     return kvmid;
 604 }
 605
 606 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 607  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 608  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 609  * TCG can assume the value to be constant (ie load at translate time)
 610  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 611  * indicates that the TB should not be ended after a write to this register
 612  * (the default is that the TB ends after cp writes). OVERRIDE permits
 613  * a register definition to override a previous definition for the
 614  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 615  * old must have the OVERRIDE bit set.
 616  * NO_MIGRATE indicates that this register should be ignored for migration;
 617  * (eg because any state is accessed via some other coprocessor register).
 618  * IO indicates that this register does I/O and therefore its accesses
 619  * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
 620  * registers which implement clocks or timers require this.
 621  */
 622 #define ARM_CP_SPECIAL 1
 623 #define ARM_CP_CONST 2
 624 #define ARM_CP_64BIT 4
 625 #define ARM_CP_SUPPRESS_TB_END 8
 626 #define ARM_CP_OVERRIDE 16
 627 #define ARM_CP_NO_MIGRATE 32
 628 #define ARM_CP_IO 64
 629 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 630 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 631 #define ARM_LAST_SPECIAL ARM_CP_WFI
 632 /* Used only as a terminator for ARMCPRegInfo lists */
 633 #define ARM_CP_SENTINEL 0xffff
 634 /* Mask of only the flag bits in a type field */
 635 #define ARM_CP_FLAG_MASK 0x7f
 636
 637 /* Return true if cptype is a valid type field. This is used to try to
 638  * catch errors where the sentinel has been accidentally left off the end
 639  * of a list of registers.
 640  */
 641 static inline bool cptype_valid(int cptype)
 642 {
 643     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 644         || ((cptype & ARM_CP_SPECIAL) &&
 645             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 646 }
 647
 648 /* Access rights:
 649  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 650  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 651  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 652  * (ie any of the privileged modes in Secure state, or Monitor mode).
 653  * If a register is accessible in one privilege level it's always accessible
 654  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 655  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 656  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 657  * terminology a little and call this PL3.
 658  *
 659  * If access permissions for a register are more complex than can be
 660  * described with these bits, then use a laxer set of restrictions, and
 661  * do the more restrictive/complex check inside a helper function.
 662  */
 663 #define PL3_R 0x80
 664 #define PL3_W 0x40
 665 #define PL2_R (0x20 | PL3_R)
 666 #define PL2_W (0x10 | PL3_W)
 667 #define PL1_R (0x08 | PL2_R)
 668 #define PL1_W (0x04 | PL2_W)
 669 #define PL0_R (0x02 | PL1_R)
 670 #define PL0_W (0x01 | PL1_W)
 671
 672 #define PL3_RW (PL3_R | PL3_W)
 673 #define PL2_RW (PL2_R | PL2_W)
 674 #define PL1_RW (PL1_R | PL1_W)
 675 #define PL0_RW (PL0_R | PL0_W)
 676
 677 static inline int arm_current_pl(CPUARMState *env)
 678 {
 679     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 680         return 0;
 681     }
 682     /* We don't currently implement the Virtualization or TrustZone
 683      * extensions, so PL2 and PL3 don't exist for us.
 684      */
 685     return 1;
 686 }
 687
 688 typedef struct ARMCPRegInfo ARMCPRegInfo;
 689
 690 /* Access functions for coprocessor registers. These should return
 691  * 0 on success, or one of the EXCP_* constants if access should cause
 692  * an exception (in which case *value is not written).
 693  */
 694 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 695                      uint64_t *value);
 696 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 697                       uint64_t value);
 698 /* Hook function for register reset */
 699 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 700
 701 #define CP_ANY 0xff
 702
 703 /* Definition of an ARM coprocessor register */
 704 struct ARMCPRegInfo {
 705     /* Name of register (useful mainly for debugging, need not be unique) */
 706     const char *name;
 707     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 708      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 709      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 710      * will be decoded to this register. The register read and write
 711      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 712      * used by the program, so it is possible to register a wildcard and
 713      * then behave differently on read/write if necessary.
 714      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 715      * must both be zero.
 716      */
 717     uint8_t cp;
 718     uint8_t crn;
 719     uint8_t crm;
 720     uint8_t opc1;
 721     uint8_t opc2;
 722     /* Register type: ARM_CP_* bits/values */
 723     int type;
 724     /* Access rights: PL*_[RW] */
 725     int access;
 726     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 727      * this register was defined: can be used to hand data through to the
 728      * register read/write functions, since they are passed the ARMCPRegInfo*.
 729      */
 730     void *opaque;
 731     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 732      * fieldoffset is non-zero, the reset value of the register.
 733      */
 734     uint64_t resetvalue;
 735     /* Offset of the field in CPUARMState for this register. This is not
 736      * needed if either:
 737      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 738      *  2. both readfn and writefn are specified
 739      */
 740     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 741     /* Function for handling reads of this register. If NULL, then reads
 742      * will be done by loading from the offset into CPUARMState specified
 743      * by fieldoffset.
 744      */
 745     CPReadFn *readfn;
 746     /* Function for handling writes of this register. If NULL, then writes
 747      * will be done by writing to the offset into CPUARMState specified
 748      * by fieldoffset.
 749      */
 750     CPWriteFn *writefn;
 751     /* Function for doing a "raw" read; used when we need to copy
 752      * coprocessor state to the kernel for KVM or out for
 753      * migration. This only needs to be provided if there is also a
 754      * readfn and it makes an access permission check.
 755      */
 756     CPReadFn *raw_readfn;
 757     /* Function for doing a "raw" write; used when we need to copy KVM
 758      * kernel coprocessor state into userspace, or for inbound
 759      * migration. This only needs to be provided if there is also a
 760      * writefn and it makes an access permission check or masks out
 761      * "unwritable" bits or has write-one-to-clear or similar behaviour.
 762      */
 763     CPWriteFn *raw_writefn;
 764     /* Function for resetting the register. If NULL, then reset will be done
 765      * by writing resetvalue to the field specified in fieldoffset. If
 766      * fieldoffset is 0 then no reset will be done.
 767      */
 768     CPResetFn *resetfn;
 769 };
 770
 771 /* Macros which are lvalues for the field in CPUARMState for the
 772  * ARMCPRegInfo *ri.
 773  */
 774 #define CPREG_FIELD32(env, ri) \
 775     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 776 #define CPREG_FIELD64(env, ri) \
 777     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 778
 779 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 780
 781 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 782                                     const ARMCPRegInfo *regs, void *opaque);
 783 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 784                                        const ARMCPRegInfo *regs, void *opaque);
 785 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 786 {
 787     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 788 }
 789 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 790 {
 791     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 792 }
 793 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 794
 795 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 796 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 797                         uint64_t value);
 798 /* CPReadFn that can be used for read-as-zero behaviour */
 799 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 800
 801 static inline bool cp_access_ok(CPUARMState *env,
 802                                 const ARMCPRegInfo *ri, int isread)
 803 {
 804     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 805 }
 806
 807 /**
 808  * write_list_to_cpustate
 809  * @cpu: ARMCPU
 810  *
 811  * For each register listed in the ARMCPU cpreg_indexes list, write
 812  * its value from the cpreg_values list into the ARMCPUState structure.
 813  * This updates TCG's working data structures from KVM data or
 814  * from incoming migration state.
 815  *
 816  * Returns: true if all register values were updated correctly,
 817  * false if some register was unknown or could not be written.
 818  * Note that we do not stop early on failure -- we will attempt
 819  * writing all registers in the list.
 820  */
 821 bool write_list_to_cpustate(ARMCPU *cpu);
 822
 823 /**
 824  * write_cpustate_to_list:
 825  * @cpu: ARMCPU
 826  *
 827  * For each register listed in the ARMCPU cpreg_indexes list, write
 828  * its value from the ARMCPUState structure into the cpreg_values list.
 829  * This is used to copy info from TCG's working data structures into
 830  * KVM or for outbound migration.
 831  *
 832  * Returns: true if all register values were read correctly,
 833  * false if some register was unknown or could not be read.
 834  * Note that we do not stop early on failure -- we will attempt
 835  * reading all registers in the list.
 836  */
 837 bool write_cpustate_to_list(ARMCPU *cpu);
 838
 839 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 840    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 841    conventional cores (ie. Application or Realtime profile).  */
 842
 843 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 844
 845 #define ARM_CPUID_TI915T      0x54029152
 846 #define ARM_CPUID_TI925T      0x54029252
 847
 848 #if defined(CONFIG_USER_ONLY)
 849 #define TARGET_PAGE_BITS 12
 850 #else
 851 /* The ARM MMU allows 1k pages.  */
 852 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 853    architecture revisions.  Maybe a configure option to disable them.  */
 854 #define TARGET_PAGE_BITS 10
 855 #endif
 856
 857 #if defined(TARGET_AARCH64)
 858 #  define TARGET_PHYS_ADDR_SPACE_BITS 48
 859 #  define TARGET_VIRT_ADDR_SPACE_BITS 64
 860 #else
 861 #  define TARGET_PHYS_ADDR_SPACE_BITS 40
 862 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 863 #endif
 864
 865 static inline CPUARMState *cpu_init(const char *cpu_model)
 866 {
 867     ARMCPU *cpu = cpu_arm_init(cpu_model);
 868     if (cpu) {
 869         return &cpu->env;
 870     }
 871     return NULL;
 872 }
 873
 874 #define cpu_exec cpu_arm_exec
 875 #define cpu_gen_code cpu_arm_gen_code
 876 #define cpu_signal_handler cpu_arm_signal_handler
 877 #define cpu_list arm_cpu_list
 878
 879 /* MMU modes definitions */
 880 #define MMU_MODE0_SUFFIX _kernel
 881 #define MMU_MODE1_SUFFIX _user
 882 #define MMU_USER_IDX 1
 883 static inline int cpu_mmu_index (CPUARMState *env)
 884 {
 885     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 886 }
 887
 888 #include "exec/cpu-all.h"
 889
 890 /* Bit usage in the TB flags field: bit 31 indicates whether we are
 891  * in 32 or 64 bit mode. The meaning of the other bits depends on that.
 892  */
 893 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
 894 #define ARM_TBFLAG_AARCH64_STATE_MASK  (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
 895
 896 /* Bit usage when in AArch32 state: */
 897 #define ARM_TBFLAG_THUMB_SHIFT      0
 898 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 899 #define ARM_TBFLAG_VECLEN_SHIFT     1
 900 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 901 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 902 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 903 #define ARM_TBFLAG_PRIV_SHIFT       6
 904 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 905 #define ARM_TBFLAG_VFPEN_SHIFT      7
 906 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 907 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 908 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 909 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 910 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 911
 912 /* Bit usage when in AArch64 state: currently no bits defined */
 913
 914 /* some convenience accessor macros */
 915 #define ARM_TBFLAG_AARCH64_STATE(F) \
 916     (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
 917 #define ARM_TBFLAG_THUMB(F) \
 918     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 919 #define ARM_TBFLAG_VECLEN(F) \
 920     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 921 #define ARM_TBFLAG_VECSTRIDE(F) \
 922     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 923 #define ARM_TBFLAG_PRIV(F) \
 924     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 925 #define ARM_TBFLAG_VFPEN(F) \
 926     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 927 #define ARM_TBFLAG_CONDEXEC(F) \
 928     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 929 #define ARM_TBFLAG_BSWAP_CODE(F) \
 930     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 931
 932 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 933                                         target_ulong *cs_base, int *flags)
 934 {
 935     if (is_a64(env)) {
 936         *pc = env->pc;
 937         *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
 938     } else {
 939         int privmode;
 940         *pc = env->regs[15];
 941         *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 942             | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 943             | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 944             | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 945             | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 946         if (arm_feature(env, ARM_FEATURE_M)) {
 947             privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 948         } else {
 949             privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 950         }
 951         if (privmode) {
 952             *flags |= ARM_TBFLAG_PRIV_MASK;
 953         }
 954         if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 955             *flags |= ARM_TBFLAG_VFPEN_MASK;
 956         }
 957     }
 958
 959     *cs_base = 0;
 960 }
 961
 962 static inline bool cpu_has_work(CPUState *cpu)
 963 {
 964     return cpu->interrupt_request &
 965         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 966 }
 967
 968 #include "exec/exec-all.h"
 969
 970 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 971 {
 972     if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
 973         env->pc = tb->pc;
 974     } else {
 975         env->regs[15] = tb->pc;
 976     }
 977 }
 978
 979 /* Load an instruction and return it in the standard little-endian order */
 980 static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
 981                                     bool do_swap)
 982 {
 983     uint32_t insn = cpu_ldl_code(env, addr);
 984     if (do_swap) {
 985         return bswap32(insn);
 986     }
 987     return insn;
 988 }
 989
 990 /* Ditto, for a halfword (Thumb) instruction */
 991 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
 992                                      bool do_swap)
 993 {
 994     uint16_t insn = cpu_lduw_code(env, addr);
 995     if (do_swap) {
 996         return bswap16(insn);
 997     }
 998     return insn;
 999 }
1000
1001 #endif