1 # AArch32 Neon data-processing instruction descriptions
3 # Copyright (c) 2020 Linaro, Ltd
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2 of the License, or (at your option) any later version.
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 # This file is processed by scripts/decodetree.py
21 # VFP/Neon register fields; same as vfp.decode
26 # Encodings for Neon data processing instructions where the T32 encoding
27 # is a simple transformation of the A32 encoding.
28 # More specifically, this file covers instructions where the A32 encoding is
29 # 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
30 # and the T32 encoding is
31 # 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
32 # This file works on the A32 encoding only; calling code for T32 has to
33 # transform the insn into the A32 version first.
35 ######################################################################
36 # 3-reg-same grouping:
37 # 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
38 ######################################################################
40 &3same vm vn vd q size
42 @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
43 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
45 @3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
46 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
48 # For FP insns the high bit of 'size' is used as part of opcode decode
49 @3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
50 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
51 @3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \
52 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
54 VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
55 VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
56 VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
57 VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
59 VRHADD_S_3s 1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
60 VRHADD_U_3s 1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
62 @3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
63 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
65 VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
66 VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
67 VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
68 VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
69 VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
70 VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
71 VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
72 VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
74 VHSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
75 VHSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
77 VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
78 VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
80 VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
81 VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
82 VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
83 VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
85 # The _rev suffix indicates that Vn and Vm are reversed. This is
86 # the case for shifts. In the Arm ARM these insns are documented
87 # with the Vm and Vn fields in their usual places, but in the
88 # assembly the operands are listed "backwards", ie in the order
89 # Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
90 # to consider Vm and Vn as being in different fields in the insn,
91 # which allows us to avoid special-casing shifts in the trans_
92 # function code. We would otherwise need to manually swap the operands
93 # over to call Neon helper functions that are shared with AArch64,
94 # which does not have this odd reversed-operand situation.
95 @3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \
96 &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
98 VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
99 VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
101 # Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
102 # The _rev suffix indicates that Vn and Vm are reversed (as explained
103 # by the comment for the @3same_rev format).
104 @3same_64_rev .... ... . . . 11 .... .... .... . q:1 . . .... \
105 &3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3
108 VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
109 VQSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
112 VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
113 VQSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
116 VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
117 VRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
120 VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
121 VRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
124 VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
125 VQRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
128 VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
129 VQRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
132 VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
133 VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
134 VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
135 VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
137 VABD_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
138 VABD_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
140 VABA_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
141 VABA_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
143 VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
144 VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
146 VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
147 VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
149 VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
150 VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
152 VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
153 VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
155 VPMAX_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
156 VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
158 VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
159 VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
161 VQDMULH_3s 1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
162 VQRDMULH_3s 1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
164 VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
166 VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
168 @3same_crypto .... .... .... .... .... .... .... .... \
169 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
171 SHA1C_3s 1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
172 SHA1P_3s 1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
173 SHA1M_3s 1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
174 SHA1SU0_3s 1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
175 SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
176 SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
177 SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
179 VFMA_fp_3s 1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
180 VFMS_fp_3s 1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
182 VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
184 VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
185 VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
186 VPADD_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
187 VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
188 VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
189 VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
190 VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
191 VCEQ_fp_3s 1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
192 VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
193 VACGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp
194 VCGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp
195 VACGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp
196 VMAX_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp
197 VMIN_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp
198 VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
199 VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
200 VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
201 VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
202 VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
203 VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
205 ######################################################################
206 # 2-reg-and-shift grouping:
207 # 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
208 ######################################################################
209 &2reg_shift vm vd q shift size
211 # Right shifts are encoded as N - shift, where N is the element size in bits.
212 %neon_rshift_i6 16:6 !function=rsub_64
213 %neon_rshift_i5 16:5 !function=rsub_32
214 %neon_rshift_i4 16:4 !function=rsub_16
215 %neon_rshift_i3 16:3 !function=rsub_8
217 @2reg_shr_d .... ... . . . ...... .... .... 1 q:1 . . .... \
218 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
219 @2reg_shr_s .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
220 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
221 @2reg_shr_h .... ... . . . 01 .... .... .... 0 q:1 . . .... \
222 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
223 @2reg_shr_b .... ... . . . 001 ... .... .... 0 q:1 . . .... \
224 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
226 @2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \
227 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
228 @2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \
229 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
230 @2reg_shl_h .... ... . . . 01 shift:4 .... .... 0 q:1 . . .... \
231 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
232 @2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \
233 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
235 # Narrowing right shifts: here the Q bit is part of the opcode decode
236 @2reg_shrn_d .... ... . . . 1 ..... .... .... 0 . . . .... \
237 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
238 shift=%neon_rshift_i5
239 @2reg_shrn_s .... ... . . . 01 .... .... .... 0 . . . .... \
240 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
241 shift=%neon_rshift_i4
242 @2reg_shrn_h .... ... . . . 001 ... .... .... 0 . . . .... \
243 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
244 shift=%neon_rshift_i3
246 # Long left shifts: again Q is part of opcode decode
247 @2reg_shll_s .... ... . . . 1 shift:5 .... .... 0 . . . .... \
248 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
249 @2reg_shll_h .... ... . . . 01 shift:4 .... .... 0 . . . .... \
250 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
251 @2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \
252 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
254 # We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
255 @2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \
256 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
258 VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
259 VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
260 VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
261 VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
263 VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
264 VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
265 VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
266 VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
268 VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
269 VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
270 VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
271 VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
273 VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
274 VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
275 VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
276 VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
278 VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
279 VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
280 VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
281 VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
283 VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
284 VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
285 VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
286 VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
288 VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
289 VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
290 VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
291 VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
293 VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
294 VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
295 VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
296 VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
298 VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
299 VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
300 VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
301 VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
303 VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
304 VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
305 VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
306 VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
308 VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
309 VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
310 VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
311 VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
313 VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
314 VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
315 VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
316 VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
318 VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
319 VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
320 VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
321 VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
323 VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
324 VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
325 VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
326 VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
328 VSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
329 VSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
330 VSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
332 VRSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
333 VRSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
334 VRSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
336 VQSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
337 VQSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
338 VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
340 VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
341 VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
342 VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
344 # VQSHRN with signed input
345 VQSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
346 VQSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
347 VQSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
349 # VQRSHRN with signed input
350 VQRSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
351 VQRSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
352 VQRSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
354 # VQSHRN with unsigned input
355 VQSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
356 VQSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
357 VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
359 # VQRSHRN with unsigned input
360 VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
361 VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
362 VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
364 VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
365 VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
366 VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
368 VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
369 VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
370 VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
372 # VCVT fixed<->float conversions
373 # TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
374 VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
375 VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
376 VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
377 VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
379 ######################################################################
380 # 1-reg-and-modified-immediate grouping:
381 # 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
382 ######################################################################
384 &1reg_imm vd q imm cmode op
386 %asimd_imm_value 24:1 16:3 0:4
388 @1reg_imm .... ... . . . ... ... .... .... . q:1 . . .... \
389 &1reg_imm imm=%asimd_imm_value vd=%vd_dp
391 # The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
392 # not in a way we can conveniently represent in decodetree without
393 # a lot of repetition:
394 # VORR: op=0, (cmode & 1) && cmode < 12
395 # VBIC: op=1, (cmode & 1) && cmode < 12
396 # VMOV: everything else
397 # So we have a single decode line and check the cmode/op in the
399 Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
401 ######################################################################
402 # Within the "two registers, or three registers of different lengths"
403 # grouping ([23,4]=0b10), bits [21:20] are either part of the opcode
404 # decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar;
405 # or they are a size field for the three-reg-different-lengths and
406 # two-reg-and-scalar insn groups (where size cannot be 0b11). This
407 # is slightly awkward for decodetree: we handle it with this
408 # non-exclusive group which contains within it two exclusive groups:
409 # one for the size=0b11 patterns, and one for the size-not-0b11
410 # patterns. This allows us to check that none of the insns within
411 # each subgroup accidentally overlap each other. Note that all the
412 # trans functions for the size-not-0b11 patterns must check and
413 # return false for size==3.
414 ######################################################################
417 ##################################################################
418 # Miscellaneous size=0b11 insns
419 ##################################################################
420 VEXT 1111 001 0 1 . 11 .... .... imm:4 . q:1 . 0 .... \
421 vm=%vm_dp vn=%vn_dp vd=%vd_dp
424 # Subgroup for size != 0b11
426 ##################################################################
427 # 3-reg-different-length grouping:
428 # 1111 001 U 1 D sz!=11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4
429 ##################################################################
433 @3diff .... ... . . . size:2 .... .... .... . . . . .... \
434 &3diff vm=%vm_dp vn=%vn_dp vd=%vd_dp
436 VADDL_S_3d 1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff
437 VADDL_U_3d 1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff
439 VADDW_S_3d 1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff
440 VADDW_U_3d 1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff
442 VSUBL_S_3d 1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff
443 VSUBL_U_3d 1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff
445 VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff
446 VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff
448 VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff
449 VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff
451 VABAL_S_3d 1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff
452 VABAL_U_3d 1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff
454 VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff
455 VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff
457 VABDL_S_3d 1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff
458 VABDL_U_3d 1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff
460 VMLAL_S_3d 1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff
461 VMLAL_U_3d 1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff
463 VQDMLAL_3d 1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff
465 VMLSL_S_3d 1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff
466 VMLSL_U_3d 1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff
468 VQDMLSL_3d 1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff
470 VMULL_S_3d 1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff
471 VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff
473 VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff
475 VMULL_P_3d 1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff
477 ##################################################################
478 # 2-regs-plus-scalar grouping:
479 # 1111 001 Q 1 D sz!=11 Vn:4 Vd:4 opc:4 N 1 M 0 Vm:4
480 ##################################################################
481 &2scalar vm vn vd size q
483 @2scalar .... ... q:1 . . size:2 .... .... .... . . . . .... \
484 &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
485 # For the 'long' ops the Q bit is part of insn decode
486 @2scalar_q0 .... ... . . . size:2 .... .... .... . . . . .... \
487 &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
489 VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
490 VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
492 VMLAL_S_2sc 1111 001 0 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
493 VMLAL_U_2sc 1111 001 1 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
495 VQDMLAL_2sc 1111 001 0 1 . .. .... .... 0011 . 1 . 0 .... @2scalar_q0
497 VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
498 VMLS_F_2sc 1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
500 VMLSL_S_2sc 1111 001 0 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
501 VMLSL_U_2sc 1111 001 1 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
503 VQDMLSL_2sc 1111 001 0 1 . .. .... .... 0111 . 1 . 0 .... @2scalar_q0
505 VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
506 VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
508 VMULL_S_2sc 1111 001 0 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
509 VMULL_U_2sc 1111 001 1 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
511 VQDMULL_2sc 1111 001 0 1 . .. .... .... 1011 . 1 . 0 .... @2scalar_q0
513 VQDMULH_2sc 1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar
514 VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar
516 VQRDMLAH_2sc 1111 001 . 1 . .. .... .... 1110 . 1 . 0 .... @2scalar
517 VQRDMLSH_2sc 1111 001 . 1 . .. .... .... 1111 . 1 . 0 .... @2scalar