4 * Copyright (c) 2008 OK Labs
5 * Copyright (c) 2011 NICTA Pty Ltd
6 * Originally written by Hans Jiang
7 * Updated by Peter Chubb
8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
10 * This code is licensed under GPL version 2 or later. See
11 * the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "hw/timer/imx_gpt.h"
17 #include "qemu/main-loop.h"
21 #define DEBUG_IMX_GPT 0
24 #define DPRINTF(fmt, args...) \
26 if (DEBUG_IMX_GPT) { \
27 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
32 static char const *imx_gpt_reg_name(uint32_t reg
)
60 static const VMStateDescription vmstate_imx_timer_gpt
= {
63 .minimum_version_id
= 3,
64 .fields
= (VMStateField
[]) {
65 VMSTATE_UINT32(cr
, IMXGPTState
),
66 VMSTATE_UINT32(pr
, IMXGPTState
),
67 VMSTATE_UINT32(sr
, IMXGPTState
),
68 VMSTATE_UINT32(ir
, IMXGPTState
),
69 VMSTATE_UINT32(ocr1
, IMXGPTState
),
70 VMSTATE_UINT32(ocr2
, IMXGPTState
),
71 VMSTATE_UINT32(ocr3
, IMXGPTState
),
72 VMSTATE_UINT32(icr1
, IMXGPTState
),
73 VMSTATE_UINT32(icr2
, IMXGPTState
),
74 VMSTATE_UINT32(cnt
, IMXGPTState
),
75 VMSTATE_UINT32(next_timeout
, IMXGPTState
),
76 VMSTATE_UINT32(next_int
, IMXGPTState
),
77 VMSTATE_UINT32(freq
, IMXGPTState
),
78 VMSTATE_PTIMER(timer
, IMXGPTState
),
83 static const IMXClk imx25_gpt_clocks
[] = {
84 CLK_NONE
, /* 000 No clock source */
85 CLK_IPG
, /* 001 ipg_clk, 532MHz*/
86 CLK_IPG_HIGH
, /* 010 ipg_clk_highfreq */
87 CLK_NONE
, /* 011 not defined */
88 CLK_32k
, /* 100 ipg_clk_32k */
89 CLK_32k
, /* 101 ipg_clk_32k */
90 CLK_32k
, /* 110 ipg_clk_32k */
91 CLK_32k
, /* 111 ipg_clk_32k */
94 static const IMXClk imx31_gpt_clocks
[] = {
95 CLK_NONE
, /* 000 No clock source */
96 CLK_IPG
, /* 001 ipg_clk, 532MHz*/
97 CLK_IPG_HIGH
, /* 010 ipg_clk_highfreq */
98 CLK_NONE
, /* 011 not defined */
99 CLK_32k
, /* 100 ipg_clk_32k */
100 CLK_NONE
, /* 101 not defined */
101 CLK_NONE
, /* 110 not defined */
102 CLK_NONE
, /* 111 not defined */
105 static const IMXClk imx6_gpt_clocks
[] = {
106 CLK_NONE
, /* 000 No clock source */
107 CLK_IPG
, /* 001 ipg_clk, 532MHz*/
108 CLK_IPG_HIGH
, /* 010 ipg_clk_highfreq */
109 CLK_EXT
, /* 011 External clock */
110 CLK_32k
, /* 100 ipg_clk_32k */
111 CLK_HIGH_DIV
, /* 101 reference clock / 8 */
112 CLK_NONE
, /* 110 not defined */
113 CLK_HIGH
, /* 111 reference clock */
116 static void imx_gpt_set_freq(IMXGPTState
*s
)
118 uint32_t clksrc
= extract32(s
->cr
, GPT_CR_CLKSRC_SHIFT
, 3);
120 s
->freq
= imx_ccm_get_clock_frequency(s
->ccm
,
121 s
->clocks
[clksrc
]) / (1 + s
->pr
);
123 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc
, s
->freq
);
126 ptimer_set_freq(s
->timer
, s
->freq
);
130 static void imx_gpt_update_int(IMXGPTState
*s
)
132 if ((s
->sr
& s
->ir
) && (s
->cr
& GPT_CR_EN
)) {
133 qemu_irq_raise(s
->irq
);
135 qemu_irq_lower(s
->irq
);
139 static uint32_t imx_gpt_update_count(IMXGPTState
*s
)
141 s
->cnt
= s
->next_timeout
- (uint32_t)ptimer_get_count(s
->timer
);
146 static inline uint32_t imx_gpt_find_limit(uint32_t count
, uint32_t reg
,
149 if ((count
< reg
) && (timeout
> reg
)) {
156 static void imx_gpt_compute_next_timeout(IMXGPTState
*s
, bool event
)
158 uint32_t timeout
= GPT_TIMER_MAX
;
162 if (!(s
->cr
& GPT_CR_EN
)) {
163 /* if not enabled just return */
167 /* update the count */
168 count
= imx_gpt_update_count(s
);
172 * This is an event (the ptimer reached 0 and stopped), and the
173 * timer counter is now equal to s->next_timeout.
175 if (!(s
->cr
& GPT_CR_FRR
) && (count
== s
->ocr1
)) {
176 /* We are in restart mode and we crossed the compare channel 1
177 * value. We need to reset the counter to 0.
179 count
= s
->cnt
= s
->next_timeout
= 0;
180 } else if (count
== GPT_TIMER_MAX
) {
181 /* We reached GPT_TIMER_MAX so we need to rollover */
182 count
= s
->cnt
= s
->next_timeout
= 0;
186 /* now, find the next timeout related to count */
188 if (s
->ir
& GPT_IR_OF1IE
) {
189 timeout
= imx_gpt_find_limit(count
, s
->ocr1
, timeout
);
191 if (s
->ir
& GPT_IR_OF2IE
) {
192 timeout
= imx_gpt_find_limit(count
, s
->ocr2
, timeout
);
194 if (s
->ir
& GPT_IR_OF3IE
) {
195 timeout
= imx_gpt_find_limit(count
, s
->ocr3
, timeout
);
198 /* find the next set of interrupts to raise for next timer event */
201 if ((s
->ir
& GPT_IR_OF1IE
) && (timeout
== s
->ocr1
)) {
202 s
->next_int
|= GPT_SR_OF1
;
204 if ((s
->ir
& GPT_IR_OF2IE
) && (timeout
== s
->ocr2
)) {
205 s
->next_int
|= GPT_SR_OF2
;
207 if ((s
->ir
& GPT_IR_OF3IE
) && (timeout
== s
->ocr3
)) {
208 s
->next_int
|= GPT_SR_OF3
;
210 if ((s
->ir
& GPT_IR_ROVIE
) && (timeout
== GPT_TIMER_MAX
)) {
211 s
->next_int
|= GPT_SR_ROV
;
214 /* the new range to count down from */
215 limit
= timeout
- imx_gpt_update_count(s
);
219 * if we reach here, then QEMU is running too slow and we pass the
220 * timeout limit while computing it. Let's deliver the interrupt
221 * and compute a new limit.
223 s
->sr
|= s
->next_int
;
225 imx_gpt_compute_next_timeout(s
, event
);
227 imx_gpt_update_int(s
);
229 /* New timeout value */
230 s
->next_timeout
= timeout
;
232 /* reset the limit to the computed range */
233 ptimer_set_limit(s
->timer
, limit
, 1);
237 static uint64_t imx_gpt_read(void *opaque
, hwaddr offset
, unsigned size
)
239 IMXGPTState
*s
= IMX_GPT(opaque
);
240 uint32_t reg_value
= 0;
242 switch (offset
>> 2) {
243 case 0: /* Control Register */
247 case 1: /* prescaler */
251 case 2: /* Status Register */
255 case 3: /* Interrupt Register */
259 case 4: /* Output Compare Register 1 */
263 case 5: /* Output Compare Register 2 */
267 case 6: /* Output Compare Register 3 */
271 case 7: /* input Capture Register 1 */
272 qemu_log_mask(LOG_UNIMP
, "[%s]%s: icr1 feature is not implemented\n",
273 TYPE_IMX_GPT
, __func__
);
277 case 8: /* input Capture Register 2 */
278 qemu_log_mask(LOG_UNIMP
, "[%s]%s: icr2 feature is not implemented\n",
279 TYPE_IMX_GPT
, __func__
);
284 imx_gpt_update_count(s
);
289 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
290 HWADDR_PRIx
"\n", TYPE_IMX_GPT
, __func__
, offset
);
294 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset
>> 2), reg_value
);
299 static void imx_gpt_reset(DeviceState
*dev
)
301 IMXGPTState
*s
= IMX_GPT(dev
);
304 ptimer_stop(s
->timer
);
307 * Soft reset doesn't touch some bits; hard reset clears them
309 s
->cr
&= ~(GPT_CR_EN
|GPT_CR_ENMOD
|GPT_CR_STOPEN
|GPT_CR_DOZEN
|
310 GPT_CR_WAITEN
|GPT_CR_DBGEN
);
315 s
->ocr1
= GPT_TIMER_MAX
;
316 s
->ocr2
= GPT_TIMER_MAX
;
317 s
->ocr3
= GPT_TIMER_MAX
;
321 s
->next_timeout
= GPT_TIMER_MAX
;
324 /* compute new freq */
327 /* reset the limit to GPT_TIMER_MAX */
328 ptimer_set_limit(s
->timer
, GPT_TIMER_MAX
, 1);
330 /* if the timer is still enabled, restart it */
331 if (s
->freq
&& (s
->cr
& GPT_CR_EN
)) {
332 ptimer_run(s
->timer
, 1);
336 static void imx_gpt_write(void *opaque
, hwaddr offset
, uint64_t value
,
339 IMXGPTState
*s
= IMX_GPT(opaque
);
342 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset
>> 2),
345 switch (offset
>> 2) {
348 s
->cr
= value
& ~0x7c14;
349 if (s
->cr
& GPT_CR_SWR
) { /* force reset */
350 /* handle the reset */
351 imx_gpt_reset(DEVICE(s
));
353 /* set our freq, as the source might have changed */
356 if ((oldreg
^ s
->cr
) & GPT_CR_EN
) {
357 if (s
->cr
& GPT_CR_EN
) {
358 if (s
->cr
& GPT_CR_ENMOD
) {
359 s
->next_timeout
= GPT_TIMER_MAX
;
360 ptimer_set_count(s
->timer
, GPT_TIMER_MAX
);
361 imx_gpt_compute_next_timeout(s
, false);
363 ptimer_run(s
->timer
, 1);
366 ptimer_stop(s
->timer
);
372 case 1: /* Prescaler */
373 s
->pr
= value
& 0xfff;
378 s
->sr
&= ~(value
& 0x3f);
379 imx_gpt_update_int(s
);
382 case 3: /* IR -- interrupt register */
383 s
->ir
= value
& 0x3f;
384 imx_gpt_update_int(s
);
386 imx_gpt_compute_next_timeout(s
, false);
390 case 4: /* OCR1 -- output compare register */
393 /* In non-freerun mode, reset count when this register is written */
394 if (!(s
->cr
& GPT_CR_FRR
)) {
395 s
->next_timeout
= GPT_TIMER_MAX
;
396 ptimer_set_limit(s
->timer
, GPT_TIMER_MAX
, 1);
399 /* compute the new timeout */
400 imx_gpt_compute_next_timeout(s
, false);
404 case 5: /* OCR2 -- output compare register */
407 /* compute the new timeout */
408 imx_gpt_compute_next_timeout(s
, false);
412 case 6: /* OCR3 -- output compare register */
415 /* compute the new timeout */
416 imx_gpt_compute_next_timeout(s
, false);
421 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
422 HWADDR_PRIx
"\n", TYPE_IMX_GPT
, __func__
, offset
);
427 static void imx_gpt_timeout(void *opaque
)
429 IMXGPTState
*s
= IMX_GPT(opaque
);
433 s
->sr
|= s
->next_int
;
436 imx_gpt_compute_next_timeout(s
, true);
438 imx_gpt_update_int(s
);
440 if (s
->freq
&& (s
->cr
& GPT_CR_EN
)) {
441 ptimer_run(s
->timer
, 1);
445 static const MemoryRegionOps imx_gpt_ops
= {
446 .read
= imx_gpt_read
,
447 .write
= imx_gpt_write
,
448 .endianness
= DEVICE_NATIVE_ENDIAN
,
452 static void imx_gpt_realize(DeviceState
*dev
, Error
**errp
)
454 IMXGPTState
*s
= IMX_GPT(dev
);
455 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
458 sysbus_init_irq(sbd
, &s
->irq
);
459 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_gpt_ops
, s
, TYPE_IMX_GPT
,
461 sysbus_init_mmio(sbd
, &s
->iomem
);
463 bh
= qemu_bh_new(imx_gpt_timeout
, s
);
464 s
->timer
= ptimer_init(bh
);
467 static void imx_gpt_class_init(ObjectClass
*klass
, void *data
)
469 DeviceClass
*dc
= DEVICE_CLASS(klass
);
471 dc
->realize
= imx_gpt_realize
;
472 dc
->reset
= imx_gpt_reset
;
473 dc
->vmsd
= &vmstate_imx_timer_gpt
;
474 dc
->desc
= "i.MX general timer";
477 static void imx25_gpt_init(Object
*obj
)
479 IMXGPTState
*s
= IMX_GPT(obj
);
481 s
->clocks
= imx25_gpt_clocks
;
484 static void imx31_gpt_init(Object
*obj
)
486 IMXGPTState
*s
= IMX_GPT(obj
);
488 s
->clocks
= imx31_gpt_clocks
;
491 static void imx6_gpt_init(Object
*obj
)
493 IMXGPTState
*s
= IMX_GPT(obj
);
495 s
->clocks
= imx6_gpt_clocks
;
498 static const TypeInfo imx25_gpt_info
= {
499 .name
= TYPE_IMX25_GPT
,
500 .parent
= TYPE_SYS_BUS_DEVICE
,
501 .instance_size
= sizeof(IMXGPTState
),
502 .instance_init
= imx25_gpt_init
,
503 .class_init
= imx_gpt_class_init
,
506 static const TypeInfo imx31_gpt_info
= {
507 .name
= TYPE_IMX31_GPT
,
508 .parent
= TYPE_IMX25_GPT
,
509 .instance_init
= imx31_gpt_init
,
512 static const TypeInfo imx6_gpt_info
= {
513 .name
= TYPE_IMX6_GPT
,
514 .parent
= TYPE_IMX25_GPT
,
515 .instance_init
= imx6_gpt_init
,
518 static void imx_gpt_register_types(void)
520 type_register_static(&imx25_gpt_info
);
521 type_register_static(&imx31_gpt_info
);
522 type_register_static(&imx6_gpt_info
);
525 type_init(imx_gpt_register_types
)