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x3130/downstream: support aer.
[qemu.git] / hw / usb-musb.c
blob7f158429626cc1a0978d3984c6a5e88243eeb317
1 /*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "usb.h"
26 #include "irq.h"
27 #include "hw.h"
28
29 /* Common USB registers */
30 #define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31 #define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33 #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34 #define MUSB_HDRC_INTRRX 0x04
35 #define MUSB_HDRC_INTRTXE 0x06
36 #define MUSB_HDRC_INTRRXE 0x08
37 #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38 #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39 #define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40 #define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41 #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43 /* Per-EP registers in indexed mode */
44 #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46 /* EP FIFOs */
47 #define MUSB_HDRC_FIFO 0x20
48
49 /* Additional Control Registers */
50 #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52 /* These are indexed */
53 #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54 #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55 #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56 #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58 /* Some more registers */
59 #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60 #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
63 /* ULPI pass-through */
64 #define MUSB_HDRC_ULPI_VBUSCTL 0x70
65 #define MUSB_HDRC_ULPI_REGDATA 0x74
66 #define MUSB_HDRC_ULPI_REGADDR 0x75
67 #define MUSB_HDRC_ULPI_REGCTL 0x76
68
69 /* Extended config & PHY control */
70 #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71 #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72 #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73 #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74 #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75 #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76 #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78 /* Per-EP BUSCTL registers */
79 #define MUSB_HDRC_BUSCTL 0x80
80
81 /* Per-EP registers in flat mode */
82 #define MUSB_HDRC_EP 0x100
83
84 /* offsets to registers in flat model */
85 #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86 #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87 #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88 #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89 #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90 #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91 #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92 #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93 #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94 #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95 #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96 #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97 #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98 #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99 #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101 /* "Bus control" registers */
102 #define MUSB_HDRC_TXFUNCADDR 0x00
103 #define MUSB_HDRC_TXHUBADDR 0x02
104 #define MUSB_HDRC_TXHUBPORT 0x03
105
106 #define MUSB_HDRC_RXFUNCADDR 0x04
107 #define MUSB_HDRC_RXHUBADDR 0x06
108 #define MUSB_HDRC_RXHUBPORT 0x07
109
110 /*
111 * MUSBHDRC Register bit masks
112 */
113
114 /* POWER */
115 #define MGC_M_POWER_ISOUPDATE 0x80
116 #define MGC_M_POWER_SOFTCONN 0x40
117 #define MGC_M_POWER_HSENAB 0x20
118 #define MGC_M_POWER_HSMODE 0x10
119 #define MGC_M_POWER_RESET 0x08
120 #define MGC_M_POWER_RESUME 0x04
121 #define MGC_M_POWER_SUSPENDM 0x02
122 #define MGC_M_POWER_ENSUSPEND 0x01
123
124 /* INTRUSB */
125 #define MGC_M_INTR_SUSPEND 0x01
126 #define MGC_M_INTR_RESUME 0x02
127 #define MGC_M_INTR_RESET 0x04
128 #define MGC_M_INTR_BABBLE 0x04
129 #define MGC_M_INTR_SOF 0x08
130 #define MGC_M_INTR_CONNECT 0x10
131 #define MGC_M_INTR_DISCONNECT 0x20
132 #define MGC_M_INTR_SESSREQ 0x40
133 #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134 #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136 /* DEVCTL */
137 #define MGC_M_DEVCTL_BDEVICE 0x80
138 #define MGC_M_DEVCTL_FSDEV 0x40
139 #define MGC_M_DEVCTL_LSDEV 0x20
140 #define MGC_M_DEVCTL_VBUS 0x18
141 #define MGC_S_DEVCTL_VBUS 3
142 #define MGC_M_DEVCTL_HM 0x04
143 #define MGC_M_DEVCTL_HR 0x02
144 #define MGC_M_DEVCTL_SESSION 0x01
145
146 /* TESTMODE */
147 #define MGC_M_TEST_FORCE_HOST 0x80
148 #define MGC_M_TEST_FIFO_ACCESS 0x40
149 #define MGC_M_TEST_FORCE_FS 0x20
150 #define MGC_M_TEST_FORCE_HS 0x10
151 #define MGC_M_TEST_PACKET 0x08
152 #define MGC_M_TEST_K 0x04
153 #define MGC_M_TEST_J 0x02
154 #define MGC_M_TEST_SE0_NAK 0x01
155
156 /* CSR0 */
157 #define MGC_M_CSR0_FLUSHFIFO 0x0100
158 #define MGC_M_CSR0_TXPKTRDY 0x0002
159 #define MGC_M_CSR0_RXPKTRDY 0x0001
160
161 /* CSR0 in Peripheral mode */
162 #define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163 #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164 #define MGC_M_CSR0_P_SENDSTALL 0x0020
165 #define MGC_M_CSR0_P_SETUPEND 0x0010
166 #define MGC_M_CSR0_P_DATAEND 0x0008
167 #define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169 /* CSR0 in Host mode */
170 #define MGC_M_CSR0_H_NO_PING 0x0800
171 #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172 #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173 #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174 #define MGC_M_CSR0_H_STATUSPKT 0x0040
175 #define MGC_M_CSR0_H_REQPKT 0x0020
176 #define MGC_M_CSR0_H_ERROR 0x0010
177 #define MGC_M_CSR0_H_SETUPPKT 0x0008
178 #define MGC_M_CSR0_H_RXSTALL 0x0004
179
180 /* CONFIGDATA */
181 #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182 #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183 #define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184 #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185 #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186 #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187 #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188 #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190 /* TXCSR in Peripheral and Host mode */
191 #define MGC_M_TXCSR_AUTOSET 0x8000
192 #define MGC_M_TXCSR_ISO 0x4000
193 #define MGC_M_TXCSR_MODE 0x2000
194 #define MGC_M_TXCSR_DMAENAB 0x1000
195 #define MGC_M_TXCSR_FRCDATATOG 0x0800
196 #define MGC_M_TXCSR_DMAMODE 0x0400
197 #define MGC_M_TXCSR_CLRDATATOG 0x0040
198 #define MGC_M_TXCSR_FLUSHFIFO 0x0008
199 #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200 #define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202 /* TXCSR in Peripheral mode */
203 #define MGC_M_TXCSR_P_INCOMPTX 0x0080
204 #define MGC_M_TXCSR_P_SENTSTALL 0x0020
205 #define MGC_M_TXCSR_P_SENDSTALL 0x0010
206 #define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208 /* TXCSR in Host mode */
209 #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210 #define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211 #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212 #define MGC_M_TXCSR_H_RXSTALL 0x0020
213 #define MGC_M_TXCSR_H_ERROR 0x0004
214
215 /* RXCSR in Peripheral and Host mode */
216 #define MGC_M_RXCSR_AUTOCLEAR 0x8000
217 #define MGC_M_RXCSR_DMAENAB 0x2000
218 #define MGC_M_RXCSR_DISNYET 0x1000
219 #define MGC_M_RXCSR_DMAMODE 0x0800
220 #define MGC_M_RXCSR_INCOMPRX 0x0100
221 #define MGC_M_RXCSR_CLRDATATOG 0x0080
222 #define MGC_M_RXCSR_FLUSHFIFO 0x0010
223 #define MGC_M_RXCSR_DATAERROR 0x0008
224 #define MGC_M_RXCSR_FIFOFULL 0x0002
225 #define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227 /* RXCSR in Peripheral mode */
228 #define MGC_M_RXCSR_P_ISO 0x4000
229 #define MGC_M_RXCSR_P_SENTSTALL 0x0040
230 #define MGC_M_RXCSR_P_SENDSTALL 0x0020
231 #define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233 /* RXCSR in Host mode */
234 #define MGC_M_RXCSR_H_AUTOREQ 0x4000
235 #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236 #define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237 #define MGC_M_RXCSR_H_RXSTALL 0x0040
238 #define MGC_M_RXCSR_H_REQPKT 0x0020
239 #define MGC_M_RXCSR_H_ERROR 0x0004
240
241 /* HUBADDR */
242 #define MGC_M_HUBADDR_MULTI_TT 0x80
243
244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247 #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248 #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249 #define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250 #define MGC_M_ULPI_REGCTL_REG 0x01
251
252 /* #define MUSB_DEBUG */
253
254 #ifdef MUSB_DEBUG
255 #define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257 #else
258 #define TRACE(...)
259 #endif
260
261
262 static void musb_attach(USBPort *port, USBDevice *dev);
263
264 typedef struct {
265 uint16_t faddr[2];
266 uint8_t haddr[2];
267 uint8_t hport[2];
268 uint16_t csr[2];
269 uint16_t maxp[2];
270 uint16_t rxcount;
271 uint8_t type[2];
272 uint8_t interval[2];
273 uint8_t config;
274 uint8_t fifosize;
275 int timeout[2]; /* Always in microframes */
276
277 uint8_t *buf[2];
278 int fifolen[2];
279 int fifostart[2];
280 int fifoaddr[2];
281 USBPacket packey[2];
282 int status[2];
283 int ext_size[2];
284
285 /* For callbacks' use */
286 int epnum;
287 int interrupt[2];
288 MUSBState *musb;
289 USBCallback *delayed_cb[2];
290 QEMUTimer *intv_timer[2];
291 } MUSBEndPoint;
292
293 struct MUSBState {
294 qemu_irq *irqs;
295 USBBus bus;
296 USBPort port;
297
298 int idx;
299 uint8_t devctl;
300 uint8_t power;
301 uint8_t faddr;
302
303 uint8_t intr;
304 uint8_t mask;
305 uint16_t tx_intr;
306 uint16_t tx_mask;
307 uint16_t rx_intr;
308 uint16_t rx_mask;
309
310 int setup_len;
311 int session;
312
313 uint8_t buf[0x8000];
314
315 /* Duplicating the world since 2008!... probably we should have 32
316 * logical, single endpoints instead. */
317 MUSBEndPoint ep[16];
318 } *musb_init(qemu_irq *irqs)
319 {
320 MUSBState *s = qemu_mallocz(sizeof(*s));
321 int i;
322
323 s->irqs = irqs;
324
325 s->faddr = 0x00;
326 s->power = MGC_M_POWER_HSENAB;
327 s->tx_intr = 0x0000;
328 s->rx_intr = 0x0000;
329 s->tx_mask = 0xffff;
330 s->rx_mask = 0xffff;
331 s->intr = 0x00;
332 s->mask = 0x06;
333 s->idx = 0;
334
335 /* TODO: _DW */
336 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
337 for (i = 0; i < 16; i ++) {
338 s->ep[i].fifosize = 64;
339 s->ep[i].maxp[0] = 0x40;
340 s->ep[i].maxp[1] = 0x40;
341 s->ep[i].musb = s;
342 s->ep[i].epnum = i;
343 }
344
345 usb_bus_new(&s->bus, NULL /* FIXME */);
346 usb_register_port(&s->bus, &s->port, s, 0, musb_attach);
347
348 return s;
349 }
350
351 static void musb_vbus_set(MUSBState *s, int level)
352 {
353 if (level)
354 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
355 else
356 s->devctl &= ~MGC_M_DEVCTL_VBUS;
357
358 qemu_set_irq(s->irqs[musb_set_vbus], level);
359 }
360
361 static void musb_intr_set(MUSBState *s, int line, int level)
362 {
363 if (!level) {
364 s->intr &= ~(1 << line);
365 qemu_irq_lower(s->irqs[line]);
366 } else if (s->mask & (1 << line)) {
367 s->intr |= 1 << line;
368 qemu_irq_raise(s->irqs[line]);
369 }
370 }
371
372 static void musb_tx_intr_set(MUSBState *s, int line, int level)
373 {
374 if (!level) {
375 s->tx_intr &= ~(1 << line);
376 if (!s->tx_intr)
377 qemu_irq_lower(s->irqs[musb_irq_tx]);
378 } else if (s->tx_mask & (1 << line)) {
379 s->tx_intr |= 1 << line;
380 qemu_irq_raise(s->irqs[musb_irq_tx]);
381 }
382 }
383
384 static void musb_rx_intr_set(MUSBState *s, int line, int level)
385 {
386 if (line) {
387 if (!level) {
388 s->rx_intr &= ~(1 << line);
389 if (!s->rx_intr)
390 qemu_irq_lower(s->irqs[musb_irq_rx]);
391 } else if (s->rx_mask & (1 << line)) {
392 s->rx_intr |= 1 << line;
393 qemu_irq_raise(s->irqs[musb_irq_rx]);
394 }
395 } else
396 musb_tx_intr_set(s, line, level);
397 }
398
399 uint32_t musb_core_intr_get(MUSBState *s)
400 {
401 return (s->rx_intr << 15) | s->tx_intr;
402 }
403
404 void musb_core_intr_clear(MUSBState *s, uint32_t mask)
405 {
406 if (s->rx_intr) {
407 s->rx_intr &= mask >> 15;
408 if (!s->rx_intr)
409 qemu_irq_lower(s->irqs[musb_irq_rx]);
410 }
411
412 if (s->tx_intr) {
413 s->tx_intr &= mask & 0xffff;
414 if (!s->tx_intr)
415 qemu_irq_lower(s->irqs[musb_irq_tx]);
416 }
417 }
418
419 void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
420 {
421 s->ep[epnum].ext_size[!is_tx] = size;
422 s->ep[epnum].fifostart[0] = 0;
423 s->ep[epnum].fifostart[1] = 0;
424 s->ep[epnum].fifolen[0] = 0;
425 s->ep[epnum].fifolen[1] = 0;
426 }
427
428 static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
429 {
430 int detect_prev = prev_dev && prev_sess;
431 int detect = !!s->port.dev && s->session;
432
433 if (detect && !detect_prev) {
434 /* Let's skip the ID pin sense and VBUS sense formalities and
435 * and signal a successful SRP directly. This should work at least
436 * for the Linux driver stack. */
437 musb_intr_set(s, musb_irq_connect, 1);
438
439 if (s->port.dev->speed == USB_SPEED_LOW) {
440 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
441 s->devctl |= MGC_M_DEVCTL_LSDEV;
442 } else {
443 s->devctl |= MGC_M_DEVCTL_FSDEV;
444 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
445 }
446
447 /* A-mode? */
448 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
449
450 /* Host-mode bit? */
451 s->devctl |= MGC_M_DEVCTL_HM;
452 #if 1
453 musb_vbus_set(s, 1);
454 #endif
455 } else if (!detect && detect_prev) {
456 #if 1
457 musb_vbus_set(s, 0);
458 #endif
459 }
460 }
461
462 /* Attach or detach a device on our only port. */
463 static void musb_attach(USBPort *port, USBDevice *dev)
464 {
465 MUSBState *s = (MUSBState *) port->opaque;
466 USBDevice *curr;
467
468 port = &s->port;
469 curr = port->dev;
470
471 if (dev) {
472 if (curr) {
473 usb_attach(port, NULL);
474 /* TODO: signal some interrupts */
475 }
476
477 musb_intr_set(s, musb_irq_vbus_request, 1);
478
479 /* Send the attach message to device */
480 usb_send_msg(dev, USB_MSG_ATTACH);
481 } else if (curr) {
482 /* Send the detach message */
483 usb_send_msg(curr, USB_MSG_DETACH);
484
485 musb_intr_set(s, musb_irq_disconnect, 1);
486 }
487
488 port->dev = dev;
489
490 musb_session_update(s, !!curr, s->session);
491 }
492
493 static inline void musb_cb_tick0(void *opaque)
494 {
495 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
496
497 ep->delayed_cb[0](&ep->packey[0], opaque);
498 }
499
500 static inline void musb_cb_tick1(void *opaque)
501 {
502 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
503
504 ep->delayed_cb[1](&ep->packey[1], opaque);
505 }
506
507 #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
508
509 static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
510 {
511 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
512 int timeout = 0;
513
514 if (ep->status[dir] == USB_RET_NAK)
515 timeout = ep->timeout[dir];
516 else if (ep->interrupt[dir])
517 timeout = 8;
518 else
519 return musb_cb_tick(opaque);
520
521 if (!ep->intv_timer[dir])
522 ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque);
523
524 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) +
525 muldiv64(timeout, get_ticks_per_sec(), 8000));
526 }
527
528 static void musb_schedule0_cb(USBPacket *packey, void *opaque)
529 {
530 return musb_schedule_cb(packey, opaque, 0);
531 }
532
533 static void musb_schedule1_cb(USBPacket *packey, void *opaque)
534 {
535 return musb_schedule_cb(packey, opaque, 1);
536 }
537
538 static int musb_timeout(int ttype, int speed, int val)
539 {
540 #if 1
541 return val << 3;
542 #endif
543
544 switch (ttype) {
545 case USB_ENDPOINT_XFER_CONTROL:
546 if (val < 2)
547 return 0;
548 else if (speed == USB_SPEED_HIGH)
549 return 1 << (val - 1);
550 else
551 return 8 << (val - 1);
552
553 case USB_ENDPOINT_XFER_INT:
554 if (speed == USB_SPEED_HIGH)
555 if (val < 2)
556 return 0;
557 else
558 return 1 << (val - 1);
559 else
560 return val << 3;
561
562 case USB_ENDPOINT_XFER_BULK:
563 case USB_ENDPOINT_XFER_ISOC:
564 if (val < 2)
565 return 0;
566 else if (speed == USB_SPEED_HIGH)
567 return 1 << (val - 1);
568 else
569 return 8 << (val - 1);
570 /* TODO: what with low-speed Bulk and Isochronous? */
571 }
572
573 hw_error("bad interval\n");
574 }
575
576 static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
577 int epnum, int pid, int len, USBCallback cb, int dir)
578 {
579 int ret;
580 int idx = epnum && dir;
581 int ttype;
582
583 /* ep->type[0,1] contains:
584 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
585 * in bits 5:4 the transfer type (BULK / INT)
586 * in bits 3:0 the EP num
587 */
588 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
589
590 ep->timeout[dir] = musb_timeout(ttype,
591 ep->type[idx] >> 6, ep->interval[idx]);
592 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
593 ep->delayed_cb[dir] = cb;
594 cb = dir ? musb_schedule1_cb : musb_schedule0_cb;
595
596 ep->packey[dir].pid = pid;
597 /* A wild guess on the FADDR semantics... */
598 ep->packey[dir].devaddr = ep->faddr[idx];
599 ep->packey[dir].devep = ep->type[idx] & 0xf;
600 ep->packey[dir].data = (void *) ep->buf[idx];
601 ep->packey[dir].len = len;
602 ep->packey[dir].complete_cb = cb;
603 ep->packey[dir].complete_opaque = ep;
604
605 if (s->port.dev)
606 ret = s->port.dev->info->handle_packet(s->port.dev, &ep->packey[dir]);
607 else
608 ret = USB_RET_NODEV;
609
610 if (ret == USB_RET_ASYNC) {
611 ep->status[dir] = len;
612 return;
613 }
614
615 ep->status[dir] = ret;
616 usb_packet_complete(&ep->packey[dir]);
617 }
618
619 static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
620 {
621 /* Unfortunately we can't use packey->devep because that's the remote
622 * endpoint number and may be different than our local. */
623 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
624 int epnum = ep->epnum;
625 MUSBState *s = ep->musb;
626
627 ep->fifostart[0] = 0;
628 ep->fifolen[0] = 0;
629 #ifdef CLEAR_NAK
630 if (ep->status[0] != USB_RET_NAK) {
631 #endif
632 if (epnum)
633 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
634 else
635 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
636 #ifdef CLEAR_NAK
637 }
638 #endif
639
640 /* Clear all of the error bits first */
641 if (epnum)
642 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
643 MGC_M_TXCSR_H_NAKTIMEOUT);
644 else
645 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
646 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
647
648 if (ep->status[0] == USB_RET_STALL) {
649 /* Command not supported by target! */
650 ep->status[0] = 0;
651
652 if (epnum)
653 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
654 else
655 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
656 }
657
658 if (ep->status[0] == USB_RET_NAK) {
659 ep->status[0] = 0;
660
661 /* NAK timeouts are only generated in Bulk transfers and
662 * Data-errors in Isochronous. */
663 if (ep->interrupt[0]) {
664 return;
665 }
666
667 if (epnum)
668 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
669 else
670 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
671 }
672
673 if (ep->status[0] < 0) {
674 if (ep->status[0] == USB_RET_BABBLE)
675 musb_intr_set(s, musb_irq_rst_babble, 1);
676
677 /* Pretend we've tried three times already and failed (in
678 * case of USB_TOKEN_SETUP). */
679 if (epnum)
680 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
681 else
682 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
683
684 musb_tx_intr_set(s, epnum, 1);
685 return;
686 }
687 /* TODO: check len for over/underruns of an OUT packet? */
688
689 #ifdef SETUPLEN_HACK
690 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
691 s->setup_len = ep->packey[0].data[6];
692 #endif
693
694 /* In DMA mode: if no error, assert DMA request for this EP,
695 * and skip the interrupt. */
696 musb_tx_intr_set(s, epnum, 1);
697 }
698
699 static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
700 {
701 /* Unfortunately we can't use packey->devep because that's the remote
702 * endpoint number and may be different than our local. */
703 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
704 int epnum = ep->epnum;
705 MUSBState *s = ep->musb;
706
707 ep->fifostart[1] = 0;
708 ep->fifolen[1] = 0;
709
710 #ifdef CLEAR_NAK
711 if (ep->status[1] != USB_RET_NAK) {
712 #endif
713 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
714 if (!epnum)
715 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
716 #ifdef CLEAR_NAK
717 }
718 #endif
719
720 /* Clear all of the imaginable error bits first */
721 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
722 MGC_M_RXCSR_DATAERROR);
723 if (!epnum)
724 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
725 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
726
727 if (ep->status[1] == USB_RET_STALL) {
728 ep->status[1] = 0;
729 packey->len = 0;
730
731 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
732 if (!epnum)
733 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
734 }
735
736 if (ep->status[1] == USB_RET_NAK) {
737 ep->status[1] = 0;
738
739 /* NAK timeouts are only generated in Bulk transfers and
740 * Data-errors in Isochronous. */
741 if (ep->interrupt[1])
742 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
743 packey->len, musb_rx_packet_complete, 1);
744
745 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
746 if (!epnum)
747 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
748 }
749
750 if (ep->status[1] < 0) {
751 if (ep->status[1] == USB_RET_BABBLE) {
752 musb_intr_set(s, musb_irq_rst_babble, 1);
753 return;
754 }
755
756 /* Pretend we've tried three times already and failed (in
757 * case of a control transfer). */
758 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
759 if (!epnum)
760 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
761
762 musb_rx_intr_set(s, epnum, 1);
763 return;
764 }
765 /* TODO: check len for over/underruns of an OUT packet? */
766 /* TODO: perhaps make use of e->ext_size[1] here. */
767
768 packey->len = ep->status[1];
769
770 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
771 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
772 if (!epnum)
773 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
774
775 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
776 /* In DMA mode: assert DMA request for this EP */
777 }
778
779 /* Only if DMA has not been asserted */
780 musb_rx_intr_set(s, epnum, 1);
781 }
782
783 static void musb_tx_rdy(MUSBState *s, int epnum)
784 {
785 MUSBEndPoint *ep = s->ep + epnum;
786 int pid;
787 int total, valid = 0;
788 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
789 ep->fifostart[0] += ep->fifolen[0];
790 ep->fifolen[0] = 0;
791
792 /* XXX: how's the total size of the packet retrieved exactly in
793 * the generic case? */
794 total = ep->maxp[0] & 0x3ff;
795
796 if (ep->ext_size[0]) {
797 total = ep->ext_size[0];
798 ep->ext_size[0] = 0;
799 valid = 1;
800 }
801
802 /* If the packet is not fully ready yet, wait for a next segment. */
803 if (epnum && (ep->fifostart[0]) < total)
804 return;
805
806 if (!valid)
807 total = ep->fifostart[0];
808
809 pid = USB_TOKEN_OUT;
810 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
811 pid = USB_TOKEN_SETUP;
812 if (total != 8) {
813 TRACE("illegal SETUPPKT length of %i bytes", total);
814 }
815 /* Controller should retry SETUP packets three times on errors
816 * but it doesn't make sense for us to do that. */
817 }
818
819 return musb_packet(s, ep, epnum, pid,
820 total, musb_tx_packet_complete, 0);
821 }
822
823 static void musb_rx_req(MUSBState *s, int epnum)
824 {
825 MUSBEndPoint *ep = s->ep + epnum;
826 int total;
827
828 /* If we already have a packet, which didn't fit into the
829 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
830 if (ep->packey[1].pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
831 (ep->fifostart[1]) + ep->rxcount <
832 ep->packey[1].len) {
833 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
834 ep->fifostart[1] += ep->rxcount;
835 ep->fifolen[1] = 0;
836
837 ep->rxcount = MIN(ep->packey[0].len - (ep->fifostart[1]),
838 ep->maxp[1]);
839
840 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
841 if (!epnum)
842 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
843
844 /* Clear all of the error bits first */
845 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
846 MGC_M_RXCSR_DATAERROR);
847 if (!epnum)
848 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
849 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
850
851 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
852 if (!epnum)
853 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
854 musb_rx_intr_set(s, epnum, 1);
855 return;
856 }
857
858 /* The driver sets maxp[1] to 64 or less because it knows the hardware
859 * FIFO is this deep. Bigger packets get split in
860 * usb_generic_handle_packet but we can also do the splitting locally
861 * for performance. It turns out we can also have a bigger FIFO and
862 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
863 * OK with single packets of even 32KB and we avoid splitting, however
864 * usb_msd.c sometimes sends a packet bigger than what Linux expects
865 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
866 * hides this overrun from Linux. Up to 4096 everything is fine
867 * though. Currently this is disabled.
868 *
869 * XXX: mind ep->fifosize. */
870 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
871
872 #ifdef SETUPLEN_HACK
873 /* Why should *we* do that instead of Linux? */
874 if (!epnum) {
875 if (ep->packey[0].devaddr == 2)
876 total = MIN(s->setup_len, 8);
877 else
878 total = MIN(s->setup_len, 64);
879 s->setup_len -= total;
880 }
881 #endif
882
883 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
884 total, musb_rx_packet_complete, 1);
885 }
886
887 static uint8_t musb_read_fifo(MUSBEndPoint *ep)
888 {
889 uint8_t value;
890 if (ep->fifolen[1] >= 64) {
891 /* We have a FIFO underrun */
892 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
893 return 0x00000000;
894 }
895 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
896 * (if AUTOREQ is set) */
897
898 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
899 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
900 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
901 return value;
902 }
903
904 static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
905 {
906 TRACE("EP%d = %02x", ep->epnum, value);
907 if (ep->fifolen[0] >= 64) {
908 /* We have a FIFO overrun */
909 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
910 return;
911 }
912
913 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
914 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
915 }
916
917 static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
918 {
919 if (ep->intv_timer[dir])
920 qemu_del_timer(ep->intv_timer[dir]);
921 }
922
923 /* Bus control */
924 static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
925 {
926 MUSBState *s = (MUSBState *) opaque;
927
928 switch (addr) {
929 /* For USB2.0 HS hubs only */
930 case MUSB_HDRC_TXHUBADDR:
931 return s->ep[ep].haddr[0];
932 case MUSB_HDRC_TXHUBPORT:
933 return s->ep[ep].hport[0];
934 case MUSB_HDRC_RXHUBADDR:
935 return s->ep[ep].haddr[1];
936 case MUSB_HDRC_RXHUBPORT:
937 return s->ep[ep].hport[1];
938
939 default:
940 TRACE("unknown register 0x%02x", addr);
941 return 0x00;
942 };
943 }
944
945 static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
946 {
947 MUSBState *s = (MUSBState *) opaque;
948
949 switch (addr) {
950 case MUSB_HDRC_TXFUNCADDR:
951 s->ep[ep].faddr[0] = value;
952 break;
953 case MUSB_HDRC_RXFUNCADDR:
954 s->ep[ep].faddr[1] = value;
955 break;
956 case MUSB_HDRC_TXHUBADDR:
957 s->ep[ep].haddr[0] = value;
958 break;
959 case MUSB_HDRC_TXHUBPORT:
960 s->ep[ep].hport[0] = value;
961 break;
962 case MUSB_HDRC_RXHUBADDR:
963 s->ep[ep].haddr[1] = value;
964 break;
965 case MUSB_HDRC_RXHUBPORT:
966 s->ep[ep].hport[1] = value;
967 break;
968
969 default:
970 TRACE("unknown register 0x%02x", addr);
971 break;
972 };
973 }
974
975 static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
976 {
977 MUSBState *s = (MUSBState *) opaque;
978
979 switch (addr) {
980 case MUSB_HDRC_TXFUNCADDR:
981 return s->ep[ep].faddr[0];
982 case MUSB_HDRC_RXFUNCADDR:
983 return s->ep[ep].faddr[1];
984
985 default:
986 return musb_busctl_readb(s, ep, addr) |
987 (musb_busctl_readb(s, ep, addr | 1) << 8);
988 };
989 }
990
991 static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
992 {
993 MUSBState *s = (MUSBState *) opaque;
994
995 switch (addr) {
996 case MUSB_HDRC_TXFUNCADDR:
997 s->ep[ep].faddr[0] = value;
998 break;
999 case MUSB_HDRC_RXFUNCADDR:
1000 s->ep[ep].faddr[1] = value;
1001 break;
1002
1003 default:
1004 musb_busctl_writeb(s, ep, addr, value & 0xff);
1005 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1006 };
1007 }
1008
1009 /* Endpoint control */
1010 static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1011 {
1012 MUSBState *s = (MUSBState *) opaque;
1013
1014 switch (addr) {
1015 case MUSB_HDRC_TXTYPE:
1016 return s->ep[ep].type[0];
1017 case MUSB_HDRC_TXINTERVAL:
1018 return s->ep[ep].interval[0];
1019 case MUSB_HDRC_RXTYPE:
1020 return s->ep[ep].type[1];
1021 case MUSB_HDRC_RXINTERVAL:
1022 return s->ep[ep].interval[1];
1023 case (MUSB_HDRC_FIFOSIZE & ~1):
1024 return 0x00;
1025 case MUSB_HDRC_FIFOSIZE:
1026 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
1027 case MUSB_HDRC_RXCOUNT:
1028 return s->ep[ep].rxcount;
1029
1030 default:
1031 TRACE("unknown register 0x%02x", addr);
1032 return 0x00;
1033 };
1034 }
1035
1036 static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1037 {
1038 MUSBState *s = (MUSBState *) opaque;
1039
1040 switch (addr) {
1041 case MUSB_HDRC_TXTYPE:
1042 s->ep[ep].type[0] = value;
1043 break;
1044 case MUSB_HDRC_TXINTERVAL:
1045 s->ep[ep].interval[0] = value;
1046 musb_ep_frame_cancel(&s->ep[ep], 0);
1047 break;
1048 case MUSB_HDRC_RXTYPE:
1049 s->ep[ep].type[1] = value;
1050 break;
1051 case MUSB_HDRC_RXINTERVAL:
1052 s->ep[ep].interval[1] = value;
1053 musb_ep_frame_cancel(&s->ep[ep], 1);
1054 break;
1055 case (MUSB_HDRC_FIFOSIZE & ~1):
1056 break;
1057 case MUSB_HDRC_FIFOSIZE:
1058 TRACE("somebody messes with fifosize (now %i bytes)", value);
1059 s->ep[ep].fifosize = value;
1060 break;
1061 default:
1062 TRACE("unknown register 0x%02x", addr);
1063 break;
1064 };
1065 }
1066
1067 static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1068 {
1069 MUSBState *s = (MUSBState *) opaque;
1070 uint16_t ret;
1071
1072 switch (addr) {
1073 case MUSB_HDRC_TXMAXP:
1074 return s->ep[ep].maxp[0];
1075 case MUSB_HDRC_TXCSR:
1076 return s->ep[ep].csr[0];
1077 case MUSB_HDRC_RXMAXP:
1078 return s->ep[ep].maxp[1];
1079 case MUSB_HDRC_RXCSR:
1080 ret = s->ep[ep].csr[1];
1081
1082 /* TODO: This and other bits probably depend on
1083 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1084 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1085 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1086
1087 return ret;
1088 case MUSB_HDRC_RXCOUNT:
1089 return s->ep[ep].rxcount;
1090
1091 default:
1092 return musb_ep_readb(s, ep, addr) |
1093 (musb_ep_readb(s, ep, addr | 1) << 8);
1094 };
1095 }
1096
1097 static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1098 {
1099 MUSBState *s = (MUSBState *) opaque;
1100
1101 switch (addr) {
1102 case MUSB_HDRC_TXMAXP:
1103 s->ep[ep].maxp[0] = value;
1104 break;
1105 case MUSB_HDRC_TXCSR:
1106 if (ep) {
1107 s->ep[ep].csr[0] &= value & 0xa6;
1108 s->ep[ep].csr[0] |= value & 0xff59;
1109 } else {
1110 s->ep[ep].csr[0] &= value & 0x85;
1111 s->ep[ep].csr[0] |= value & 0xf7a;
1112 }
1113
1114 musb_ep_frame_cancel(&s->ep[ep], 0);
1115
1116 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1117 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1118 s->ep[ep].fifolen[0] = 0;
1119 s->ep[ep].fifostart[0] = 0;
1120 if (ep)
1121 s->ep[ep].csr[0] &=
1122 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1123 else
1124 s->ep[ep].csr[0] &=
1125 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1126 }
1127 if (
1128 (ep &&
1129 #ifdef CLEAR_NAK
1130 (value & MGC_M_TXCSR_TXPKTRDY) &&
1131 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1132 #else
1133 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1134 #endif
1135 (!ep &&
1136 #ifdef CLEAR_NAK
1137 (value & MGC_M_CSR0_TXPKTRDY) &&
1138 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1139 #else
1140 (value & MGC_M_CSR0_TXPKTRDY)))
1141 #endif
1142 musb_tx_rdy(s, ep);
1143 if (!ep &&
1144 (value & MGC_M_CSR0_H_REQPKT) &&
1145 #ifdef CLEAR_NAK
1146 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1147 MGC_M_CSR0_RXPKTRDY)))
1148 #else
1149 !(value & MGC_M_CSR0_RXPKTRDY))
1150 #endif
1151 musb_rx_req(s, ep);
1152 break;
1153
1154 case MUSB_HDRC_RXMAXP:
1155 s->ep[ep].maxp[1] = value;
1156 break;
1157 case MUSB_HDRC_RXCSR:
1158 /* (DMA mode only) */
1159 if (
1160 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1161 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1162 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1163 value |= MGC_M_RXCSR_H_REQPKT;
1164
1165 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1166 s->ep[ep].csr[1] |= value & 0xfeb0;
1167
1168 musb_ep_frame_cancel(&s->ep[ep], 1);
1169
1170 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1171 s->ep[ep].fifolen[1] = 0;
1172 s->ep[ep].fifostart[1] = 0;
1173 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1174 /* If double buffering and we have two packets ready, flush
1175 * only the first one and set up the fifo at the second packet. */
1176 }
1177 #ifdef CLEAR_NAK
1178 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1179 #else
1180 if (value & MGC_M_RXCSR_H_REQPKT)
1181 #endif
1182 musb_rx_req(s, ep);
1183 break;
1184 case MUSB_HDRC_RXCOUNT:
1185 s->ep[ep].rxcount = value;
1186 break;
1187
1188 default:
1189 musb_ep_writeb(s, ep, addr, value & 0xff);
1190 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1191 };
1192 }
1193
1194 /* Generic control */
1195 static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
1196 {
1197 MUSBState *s = (MUSBState *) opaque;
1198 int ep, i;
1199 uint8_t ret;
1200
1201 switch (addr) {
1202 case MUSB_HDRC_FADDR:
1203 return s->faddr;
1204 case MUSB_HDRC_POWER:
1205 return s->power;
1206 case MUSB_HDRC_INTRUSB:
1207 ret = s->intr;
1208 for (i = 0; i < sizeof(ret) * 8; i ++)
1209 if (ret & (1 << i))
1210 musb_intr_set(s, i, 0);
1211 return ret;
1212 case MUSB_HDRC_INTRUSBE:
1213 return s->mask;
1214 case MUSB_HDRC_INDEX:
1215 return s->idx;
1216 case MUSB_HDRC_TESTMODE:
1217 return 0x00;
1218
1219 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1220 return musb_ep_readb(s, s->idx, addr & 0xf);
1221
1222 case MUSB_HDRC_DEVCTL:
1223 return s->devctl;
1224
1225 case MUSB_HDRC_TXFIFOSZ:
1226 case MUSB_HDRC_RXFIFOSZ:
1227 case MUSB_HDRC_VCTRL:
1228 /* TODO */
1229 return 0x00;
1230
1231 case MUSB_HDRC_HWVERS:
1232 return (1 << 10) | 400;
1233
1234 case (MUSB_HDRC_VCTRL | 1):
1235 case (MUSB_HDRC_HWVERS | 1):
1236 case (MUSB_HDRC_DEVCTL | 1):
1237 return 0x00;
1238
1239 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1240 ep = (addr >> 3) & 0xf;
1241 return musb_busctl_readb(s, ep, addr & 0x7);
1242
1243 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1244 ep = (addr >> 4) & 0xf;
1245 return musb_ep_readb(s, ep, addr & 0xf);
1246
1247 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1248 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1249 return musb_read_fifo(s->ep + ep);
1250
1251 default:
1252 TRACE("unknown register 0x%02x", (int) addr);
1253 return 0x00;
1254 };
1255 }
1256
1257 static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1258 {
1259 MUSBState *s = (MUSBState *) opaque;
1260 int ep;
1261
1262 switch (addr) {
1263 case MUSB_HDRC_FADDR:
1264 s->faddr = value & 0x7f;
1265 break;
1266 case MUSB_HDRC_POWER:
1267 s->power = (value & 0xef) | (s->power & 0x10);
1268 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1269 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1270 usb_send_msg(s->port.dev, USB_MSG_RESET);
1271 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1272 if ((value & MGC_M_POWER_HSENAB) &&
1273 s->port.dev->speed == USB_SPEED_HIGH)
1274 s->power |= MGC_M_POWER_HSMODE; /* Success */
1275 /* Restart frame counting. */
1276 }
1277 if (value & MGC_M_POWER_SUSPENDM) {
1278 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1279 * is set, also go into low power mode. Frame counting stops. */
1280 /* XXX: Cleared when the interrupt register is read */
1281 }
1282 if (value & MGC_M_POWER_RESUME) {
1283 /* Wait 20ms and signal resuming on the bus. Frame counting
1284 * restarts. */
1285 }
1286 break;
1287 case MUSB_HDRC_INTRUSB:
1288 break;
1289 case MUSB_HDRC_INTRUSBE:
1290 s->mask = value & 0xff;
1291 break;
1292 case MUSB_HDRC_INDEX:
1293 s->idx = value & 0xf;
1294 break;
1295 case MUSB_HDRC_TESTMODE:
1296 break;
1297
1298 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1299 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1300 break;
1301
1302 case MUSB_HDRC_DEVCTL:
1303 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1304 musb_session_update(s,
1305 !!s->port.dev,
1306 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1307
1308 /* It seems this is the only R/W bit in this register? */
1309 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1310 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1311 break;
1312
1313 case MUSB_HDRC_TXFIFOSZ:
1314 case MUSB_HDRC_RXFIFOSZ:
1315 case MUSB_HDRC_VCTRL:
1316 /* TODO */
1317 break;
1318
1319 case (MUSB_HDRC_VCTRL | 1):
1320 case (MUSB_HDRC_DEVCTL | 1):
1321 break;
1322
1323 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1324 ep = (addr >> 3) & 0xf;
1325 musb_busctl_writeb(s, ep, addr & 0x7, value);
1326 break;
1327
1328 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1329 ep = (addr >> 4) & 0xf;
1330 musb_ep_writeb(s, ep, addr & 0xf, value);
1331 break;
1332
1333 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1334 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1335 musb_write_fifo(s->ep + ep, value & 0xff);
1336 break;
1337
1338 default:
1339 TRACE("unknown register 0x%02x", (int) addr);
1340 break;
1341 };
1342 }
1343
1344 static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
1345 {
1346 MUSBState *s = (MUSBState *) opaque;
1347 int ep, i;
1348 uint16_t ret;
1349
1350 switch (addr) {
1351 case MUSB_HDRC_INTRTX:
1352 ret = s->tx_intr;
1353 /* Auto clear */
1354 for (i = 0; i < sizeof(ret) * 8; i ++)
1355 if (ret & (1 << i))
1356 musb_tx_intr_set(s, i, 0);
1357 return ret;
1358 case MUSB_HDRC_INTRRX:
1359 ret = s->rx_intr;
1360 /* Auto clear */
1361 for (i = 0; i < sizeof(ret) * 8; i ++)
1362 if (ret & (1 << i))
1363 musb_rx_intr_set(s, i, 0);
1364 return ret;
1365 case MUSB_HDRC_INTRTXE:
1366 return s->tx_mask;
1367 case MUSB_HDRC_INTRRXE:
1368 return s->rx_mask;
1369
1370 case MUSB_HDRC_FRAME:
1371 /* TODO */
1372 return 0x0000;
1373 case MUSB_HDRC_TXFIFOADDR:
1374 return s->ep[s->idx].fifoaddr[0];
1375 case MUSB_HDRC_RXFIFOADDR:
1376 return s->ep[s->idx].fifoaddr[1];
1377
1378 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1379 return musb_ep_readh(s, s->idx, addr & 0xf);
1380
1381 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1382 ep = (addr >> 3) & 0xf;
1383 return musb_busctl_readh(s, ep, addr & 0x7);
1384
1385 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1386 ep = (addr >> 4) & 0xf;
1387 return musb_ep_readh(s, ep, addr & 0xf);
1388
1389 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1390 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1391 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1392
1393 default:
1394 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1395 };
1396 }
1397
1398 static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1399 {
1400 MUSBState *s = (MUSBState *) opaque;
1401 int ep;
1402
1403 switch (addr) {
1404 case MUSB_HDRC_INTRTXE:
1405 s->tx_mask = value;
1406 /* XXX: the masks seem to apply on the raising edge like with
1407 * edge-triggered interrupts, thus no need to update. I may be
1408 * wrong though. */
1409 break;
1410 case MUSB_HDRC_INTRRXE:
1411 s->rx_mask = value;
1412 break;
1413
1414 case MUSB_HDRC_FRAME:
1415 /* TODO */
1416 break;
1417 case MUSB_HDRC_TXFIFOADDR:
1418 s->ep[s->idx].fifoaddr[0] = value;
1419 s->ep[s->idx].buf[0] =
1420 s->buf + ((value << 3) & 0x7ff );
1421 break;
1422 case MUSB_HDRC_RXFIFOADDR:
1423 s->ep[s->idx].fifoaddr[1] = value;
1424 s->ep[s->idx].buf[1] =
1425 s->buf + ((value << 3) & 0x7ff);
1426 break;
1427
1428 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1429 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1430 break;
1431
1432 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1433 ep = (addr >> 3) & 0xf;
1434 musb_busctl_writeh(s, ep, addr & 0x7, value);
1435 break;
1436
1437 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1438 ep = (addr >> 4) & 0xf;
1439 musb_ep_writeh(s, ep, addr & 0xf, value);
1440 break;
1441
1442 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1443 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1444 musb_write_fifo(s->ep + ep, value & 0xff);
1445 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1446 break;
1447
1448 default:
1449 musb_writeb(s, addr, value & 0xff);
1450 musb_writeb(s, addr | 1, value >> 8);
1451 };
1452 }
1453
1454 static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
1455 {
1456 MUSBState *s = (MUSBState *) opaque;
1457 int ep;
1458
1459 switch (addr) {
1460 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1461 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1462 return ( musb_read_fifo(s->ep + ep) |
1463 musb_read_fifo(s->ep + ep) << 8 |
1464 musb_read_fifo(s->ep + ep) << 16 |
1465 musb_read_fifo(s->ep + ep) << 24 );
1466 default:
1467 TRACE("unknown register 0x%02x", (int) addr);
1468 return 0x00000000;
1469 };
1470 }
1471
1472 static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1473 {
1474 MUSBState *s = (MUSBState *) opaque;
1475 int ep;
1476
1477 switch (addr) {
1478 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1479 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1480 musb_write_fifo(s->ep + ep, value & 0xff);
1481 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1482 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1483 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
1484 break;
1485 default:
1486 TRACE("unknown register 0x%02x", (int) addr);
1487 break;
1488 };
1489 }
1490
1491 CPUReadMemoryFunc * const musb_read[] = {
1492 musb_readb,
1493 musb_readh,
1494 musb_readw,
1495 };
1496
1497 CPUWriteMemoryFunc * const musb_write[] = {
1498 musb_writeb,
1499 musb_writeh,
1500 musb_writew,
1501 };
QEmu