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x3130/downstream: support aer.
[qemu.git] / hw / ppc405_uc.c
blob360073741268cfc5d41c64142662dc0f63cd14f5
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_phys(bdloc + 0x00, bd->bi_memstart);
55 stl_phys(bdloc + 0x04, bd->bi_memsize);
56 stl_phys(bdloc + 0x08, bd->bi_flashstart);
57 stl_phys(bdloc + 0x0C, bd->bi_flashsize);
58 stl_phys(bdloc + 0x10, bd->bi_flashoffset);
59 stl_phys(bdloc + 0x14, bd->bi_sramstart);
60 stl_phys(bdloc + 0x18, bd->bi_sramsize);
61 stl_phys(bdloc + 0x1C, bd->bi_bootflags);
62 stl_phys(bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++)
64 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
66 stl_phys(bdloc + 0x2C, bd->bi_intfreq);
67 stl_phys(bdloc + 0x30, bd->bi_busfreq);
68 stl_phys(bdloc + 0x34, bd->bi_baudrate);
69 for (i = 0; i < 4; i++)
70 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
71 for (i = 0; i < 32; i++)
72 stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
73 stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
74 stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
75 for (i = 0; i < 6; i++)
76 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
77 n = 0x6A;
78 if (flags & 0x00000001) {
79 for (i = 0; i < 6; i++)
80 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
81 }
82 stl_phys(bdloc + n, bd->bi_opbfreq);
83 n += 4;
84 for (i = 0; i < 2; i++) {
85 stl_phys(bdloc + n, bd->bi_iic_fast[i]);
86 n += 4;
87 }
88
89 return bdloc;
90 }
91
92 /*****************************************************************************/
93 /* Shared peripherals */
94
95 /*****************************************************************************/
96 /* Peripheral local bus arbitrer */
97 enum {
98 PLB0_BESR = 0x084,
99 PLB0_BEAR = 0x086,
100 PLB0_ACR = 0x087,
101 };
102
103 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
104 struct ppc4xx_plb_t {
105 uint32_t acr;
106 uint32_t bear;
107 uint32_t besr;
108 };
109
110 static uint32_t dcr_read_plb (void *opaque, int dcrn)
111 {
112 ppc4xx_plb_t *plb;
113 uint32_t ret;
114
115 plb = opaque;
116 switch (dcrn) {
117 case PLB0_ACR:
118 ret = plb->acr;
119 break;
120 case PLB0_BEAR:
121 ret = plb->bear;
122 break;
123 case PLB0_BESR:
124 ret = plb->besr;
125 break;
126 default:
127 /* Avoid gcc warning */
128 ret = 0;
129 break;
130 }
131
132 return ret;
133 }
134
135 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
136 {
137 ppc4xx_plb_t *plb;
138
139 plb = opaque;
140 switch (dcrn) {
141 case PLB0_ACR:
142 /* We don't care about the actual parameters written as
143 * we don't manage any priorities on the bus
144 */
145 plb->acr = val & 0xF8000000;
146 break;
147 case PLB0_BEAR:
148 /* Read only */
149 break;
150 case PLB0_BESR:
151 /* Write-clear */
152 plb->besr &= ~val;
153 break;
154 }
155 }
156
157 static void ppc4xx_plb_reset (void *opaque)
158 {
159 ppc4xx_plb_t *plb;
160
161 plb = opaque;
162 plb->acr = 0x00000000;
163 plb->bear = 0x00000000;
164 plb->besr = 0x00000000;
165 }
166
167 static void ppc4xx_plb_init(CPUState *env)
168 {
169 ppc4xx_plb_t *plb;
170
171 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
172 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
173 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
174 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
175 qemu_register_reset(ppc4xx_plb_reset, plb);
176 }
177
178 /*****************************************************************************/
179 /* PLB to OPB bridge */
180 enum {
181 POB0_BESR0 = 0x0A0,
182 POB0_BESR1 = 0x0A2,
183 POB0_BEAR = 0x0A4,
184 };
185
186 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
187 struct ppc4xx_pob_t {
188 uint32_t bear;
189 uint32_t besr[2];
190 };
191
192 static uint32_t dcr_read_pob (void *opaque, int dcrn)
193 {
194 ppc4xx_pob_t *pob;
195 uint32_t ret;
196
197 pob = opaque;
198 switch (dcrn) {
199 case POB0_BEAR:
200 ret = pob->bear;
201 break;
202 case POB0_BESR0:
203 case POB0_BESR1:
204 ret = pob->besr[dcrn - POB0_BESR0];
205 break;
206 default:
207 /* Avoid gcc warning */
208 ret = 0;
209 break;
210 }
211
212 return ret;
213 }
214
215 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
216 {
217 ppc4xx_pob_t *pob;
218
219 pob = opaque;
220 switch (dcrn) {
221 case POB0_BEAR:
222 /* Read only */
223 break;
224 case POB0_BESR0:
225 case POB0_BESR1:
226 /* Write-clear */
227 pob->besr[dcrn - POB0_BESR0] &= ~val;
228 break;
229 }
230 }
231
232 static void ppc4xx_pob_reset (void *opaque)
233 {
234 ppc4xx_pob_t *pob;
235
236 pob = opaque;
237 /* No error */
238 pob->bear = 0x00000000;
239 pob->besr[0] = 0x0000000;
240 pob->besr[1] = 0x0000000;
241 }
242
243 static void ppc4xx_pob_init(CPUState *env)
244 {
245 ppc4xx_pob_t *pob;
246
247 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
248 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
249 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
250 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
251 qemu_register_reset(ppc4xx_pob_reset, pob);
252 }
253
254 /*****************************************************************************/
255 /* OPB arbitrer */
256 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
257 struct ppc4xx_opba_t {
258 uint8_t cr;
259 uint8_t pr;
260 };
261
262 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
263 {
264 ppc4xx_opba_t *opba;
265 uint32_t ret;
266
267 #ifdef DEBUG_OPBA
268 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
269 #endif
270 opba = opaque;
271 switch (addr) {
272 case 0x00:
273 ret = opba->cr;
274 break;
275 case 0x01:
276 ret = opba->pr;
277 break;
278 default:
279 ret = 0x00;
280 break;
281 }
282
283 return ret;
284 }
285
286 static void opba_writeb (void *opaque,
287 target_phys_addr_t addr, uint32_t value)
288 {
289 ppc4xx_opba_t *opba;
290
291 #ifdef DEBUG_OPBA
292 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
293 value);
294 #endif
295 opba = opaque;
296 switch (addr) {
297 case 0x00:
298 opba->cr = value & 0xF8;
299 break;
300 case 0x01:
301 opba->pr = value & 0xFF;
302 break;
303 default:
304 break;
305 }
306 }
307
308 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
309 {
310 uint32_t ret;
311
312 #ifdef DEBUG_OPBA
313 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
314 #endif
315 ret = opba_readb(opaque, addr) << 8;
316 ret |= opba_readb(opaque, addr + 1);
317
318 return ret;
319 }
320
321 static void opba_writew (void *opaque,
322 target_phys_addr_t addr, uint32_t value)
323 {
324 #ifdef DEBUG_OPBA
325 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
326 value);
327 #endif
328 opba_writeb(opaque, addr, value >> 8);
329 opba_writeb(opaque, addr + 1, value);
330 }
331
332 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
333 {
334 uint32_t ret;
335
336 #ifdef DEBUG_OPBA
337 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
338 #endif
339 ret = opba_readb(opaque, addr) << 24;
340 ret |= opba_readb(opaque, addr + 1) << 16;
341
342 return ret;
343 }
344
345 static void opba_writel (void *opaque,
346 target_phys_addr_t addr, uint32_t value)
347 {
348 #ifdef DEBUG_OPBA
349 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
350 value);
351 #endif
352 opba_writeb(opaque, addr, value >> 24);
353 opba_writeb(opaque, addr + 1, value >> 16);
354 }
355
356 static CPUReadMemoryFunc * const opba_read[] = {
357 &opba_readb,
358 &opba_readw,
359 &opba_readl,
360 };
361
362 static CPUWriteMemoryFunc * const opba_write[] = {
363 &opba_writeb,
364 &opba_writew,
365 &opba_writel,
366 };
367
368 static void ppc4xx_opba_reset (void *opaque)
369 {
370 ppc4xx_opba_t *opba;
371
372 opba = opaque;
373 opba->cr = 0x00; /* No dynamic priorities - park disabled */
374 opba->pr = 0x11;
375 }
376
377 static void ppc4xx_opba_init(target_phys_addr_t base)
378 {
379 ppc4xx_opba_t *opba;
380 int io;
381
382 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
383 #ifdef DEBUG_OPBA
384 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
385 #endif
386 io = cpu_register_io_memory(opba_read, opba_write, opba);
387 cpu_register_physical_memory(base, 0x002, io);
388 qemu_register_reset(ppc4xx_opba_reset, opba);
389 }
390
391 /*****************************************************************************/
392 /* Code decompression controller */
393 /* XXX: TODO */
394
395 /*****************************************************************************/
396 /* Peripheral controller */
397 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
398 struct ppc4xx_ebc_t {
399 uint32_t addr;
400 uint32_t bcr[8];
401 uint32_t bap[8];
402 uint32_t bear;
403 uint32_t besr0;
404 uint32_t besr1;
405 uint32_t cfg;
406 };
407
408 enum {
409 EBC0_CFGADDR = 0x012,
410 EBC0_CFGDATA = 0x013,
411 };
412
413 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
414 {
415 ppc4xx_ebc_t *ebc;
416 uint32_t ret;
417
418 ebc = opaque;
419 switch (dcrn) {
420 case EBC0_CFGADDR:
421 ret = ebc->addr;
422 break;
423 case EBC0_CFGDATA:
424 switch (ebc->addr) {
425 case 0x00: /* B0CR */
426 ret = ebc->bcr[0];
427 break;
428 case 0x01: /* B1CR */
429 ret = ebc->bcr[1];
430 break;
431 case 0x02: /* B2CR */
432 ret = ebc->bcr[2];
433 break;
434 case 0x03: /* B3CR */
435 ret = ebc->bcr[3];
436 break;
437 case 0x04: /* B4CR */
438 ret = ebc->bcr[4];
439 break;
440 case 0x05: /* B5CR */
441 ret = ebc->bcr[5];
442 break;
443 case 0x06: /* B6CR */
444 ret = ebc->bcr[6];
445 break;
446 case 0x07: /* B7CR */
447 ret = ebc->bcr[7];
448 break;
449 case 0x10: /* B0AP */
450 ret = ebc->bap[0];
451 break;
452 case 0x11: /* B1AP */
453 ret = ebc->bap[1];
454 break;
455 case 0x12: /* B2AP */
456 ret = ebc->bap[2];
457 break;
458 case 0x13: /* B3AP */
459 ret = ebc->bap[3];
460 break;
461 case 0x14: /* B4AP */
462 ret = ebc->bap[4];
463 break;
464 case 0x15: /* B5AP */
465 ret = ebc->bap[5];
466 break;
467 case 0x16: /* B6AP */
468 ret = ebc->bap[6];
469 break;
470 case 0x17: /* B7AP */
471 ret = ebc->bap[7];
472 break;
473 case 0x20: /* BEAR */
474 ret = ebc->bear;
475 break;
476 case 0x21: /* BESR0 */
477 ret = ebc->besr0;
478 break;
479 case 0x22: /* BESR1 */
480 ret = ebc->besr1;
481 break;
482 case 0x23: /* CFG */
483 ret = ebc->cfg;
484 break;
485 default:
486 ret = 0x00000000;
487 break;
488 }
489 break;
490 default:
491 ret = 0x00000000;
492 break;
493 }
494
495 return ret;
496 }
497
498 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
499 {
500 ppc4xx_ebc_t *ebc;
501
502 ebc = opaque;
503 switch (dcrn) {
504 case EBC0_CFGADDR:
505 ebc->addr = val;
506 break;
507 case EBC0_CFGDATA:
508 switch (ebc->addr) {
509 case 0x00: /* B0CR */
510 break;
511 case 0x01: /* B1CR */
512 break;
513 case 0x02: /* B2CR */
514 break;
515 case 0x03: /* B3CR */
516 break;
517 case 0x04: /* B4CR */
518 break;
519 case 0x05: /* B5CR */
520 break;
521 case 0x06: /* B6CR */
522 break;
523 case 0x07: /* B7CR */
524 break;
525 case 0x10: /* B0AP */
526 break;
527 case 0x11: /* B1AP */
528 break;
529 case 0x12: /* B2AP */
530 break;
531 case 0x13: /* B3AP */
532 break;
533 case 0x14: /* B4AP */
534 break;
535 case 0x15: /* B5AP */
536 break;
537 case 0x16: /* B6AP */
538 break;
539 case 0x17: /* B7AP */
540 break;
541 case 0x20: /* BEAR */
542 break;
543 case 0x21: /* BESR0 */
544 break;
545 case 0x22: /* BESR1 */
546 break;
547 case 0x23: /* CFG */
548 break;
549 default:
550 break;
551 }
552 break;
553 default:
554 break;
555 }
556 }
557
558 static void ebc_reset (void *opaque)
559 {
560 ppc4xx_ebc_t *ebc;
561 int i;
562
563 ebc = opaque;
564 ebc->addr = 0x00000000;
565 ebc->bap[0] = 0x7F8FFE80;
566 ebc->bcr[0] = 0xFFE28000;
567 for (i = 0; i < 8; i++) {
568 ebc->bap[i] = 0x00000000;
569 ebc->bcr[i] = 0x00000000;
570 }
571 ebc->besr0 = 0x00000000;
572 ebc->besr1 = 0x00000000;
573 ebc->cfg = 0x80400000;
574 }
575
576 static void ppc405_ebc_init(CPUState *env)
577 {
578 ppc4xx_ebc_t *ebc;
579
580 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
581 qemu_register_reset(&ebc_reset, ebc);
582 ppc_dcr_register(env, EBC0_CFGADDR,
583 ebc, &dcr_read_ebc, &dcr_write_ebc);
584 ppc_dcr_register(env, EBC0_CFGDATA,
585 ebc, &dcr_read_ebc, &dcr_write_ebc);
586 }
587
588 /*****************************************************************************/
589 /* DMA controller */
590 enum {
591 DMA0_CR0 = 0x100,
592 DMA0_CT0 = 0x101,
593 DMA0_DA0 = 0x102,
594 DMA0_SA0 = 0x103,
595 DMA0_SG0 = 0x104,
596 DMA0_CR1 = 0x108,
597 DMA0_CT1 = 0x109,
598 DMA0_DA1 = 0x10A,
599 DMA0_SA1 = 0x10B,
600 DMA0_SG1 = 0x10C,
601 DMA0_CR2 = 0x110,
602 DMA0_CT2 = 0x111,
603 DMA0_DA2 = 0x112,
604 DMA0_SA2 = 0x113,
605 DMA0_SG2 = 0x114,
606 DMA0_CR3 = 0x118,
607 DMA0_CT3 = 0x119,
608 DMA0_DA3 = 0x11A,
609 DMA0_SA3 = 0x11B,
610 DMA0_SG3 = 0x11C,
611 DMA0_SR = 0x120,
612 DMA0_SGC = 0x123,
613 DMA0_SLP = 0x125,
614 DMA0_POL = 0x126,
615 };
616
617 typedef struct ppc405_dma_t ppc405_dma_t;
618 struct ppc405_dma_t {
619 qemu_irq irqs[4];
620 uint32_t cr[4];
621 uint32_t ct[4];
622 uint32_t da[4];
623 uint32_t sa[4];
624 uint32_t sg[4];
625 uint32_t sr;
626 uint32_t sgc;
627 uint32_t slp;
628 uint32_t pol;
629 };
630
631 static uint32_t dcr_read_dma (void *opaque, int dcrn)
632 {
633 return 0;
634 }
635
636 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
637 {
638 }
639
640 static void ppc405_dma_reset (void *opaque)
641 {
642 ppc405_dma_t *dma;
643 int i;
644
645 dma = opaque;
646 for (i = 0; i < 4; i++) {
647 dma->cr[i] = 0x00000000;
648 dma->ct[i] = 0x00000000;
649 dma->da[i] = 0x00000000;
650 dma->sa[i] = 0x00000000;
651 dma->sg[i] = 0x00000000;
652 }
653 dma->sr = 0x00000000;
654 dma->sgc = 0x00000000;
655 dma->slp = 0x7C000000;
656 dma->pol = 0x00000000;
657 }
658
659 static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
660 {
661 ppc405_dma_t *dma;
662
663 dma = qemu_mallocz(sizeof(ppc405_dma_t));
664 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
665 qemu_register_reset(&ppc405_dma_reset, dma);
666 ppc_dcr_register(env, DMA0_CR0,
667 dma, &dcr_read_dma, &dcr_write_dma);
668 ppc_dcr_register(env, DMA0_CT0,
669 dma, &dcr_read_dma, &dcr_write_dma);
670 ppc_dcr_register(env, DMA0_DA0,
671 dma, &dcr_read_dma, &dcr_write_dma);
672 ppc_dcr_register(env, DMA0_SA0,
673 dma, &dcr_read_dma, &dcr_write_dma);
674 ppc_dcr_register(env, DMA0_SG0,
675 dma, &dcr_read_dma, &dcr_write_dma);
676 ppc_dcr_register(env, DMA0_CR1,
677 dma, &dcr_read_dma, &dcr_write_dma);
678 ppc_dcr_register(env, DMA0_CT1,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_DA1,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_SA1,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_SG1,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_CR2,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_CT2,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_DA2,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_SA2,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_SG2,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_CR3,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_CT3,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_DA3,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_SA3,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_SG3,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_SR,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_SGC,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_SLP,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 ppc_dcr_register(env, DMA0_POL,
713 dma, &dcr_read_dma, &dcr_write_dma);
714 }
715
716 /*****************************************************************************/
717 /* GPIO */
718 typedef struct ppc405_gpio_t ppc405_gpio_t;
719 struct ppc405_gpio_t {
720 uint32_t or;
721 uint32_t tcr;
722 uint32_t osrh;
723 uint32_t osrl;
724 uint32_t tsrh;
725 uint32_t tsrl;
726 uint32_t odr;
727 uint32_t ir;
728 uint32_t rr1;
729 uint32_t isr1h;
730 uint32_t isr1l;
731 };
732
733 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
734 {
735 #ifdef DEBUG_GPIO
736 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
737 #endif
738
739 return 0;
740 }
741
742 static void ppc405_gpio_writeb (void *opaque,
743 target_phys_addr_t addr, uint32_t value)
744 {
745 #ifdef DEBUG_GPIO
746 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
747 value);
748 #endif
749 }
750
751 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
752 {
753 #ifdef DEBUG_GPIO
754 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
755 #endif
756
757 return 0;
758 }
759
760 static void ppc405_gpio_writew (void *opaque,
761 target_phys_addr_t addr, uint32_t value)
762 {
763 #ifdef DEBUG_GPIO
764 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
765 value);
766 #endif
767 }
768
769 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
770 {
771 #ifdef DEBUG_GPIO
772 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
773 #endif
774
775 return 0;
776 }
777
778 static void ppc405_gpio_writel (void *opaque,
779 target_phys_addr_t addr, uint32_t value)
780 {
781 #ifdef DEBUG_GPIO
782 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
783 value);
784 #endif
785 }
786
787 static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
788 &ppc405_gpio_readb,
789 &ppc405_gpio_readw,
790 &ppc405_gpio_readl,
791 };
792
793 static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
794 &ppc405_gpio_writeb,
795 &ppc405_gpio_writew,
796 &ppc405_gpio_writel,
797 };
798
799 static void ppc405_gpio_reset (void *opaque)
800 {
801 }
802
803 static void ppc405_gpio_init(target_phys_addr_t base)
804 {
805 ppc405_gpio_t *gpio;
806 int io;
807
808 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
809 #ifdef DEBUG_GPIO
810 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
811 #endif
812 io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
813 cpu_register_physical_memory(base, 0x038, io);
814 qemu_register_reset(&ppc405_gpio_reset, gpio);
815 }
816
817 /*****************************************************************************/
818 /* On Chip Memory */
819 enum {
820 OCM0_ISARC = 0x018,
821 OCM0_ISACNTL = 0x019,
822 OCM0_DSARC = 0x01A,
823 OCM0_DSACNTL = 0x01B,
824 };
825
826 typedef struct ppc405_ocm_t ppc405_ocm_t;
827 struct ppc405_ocm_t {
828 target_ulong offset;
829 uint32_t isarc;
830 uint32_t isacntl;
831 uint32_t dsarc;
832 uint32_t dsacntl;
833 };
834
835 static void ocm_update_mappings (ppc405_ocm_t *ocm,
836 uint32_t isarc, uint32_t isacntl,
837 uint32_t dsarc, uint32_t dsacntl)
838 {
839 #ifdef DEBUG_OCM
840 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
841 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
842 " (%08" PRIx32 " %08" PRIx32 ")\n",
843 isarc, isacntl, dsarc, dsacntl,
844 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
845 #endif
846 if (ocm->isarc != isarc ||
847 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
848 if (ocm->isacntl & 0x80000000) {
849 /* Unmap previously assigned memory region */
850 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
851 cpu_register_physical_memory(ocm->isarc, 0x04000000,
852 IO_MEM_UNASSIGNED);
853 }
854 if (isacntl & 0x80000000) {
855 /* Map new instruction memory region */
856 #ifdef DEBUG_OCM
857 printf("OCM map ISA %08" PRIx32 "\n", isarc);
858 #endif
859 cpu_register_physical_memory(isarc, 0x04000000,
860 ocm->offset | IO_MEM_RAM);
861 }
862 }
863 if (ocm->dsarc != dsarc ||
864 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
865 if (ocm->dsacntl & 0x80000000) {
866 /* Beware not to unmap the region we just mapped */
867 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
868 /* Unmap previously assigned memory region */
869 #ifdef DEBUG_OCM
870 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
871 #endif
872 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
873 IO_MEM_UNASSIGNED);
874 }
875 }
876 if (dsacntl & 0x80000000) {
877 /* Beware not to remap the region we just mapped */
878 if (!(isacntl & 0x80000000) || dsarc != isarc) {
879 /* Map new data memory region */
880 #ifdef DEBUG_OCM
881 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
882 #endif
883 cpu_register_physical_memory(dsarc, 0x04000000,
884 ocm->offset | IO_MEM_RAM);
885 }
886 }
887 }
888 }
889
890 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
891 {
892 ppc405_ocm_t *ocm;
893 uint32_t ret;
894
895 ocm = opaque;
896 switch (dcrn) {
897 case OCM0_ISARC:
898 ret = ocm->isarc;
899 break;
900 case OCM0_ISACNTL:
901 ret = ocm->isacntl;
902 break;
903 case OCM0_DSARC:
904 ret = ocm->dsarc;
905 break;
906 case OCM0_DSACNTL:
907 ret = ocm->dsacntl;
908 break;
909 default:
910 ret = 0;
911 break;
912 }
913
914 return ret;
915 }
916
917 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
918 {
919 ppc405_ocm_t *ocm;
920 uint32_t isarc, dsarc, isacntl, dsacntl;
921
922 ocm = opaque;
923 isarc = ocm->isarc;
924 dsarc = ocm->dsarc;
925 isacntl = ocm->isacntl;
926 dsacntl = ocm->dsacntl;
927 switch (dcrn) {
928 case OCM0_ISARC:
929 isarc = val & 0xFC000000;
930 break;
931 case OCM0_ISACNTL:
932 isacntl = val & 0xC0000000;
933 break;
934 case OCM0_DSARC:
935 isarc = val & 0xFC000000;
936 break;
937 case OCM0_DSACNTL:
938 isacntl = val & 0xC0000000;
939 break;
940 }
941 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
942 ocm->isarc = isarc;
943 ocm->dsarc = dsarc;
944 ocm->isacntl = isacntl;
945 ocm->dsacntl = dsacntl;
946 }
947
948 static void ocm_reset (void *opaque)
949 {
950 ppc405_ocm_t *ocm;
951 uint32_t isarc, dsarc, isacntl, dsacntl;
952
953 ocm = opaque;
954 isarc = 0x00000000;
955 isacntl = 0x00000000;
956 dsarc = 0x00000000;
957 dsacntl = 0x00000000;
958 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
959 ocm->isarc = isarc;
960 ocm->dsarc = dsarc;
961 ocm->isacntl = isacntl;
962 ocm->dsacntl = dsacntl;
963 }
964
965 static void ppc405_ocm_init(CPUState *env)
966 {
967 ppc405_ocm_t *ocm;
968
969 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
970 ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
971 qemu_register_reset(&ocm_reset, ocm);
972 ppc_dcr_register(env, OCM0_ISARC,
973 ocm, &dcr_read_ocm, &dcr_write_ocm);
974 ppc_dcr_register(env, OCM0_ISACNTL,
975 ocm, &dcr_read_ocm, &dcr_write_ocm);
976 ppc_dcr_register(env, OCM0_DSARC,
977 ocm, &dcr_read_ocm, &dcr_write_ocm);
978 ppc_dcr_register(env, OCM0_DSACNTL,
979 ocm, &dcr_read_ocm, &dcr_write_ocm);
980 }
981
982 /*****************************************************************************/
983 /* I2C controller */
984 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
985 struct ppc4xx_i2c_t {
986 qemu_irq irq;
987 uint8_t mdata;
988 uint8_t lmadr;
989 uint8_t hmadr;
990 uint8_t cntl;
991 uint8_t mdcntl;
992 uint8_t sts;
993 uint8_t extsts;
994 uint8_t sdata;
995 uint8_t lsadr;
996 uint8_t hsadr;
997 uint8_t clkdiv;
998 uint8_t intrmsk;
999 uint8_t xfrcnt;
1000 uint8_t xtcntlss;
1001 uint8_t directcntl;
1002 };
1003
1004 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1005 {
1006 ppc4xx_i2c_t *i2c;
1007 uint32_t ret;
1008
1009 #ifdef DEBUG_I2C
1010 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1011 #endif
1012 i2c = opaque;
1013 switch (addr) {
1014 case 0x00:
1015 // i2c_readbyte(&i2c->mdata);
1016 ret = i2c->mdata;
1017 break;
1018 case 0x02:
1019 ret = i2c->sdata;
1020 break;
1021 case 0x04:
1022 ret = i2c->lmadr;
1023 break;
1024 case 0x05:
1025 ret = i2c->hmadr;
1026 break;
1027 case 0x06:
1028 ret = i2c->cntl;
1029 break;
1030 case 0x07:
1031 ret = i2c->mdcntl;
1032 break;
1033 case 0x08:
1034 ret = i2c->sts;
1035 break;
1036 case 0x09:
1037 ret = i2c->extsts;
1038 break;
1039 case 0x0A:
1040 ret = i2c->lsadr;
1041 break;
1042 case 0x0B:
1043 ret = i2c->hsadr;
1044 break;
1045 case 0x0C:
1046 ret = i2c->clkdiv;
1047 break;
1048 case 0x0D:
1049 ret = i2c->intrmsk;
1050 break;
1051 case 0x0E:
1052 ret = i2c->xfrcnt;
1053 break;
1054 case 0x0F:
1055 ret = i2c->xtcntlss;
1056 break;
1057 case 0x10:
1058 ret = i2c->directcntl;
1059 break;
1060 default:
1061 ret = 0x00;
1062 break;
1063 }
1064 #ifdef DEBUG_I2C
1065 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1066 #endif
1067
1068 return ret;
1069 }
1070
1071 static void ppc4xx_i2c_writeb (void *opaque,
1072 target_phys_addr_t addr, uint32_t value)
1073 {
1074 ppc4xx_i2c_t *i2c;
1075
1076 #ifdef DEBUG_I2C
1077 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1078 value);
1079 #endif
1080 i2c = opaque;
1081 switch (addr) {
1082 case 0x00:
1083 i2c->mdata = value;
1084 // i2c_sendbyte(&i2c->mdata);
1085 break;
1086 case 0x02:
1087 i2c->sdata = value;
1088 break;
1089 case 0x04:
1090 i2c->lmadr = value;
1091 break;
1092 case 0x05:
1093 i2c->hmadr = value;
1094 break;
1095 case 0x06:
1096 i2c->cntl = value;
1097 break;
1098 case 0x07:
1099 i2c->mdcntl = value & 0xDF;
1100 break;
1101 case 0x08:
1102 i2c->sts &= ~(value & 0x0A);
1103 break;
1104 case 0x09:
1105 i2c->extsts &= ~(value & 0x8F);
1106 break;
1107 case 0x0A:
1108 i2c->lsadr = value;
1109 break;
1110 case 0x0B:
1111 i2c->hsadr = value;
1112 break;
1113 case 0x0C:
1114 i2c->clkdiv = value;
1115 break;
1116 case 0x0D:
1117 i2c->intrmsk = value;
1118 break;
1119 case 0x0E:
1120 i2c->xfrcnt = value & 0x77;
1121 break;
1122 case 0x0F:
1123 i2c->xtcntlss = value;
1124 break;
1125 case 0x10:
1126 i2c->directcntl = value & 0x7;
1127 break;
1128 }
1129 }
1130
1131 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1132 {
1133 uint32_t ret;
1134
1135 #ifdef DEBUG_I2C
1136 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1137 #endif
1138 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1139 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1140
1141 return ret;
1142 }
1143
1144 static void ppc4xx_i2c_writew (void *opaque,
1145 target_phys_addr_t addr, uint32_t value)
1146 {
1147 #ifdef DEBUG_I2C
1148 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1149 value);
1150 #endif
1151 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1152 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1153 }
1154
1155 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1156 {
1157 uint32_t ret;
1158
1159 #ifdef DEBUG_I2C
1160 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1161 #endif
1162 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1163 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1164 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1165 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1166
1167 return ret;
1168 }
1169
1170 static void ppc4xx_i2c_writel (void *opaque,
1171 target_phys_addr_t addr, uint32_t value)
1172 {
1173 #ifdef DEBUG_I2C
1174 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1175 value);
1176 #endif
1177 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1178 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1179 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1180 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1181 }
1182
1183 static CPUReadMemoryFunc * const i2c_read[] = {
1184 &ppc4xx_i2c_readb,
1185 &ppc4xx_i2c_readw,
1186 &ppc4xx_i2c_readl,
1187 };
1188
1189 static CPUWriteMemoryFunc * const i2c_write[] = {
1190 &ppc4xx_i2c_writeb,
1191 &ppc4xx_i2c_writew,
1192 &ppc4xx_i2c_writel,
1193 };
1194
1195 static void ppc4xx_i2c_reset (void *opaque)
1196 {
1197 ppc4xx_i2c_t *i2c;
1198
1199 i2c = opaque;
1200 i2c->mdata = 0x00;
1201 i2c->sdata = 0x00;
1202 i2c->cntl = 0x00;
1203 i2c->mdcntl = 0x00;
1204 i2c->sts = 0x00;
1205 i2c->extsts = 0x00;
1206 i2c->clkdiv = 0x00;
1207 i2c->xfrcnt = 0x00;
1208 i2c->directcntl = 0x0F;
1209 }
1210
1211 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1212 {
1213 ppc4xx_i2c_t *i2c;
1214 int io;
1215
1216 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1217 i2c->irq = irq;
1218 #ifdef DEBUG_I2C
1219 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1220 #endif
1221 io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
1222 cpu_register_physical_memory(base, 0x011, io);
1223 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1224 }
1225
1226 /*****************************************************************************/
1227 /* General purpose timers */
1228 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1229 struct ppc4xx_gpt_t {
1230 int64_t tb_offset;
1231 uint32_t tb_freq;
1232 struct QEMUTimer *timer;
1233 qemu_irq irqs[5];
1234 uint32_t oe;
1235 uint32_t ol;
1236 uint32_t im;
1237 uint32_t is;
1238 uint32_t ie;
1239 uint32_t comp[5];
1240 uint32_t mask[5];
1241 };
1242
1243 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1244 {
1245 #ifdef DEBUG_GPT
1246 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1247 #endif
1248 /* XXX: generate a bus fault */
1249 return -1;
1250 }
1251
1252 static void ppc4xx_gpt_writeb (void *opaque,
1253 target_phys_addr_t addr, uint32_t value)
1254 {
1255 #ifdef DEBUG_I2C
1256 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1257 value);
1258 #endif
1259 /* XXX: generate a bus fault */
1260 }
1261
1262 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1263 {
1264 #ifdef DEBUG_GPT
1265 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1266 #endif
1267 /* XXX: generate a bus fault */
1268 return -1;
1269 }
1270
1271 static void ppc4xx_gpt_writew (void *opaque,
1272 target_phys_addr_t addr, uint32_t value)
1273 {
1274 #ifdef DEBUG_I2C
1275 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1276 value);
1277 #endif
1278 /* XXX: generate a bus fault */
1279 }
1280
1281 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1282 {
1283 /* XXX: TODO */
1284 return 0;
1285 }
1286
1287 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1288 {
1289 /* XXX: TODO */
1290 }
1291
1292 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1293 {
1294 uint32_t mask;
1295 int i;
1296
1297 mask = 0x80000000;
1298 for (i = 0; i < 5; i++) {
1299 if (gpt->oe & mask) {
1300 /* Output is enabled */
1301 if (ppc4xx_gpt_compare(gpt, i)) {
1302 /* Comparison is OK */
1303 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1304 } else {
1305 /* Comparison is KO */
1306 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1307 }
1308 }
1309 mask = mask >> 1;
1310 }
1311 }
1312
1313 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1314 {
1315 uint32_t mask;
1316 int i;
1317
1318 mask = 0x00008000;
1319 for (i = 0; i < 5; i++) {
1320 if (gpt->is & gpt->im & mask)
1321 qemu_irq_raise(gpt->irqs[i]);
1322 else
1323 qemu_irq_lower(gpt->irqs[i]);
1324 mask = mask >> 1;
1325 }
1326 }
1327
1328 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1329 {
1330 /* XXX: TODO */
1331 }
1332
1333 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1334 {
1335 ppc4xx_gpt_t *gpt;
1336 uint32_t ret;
1337 int idx;
1338
1339 #ifdef DEBUG_GPT
1340 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1341 #endif
1342 gpt = opaque;
1343 switch (addr) {
1344 case 0x00:
1345 /* Time base counter */
1346 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1347 gpt->tb_freq, get_ticks_per_sec());
1348 break;
1349 case 0x10:
1350 /* Output enable */
1351 ret = gpt->oe;
1352 break;
1353 case 0x14:
1354 /* Output level */
1355 ret = gpt->ol;
1356 break;
1357 case 0x18:
1358 /* Interrupt mask */
1359 ret = gpt->im;
1360 break;
1361 case 0x1C:
1362 case 0x20:
1363 /* Interrupt status */
1364 ret = gpt->is;
1365 break;
1366 case 0x24:
1367 /* Interrupt enable */
1368 ret = gpt->ie;
1369 break;
1370 case 0x80 ... 0x90:
1371 /* Compare timer */
1372 idx = (addr - 0x80) >> 2;
1373 ret = gpt->comp[idx];
1374 break;
1375 case 0xC0 ... 0xD0:
1376 /* Compare mask */
1377 idx = (addr - 0xC0) >> 2;
1378 ret = gpt->mask[idx];
1379 break;
1380 default:
1381 ret = -1;
1382 break;
1383 }
1384
1385 return ret;
1386 }
1387
1388 static void ppc4xx_gpt_writel (void *opaque,
1389 target_phys_addr_t addr, uint32_t value)
1390 {
1391 ppc4xx_gpt_t *gpt;
1392 int idx;
1393
1394 #ifdef DEBUG_I2C
1395 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1396 value);
1397 #endif
1398 gpt = opaque;
1399 switch (addr) {
1400 case 0x00:
1401 /* Time base counter */
1402 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1403 - qemu_get_clock(vm_clock);
1404 ppc4xx_gpt_compute_timer(gpt);
1405 break;
1406 case 0x10:
1407 /* Output enable */
1408 gpt->oe = value & 0xF8000000;
1409 ppc4xx_gpt_set_outputs(gpt);
1410 break;
1411 case 0x14:
1412 /* Output level */
1413 gpt->ol = value & 0xF8000000;
1414 ppc4xx_gpt_set_outputs(gpt);
1415 break;
1416 case 0x18:
1417 /* Interrupt mask */
1418 gpt->im = value & 0x0000F800;
1419 break;
1420 case 0x1C:
1421 /* Interrupt status set */
1422 gpt->is |= value & 0x0000F800;
1423 ppc4xx_gpt_set_irqs(gpt);
1424 break;
1425 case 0x20:
1426 /* Interrupt status clear */
1427 gpt->is &= ~(value & 0x0000F800);
1428 ppc4xx_gpt_set_irqs(gpt);
1429 break;
1430 case 0x24:
1431 /* Interrupt enable */
1432 gpt->ie = value & 0x0000F800;
1433 ppc4xx_gpt_set_irqs(gpt);
1434 break;
1435 case 0x80 ... 0x90:
1436 /* Compare timer */
1437 idx = (addr - 0x80) >> 2;
1438 gpt->comp[idx] = value & 0xF8000000;
1439 ppc4xx_gpt_compute_timer(gpt);
1440 break;
1441 case 0xC0 ... 0xD0:
1442 /* Compare mask */
1443 idx = (addr - 0xC0) >> 2;
1444 gpt->mask[idx] = value & 0xF8000000;
1445 ppc4xx_gpt_compute_timer(gpt);
1446 break;
1447 }
1448 }
1449
1450 static CPUReadMemoryFunc * const gpt_read[] = {
1451 &ppc4xx_gpt_readb,
1452 &ppc4xx_gpt_readw,
1453 &ppc4xx_gpt_readl,
1454 };
1455
1456 static CPUWriteMemoryFunc * const gpt_write[] = {
1457 &ppc4xx_gpt_writeb,
1458 &ppc4xx_gpt_writew,
1459 &ppc4xx_gpt_writel,
1460 };
1461
1462 static void ppc4xx_gpt_cb (void *opaque)
1463 {
1464 ppc4xx_gpt_t *gpt;
1465
1466 gpt = opaque;
1467 ppc4xx_gpt_set_irqs(gpt);
1468 ppc4xx_gpt_set_outputs(gpt);
1469 ppc4xx_gpt_compute_timer(gpt);
1470 }
1471
1472 static void ppc4xx_gpt_reset (void *opaque)
1473 {
1474 ppc4xx_gpt_t *gpt;
1475 int i;
1476
1477 gpt = opaque;
1478 qemu_del_timer(gpt->timer);
1479 gpt->oe = 0x00000000;
1480 gpt->ol = 0x00000000;
1481 gpt->im = 0x00000000;
1482 gpt->is = 0x00000000;
1483 gpt->ie = 0x00000000;
1484 for (i = 0; i < 5; i++) {
1485 gpt->comp[i] = 0x00000000;
1486 gpt->mask[i] = 0x00000000;
1487 }
1488 }
1489
1490 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1491 {
1492 ppc4xx_gpt_t *gpt;
1493 int i;
1494 int io;
1495
1496 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1497 for (i = 0; i < 5; i++) {
1498 gpt->irqs[i] = irqs[i];
1499 }
1500 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1501 #ifdef DEBUG_GPT
1502 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1503 #endif
1504 io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
1505 cpu_register_physical_memory(base, 0x0d4, io);
1506 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1507 }
1508
1509 /*****************************************************************************/
1510 /* MAL */
1511 enum {
1512 MAL0_CFG = 0x180,
1513 MAL0_ESR = 0x181,
1514 MAL0_IER = 0x182,
1515 MAL0_TXCASR = 0x184,
1516 MAL0_TXCARR = 0x185,
1517 MAL0_TXEOBISR = 0x186,
1518 MAL0_TXDEIR = 0x187,
1519 MAL0_RXCASR = 0x190,
1520 MAL0_RXCARR = 0x191,
1521 MAL0_RXEOBISR = 0x192,
1522 MAL0_RXDEIR = 0x193,
1523 MAL0_TXCTP0R = 0x1A0,
1524 MAL0_TXCTP1R = 0x1A1,
1525 MAL0_TXCTP2R = 0x1A2,
1526 MAL0_TXCTP3R = 0x1A3,
1527 MAL0_RXCTP0R = 0x1C0,
1528 MAL0_RXCTP1R = 0x1C1,
1529 MAL0_RCBS0 = 0x1E0,
1530 MAL0_RCBS1 = 0x1E1,
1531 };
1532
1533 typedef struct ppc40x_mal_t ppc40x_mal_t;
1534 struct ppc40x_mal_t {
1535 qemu_irq irqs[4];
1536 uint32_t cfg;
1537 uint32_t esr;
1538 uint32_t ier;
1539 uint32_t txcasr;
1540 uint32_t txcarr;
1541 uint32_t txeobisr;
1542 uint32_t txdeir;
1543 uint32_t rxcasr;
1544 uint32_t rxcarr;
1545 uint32_t rxeobisr;
1546 uint32_t rxdeir;
1547 uint32_t txctpr[4];
1548 uint32_t rxctpr[2];
1549 uint32_t rcbs[2];
1550 };
1551
1552 static void ppc40x_mal_reset (void *opaque);
1553
1554 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1555 {
1556 ppc40x_mal_t *mal;
1557 uint32_t ret;
1558
1559 mal = opaque;
1560 switch (dcrn) {
1561 case MAL0_CFG:
1562 ret = mal->cfg;
1563 break;
1564 case MAL0_ESR:
1565 ret = mal->esr;
1566 break;
1567 case MAL0_IER:
1568 ret = mal->ier;
1569 break;
1570 case MAL0_TXCASR:
1571 ret = mal->txcasr;
1572 break;
1573 case MAL0_TXCARR:
1574 ret = mal->txcarr;
1575 break;
1576 case MAL0_TXEOBISR:
1577 ret = mal->txeobisr;
1578 break;
1579 case MAL0_TXDEIR:
1580 ret = mal->txdeir;
1581 break;
1582 case MAL0_RXCASR:
1583 ret = mal->rxcasr;
1584 break;
1585 case MAL0_RXCARR:
1586 ret = mal->rxcarr;
1587 break;
1588 case MAL0_RXEOBISR:
1589 ret = mal->rxeobisr;
1590 break;
1591 case MAL0_RXDEIR:
1592 ret = mal->rxdeir;
1593 break;
1594 case MAL0_TXCTP0R:
1595 ret = mal->txctpr[0];
1596 break;
1597 case MAL0_TXCTP1R:
1598 ret = mal->txctpr[1];
1599 break;
1600 case MAL0_TXCTP2R:
1601 ret = mal->txctpr[2];
1602 break;
1603 case MAL0_TXCTP3R:
1604 ret = mal->txctpr[3];
1605 break;
1606 case MAL0_RXCTP0R:
1607 ret = mal->rxctpr[0];
1608 break;
1609 case MAL0_RXCTP1R:
1610 ret = mal->rxctpr[1];
1611 break;
1612 case MAL0_RCBS0:
1613 ret = mal->rcbs[0];
1614 break;
1615 case MAL0_RCBS1:
1616 ret = mal->rcbs[1];
1617 break;
1618 default:
1619 ret = 0;
1620 break;
1621 }
1622
1623 return ret;
1624 }
1625
1626 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1627 {
1628 ppc40x_mal_t *mal;
1629 int idx;
1630
1631 mal = opaque;
1632 switch (dcrn) {
1633 case MAL0_CFG:
1634 if (val & 0x80000000)
1635 ppc40x_mal_reset(mal);
1636 mal->cfg = val & 0x00FFC087;
1637 break;
1638 case MAL0_ESR:
1639 /* Read/clear */
1640 mal->esr &= ~val;
1641 break;
1642 case MAL0_IER:
1643 mal->ier = val & 0x0000001F;
1644 break;
1645 case MAL0_TXCASR:
1646 mal->txcasr = val & 0xF0000000;
1647 break;
1648 case MAL0_TXCARR:
1649 mal->txcarr = val & 0xF0000000;
1650 break;
1651 case MAL0_TXEOBISR:
1652 /* Read/clear */
1653 mal->txeobisr &= ~val;
1654 break;
1655 case MAL0_TXDEIR:
1656 /* Read/clear */
1657 mal->txdeir &= ~val;
1658 break;
1659 case MAL0_RXCASR:
1660 mal->rxcasr = val & 0xC0000000;
1661 break;
1662 case MAL0_RXCARR:
1663 mal->rxcarr = val & 0xC0000000;
1664 break;
1665 case MAL0_RXEOBISR:
1666 /* Read/clear */
1667 mal->rxeobisr &= ~val;
1668 break;
1669 case MAL0_RXDEIR:
1670 /* Read/clear */
1671 mal->rxdeir &= ~val;
1672 break;
1673 case MAL0_TXCTP0R:
1674 idx = 0;
1675 goto update_tx_ptr;
1676 case MAL0_TXCTP1R:
1677 idx = 1;
1678 goto update_tx_ptr;
1679 case MAL0_TXCTP2R:
1680 idx = 2;
1681 goto update_tx_ptr;
1682 case MAL0_TXCTP3R:
1683 idx = 3;
1684 update_tx_ptr:
1685 mal->txctpr[idx] = val;
1686 break;
1687 case MAL0_RXCTP0R:
1688 idx = 0;
1689 goto update_rx_ptr;
1690 case MAL0_RXCTP1R:
1691 idx = 1;
1692 update_rx_ptr:
1693 mal->rxctpr[idx] = val;
1694 break;
1695 case MAL0_RCBS0:
1696 idx = 0;
1697 goto update_rx_size;
1698 case MAL0_RCBS1:
1699 idx = 1;
1700 update_rx_size:
1701 mal->rcbs[idx] = val & 0x000000FF;
1702 break;
1703 }
1704 }
1705
1706 static void ppc40x_mal_reset (void *opaque)
1707 {
1708 ppc40x_mal_t *mal;
1709
1710 mal = opaque;
1711 mal->cfg = 0x0007C000;
1712 mal->esr = 0x00000000;
1713 mal->ier = 0x00000000;
1714 mal->rxcasr = 0x00000000;
1715 mal->rxdeir = 0x00000000;
1716 mal->rxeobisr = 0x00000000;
1717 mal->txcasr = 0x00000000;
1718 mal->txdeir = 0x00000000;
1719 mal->txeobisr = 0x00000000;
1720 }
1721
1722 static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
1723 {
1724 ppc40x_mal_t *mal;
1725 int i;
1726
1727 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
1728 for (i = 0; i < 4; i++)
1729 mal->irqs[i] = irqs[i];
1730 qemu_register_reset(&ppc40x_mal_reset, mal);
1731 ppc_dcr_register(env, MAL0_CFG,
1732 mal, &dcr_read_mal, &dcr_write_mal);
1733 ppc_dcr_register(env, MAL0_ESR,
1734 mal, &dcr_read_mal, &dcr_write_mal);
1735 ppc_dcr_register(env, MAL0_IER,
1736 mal, &dcr_read_mal, &dcr_write_mal);
1737 ppc_dcr_register(env, MAL0_TXCASR,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_TXCARR,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_TXEOBISR,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_TXDEIR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_RXCASR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_RXCARR,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_RXEOBISR,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_RXDEIR,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_TXCTP0R,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_TXCTP1R,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_TXCTP2R,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_TXCTP3R,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_RXCTP0R,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_RXCTP1R,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_RCBS0,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_RCBS1,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1769 }
1770
1771 /*****************************************************************************/
1772 /* SPR */
1773 void ppc40x_core_reset (CPUState *env)
1774 {
1775 target_ulong dbsr;
1776
1777 printf("Reset PowerPC core\n");
1778 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1779 /* XXX: TOFIX */
1780 #if 0
1781 cpu_reset(env);
1782 #else
1783 qemu_system_reset_request();
1784 #endif
1785 dbsr = env->spr[SPR_40x_DBSR];
1786 dbsr &= ~0x00000300;
1787 dbsr |= 0x00000100;
1788 env->spr[SPR_40x_DBSR] = dbsr;
1789 }
1790
1791 void ppc40x_chip_reset (CPUState *env)
1792 {
1793 target_ulong dbsr;
1794
1795 printf("Reset PowerPC chip\n");
1796 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1797 /* XXX: TOFIX */
1798 #if 0
1799 cpu_reset(env);
1800 #else
1801 qemu_system_reset_request();
1802 #endif
1803 /* XXX: TODO reset all internal peripherals */
1804 dbsr = env->spr[SPR_40x_DBSR];
1805 dbsr &= ~0x00000300;
1806 dbsr |= 0x00000200;
1807 env->spr[SPR_40x_DBSR] = dbsr;
1808 }
1809
1810 void ppc40x_system_reset (CPUState *env)
1811 {
1812 printf("Reset PowerPC system\n");
1813 qemu_system_reset_request();
1814 }
1815
1816 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1817 {
1818 switch ((val >> 28) & 0x3) {
1819 case 0x0:
1820 /* No action */
1821 break;
1822 case 0x1:
1823 /* Core reset */
1824 ppc40x_core_reset(env);
1825 break;
1826 case 0x2:
1827 /* Chip reset */
1828 ppc40x_chip_reset(env);
1829 break;
1830 case 0x3:
1831 /* System reset */
1832 ppc40x_system_reset(env);
1833 break;
1834 }
1835 }
1836
1837 /*****************************************************************************/
1838 /* PowerPC 405CR */
1839 enum {
1840 PPC405CR_CPC0_PLLMR = 0x0B0,
1841 PPC405CR_CPC0_CR0 = 0x0B1,
1842 PPC405CR_CPC0_CR1 = 0x0B2,
1843 PPC405CR_CPC0_PSR = 0x0B4,
1844 PPC405CR_CPC0_JTAGID = 0x0B5,
1845 PPC405CR_CPC0_ER = 0x0B9,
1846 PPC405CR_CPC0_FR = 0x0BA,
1847 PPC405CR_CPC0_SR = 0x0BB,
1848 };
1849
1850 enum {
1851 PPC405CR_CPU_CLK = 0,
1852 PPC405CR_TMR_CLK = 1,
1853 PPC405CR_PLB_CLK = 2,
1854 PPC405CR_SDRAM_CLK = 3,
1855 PPC405CR_OPB_CLK = 4,
1856 PPC405CR_EXT_CLK = 5,
1857 PPC405CR_UART_CLK = 6,
1858 PPC405CR_CLK_NB = 7,
1859 };
1860
1861 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1862 struct ppc405cr_cpc_t {
1863 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1864 uint32_t sysclk;
1865 uint32_t psr;
1866 uint32_t cr0;
1867 uint32_t cr1;
1868 uint32_t jtagid;
1869 uint32_t pllmr;
1870 uint32_t er;
1871 uint32_t fr;
1872 };
1873
1874 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1875 {
1876 uint64_t VCO_out, PLL_out;
1877 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1878 int M, D0, D1, D2;
1879
1880 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1881 if (cpc->pllmr & 0x80000000) {
1882 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1883 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1884 M = D0 * D1 * D2;
1885 VCO_out = cpc->sysclk * M;
1886 if (VCO_out < 400000000 || VCO_out > 800000000) {
1887 /* PLL cannot lock */
1888 cpc->pllmr &= ~0x80000000;
1889 goto bypass_pll;
1890 }
1891 PLL_out = VCO_out / D2;
1892 } else {
1893 /* Bypass PLL */
1894 bypass_pll:
1895 M = D0;
1896 PLL_out = cpc->sysclk * M;
1897 }
1898 CPU_clk = PLL_out;
1899 if (cpc->cr1 & 0x00800000)
1900 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1901 else
1902 TMR_clk = CPU_clk;
1903 PLB_clk = CPU_clk / D0;
1904 SDRAM_clk = PLB_clk;
1905 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1906 OPB_clk = PLB_clk / D0;
1907 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1908 EXT_clk = PLB_clk / D0;
1909 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1910 UART_clk = CPU_clk / D0;
1911 /* Setup CPU clocks */
1912 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1913 /* Setup time-base clock */
1914 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1915 /* Setup PLB clock */
1916 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1917 /* Setup SDRAM clock */
1918 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1919 /* Setup OPB clock */
1920 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1921 /* Setup external clock */
1922 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1923 /* Setup UART clock */
1924 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1925 }
1926
1927 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1928 {
1929 ppc405cr_cpc_t *cpc;
1930 uint32_t ret;
1931
1932 cpc = opaque;
1933 switch (dcrn) {
1934 case PPC405CR_CPC0_PLLMR:
1935 ret = cpc->pllmr;
1936 break;
1937 case PPC405CR_CPC0_CR0:
1938 ret = cpc->cr0;
1939 break;
1940 case PPC405CR_CPC0_CR1:
1941 ret = cpc->cr1;
1942 break;
1943 case PPC405CR_CPC0_PSR:
1944 ret = cpc->psr;
1945 break;
1946 case PPC405CR_CPC0_JTAGID:
1947 ret = cpc->jtagid;
1948 break;
1949 case PPC405CR_CPC0_ER:
1950 ret = cpc->er;
1951 break;
1952 case PPC405CR_CPC0_FR:
1953 ret = cpc->fr;
1954 break;
1955 case PPC405CR_CPC0_SR:
1956 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1957 break;
1958 default:
1959 /* Avoid gcc warning */
1960 ret = 0;
1961 break;
1962 }
1963
1964 return ret;
1965 }
1966
1967 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1968 {
1969 ppc405cr_cpc_t *cpc;
1970
1971 cpc = opaque;
1972 switch (dcrn) {
1973 case PPC405CR_CPC0_PLLMR:
1974 cpc->pllmr = val & 0xFFF77C3F;
1975 break;
1976 case PPC405CR_CPC0_CR0:
1977 cpc->cr0 = val & 0x0FFFFFFE;
1978 break;
1979 case PPC405CR_CPC0_CR1:
1980 cpc->cr1 = val & 0x00800000;
1981 break;
1982 case PPC405CR_CPC0_PSR:
1983 /* Read-only */
1984 break;
1985 case PPC405CR_CPC0_JTAGID:
1986 /* Read-only */
1987 break;
1988 case PPC405CR_CPC0_ER:
1989 cpc->er = val & 0xBFFC0000;
1990 break;
1991 case PPC405CR_CPC0_FR:
1992 cpc->fr = val & 0xBFFC0000;
1993 break;
1994 case PPC405CR_CPC0_SR:
1995 /* Read-only */
1996 break;
1997 }
1998 }
1999
2000 static void ppc405cr_cpc_reset (void *opaque)
2001 {
2002 ppc405cr_cpc_t *cpc;
2003 int D;
2004
2005 cpc = opaque;
2006 /* Compute PLLMR value from PSR settings */
2007 cpc->pllmr = 0x80000000;
2008 /* PFWD */
2009 switch ((cpc->psr >> 30) & 3) {
2010 case 0:
2011 /* Bypass */
2012 cpc->pllmr &= ~0x80000000;
2013 break;
2014 case 1:
2015 /* Divide by 3 */
2016 cpc->pllmr |= 5 << 16;
2017 break;
2018 case 2:
2019 /* Divide by 4 */
2020 cpc->pllmr |= 4 << 16;
2021 break;
2022 case 3:
2023 /* Divide by 6 */
2024 cpc->pllmr |= 2 << 16;
2025 break;
2026 }
2027 /* PFBD */
2028 D = (cpc->psr >> 28) & 3;
2029 cpc->pllmr |= (D + 1) << 20;
2030 /* PT */
2031 D = (cpc->psr >> 25) & 7;
2032 switch (D) {
2033 case 0x2:
2034 cpc->pllmr |= 0x13;
2035 break;
2036 case 0x4:
2037 cpc->pllmr |= 0x15;
2038 break;
2039 case 0x5:
2040 cpc->pllmr |= 0x16;
2041 break;
2042 default:
2043 break;
2044 }
2045 /* PDC */
2046 D = (cpc->psr >> 23) & 3;
2047 cpc->pllmr |= D << 26;
2048 /* ODP */
2049 D = (cpc->psr >> 21) & 3;
2050 cpc->pllmr |= D << 10;
2051 /* EBPD */
2052 D = (cpc->psr >> 17) & 3;
2053 cpc->pllmr |= D << 24;
2054 cpc->cr0 = 0x0000003C;
2055 cpc->cr1 = 0x2B0D8800;
2056 cpc->er = 0x00000000;
2057 cpc->fr = 0x00000000;
2058 ppc405cr_clk_setup(cpc);
2059 }
2060
2061 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2062 {
2063 int D;
2064
2065 /* XXX: this should be read from IO pins */
2066 cpc->psr = 0x00000000; /* 8 bits ROM */
2067 /* PFWD */
2068 D = 0x2; /* Divide by 4 */
2069 cpc->psr |= D << 30;
2070 /* PFBD */
2071 D = 0x1; /* Divide by 2 */
2072 cpc->psr |= D << 28;
2073 /* PDC */
2074 D = 0x1; /* Divide by 2 */
2075 cpc->psr |= D << 23;
2076 /* PT */
2077 D = 0x5; /* M = 16 */
2078 cpc->psr |= D << 25;
2079 /* ODP */
2080 D = 0x1; /* Divide by 2 */
2081 cpc->psr |= D << 21;
2082 /* EBDP */
2083 D = 0x2; /* Divide by 4 */
2084 cpc->psr |= D << 17;
2085 }
2086
2087 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2088 uint32_t sysclk)
2089 {
2090 ppc405cr_cpc_t *cpc;
2091
2092 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2093 memcpy(cpc->clk_setup, clk_setup,
2094 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2095 cpc->sysclk = sysclk;
2096 cpc->jtagid = 0x42051049;
2097 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2098 &dcr_read_crcpc, &dcr_write_crcpc);
2099 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2100 &dcr_read_crcpc, &dcr_write_crcpc);
2101 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2102 &dcr_read_crcpc, &dcr_write_crcpc);
2103 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2104 &dcr_read_crcpc, &dcr_write_crcpc);
2105 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2106 &dcr_read_crcpc, &dcr_write_crcpc);
2107 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2108 &dcr_read_crcpc, &dcr_write_crcpc);
2109 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2110 &dcr_read_crcpc, &dcr_write_crcpc);
2111 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2112 &dcr_read_crcpc, &dcr_write_crcpc);
2113 ppc405cr_clk_init(cpc);
2114 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2115 }
2116
2117 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2118 target_phys_addr_t ram_sizes[4],
2119 uint32_t sysclk, qemu_irq **picp,
2120 int do_init)
2121 {
2122 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2123 qemu_irq dma_irqs[4];
2124 CPUState *env;
2125 qemu_irq *pic, *irqs;
2126
2127 memset(clk_setup, 0, sizeof(clk_setup));
2128 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2129 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2130 /* Memory mapped devices registers */
2131 /* PLB arbitrer */
2132 ppc4xx_plb_init(env);
2133 /* PLB to OPB bridge */
2134 ppc4xx_pob_init(env);
2135 /* OBP arbitrer */
2136 ppc4xx_opba_init(0xef600600);
2137 /* Universal interrupt controller */
2138 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2139 irqs[PPCUIC_OUTPUT_INT] =
2140 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2141 irqs[PPCUIC_OUTPUT_CINT] =
2142 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2143 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2144 *picp = pic;
2145 /* SDRAM controller */
2146 ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2147 /* External bus controller */
2148 ppc405_ebc_init(env);
2149 /* DMA controller */
2150 dma_irqs[0] = pic[26];
2151 dma_irqs[1] = pic[25];
2152 dma_irqs[2] = pic[24];
2153 dma_irqs[3] = pic[23];
2154 ppc405_dma_init(env, dma_irqs);
2155 /* Serial ports */
2156 if (serial_hds[0] != NULL) {
2157 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2158 serial_hds[0], 1, 1);
2159 }
2160 if (serial_hds[1] != NULL) {
2161 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2162 serial_hds[1], 1, 1);
2163 }
2164 /* IIC controller */
2165 ppc405_i2c_init(0xef600500, pic[2]);
2166 /* GPIO */
2167 ppc405_gpio_init(0xef600700);
2168 /* CPU control */
2169 ppc405cr_cpc_init(env, clk_setup, sysclk);
2170
2171 return env;
2172 }
2173
2174 /*****************************************************************************/
2175 /* PowerPC 405EP */
2176 /* CPU control */
2177 enum {
2178 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2179 PPC405EP_CPC0_BOOT = 0x0F1,
2180 PPC405EP_CPC0_EPCTL = 0x0F3,
2181 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2182 PPC405EP_CPC0_UCR = 0x0F5,
2183 PPC405EP_CPC0_SRR = 0x0F6,
2184 PPC405EP_CPC0_JTAGID = 0x0F7,
2185 PPC405EP_CPC0_PCI = 0x0F9,
2186 #if 0
2187 PPC405EP_CPC0_ER = xxx,
2188 PPC405EP_CPC0_FR = xxx,
2189 PPC405EP_CPC0_SR = xxx,
2190 #endif
2191 };
2192
2193 enum {
2194 PPC405EP_CPU_CLK = 0,
2195 PPC405EP_PLB_CLK = 1,
2196 PPC405EP_OPB_CLK = 2,
2197 PPC405EP_EBC_CLK = 3,
2198 PPC405EP_MAL_CLK = 4,
2199 PPC405EP_PCI_CLK = 5,
2200 PPC405EP_UART0_CLK = 6,
2201 PPC405EP_UART1_CLK = 7,
2202 PPC405EP_CLK_NB = 8,
2203 };
2204
2205 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2206 struct ppc405ep_cpc_t {
2207 uint32_t sysclk;
2208 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2209 uint32_t boot;
2210 uint32_t epctl;
2211 uint32_t pllmr[2];
2212 uint32_t ucr;
2213 uint32_t srr;
2214 uint32_t jtagid;
2215 uint32_t pci;
2216 /* Clock and power management */
2217 uint32_t er;
2218 uint32_t fr;
2219 uint32_t sr;
2220 };
2221
2222 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2223 {
2224 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2225 uint32_t UART0_clk, UART1_clk;
2226 uint64_t VCO_out, PLL_out;
2227 int M, D;
2228
2229 VCO_out = 0;
2230 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2231 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2232 #ifdef DEBUG_CLOCKS_LL
2233 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2234 #endif
2235 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2236 #ifdef DEBUG_CLOCKS_LL
2237 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2238 #endif
2239 VCO_out = cpc->sysclk * M * D;
2240 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2241 /* Error - unlock the PLL */
2242 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2243 #if 0
2244 cpc->pllmr[1] &= ~0x80000000;
2245 goto pll_bypass;
2246 #endif
2247 }
2248 PLL_out = VCO_out / D;
2249 /* Pretend the PLL is locked */
2250 cpc->boot |= 0x00000001;
2251 } else {
2252 #if 0
2253 pll_bypass:
2254 #endif
2255 PLL_out = cpc->sysclk;
2256 if (cpc->pllmr[1] & 0x40000000) {
2257 /* Pretend the PLL is not locked */
2258 cpc->boot &= ~0x00000001;
2259 }
2260 }
2261 /* Now, compute all other clocks */
2262 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2263 #ifdef DEBUG_CLOCKS_LL
2264 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2265 #endif
2266 CPU_clk = PLL_out / D;
2267 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2268 #ifdef DEBUG_CLOCKS_LL
2269 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2270 #endif
2271 PLB_clk = CPU_clk / D;
2272 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2273 #ifdef DEBUG_CLOCKS_LL
2274 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2275 #endif
2276 OPB_clk = PLB_clk / D;
2277 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2278 #ifdef DEBUG_CLOCKS_LL
2279 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2280 #endif
2281 EBC_clk = PLB_clk / D;
2282 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2283 #ifdef DEBUG_CLOCKS_LL
2284 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2285 #endif
2286 MAL_clk = PLB_clk / D;
2287 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2288 #ifdef DEBUG_CLOCKS_LL
2289 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2290 #endif
2291 PCI_clk = PLB_clk / D;
2292 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2293 #ifdef DEBUG_CLOCKS_LL
2294 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2295 #endif
2296 UART0_clk = PLL_out / D;
2297 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2298 #ifdef DEBUG_CLOCKS_LL
2299 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2300 #endif
2301 UART1_clk = PLL_out / D;
2302 #ifdef DEBUG_CLOCKS
2303 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2304 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2305 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2306 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2307 " UART1 %" PRIu32 "\n",
2308 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2309 UART0_clk, UART1_clk);
2310 #endif
2311 /* Setup CPU clocks */
2312 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2313 /* Setup PLB clock */
2314 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2315 /* Setup OPB clock */
2316 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2317 /* Setup external clock */
2318 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2319 /* Setup MAL clock */
2320 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2321 /* Setup PCI clock */
2322 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2323 /* Setup UART0 clock */
2324 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2325 /* Setup UART1 clock */
2326 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2327 }
2328
2329 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2330 {
2331 ppc405ep_cpc_t *cpc;
2332 uint32_t ret;
2333
2334 cpc = opaque;
2335 switch (dcrn) {
2336 case PPC405EP_CPC0_BOOT:
2337 ret = cpc->boot;
2338 break;
2339 case PPC405EP_CPC0_EPCTL:
2340 ret = cpc->epctl;
2341 break;
2342 case PPC405EP_CPC0_PLLMR0:
2343 ret = cpc->pllmr[0];
2344 break;
2345 case PPC405EP_CPC0_PLLMR1:
2346 ret = cpc->pllmr[1];
2347 break;
2348 case PPC405EP_CPC0_UCR:
2349 ret = cpc->ucr;
2350 break;
2351 case PPC405EP_CPC0_SRR:
2352 ret = cpc->srr;
2353 break;
2354 case PPC405EP_CPC0_JTAGID:
2355 ret = cpc->jtagid;
2356 break;
2357 case PPC405EP_CPC0_PCI:
2358 ret = cpc->pci;
2359 break;
2360 default:
2361 /* Avoid gcc warning */
2362 ret = 0;
2363 break;
2364 }
2365
2366 return ret;
2367 }
2368
2369 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2370 {
2371 ppc405ep_cpc_t *cpc;
2372
2373 cpc = opaque;
2374 switch (dcrn) {
2375 case PPC405EP_CPC0_BOOT:
2376 /* Read-only register */
2377 break;
2378 case PPC405EP_CPC0_EPCTL:
2379 /* Don't care for now */
2380 cpc->epctl = val & 0xC00000F3;
2381 break;
2382 case PPC405EP_CPC0_PLLMR0:
2383 cpc->pllmr[0] = val & 0x00633333;
2384 ppc405ep_compute_clocks(cpc);
2385 break;
2386 case PPC405EP_CPC0_PLLMR1:
2387 cpc->pllmr[1] = val & 0xC0F73FFF;
2388 ppc405ep_compute_clocks(cpc);
2389 break;
2390 case PPC405EP_CPC0_UCR:
2391 /* UART control - don't care for now */
2392 cpc->ucr = val & 0x003F7F7F;
2393 break;
2394 case PPC405EP_CPC0_SRR:
2395 cpc->srr = val;
2396 break;
2397 case PPC405EP_CPC0_JTAGID:
2398 /* Read-only */
2399 break;
2400 case PPC405EP_CPC0_PCI:
2401 cpc->pci = val;
2402 break;
2403 }
2404 }
2405
2406 static void ppc405ep_cpc_reset (void *opaque)
2407 {
2408 ppc405ep_cpc_t *cpc = opaque;
2409
2410 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2411 cpc->epctl = 0x00000000;
2412 cpc->pllmr[0] = 0x00011010;
2413 cpc->pllmr[1] = 0x40000000;
2414 cpc->ucr = 0x00000000;
2415 cpc->srr = 0x00040000;
2416 cpc->pci = 0x00000000;
2417 cpc->er = 0x00000000;
2418 cpc->fr = 0x00000000;
2419 cpc->sr = 0x00000000;
2420 ppc405ep_compute_clocks(cpc);
2421 }
2422
2423 /* XXX: sysclk should be between 25 and 100 MHz */
2424 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2425 uint32_t sysclk)
2426 {
2427 ppc405ep_cpc_t *cpc;
2428
2429 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2430 memcpy(cpc->clk_setup, clk_setup,
2431 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2432 cpc->jtagid = 0x20267049;
2433 cpc->sysclk = sysclk;
2434 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2435 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2436 &dcr_read_epcpc, &dcr_write_epcpc);
2437 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2438 &dcr_read_epcpc, &dcr_write_epcpc);
2439 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2440 &dcr_read_epcpc, &dcr_write_epcpc);
2441 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2442 &dcr_read_epcpc, &dcr_write_epcpc);
2443 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2444 &dcr_read_epcpc, &dcr_write_epcpc);
2445 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2446 &dcr_read_epcpc, &dcr_write_epcpc);
2447 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2448 &dcr_read_epcpc, &dcr_write_epcpc);
2449 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2450 &dcr_read_epcpc, &dcr_write_epcpc);
2451 #if 0
2452 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2453 &dcr_read_epcpc, &dcr_write_epcpc);
2454 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2455 &dcr_read_epcpc, &dcr_write_epcpc);
2456 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2457 &dcr_read_epcpc, &dcr_write_epcpc);
2458 #endif
2459 }
2460
2461 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2462 target_phys_addr_t ram_sizes[2],
2463 uint32_t sysclk, qemu_irq **picp,
2464 int do_init)
2465 {
2466 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2467 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2468 CPUState *env;
2469 qemu_irq *pic, *irqs;
2470
2471 memset(clk_setup, 0, sizeof(clk_setup));
2472 /* init CPUs */
2473 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2474 &tlb_clk_setup, sysclk);
2475 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2476 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2477 /* Internal devices init */
2478 /* Memory mapped devices registers */
2479 /* PLB arbitrer */
2480 ppc4xx_plb_init(env);
2481 /* PLB to OPB bridge */
2482 ppc4xx_pob_init(env);
2483 /* OBP arbitrer */
2484 ppc4xx_opba_init(0xef600600);
2485 /* Universal interrupt controller */
2486 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2487 irqs[PPCUIC_OUTPUT_INT] =
2488 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2489 irqs[PPCUIC_OUTPUT_CINT] =
2490 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2491 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2492 *picp = pic;
2493 /* SDRAM controller */
2494 /* XXX 405EP has no ECC interrupt */
2495 ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2496 /* External bus controller */
2497 ppc405_ebc_init(env);
2498 /* DMA controller */
2499 dma_irqs[0] = pic[5];
2500 dma_irqs[1] = pic[6];
2501 dma_irqs[2] = pic[7];
2502 dma_irqs[3] = pic[8];
2503 ppc405_dma_init(env, dma_irqs);
2504 /* IIC controller */
2505 ppc405_i2c_init(0xef600500, pic[2]);
2506 /* GPIO */
2507 ppc405_gpio_init(0xef600700);
2508 /* Serial ports */
2509 if (serial_hds[0] != NULL) {
2510 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2511 serial_hds[0], 1, 1);
2512 }
2513 if (serial_hds[1] != NULL) {
2514 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2515 serial_hds[1], 1, 1);
2516 }
2517 /* OCM */
2518 ppc405_ocm_init(env);
2519 /* GPT */
2520 gpt_irqs[0] = pic[19];
2521 gpt_irqs[1] = pic[20];
2522 gpt_irqs[2] = pic[21];
2523 gpt_irqs[3] = pic[22];
2524 gpt_irqs[4] = pic[23];
2525 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2526 /* PCI */
2527 /* Uses pic[3], pic[16], pic[18] */
2528 /* MAL */
2529 mal_irqs[0] = pic[11];
2530 mal_irqs[1] = pic[12];
2531 mal_irqs[2] = pic[13];
2532 mal_irqs[3] = pic[14];
2533 ppc405_mal_init(env, mal_irqs);
2534 /* Ethernet */
2535 /* Uses pic[9], pic[15], pic[17] */
2536 /* CPU control */
2537 ppc405ep_cpc_init(env, clk_setup, sysclk);
2538
2539 return env;
2540 }
QEmu