hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pci_bridge.h"
  27 #include "pci_internals.h"
  28 #include "msix.h"
  29 #include "msi.h"
  30 #include "monitor.h"
  31 #include "net.h"
  32 #include "sysemu.h"
  33 #include "loader.h"
  34 #include "qemu-objects.h"
  35 #include "range.h"
  36
  37 //#define DEBUG_PCI
  38 #ifdef DEBUG_PCI
  39 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  40 #else
  41 # define PCI_DPRINTF(format, ...)       do { } while (0)
  42 #endif
  43
  44 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  45 static char *pcibus_get_dev_path(DeviceState *dev);
  46
  47 struct BusInfo pci_bus_info = {
  48     .name       = "PCI",
  49     .size       = sizeof(PCIBus),
  50     .print_dev  = pcibus_dev_print,
  51     .get_dev_path = pcibus_get_dev_path,
  52     .props      = (Property[]) {
  53         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  54         DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
  55         DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
  56         DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
  57                         QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
  58         DEFINE_PROP_END_OF_LIST()
  59     }
  60 };
  61
  62 static void pci_update_mappings(PCIDevice *d);
  63 static void pci_set_irq(void *opaque, int irq_num, int level);
  64 static int pci_add_option_rom(PCIDevice *pdev);
  65 static void pci_del_option_rom(PCIDevice *pdev);
  66
  67 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  68 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  69
  70 struct PCIHostBus {
  71     int domain;
  72     struct PCIBus *bus;
  73     QLIST_ENTRY(PCIHostBus) next;
  74 };
  75 static QLIST_HEAD(, PCIHostBus) host_buses;
  76
  77 static const VMStateDescription vmstate_pcibus = {
  78     .name = "PCIBUS",
  79     .version_id = 1,
  80     .minimum_version_id = 1,
  81     .minimum_version_id_old = 1,
  82     .fields      = (VMStateField []) {
  83         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  84         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  85         VMSTATE_END_OF_LIST()
  86     }
  87 };
  88
  89 static int pci_bar(PCIDevice *d, int reg)
  90 {
  91     uint8_t type;
  92
  93     if (reg != PCI_ROM_SLOT)
  94         return PCI_BASE_ADDRESS_0 + reg * 4;
  95
  96     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
  97     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
  98 }
  99
 100 static inline int pci_irq_state(PCIDevice *d, int irq_num)
 101 {
 102         return (d->irq_state >> irq_num) & 0x1;
 103 }
 104
 105 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
 106 {
 107         d->irq_state &= ~(0x1 << irq_num);
 108         d->irq_state |= level << irq_num;
 109 }
 110
 111 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
 112 {
 113     PCIBus *bus;
 114     for (;;) {
 115         bus = pci_dev->bus;
 116         irq_num = bus->map_irq(pci_dev, irq_num);
 117         if (bus->set_irq)
 118             break;
 119         pci_dev = bus->parent_dev;
 120     }
 121     bus->irq_count[irq_num] += change;
 122     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 123 }
 124
 125 /* Update interrupt status bit in config space on interrupt
 126  * state change. */
 127 static void pci_update_irq_status(PCIDevice *dev)
 128 {
 129     if (dev->irq_state) {
 130         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
 131     } else {
 132         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 133     }
 134 }
 135
 136 static void pci_device_reset(PCIDevice *dev)
 137 {
 138     int r;
 139
 140     dev->irq_state = 0;
 141     pci_update_irq_status(dev);
 142     /* Clear all writeable bits */
 143     pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
 144                                  pci_get_word(dev->wmask + PCI_COMMAND) |
 145                                  pci_get_word(dev->w1cmask + PCI_COMMAND));
 146     pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
 147                                  pci_get_word(dev->wmask + PCI_STATUS) |
 148                                  pci_get_word(dev->w1cmask + PCI_STATUS));
 149     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 150     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 151     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 152         PCIIORegion *region = &dev->io_regions[r];
 153         if (!region->size) {
 154             continue;
 155         }
 156
 157         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 158             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 159             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
 160         } else {
 161             pci_set_long(dev->config + pci_bar(dev, r), region->type);
 162         }
 163     }
 164     pci_update_mappings(dev);
 165 }
 166
 167 static void pci_bus_reset(void *opaque)
 168 {
 169     PCIBus *bus = opaque;
 170     int i;
 171
 172     for (i = 0; i < bus->nirq; i++) {
 173         bus->irq_count[i] = 0;
 174     }
 175     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 176         if (bus->devices[i]) {
 177             pci_device_reset(bus->devices[i]);
 178         }
 179     }
 180 }
 181
 182 static void pci_host_bus_register(int domain, PCIBus *bus)
 183 {
 184     struct PCIHostBus *host;
 185     host = qemu_mallocz(sizeof(*host));
 186     host->domain = domain;
 187     host->bus = bus;
 188     QLIST_INSERT_HEAD(&host_buses, host, next);
 189 }
 190
 191 PCIBus *pci_find_root_bus(int domain)
 192 {
 193     struct PCIHostBus *host;
 194
 195     QLIST_FOREACH(host, &host_buses, next) {
 196         if (host->domain == domain) {
 197             return host->bus;
 198         }
 199     }
 200
 201     return NULL;
 202 }
 203
 204 int pci_find_domain(const PCIBus *bus)
 205 {
 206     PCIDevice *d;
 207     struct PCIHostBus *host;
 208
 209     /* obtain root bus */
 210     while ((d = bus->parent_dev) != NULL) {
 211         bus = d->bus;
 212     }
 213
 214     QLIST_FOREACH(host, &host_buses, next) {
 215         if (host->bus == bus) {
 216             return host->domain;
 217         }
 218     }
 219
 220     abort();    /* should not be reached */
 221     return -1;
 222 }
 223
 224 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 225                          const char *name, int devfn_min)
 226 {
 227     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 228     assert(PCI_FUNC(devfn_min) == 0);
 229     bus->devfn_min = devfn_min;
 230
 231     /* host bridge */
 232     QLIST_INIT(&bus->child);
 233     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 234
 235     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
 236     qemu_register_reset(pci_bus_reset, bus);
 237 }
 238
 239 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 240 {
 241     PCIBus *bus;
 242
 243     bus = qemu_mallocz(sizeof(*bus));
 244     bus->qbus.qdev_allocated = 1;
 245     pci_bus_new_inplace(bus, parent, name, devfn_min);
 246     return bus;
 247 }
 248
 249 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 250                   void *irq_opaque, int nirq)
 251 {
 252     bus->set_irq = set_irq;
 253     bus->map_irq = map_irq;
 254     bus->irq_opaque = irq_opaque;
 255     bus->nirq = nirq;
 256     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 257 }
 258
 259 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
 260 {
 261     bus->qbus.allow_hotplug = 1;
 262     bus->hotplug = hotplug;
 263     bus->hotplug_qdev = qdev;
 264 }
 265
 266 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
 267 {
 268     bus->mem_base = base;
 269 }
 270
 271 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 272                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 273                          void *irq_opaque, int devfn_min, int nirq)
 274 {
 275     PCIBus *bus;
 276
 277     bus = pci_bus_new(parent, name, devfn_min);
 278     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 279     return bus;
 280 }
 281
 282 int pci_bus_num(PCIBus *s)
 283 {
 284     if (!s->parent_dev)
 285         return 0;       /* pci host bridge */
 286     return s->parent_dev->config[PCI_SECONDARY_BUS];
 287 }
 288
 289 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 290 {
 291     PCIDevice *s = container_of(pv, PCIDevice, config);
 292     uint8_t *config;
 293     int i;
 294
 295     assert(size == pci_config_size(s));
 296     config = qemu_malloc(size);
 297
 298     qemu_get_buffer(f, config, size);
 299     for (i = 0; i < size; ++i) {
 300         if ((config[i] ^ s->config[i]) &
 301             s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
 302             qemu_free(config);
 303             return -EINVAL;
 304         }
 305     }
 306     memcpy(s->config, config, size);
 307
 308     pci_update_mappings(s);
 309
 310     qemu_free(config);
 311     return 0;
 312 }
 313
 314 /* just put buffer */
 315 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 316 {
 317     const uint8_t **v = pv;
 318     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 319     qemu_put_buffer(f, *v, size);
 320 }
 321
 322 static VMStateInfo vmstate_info_pci_config = {
 323     .name = "pci config",
 324     .get  = get_pci_config_device,
 325     .put  = put_pci_config_device,
 326 };
 327
 328 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 329 {
 330     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 331     uint32_t irq_state[PCI_NUM_PINS];
 332     int i;
 333     for (i = 0; i < PCI_NUM_PINS; ++i) {
 334         irq_state[i] = qemu_get_be32(f);
 335         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
 336             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
 337                     irq_state[i]);
 338             return -EINVAL;
 339         }
 340     }
 341
 342     for (i = 0; i < PCI_NUM_PINS; ++i) {
 343         pci_set_irq_state(s, i, irq_state[i]);
 344     }
 345
 346     return 0;
 347 }
 348
 349 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 350 {
 351     int i;
 352     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 353
 354     for (i = 0; i < PCI_NUM_PINS; ++i) {
 355         qemu_put_be32(f, pci_irq_state(s, i));
 356     }
 357 }
 358
 359 static VMStateInfo vmstate_info_pci_irq_state = {
 360     .name = "pci irq state",
 361     .get  = get_pci_irq_state,
 362     .put  = put_pci_irq_state,
 363 };
 364
 365 const VMStateDescription vmstate_pci_device = {
 366     .name = "PCIDevice",
 367     .version_id = 2,
 368     .minimum_version_id = 1,
 369     .minimum_version_id_old = 1,
 370     .fields      = (VMStateField []) {
 371         VMSTATE_INT32_LE(version_id, PCIDevice),
 372         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 373                                    vmstate_info_pci_config,
 374                                    PCI_CONFIG_SPACE_SIZE),
 375         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 376                                    vmstate_info_pci_irq_state,
 377                                    PCI_NUM_PINS * sizeof(int32_t)),
 378         VMSTATE_END_OF_LIST()
 379     }
 380 };
 381
 382 const VMStateDescription vmstate_pcie_device = {
 383     .name = "PCIDevice",
 384     .version_id = 2,
 385     .minimum_version_id = 1,
 386     .minimum_version_id_old = 1,
 387     .fields      = (VMStateField []) {
 388         VMSTATE_INT32_LE(version_id, PCIDevice),
 389         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 390                                    vmstate_info_pci_config,
 391                                    PCIE_CONFIG_SPACE_SIZE),
 392         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 393                                    vmstate_info_pci_irq_state,
 394                                    PCI_NUM_PINS * sizeof(int32_t)),
 395         VMSTATE_END_OF_LIST()
 396     }
 397 };
 398
 399 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 400 {
 401     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 402 }
 403
 404 void pci_device_save(PCIDevice *s, QEMUFile *f)
 405 {
 406     /* Clear interrupt status bit: it is implicit
 407      * in irq_state which we are saving.
 408      * This makes us compatible with old devices
 409      * which never set or clear this bit. */
 410     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 411     vmstate_save_state(f, pci_get_vmstate(s), s);
 412     /* Restore the interrupt status bit. */
 413     pci_update_irq_status(s);
 414 }
 415
 416 int pci_device_load(PCIDevice *s, QEMUFile *f)
 417 {
 418     int ret;
 419     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 420     /* Restore the interrupt status bit. */
 421     pci_update_irq_status(s);
 422     return ret;
 423 }
 424
 425 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
 426 {
 427     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
 428                  pci_default_sub_vendor_id);
 429     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
 430                  pci_default_sub_device_id);
 431 }
 432
 433 /*
 434  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
 435  *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
 436  */
 437 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 438                       unsigned int *slotp, unsigned int *funcp)
 439 {
 440     const char *p;
 441     char *e;
 442     unsigned long val;
 443     unsigned long dom = 0, bus = 0;
 444     unsigned int slot = 0;
 445     unsigned int func = 0;
 446
 447     p = addr;
 448     val = strtoul(p, &e, 16);
 449     if (e == p)
 450         return -1;
 451     if (*e == ':') {
 452         bus = val;
 453         p = e + 1;
 454         val = strtoul(p, &e, 16);
 455         if (e == p)
 456             return -1;
 457         if (*e == ':') {
 458             dom = bus;
 459             bus = val;
 460             p = e + 1;
 461             val = strtoul(p, &e, 16);
 462             if (e == p)
 463                 return -1;
 464         }
 465     }
 466
 467     slot = val;
 468
 469     if (funcp != NULL) {
 470         if (*e != '.')
 471             return -1;
 472
 473         p = e + 1;
 474         val = strtoul(p, &e, 16);
 475         if (e == p)
 476             return -1;
 477
 478         func = val;
 479     }
 480
 481     /* if funcp == NULL func is 0 */
 482     if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
 483         return -1;
 484
 485     if (*e)
 486         return -1;
 487
 488     /* Note: QEMU doesn't implement domains other than 0 */
 489     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 490         return -1;
 491
 492     *domp = dom;
 493     *busp = bus;
 494     *slotp = slot;
 495     if (funcp != NULL)
 496         *funcp = func;
 497     return 0;
 498 }
 499
 500 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 501                      unsigned *slotp)
 502 {
 503     /* strip legacy tag */
 504     if (!strncmp(addr, "pci_addr=", 9)) {
 505         addr += 9;
 506     }
 507     if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
 508         monitor_printf(mon, "Invalid pci address\n");
 509         return -1;
 510     }
 511     return 0;
 512 }
 513
 514 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 515 {
 516     int dom, bus;
 517     unsigned slot;
 518
 519     if (!devaddr) {
 520         *devfnp = -1;
 521         return pci_find_bus(pci_find_root_bus(0), 0);
 522     }
 523
 524     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
 525         return NULL;
 526     }
 527
 528     *devfnp = slot << 3;
 529     return pci_find_bus(pci_find_root_bus(dom), bus);
 530 }
 531
 532 static void pci_init_cmask(PCIDevice *dev)
 533 {
 534     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 535     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 536     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 537     dev->cmask[PCI_REVISION_ID] = 0xff;
 538     dev->cmask[PCI_CLASS_PROG] = 0xff;
 539     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 540     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 541     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 542 }
 543
 544 static void pci_init_wmask(PCIDevice *dev)
 545 {
 546     int config_size = pci_config_size(dev);
 547
 548     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 549     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 550     pci_set_word(dev->wmask + PCI_COMMAND,
 551                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 552                  PCI_COMMAND_INTX_DISABLE);
 553
 554     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 555            config_size - PCI_CONFIG_HEADER_SIZE);
 556 }
 557
 558 static void pci_init_w1cmask(PCIDevice *dev)
 559 {
 560     /*
 561      * Note: It's okay to set w1mask even for readonly bits as
 562      * long as their value is hardwired to 0.
 563      */
 564     pci_set_word(dev->w1cmask + PCI_STATUS,
 565                  PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
 566                  PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
 567                  PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
 568 }
 569
 570 static void pci_init_wmask_bridge(PCIDevice *d)
 571 {
 572     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 573        PCI_SEC_LETENCY_TIMER */
 574     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 575
 576     /* base and limit */
 577     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 578     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 579     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 580                  PCI_MEMORY_RANGE_MASK & 0xffff);
 581     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 582                  PCI_MEMORY_RANGE_MASK & 0xffff);
 583     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 584                  PCI_PREF_RANGE_MASK & 0xffff);
 585     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 586                  PCI_PREF_RANGE_MASK & 0xffff);
 587
 588     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 589     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 590
 591     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 592 }
 593
 594 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
 595 {
 596     uint8_t slot = PCI_SLOT(dev->devfn);
 597     uint8_t func;
 598
 599     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 600         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
 601     }
 602
 603     /*
 604      * multifunction bit is interpreted in two ways as follows.
 605      *   - all functions must set the bit to 1.
 606      *     Example: Intel X53
 607      *   - function 0 must set the bit, but the rest function (> 0)
 608      *     is allowed to leave the bit to 0.
 609      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
 610      *
 611      * So OS (at least Linux) checks the bit of only function 0,
 612      * and doesn't see the bit of function > 0.
 613      *
 614      * The below check allows both interpretation.
 615      */
 616     if (PCI_FUNC(dev->devfn)) {
 617         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
 618         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
 619             /* function 0 should set multifunction bit */
 620             error_report("PCI: single function device can't be populated "
 621                          "in function %x.%x", slot, PCI_FUNC(dev->devfn));
 622             return -1;
 623         }
 624         return 0;
 625     }
 626
 627     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 628         return 0;
 629     }
 630     /* function 0 indicates single function, so function > 0 must be NULL */
 631     for (func = 1; func < PCI_FUNC_MAX; ++func) {
 632         if (bus->devices[PCI_DEVFN(slot, func)]) {
 633             error_report("PCI: %x.0 indicates single function, "
 634                          "but %x.%x is already populated.",
 635                          slot, slot, func);
 636             return -1;
 637         }
 638     }
 639     return 0;
 640 }
 641
 642 static void pci_config_alloc(PCIDevice *pci_dev)
 643 {
 644     int config_size = pci_config_size(pci_dev);
 645
 646     pci_dev->config = qemu_mallocz(config_size);
 647     pci_dev->cmask = qemu_mallocz(config_size);
 648     pci_dev->wmask = qemu_mallocz(config_size);
 649     pci_dev->w1cmask = qemu_mallocz(config_size);
 650     pci_dev->used = qemu_mallocz(config_size);
 651 }
 652
 653 static void pci_config_free(PCIDevice *pci_dev)
 654 {
 655     qemu_free(pci_dev->config);
 656     qemu_free(pci_dev->cmask);
 657     qemu_free(pci_dev->wmask);
 658     qemu_free(pci_dev->w1cmask);
 659     qemu_free(pci_dev->used);
 660 }
 661
 662 /* -1 for devfn means auto assign */
 663 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 664                                          const char *name, int devfn,
 665                                          PCIConfigReadFunc *config_read,
 666                                          PCIConfigWriteFunc *config_write,
 667                                          bool is_bridge)
 668 {
 669     if (devfn < 0) {
 670         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 671             devfn += PCI_FUNC_MAX) {
 672             if (!bus->devices[devfn])
 673                 goto found;
 674         }
 675         error_report("PCI: no slot/function available for %s, all in use", name);
 676         return NULL;
 677     found: ;
 678     } else if (bus->devices[devfn]) {
 679         error_report("PCI: slot %d function %d not available for %s, in use by %s",
 680                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
 681         return NULL;
 682     }
 683     pci_dev->bus = bus;
 684     pci_dev->devfn = devfn;
 685     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 686     pci_dev->irq_state = 0;
 687     pci_config_alloc(pci_dev);
 688
 689     if (!is_bridge) {
 690         pci_set_default_subsystem_id(pci_dev);
 691     }
 692     pci_init_cmask(pci_dev);
 693     pci_init_wmask(pci_dev);
 694     pci_init_w1cmask(pci_dev);
 695     if (is_bridge) {
 696         pci_init_wmask_bridge(pci_dev);
 697     }
 698     if (pci_init_multifunction(bus, pci_dev)) {
 699         pci_config_free(pci_dev);
 700         return NULL;
 701     }
 702
 703     if (!config_read)
 704         config_read = pci_default_read_config;
 705     if (!config_write)
 706         config_write = pci_default_write_config;
 707     pci_dev->config_read = config_read;
 708     pci_dev->config_write = config_write;
 709     bus->devices[devfn] = pci_dev;
 710     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 711     pci_dev->version_id = 2; /* Current pci device vmstate version */
 712     return pci_dev;
 713 }
 714
 715 static void do_pci_unregister_device(PCIDevice *pci_dev)
 716 {
 717     qemu_free_irqs(pci_dev->irq);
 718     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 719     pci_config_free(pci_dev);
 720 }
 721
 722 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 723                                int instance_size, int devfn,
 724                                PCIConfigReadFunc *config_read,
 725                                PCIConfigWriteFunc *config_write)
 726 {
 727     PCIDevice *pci_dev;
 728
 729     pci_dev = qemu_mallocz(instance_size);
 730     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 731                                      config_read, config_write,
 732                                      PCI_HEADER_TYPE_NORMAL);
 733     if (pci_dev == NULL) {
 734         hw_error("PCI: can't register device\n");
 735     }
 736     return pci_dev;
 737 }
 738
 739 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
 740                                           target_phys_addr_t addr)
 741 {
 742     return addr + bus->mem_base;
 743 }
 744
 745 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 746 {
 747     PCIIORegion *r;
 748     int i;
 749
 750     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 751         r = &pci_dev->io_regions[i];
 752         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 753             continue;
 754         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 755             isa_unassign_ioport(r->addr, r->filtered_size);
 756         } else {
 757             cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
 758                                                          r->addr),
 759                                          r->filtered_size,
 760                                          IO_MEM_UNASSIGNED);
 761         }
 762     }
 763 }
 764
 765 static int pci_unregister_device(DeviceState *dev)
 766 {
 767     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 768     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 769     int ret = 0;
 770
 771     if (info->exit)
 772         ret = info->exit(pci_dev);
 773     if (ret)
 774         return ret;
 775
 776     pci_unregister_io_regions(pci_dev);
 777     pci_del_option_rom(pci_dev);
 778     do_pci_unregister_device(pci_dev);
 779     return 0;
 780 }
 781
 782 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 783                             pcibus_t size, uint8_t type,
 784                             PCIMapIORegionFunc *map_func)
 785 {
 786     PCIIORegion *r;
 787     uint32_t addr;
 788     uint64_t wmask;
 789
 790     assert(region_num >= 0);
 791     assert(region_num < PCI_NUM_REGIONS);
 792     if (size & (size-1)) {
 793         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 794                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 795         exit(1);
 796     }
 797
 798     r = &pci_dev->io_regions[region_num];
 799     r->addr = PCI_BAR_UNMAPPED;
 800     r->size = size;
 801     r->filtered_size = size;
 802     r->type = type;
 803     r->map_func = map_func;
 804
 805     wmask = ~(size - 1);
 806     addr = pci_bar(pci_dev, region_num);
 807     if (region_num == PCI_ROM_SLOT) {
 808         /* ROM enable bit is writeable */
 809         wmask |= PCI_ROM_ADDRESS_ENABLE;
 810     }
 811     pci_set_long(pci_dev->config + addr, type);
 812     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 813         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 814         pci_set_quad(pci_dev->wmask + addr, wmask);
 815         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 816     } else {
 817         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 818         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 819     }
 820 }
 821
 822 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 823                               uint8_t type)
 824 {
 825     pcibus_t base = *addr;
 826     pcibus_t limit = *addr + *size - 1;
 827     PCIDevice *br;
 828
 829     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 830         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 831
 832         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 833             if (!(cmd & PCI_COMMAND_IO)) {
 834                 goto no_map;
 835             }
 836         } else {
 837             if (!(cmd & PCI_COMMAND_MEMORY)) {
 838                 goto no_map;
 839             }
 840         }
 841
 842         base = MAX(base, pci_bridge_get_base(br, type));
 843         limit = MIN(limit, pci_bridge_get_limit(br, type));
 844     }
 845
 846     if (base > limit) {
 847         goto no_map;
 848     }
 849     *addr = base;
 850     *size = limit - base + 1;
 851     return;
 852 no_map:
 853     *addr = PCI_BAR_UNMAPPED;
 854     *size = 0;
 855 }
 856
 857 static pcibus_t pci_bar_address(PCIDevice *d,
 858                                 int reg, uint8_t type, pcibus_t size)
 859 {
 860     pcibus_t new_addr, last_addr;
 861     int bar = pci_bar(d, reg);
 862     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 863
 864     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 865         if (!(cmd & PCI_COMMAND_IO)) {
 866             return PCI_BAR_UNMAPPED;
 867         }
 868         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 869         last_addr = new_addr + size - 1;
 870         /* NOTE: we have only 64K ioports on PC */
 871         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 872             return PCI_BAR_UNMAPPED;
 873         }
 874         return new_addr;
 875     }
 876
 877     if (!(cmd & PCI_COMMAND_MEMORY)) {
 878         return PCI_BAR_UNMAPPED;
 879     }
 880     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 881         new_addr = pci_get_quad(d->config + bar);
 882     } else {
 883         new_addr = pci_get_long(d->config + bar);
 884     }
 885     /* the ROM slot has a specific enable bit */
 886     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 887         return PCI_BAR_UNMAPPED;
 888     }
 889     new_addr &= ~(size - 1);
 890     last_addr = new_addr + size - 1;
 891     /* NOTE: we do not support wrapping */
 892     /* XXX: as we cannot support really dynamic
 893        mappings, we handle specific values as invalid
 894        mappings. */
 895     if (last_addr <= new_addr || new_addr == 0 ||
 896         last_addr == PCI_BAR_UNMAPPED) {
 897         return PCI_BAR_UNMAPPED;
 898     }
 899
 900     /* Now pcibus_t is 64bit.
 901      * Check if 32 bit BAR wraps around explicitly.
 902      * Without this, PC ide doesn't work well.
 903      * TODO: remove this work around.
 904      */
 905     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 906         return PCI_BAR_UNMAPPED;
 907     }
 908
 909     /*
 910      * OS is allowed to set BAR beyond its addressable
 911      * bits. For example, 32 bit OS can set 64bit bar
 912      * to >4G. Check it. TODO: we might need to support
 913      * it in the future for e.g. PAE.
 914      */
 915     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 916         return PCI_BAR_UNMAPPED;
 917     }
 918
 919     return new_addr;
 920 }
 921
 922 static void pci_update_mappings(PCIDevice *d)
 923 {
 924     PCIIORegion *r;
 925     int i;
 926     pcibus_t new_addr, filtered_size;
 927
 928     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 929         r = &d->io_regions[i];
 930
 931         /* this region isn't registered */
 932         if (!r->size)
 933             continue;
 934
 935         new_addr = pci_bar_address(d, i, r->type, r->size);
 936
 937         /* bridge filtering */
 938         filtered_size = r->size;
 939         if (new_addr != PCI_BAR_UNMAPPED) {
 940             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 941         }
 942
 943         /* This bar isn't changed */
 944         if (new_addr == r->addr && filtered_size == r->filtered_size)
 945             continue;
 946
 947         /* now do the real mapping */
 948         if (r->addr != PCI_BAR_UNMAPPED) {
 949             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 950                 int class;
 951                 /* NOTE: specific hack for IDE in PC case:
 952                    only one byte must be mapped. */
 953                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 954                 if (class == 0x0101 && r->size == 4) {
 955                     isa_unassign_ioport(r->addr + 2, 1);
 956                 } else {
 957                     isa_unassign_ioport(r->addr, r->filtered_size);
 958                 }
 959             } else {
 960                 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
 961                                              r->filtered_size,
 962                                              IO_MEM_UNASSIGNED);
 963                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 964             }
 965         }
 966         r->addr = new_addr;
 967         r->filtered_size = filtered_size;
 968         if (r->addr != PCI_BAR_UNMAPPED) {
 969             /*
 970              * TODO: currently almost all the map funcions assumes
 971              * filtered_size == size and addr & ~(size - 1) == addr.
 972              * However with bridge filtering, they aren't always true.
 973              * Teach them such cases, such that filtered_size < size and
 974              * addr & (size - 1) != 0.
 975              */
 976             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 977                 r->map_func(d, i, r->addr, r->filtered_size, r->type);
 978             } else {
 979                 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
 980                             r->filtered_size, r->type);
 981             }
 982         }
 983     }
 984 }
 985
 986 static inline int pci_irq_disabled(PCIDevice *d)
 987 {
 988     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
 989 }
 990
 991 /* Called after interrupt disabled field update in config space,
 992  * assert/deassert interrupts if necessary.
 993  * Gets original interrupt disable bit value (before update). */
 994 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
 995 {
 996     int i, disabled = pci_irq_disabled(d);
 997     if (disabled == was_irq_disabled)
 998         return;
 999     for (i = 0; i < PCI_NUM_PINS; ++i) {
1000         int state = pci_irq_state(d, i);
1001         pci_change_irq_level(d, i, disabled ? -state : state);
1002     }
1003 }
1004
1005 uint32_t pci_default_read_config(PCIDevice *d,
1006                                  uint32_t address, int len)
1007 {
1008     uint32_t val = 0;
1009     assert(len == 1 || len == 2 || len == 4);
1010     len = MIN(len, pci_config_size(d) - address);
1011     memcpy(&val, d->config + address, len);
1012     return le32_to_cpu(val);
1013 }
1014
1015 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1016 {
1017     int i, was_irq_disabled = pci_irq_disabled(d);
1018     uint32_t config_size = pci_config_size(d);
1019
1020     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1021         uint8_t wmask = d->wmask[addr + i];
1022         uint8_t w1cmask = d->w1cmask[addr + i];
1023         assert(!(wmask & w1cmask));
1024         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1025         d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1026     }
1027     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1028         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1029         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1030         range_covers_byte(addr, l, PCI_COMMAND))
1031         pci_update_mappings(d);
1032
1033     if (range_covers_byte(addr, l, PCI_COMMAND))
1034         pci_update_irq_disabled(d, was_irq_disabled);
1035 }
1036
1037 /***********************************************************/
1038 /* generic PCI irq support */
1039
1040 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1041 static void pci_set_irq(void *opaque, int irq_num, int level)
1042 {
1043     PCIDevice *pci_dev = opaque;
1044     int change;
1045
1046     change = level - pci_irq_state(pci_dev, irq_num);
1047     if (!change)
1048         return;
1049
1050     pci_set_irq_state(pci_dev, irq_num, level);
1051     pci_update_irq_status(pci_dev);
1052     if (pci_irq_disabled(pci_dev))
1053         return;
1054     pci_change_irq_level(pci_dev, irq_num, change);
1055 }
1056
1057 bool pci_msi_enabled(PCIDevice *dev)
1058 {
1059     return msix_enabled(dev) || msi_enabled(dev);
1060 }
1061
1062 void pci_msi_notify(PCIDevice *dev, unsigned int vector)
1063 {
1064     if (msix_enabled(dev)) {
1065         msix_notify(dev, vector);
1066     } else if (msi_enabled(dev)) {
1067         msi_notify(dev, vector);
1068     } else {
1069         /* MSI/MSI-X must be enabled */
1070         abort();
1071     }
1072 }
1073
1074 /***********************************************************/
1075 /* monitor info on PCI */
1076
1077 typedef struct {
1078     uint16_t class;
1079     const char *desc;
1080 } pci_class_desc;
1081
1082 static const pci_class_desc pci_class_descriptions[] =
1083 {
1084     { 0x0100, "SCSI controller"},
1085     { 0x0101, "IDE controller"},
1086     { 0x0102, "Floppy controller"},
1087     { 0x0103, "IPI controller"},
1088     { 0x0104, "RAID controller"},
1089     { 0x0106, "SATA controller"},
1090     { 0x0107, "SAS controller"},
1091     { 0x0180, "Storage controller"},
1092     { 0x0200, "Ethernet controller"},
1093     { 0x0201, "Token Ring controller"},
1094     { 0x0202, "FDDI controller"},
1095     { 0x0203, "ATM controller"},
1096     { 0x0280, "Network controller"},
1097     { 0x0300, "VGA controller"},
1098     { 0x0301, "XGA controller"},
1099     { 0x0302, "3D controller"},
1100     { 0x0380, "Display controller"},
1101     { 0x0400, "Video controller"},
1102     { 0x0401, "Audio controller"},
1103     { 0x0402, "Phone"},
1104     { 0x0480, "Multimedia controller"},
1105     { 0x0500, "RAM controller"},
1106     { 0x0501, "Flash controller"},
1107     { 0x0580, "Memory controller"},
1108     { 0x0600, "Host bridge"},
1109     { 0x0601, "ISA bridge"},
1110     { 0x0602, "EISA bridge"},
1111     { 0x0603, "MC bridge"},
1112     { 0x0604, "PCI bridge"},
1113     { 0x0605, "PCMCIA bridge"},
1114     { 0x0606, "NUBUS bridge"},
1115     { 0x0607, "CARDBUS bridge"},
1116     { 0x0608, "RACEWAY bridge"},
1117     { 0x0680, "Bridge"},
1118     { 0x0c03, "USB controller"},
1119     { 0, NULL}
1120 };
1121
1122 static void pci_for_each_device_under_bus(PCIBus *bus,
1123                                           void (*fn)(PCIBus *b, PCIDevice *d))
1124 {
1125     PCIDevice *d;
1126     int devfn;
1127
1128     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1129         d = bus->devices[devfn];
1130         if (d) {
1131             fn(bus, d);
1132         }
1133     }
1134 }
1135
1136 void pci_for_each_device(PCIBus *bus, int bus_num,
1137                          void (*fn)(PCIBus *b, PCIDevice *d))
1138 {
1139     bus = pci_find_bus(bus, bus_num);
1140
1141     if (bus) {
1142         pci_for_each_device_under_bus(bus, fn);
1143     }
1144 }
1145
1146 static void pci_device_print(Monitor *mon, QDict *device)
1147 {
1148     QDict *qdict;
1149     QListEntry *entry;
1150     uint64_t addr, size;
1151
1152     monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1153     monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1154                         qdict_get_int(device, "slot"),
1155                         qdict_get_int(device, "function"));
1156     monitor_printf(mon, "    ");
1157
1158     qdict = qdict_get_qdict(device, "class_info");
1159     if (qdict_haskey(qdict, "desc")) {
1160         monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1161     } else {
1162         monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1163     }
1164
1165     qdict = qdict_get_qdict(device, "id");
1166     monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1167                         qdict_get_int(qdict, "device"),
1168                         qdict_get_int(qdict, "vendor"));
1169
1170     if (qdict_haskey(device, "irq")) {
1171         monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1172                             qdict_get_int(device, "irq"));
1173     }
1174
1175     if (qdict_haskey(device, "pci_bridge")) {
1176         QDict *info;
1177
1178         qdict = qdict_get_qdict(device, "pci_bridge");
1179
1180         info = qdict_get_qdict(qdict, "bus");
1181         monitor_printf(mon, "      BUS %" PRId64 ".\n",
1182                             qdict_get_int(info, "number"));
1183         monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1184                             qdict_get_int(info, "secondary"));
1185         monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1186                             qdict_get_int(info, "subordinate"));
1187
1188         info = qdict_get_qdict(qdict, "io_range");
1189         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1190                        qdict_get_int(info, "base"),
1191                        qdict_get_int(info, "limit"));
1192
1193         info = qdict_get_qdict(qdict, "memory_range");
1194         monitor_printf(mon,
1195                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1196                        qdict_get_int(info, "base"),
1197                        qdict_get_int(info, "limit"));
1198
1199         info = qdict_get_qdict(qdict, "prefetchable_range");
1200         monitor_printf(mon, "      prefetchable memory range "
1201                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1202                        qdict_get_int(info, "base"),
1203         qdict_get_int(info, "limit"));
1204     }
1205
1206     QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1207         qdict = qobject_to_qdict(qlist_entry_obj(entry));
1208         monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1209
1210         addr = qdict_get_int(qdict, "address");
1211         size = qdict_get_int(qdict, "size");
1212
1213         if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1214             monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1215                                 " [0x%04"FMT_PCIBUS"].\n",
1216                                 addr, addr + size - 1);
1217         } else {
1218             monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1219                                " [0x%08"FMT_PCIBUS"].\n",
1220                                 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1221                                 qdict_get_bool(qdict, "prefetch") ?
1222                                 " prefetchable" : "", addr, addr + size - 1);
1223         }
1224     }
1225
1226     monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1227
1228     if (qdict_haskey(device, "pci_bridge")) {
1229         qdict = qdict_get_qdict(device, "pci_bridge");
1230         if (qdict_haskey(qdict, "devices")) {
1231             QListEntry *dev;
1232             QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1233                 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1234             }
1235         }
1236     }
1237 }
1238
1239 void do_pci_info_print(Monitor *mon, const QObject *data)
1240 {
1241     QListEntry *bus, *dev;
1242
1243     QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1244         QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1245         QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1246             pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1247         }
1248     }
1249 }
1250
1251 static QObject *pci_get_dev_class(const PCIDevice *dev)
1252 {
1253     int class;
1254     const pci_class_desc *desc;
1255
1256     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1257     desc = pci_class_descriptions;
1258     while (desc->desc && class != desc->class)
1259         desc++;
1260
1261     if (desc->desc) {
1262         return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1263                                   desc->desc, class);
1264     } else {
1265         return qobject_from_jsonf("{ 'class': %d }", class);
1266     }
1267 }
1268
1269 static QObject *pci_get_dev_id(const PCIDevice *dev)
1270 {
1271     return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1272                               pci_get_word(dev->config + PCI_VENDOR_ID),
1273                               pci_get_word(dev->config + PCI_DEVICE_ID));
1274 }
1275
1276 static QObject *pci_get_regions_list(const PCIDevice *dev)
1277 {
1278     int i;
1279     QList *regions_list;
1280
1281     regions_list = qlist_new();
1282
1283     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1284         QObject *obj;
1285         const PCIIORegion *r = &dev->io_regions[i];
1286
1287         if (!r->size) {
1288             continue;
1289         }
1290
1291         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1292             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1293                                      "'address': %" PRId64 ", "
1294                                      "'size': %" PRId64 " }",
1295                                      i, r->addr, r->size);
1296         } else {
1297             int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1298
1299             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1300                                      "'mem_type_64': %i, 'prefetch': %i, "
1301                                      "'address': %" PRId64 ", "
1302                                      "'size': %" PRId64 " }",
1303                                      i, mem_type_64,
1304                                      r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1305                                      r->addr, r->size);
1306         }
1307
1308         qlist_append_obj(regions_list, obj);
1309     }
1310
1311     return QOBJECT(regions_list);
1312 }
1313
1314 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1315
1316 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1317 {
1318     uint8_t type;
1319     QObject *obj;
1320
1321     obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1322                               " 'qdev_id': %s }",
1323                               bus_num,
1324                               PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1325                               pci_get_dev_class(dev), pci_get_dev_id(dev),
1326                               pci_get_regions_list(dev),
1327                               dev->qdev.id ? dev->qdev.id : "");
1328
1329     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1330         QDict *qdict = qobject_to_qdict(obj);
1331         qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1332     }
1333
1334     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1335     if (type == PCI_HEADER_TYPE_BRIDGE) {
1336         QDict *qdict;
1337         QObject *pci_bridge;
1338
1339         pci_bridge = qobject_from_jsonf("{ 'bus': "
1340         "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1341         "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1342         "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1343         "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1344         dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1345         dev->config[PCI_SUBORDINATE_BUS],
1346         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1347         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1348         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1349         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1350         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1351                                PCI_BASE_ADDRESS_MEM_PREFETCH),
1352         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1353                                 PCI_BASE_ADDRESS_MEM_PREFETCH));
1354
1355         if (dev->config[PCI_SECONDARY_BUS] != 0) {
1356             PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1357
1358             if (child_bus) {
1359                 qdict = qobject_to_qdict(pci_bridge);
1360                 qdict_put_obj(qdict, "devices",
1361                               pci_get_devices_list(child_bus,
1362                                                    dev->config[PCI_SECONDARY_BUS]));
1363             }
1364         }
1365         qdict = qobject_to_qdict(obj);
1366         qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1367     }
1368
1369     return obj;
1370 }
1371
1372 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1373 {
1374     int devfn;
1375     PCIDevice *dev;
1376     QList *dev_list;
1377
1378     dev_list = qlist_new();
1379
1380     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1381         dev = bus->devices[devfn];
1382         if (dev) {
1383             qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1384         }
1385     }
1386
1387     return QOBJECT(dev_list);
1388 }
1389
1390 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1391 {
1392     bus = pci_find_bus(bus, bus_num);
1393     if (bus) {
1394         return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1395                                   bus_num, pci_get_devices_list(bus, bus_num));
1396     }
1397
1398     return NULL;
1399 }
1400
1401 void do_pci_info(Monitor *mon, QObject **ret_data)
1402 {
1403     QList *bus_list;
1404     struct PCIHostBus *host;
1405
1406     bus_list = qlist_new();
1407
1408     QLIST_FOREACH(host, &host_buses, next) {
1409         QObject *obj = pci_get_bus_dict(host->bus, 0);
1410         if (obj) {
1411             qlist_append_obj(bus_list, obj);
1412         }
1413     }
1414
1415     *ret_data = QOBJECT(bus_list);
1416 }
1417
1418 static const char * const pci_nic_models[] = {
1419     "ne2k_pci",
1420     "i82551",
1421     "i82557b",
1422     "i82559er",
1423     "rtl8139",
1424     "e1000",
1425     "pcnet",
1426     "virtio",
1427     NULL
1428 };
1429
1430 static const char * const pci_nic_names[] = {
1431     "ne2k_pci",
1432     "i82551",
1433     "i82557b",
1434     "i82559er",
1435     "rtl8139",
1436     "e1000",
1437     "pcnet",
1438     "virtio-net-pci",
1439     NULL
1440 };
1441
1442 /* Initialize a PCI NIC.  */
1443 /* FIXME callers should check for failure, but don't */
1444 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1445                         const char *default_devaddr)
1446 {
1447     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1448     PCIBus *bus;
1449     int devfn;
1450     PCIDevice *pci_dev;
1451     DeviceState *dev;
1452     int i;
1453
1454     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1455     if (i < 0)
1456         return NULL;
1457
1458     bus = pci_get_bus_devfn(&devfn, devaddr);
1459     if (!bus) {
1460         error_report("Invalid PCI device address %s for device %s",
1461                      devaddr, pci_nic_names[i]);
1462         return NULL;
1463     }
1464
1465     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1466     dev = &pci_dev->qdev;
1467     qdev_set_nic_properties(dev, nd);
1468     if (qdev_init(dev) < 0)
1469         return NULL;
1470     return pci_dev;
1471 }
1472
1473 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1474                                const char *default_devaddr)
1475 {
1476     PCIDevice *res;
1477
1478     if (qemu_show_nic_models(nd->model, pci_nic_models))
1479         exit(0);
1480
1481     res = pci_nic_init(nd, default_model, default_devaddr);
1482     if (!res)
1483         exit(1);
1484     return res;
1485 }
1486
1487 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1488 {
1489     pci_update_mappings(d);
1490 }
1491
1492 void pci_bridge_update_mappings(PCIBus *b)
1493 {
1494     PCIBus *child;
1495
1496     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1497
1498     QLIST_FOREACH(child, &b->child, sibling) {
1499         pci_bridge_update_mappings(child);
1500     }
1501 }
1502
1503 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1504 {
1505     PCIBus *sec;
1506
1507     if (!bus) {
1508         return NULL;
1509     }
1510
1511     if (pci_bus_num(bus) == bus_num) {
1512         return bus;
1513     }
1514
1515     /* try child bus */
1516     if (!bus->parent_dev /* host pci bridge */ ||
1517         (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1518          bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1519         for (; bus; bus = sec) {
1520             QLIST_FOREACH(sec, &bus->child, sibling) {
1521                 assert(sec->parent_dev);
1522                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1523                     return sec;
1524                 }
1525                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1526                     bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1527                     break;
1528                 }
1529             }
1530         }
1531     }
1532
1533     return NULL;
1534 }
1535
1536 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1537 {
1538     bus = pci_find_bus(bus, bus_num);
1539
1540     if (!bus)
1541         return NULL;
1542
1543     return bus->devices[PCI_DEVFN(slot, function)];
1544 }
1545
1546 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1547 {
1548     PCIDevice *pci_dev = (PCIDevice *)qdev;
1549     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1550     PCIBus *bus;
1551     int devfn, rc;
1552
1553     /* initialize cap_present for pci_is_express() and pci_config_size() */
1554     if (info->is_express) {
1555         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1556     }
1557
1558     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1559     devfn = pci_dev->devfn;
1560     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1561                                      info->config_read, info->config_write,
1562                                      info->is_bridge);
1563     if (pci_dev == NULL)
1564         return -1;
1565     rc = info->init(pci_dev);
1566     if (rc != 0) {
1567         do_pci_unregister_device(pci_dev);
1568         return rc;
1569     }
1570
1571     /* rom loading */
1572     if (pci_dev->romfile == NULL && info->romfile != NULL)
1573         pci_dev->romfile = qemu_strdup(info->romfile);
1574     pci_add_option_rom(pci_dev);
1575
1576     if (bus->hotplug) {
1577         /* Let buses differentiate between hotplug and when device is
1578          * enabled during qemu machine creation. */
1579         rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1580                           qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1581                           PCI_COLDPLUG_ENABLED);
1582         if (rc != 0) {
1583             int r = pci_unregister_device(&pci_dev->qdev);
1584             assert(!r);
1585             return rc;
1586         }
1587     }
1588     return 0;
1589 }
1590
1591 static int pci_unplug_device(DeviceState *qdev)
1592 {
1593     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1594
1595     return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1596                              PCI_HOTPLUG_DISABLED);
1597 }
1598
1599 void pci_qdev_register(PCIDeviceInfo *info)
1600 {
1601     info->qdev.init = pci_qdev_init;
1602     info->qdev.unplug = pci_unplug_device;
1603     info->qdev.exit = pci_unregister_device;
1604     info->qdev.bus_info = &pci_bus_info;
1605     qdev_register(&info->qdev);
1606 }
1607
1608 void pci_qdev_register_many(PCIDeviceInfo *info)
1609 {
1610     while (info->qdev.name) {
1611         pci_qdev_register(info);
1612         info++;
1613     }
1614 }
1615
1616 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1617                                     const char *name)
1618 {
1619     DeviceState *dev;
1620
1621     dev = qdev_create(&bus->qbus, name);
1622     qdev_prop_set_uint32(dev, "addr", devfn);
1623     qdev_prop_set_bit(dev, "multifunction", multifunction);
1624     return DO_UPCAST(PCIDevice, qdev, dev);
1625 }
1626
1627 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1628                                            bool multifunction,
1629                                            const char *name)
1630 {
1631     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1632     qdev_init_nofail(&dev->qdev);
1633     return dev;
1634 }
1635
1636 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1637 {
1638     return pci_create_multifunction(bus, devfn, false, name);
1639 }
1640
1641 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1642 {
1643     return pci_create_simple_multifunction(bus, devfn, false, name);
1644 }
1645
1646 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1647 {
1648     int config_size = pci_config_size(pdev);
1649     int offset = PCI_CONFIG_HEADER_SIZE;
1650     int i;
1651     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1652         if (pdev->used[i])
1653             offset = i + 1;
1654         else if (i - offset + 1 == size)
1655             return offset;
1656     return 0;
1657 }
1658
1659 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1660                                         uint8_t *prev_p)
1661 {
1662     uint8_t next, prev;
1663
1664     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1665         return 0;
1666
1667     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1668          prev = next + PCI_CAP_LIST_NEXT)
1669         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1670             break;
1671
1672     if (prev_p)
1673         *prev_p = prev;
1674     return next;
1675 }
1676
1677 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1678 {
1679     cpu_register_physical_memory(addr, size, pdev->rom_offset);
1680 }
1681
1682 /* Add an option rom for the device */
1683 static int pci_add_option_rom(PCIDevice *pdev)
1684 {
1685     int size;
1686     char *path;
1687     void *ptr;
1688     char name[32];
1689
1690     if (!pdev->romfile)
1691         return 0;
1692     if (strlen(pdev->romfile) == 0)
1693         return 0;
1694
1695     if (!pdev->rom_bar) {
1696         /*
1697          * Load rom via fw_cfg instead of creating a rom bar,
1698          * for 0.11 compatibility.
1699          */
1700         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1701         if (class == 0x0300) {
1702             rom_add_vga(pdev->romfile);
1703         } else {
1704             rom_add_option(pdev->romfile);
1705         }
1706         return 0;
1707     }
1708
1709     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1710     if (path == NULL) {
1711         path = qemu_strdup(pdev->romfile);
1712     }
1713
1714     size = get_image_size(path);
1715     if (size < 0) {
1716         error_report("%s: failed to find romfile \"%s\"",
1717                      __FUNCTION__, pdev->romfile);
1718         return -1;
1719     }
1720     if (size & (size - 1)) {
1721         size = 1 << qemu_fls(size);
1722     }
1723
1724     if (pdev->qdev.info->vmsd)
1725         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1726     else
1727         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1728     pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1729
1730     ptr = qemu_get_ram_ptr(pdev->rom_offset);
1731     load_image(path, ptr);
1732     qemu_free(path);
1733
1734     pci_register_bar(pdev, PCI_ROM_SLOT, size,
1735                      0, pci_map_option_rom);
1736
1737     return 0;
1738 }
1739
1740 static void pci_del_option_rom(PCIDevice *pdev)
1741 {
1742     if (!pdev->rom_offset)
1743         return;
1744
1745     qemu_ram_free(pdev->rom_offset);
1746     pdev->rom_offset = 0;
1747 }
1748
1749 /*
1750  * if !offset
1751  * Reserve space and add capability to the linked list in pci config space
1752  *
1753  * if offset = 0,
1754  * Find and reserve space and add capability to the linked list
1755  * in pci config space */
1756 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1757                        uint8_t offset, uint8_t size)
1758 {
1759     uint8_t *config;
1760     if (!offset) {
1761         offset = pci_find_space(pdev, size);
1762         if (!offset) {
1763             return -ENOSPC;
1764         }
1765     }
1766
1767     config = pdev->config + offset;
1768     config[PCI_CAP_LIST_ID] = cap_id;
1769     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1770     pdev->config[PCI_CAPABILITY_LIST] = offset;
1771     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1772     memset(pdev->used + offset, 0xFF, size);
1773     /* Make capability read-only by default */
1774     memset(pdev->wmask + offset, 0, size);
1775     /* Check capability by default */
1776     memset(pdev->cmask + offset, 0xFF, size);
1777     return offset;
1778 }
1779
1780 /* Unlink capability from the pci config space. */
1781 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1782 {
1783     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1784     if (!offset)
1785         return;
1786     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1787     /* Make capability writeable again */
1788     memset(pdev->wmask + offset, 0xff, size);
1789     memset(pdev->w1cmask + offset, 0, size);
1790     /* Clear cmask as device-specific registers can't be checked */
1791     memset(pdev->cmask + offset, 0, size);
1792     memset(pdev->used + offset, 0, size);
1793
1794     if (!pdev->config[PCI_CAPABILITY_LIST])
1795         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1796 }
1797
1798 /* Reserve space for capability at a known offset (to call after load). */
1799 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1800 {
1801     memset(pdev->used + offset, 0xff, size);
1802 }
1803
1804 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1805 {
1806     return pci_find_capability_list(pdev, cap_id, NULL);
1807 }
1808
1809 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1810 {
1811     PCIDevice *d = (PCIDevice *)dev;
1812     const pci_class_desc *desc;
1813     char ctxt[64];
1814     PCIIORegion *r;
1815     int i, class;
1816
1817     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1818     desc = pci_class_descriptions;
1819     while (desc->desc && class != desc->class)
1820         desc++;
1821     if (desc->desc) {
1822         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1823     } else {
1824         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1825     }
1826
1827     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1828                    "pci id %04x:%04x (sub %04x:%04x)\n",
1829                    indent, "", ctxt, pci_bus_num(d->bus),
1830                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1831                    pci_get_word(d->config + PCI_VENDOR_ID),
1832                    pci_get_word(d->config + PCI_DEVICE_ID),
1833                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1834                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1835     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1836         r = &d->io_regions[i];
1837         if (!r->size)
1838             continue;
1839         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1840                        " [0x%"FMT_PCIBUS"]\n",
1841                        indent, "",
1842                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1843                        r->addr, r->addr + r->size - 1);
1844     }
1845 }
1846
1847 static char *pcibus_get_dev_path(DeviceState *dev)
1848 {
1849     PCIDevice *d = (PCIDevice *)dev;
1850     char path[16];
1851
1852     snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1853              pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1854              PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1855
1856     return strdup(path);
1857 }
1858