hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33
  34 /*
  35  * I440FX chipset data sheet.
  36  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  37  */
  38
  39 typedef PCIHostState I440FXState;
  40
  41 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  42 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  43 #define XEN_PIIX_NUM_PIRQS      128ULL
  44 #define PIIX_PIRQC              0x60
  45
  46 typedef struct PIIX3State {
  47     PCIDevice dev;
  48
  49     /*
  50      * bitmap to track pic levels.
  51      * The pic level is the logical OR of all the PCI irqs mapped to it
  52      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  53      *
  54      * PIRQ is mapped to PIC pins, we track it by
  55      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  56      * pic_irq * PIIX_NUM_PIRQS + pirq
  57      */
  58 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  59 #error "unable to encode pic state in 64bit in pic_levels."
  60 #endif
  61     uint64_t pic_levels;
  62
  63     qemu_irq *pic;
  64
  65     /* This member isn't used. Just for save/load compatibility */
  66     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  67 } PIIX3State;
  68
  69 typedef struct PAMMemoryRegion {
  70     MemoryRegion mem;
  71     bool initialized;
  72 } PAMMemoryRegion;
  73
  74 struct PCII440FXState {
  75     PCIDevice dev;
  76     MemoryRegion *system_memory;
  77     MemoryRegion *pci_address_space;
  78     MemoryRegion *ram_memory;
  79     MemoryRegion pci_hole;
  80     MemoryRegion pci_hole_64bit;
  81     PAMMemoryRegion pam_regions[13];
  82     MemoryRegion smram_region;
  83     uint8_t smm_enabled;
  84     bool smram_enabled;
  85     PIIX3State *piix3;
  86 };
  87
  88
  89 #define I440FX_PAM      0x59
  90 #define I440FX_PAM_SIZE 7
  91 #define I440FX_SMRAM    0x72
  92
  93 static void piix3_set_irq(void *opaque, int pirq, int level);
  94 static void piix3_write_config_xen(PCIDevice *dev,
  95                                uint32_t address, uint32_t val, int len);
  96
  97 /* return the global irq number corresponding to a given device irq
  98    pin. We could also use the bus number to have a more precise
  99    mapping. */
 100 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 101 {
 102     int slot_addend;
 103     slot_addend = (pci_dev->devfn >> 3) - 1;
 104     return (pci_intx + slot_addend) & 3;
 105 }
 106
 107 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
 108                        PAMMemoryRegion *mem)
 109 {
 110     if (mem->initialized) {
 111         memory_region_del_subregion(d->system_memory, &mem->mem);
 112         memory_region_destroy(&mem->mem);
 113     }
 114
 115     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
 116     switch(r) {
 117     case 3:
 118         /* RAM */
 119         memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
 120                                  start, end - start);
 121         break;
 122     case 1:
 123         /* ROM (XXX: not quite correct) */
 124         memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
 125                                  start, end - start);
 126         memory_region_set_readonly(&mem->mem, true);
 127         break;
 128     case 2:
 129     case 0:
 130         /* XXX: should distinguish read/write cases */
 131         memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
 132                                  start, end - start);
 133         break;
 134     }
 135     memory_region_add_subregion_overlap(d->system_memory,
 136                                         start, &mem->mem, 1);
 137     mem->initialized = true;
 138 }
 139
 140 static void i440fx_update_memory_mappings(PCII440FXState *d)
 141 {
 142     int i, r;
 143     uint32_t smram;
 144
 145     memory_region_transaction_begin();
 146     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
 147                &d->pam_regions[0]);
 148     for(i = 0; i < 12; i++) {
 149         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 150         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
 151                    &d->pam_regions[i+1]);
 152     }
 153     smram = d->dev.config[I440FX_SMRAM];
 154     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 155         if (!d->smram_enabled) {
 156             memory_region_del_subregion(d->system_memory, &d->smram_region);
 157             d->smram_enabled = true;
 158         }
 159     } else {
 160         if (d->smram_enabled) {
 161             memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
 162                                                 &d->smram_region, 1);
 163             d->smram_enabled = false;
 164         }
 165     }
 166     memory_region_transaction_commit();
 167 }
 168
 169 static void i440fx_set_smm(int val, void *arg)
 170 {
 171     PCII440FXState *d = arg;
 172
 173     val = (val != 0);
 174     if (d->smm_enabled != val) {
 175         d->smm_enabled = val;
 176         i440fx_update_memory_mappings(d);
 177     }
 178 }
 179
 180
 181 static void i440fx_write_config(PCIDevice *dev,
 182                                 uint32_t address, uint32_t val, int len)
 183 {
 184     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 185
 186     /* XXX: implement SMRAM.D_LOCK */
 187     pci_default_write_config(dev, address, val, len);
 188     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 189         range_covers_byte(address, len, I440FX_SMRAM)) {
 190         i440fx_update_memory_mappings(d);
 191     }
 192 }
 193
 194 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 195 {
 196     PCII440FXState *d = opaque;
 197     int ret, i;
 198
 199     ret = pci_device_load(&d->dev, f);
 200     if (ret < 0)
 201         return ret;
 202     i440fx_update_memory_mappings(d);
 203     qemu_get_8s(f, &d->smm_enabled);
 204
 205     if (version_id == 2) {
 206         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 207             qemu_get_be32(f); /* dummy load for compatibility */
 208         }
 209     }
 210
 211     return 0;
 212 }
 213
 214 static int i440fx_post_load(void *opaque, int version_id)
 215 {
 216     PCII440FXState *d = opaque;
 217
 218     i440fx_update_memory_mappings(d);
 219     return 0;
 220 }
 221
 222 static const VMStateDescription vmstate_i440fx = {
 223     .name = "I440FX",
 224     .version_id = 3,
 225     .minimum_version_id = 3,
 226     .minimum_version_id_old = 1,
 227     .load_state_old = i440fx_load_old,
 228     .post_load = i440fx_post_load,
 229     .fields      = (VMStateField []) {
 230         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 231         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 232         VMSTATE_END_OF_LIST()
 233     }
 234 };
 235
 236 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 237 {
 238     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 239
 240     memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
 241                           "pci-conf-idx", 4);
 242     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 243     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 244
 245     memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
 246                           "pci-conf-data", 4);
 247     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 248     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 249
 250     return 0;
 251 }
 252
 253 static int i440fx_initfn(PCIDevice *dev)
 254 {
 255     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 256
 257     d->dev.config[I440FX_SMRAM] = 0x02;
 258
 259     cpu_smm_register(&i440fx_set_smm, d);
 260     return 0;
 261 }
 262
 263 static PCIBus *i440fx_common_init(const char *device_name,
 264                                   PCII440FXState **pi440fx_state,
 265                                   int *piix3_devfn,
 266                                   qemu_irq *pic,
 267                                   MemoryRegion *address_space_mem,
 268                                   MemoryRegion *address_space_io,
 269                                   ram_addr_t ram_size,
 270                                   target_phys_addr_t pci_hole_start,
 271                                   target_phys_addr_t pci_hole_size,
 272                                   target_phys_addr_t pci_hole64_start,
 273                                   target_phys_addr_t pci_hole64_size,
 274                                   MemoryRegion *pci_address_space,
 275                                   MemoryRegion *ram_memory)
 276 {
 277     DeviceState *dev;
 278     PCIBus *b;
 279     PCIDevice *d;
 280     I440FXState *s;
 281     PIIX3State *piix3;
 282     PCII440FXState *f;
 283
 284     dev = qdev_create(NULL, "i440FX-pcihost");
 285     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 286     s->address_space = address_space_mem;
 287     b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
 288                     address_space_io, 0);
 289     s->bus = b;
 290     qdev_init_nofail(dev);
 291
 292     d = pci_create_simple(b, 0, device_name);
 293     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 294     f = *pi440fx_state;
 295     f->system_memory = address_space_mem;
 296     f->pci_address_space = pci_address_space;
 297     f->ram_memory = ram_memory;
 298     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 299                              pci_hole_start, pci_hole_size);
 300     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 301     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 302                              f->pci_address_space,
 303                              pci_hole64_start, pci_hole64_size);
 304     if (pci_hole64_size) {
 305         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 306                                     &f->pci_hole_64bit);
 307     }
 308     memory_region_init_alias(&f->smram_region, "smram-region",
 309                              f->pci_address_space, 0xa0000, 0x20000);
 310     f->smram_enabled = true;
 311
 312     /* Xen supports additional interrupt routes from the PCI devices to
 313      * the IOAPIC: the four pins of each PCI device on the bus are also
 314      * connected to the IOAPIC directly.
 315      * These additional routes can be discovered through ACPI. */
 316     if (xen_enabled()) {
 317         piix3 = DO_UPCAST(PIIX3State, dev,
 318                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 319         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 320                 piix3, XEN_PIIX_NUM_PIRQS);
 321     } else {
 322         piix3 = DO_UPCAST(PIIX3State, dev,
 323                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 324         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 325                 PIIX_NUM_PIRQS);
 326     }
 327     piix3->pic = pic;
 328
 329     (*pi440fx_state)->piix3 = piix3;
 330
 331     *piix3_devfn = piix3->dev.devfn;
 332
 333     ram_size = ram_size / 8 / 1024 / 1024;
 334     if (ram_size > 255)
 335         ram_size = 255;
 336     (*pi440fx_state)->dev.config[0x57]=ram_size;
 337
 338     i440fx_update_memory_mappings(f);
 339
 340     return b;
 341 }
 342
 343 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 344                     qemu_irq *pic,
 345                     MemoryRegion *address_space_mem,
 346                     MemoryRegion *address_space_io,
 347                     ram_addr_t ram_size,
 348                     target_phys_addr_t pci_hole_start,
 349                     target_phys_addr_t pci_hole_size,
 350                     target_phys_addr_t pci_hole64_start,
 351                     target_phys_addr_t pci_hole64_size,
 352                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 353
 354 {
 355     PCIBus *b;
 356
 357     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
 358                            address_space_mem, address_space_io, ram_size,
 359                            pci_hole_start, pci_hole_size,
 360                            pci_hole64_size, pci_hole64_size,
 361                            pci_memory, ram_memory);
 362     return b;
 363 }
 364
 365 /* PIIX3 PCI to ISA bridge */
 366 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 367 {
 368     qemu_set_irq(piix3->pic[pic_irq],
 369                  !!(piix3->pic_levels &
 370                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 371                      (pic_irq * PIIX_NUM_PIRQS))));
 372 }
 373
 374 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 375 {
 376     int pic_irq;
 377     uint64_t mask;
 378
 379     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 380     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 381         return;
 382     }
 383
 384     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 385     piix3->pic_levels &= ~mask;
 386     piix3->pic_levels |= mask * !!level;
 387
 388     piix3_set_irq_pic(piix3, pic_irq);
 389 }
 390
 391 static void piix3_set_irq(void *opaque, int pirq, int level)
 392 {
 393     PIIX3State *piix3 = opaque;
 394     piix3_set_irq_level(piix3, pirq, level);
 395 }
 396
 397 /* irq routing is changed. so rebuild bitmap */
 398 static void piix3_update_irq_levels(PIIX3State *piix3)
 399 {
 400     int pirq;
 401
 402     piix3->pic_levels = 0;
 403     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 404         piix3_set_irq_level(piix3, pirq,
 405                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 406     }
 407 }
 408
 409 static void piix3_write_config(PCIDevice *dev,
 410                                uint32_t address, uint32_t val, int len)
 411 {
 412     pci_default_write_config(dev, address, val, len);
 413     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 414         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 415         int pic_irq;
 416         piix3_update_irq_levels(piix3);
 417         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 418             piix3_set_irq_pic(piix3, pic_irq);
 419         }
 420     }
 421 }
 422
 423 static void piix3_write_config_xen(PCIDevice *dev,
 424                                uint32_t address, uint32_t val, int len)
 425 {
 426     xen_piix_pci_write_config_client(address, val, len);
 427     piix3_write_config(dev, address, val, len);
 428 }
 429
 430 static void piix3_reset(void *opaque)
 431 {
 432     PIIX3State *d = opaque;
 433     uint8_t *pci_conf = d->dev.config;
 434
 435     pci_conf[0x04] = 0x07; // master, memory and I/O
 436     pci_conf[0x05] = 0x00;
 437     pci_conf[0x06] = 0x00;
 438     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 439     pci_conf[0x4c] = 0x4d;
 440     pci_conf[0x4e] = 0x03;
 441     pci_conf[0x4f] = 0x00;
 442     pci_conf[0x60] = 0x80;
 443     pci_conf[0x61] = 0x80;
 444     pci_conf[0x62] = 0x80;
 445     pci_conf[0x63] = 0x80;
 446     pci_conf[0x69] = 0x02;
 447     pci_conf[0x70] = 0x80;
 448     pci_conf[0x76] = 0x0c;
 449     pci_conf[0x77] = 0x0c;
 450     pci_conf[0x78] = 0x02;
 451     pci_conf[0x79] = 0x00;
 452     pci_conf[0x80] = 0x00;
 453     pci_conf[0x82] = 0x00;
 454     pci_conf[0xa0] = 0x08;
 455     pci_conf[0xa2] = 0x00;
 456     pci_conf[0xa3] = 0x00;
 457     pci_conf[0xa4] = 0x00;
 458     pci_conf[0xa5] = 0x00;
 459     pci_conf[0xa6] = 0x00;
 460     pci_conf[0xa7] = 0x00;
 461     pci_conf[0xa8] = 0x0f;
 462     pci_conf[0xaa] = 0x00;
 463     pci_conf[0xab] = 0x00;
 464     pci_conf[0xac] = 0x00;
 465     pci_conf[0xae] = 0x00;
 466
 467     d->pic_levels = 0;
 468 }
 469
 470 static int piix3_post_load(void *opaque, int version_id)
 471 {
 472     PIIX3State *piix3 = opaque;
 473     piix3_update_irq_levels(piix3);
 474     return 0;
 475 }
 476
 477 static void piix3_pre_save(void *opaque)
 478 {
 479     int i;
 480     PIIX3State *piix3 = opaque;
 481
 482     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 483         piix3->pci_irq_levels_vmstate[i] =
 484             pci_bus_get_irq_level(piix3->dev.bus, i);
 485     }
 486 }
 487
 488 static const VMStateDescription vmstate_piix3 = {
 489     .name = "PIIX3",
 490     .version_id = 3,
 491     .minimum_version_id = 2,
 492     .minimum_version_id_old = 2,
 493     .post_load = piix3_post_load,
 494     .pre_save = piix3_pre_save,
 495     .fields      = (VMStateField []) {
 496         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 497         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 498                               PIIX_NUM_PIRQS, 3),
 499         VMSTATE_END_OF_LIST()
 500     }
 501 };
 502
 503 static int piix3_initfn(PCIDevice *dev)
 504 {
 505     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 506
 507     isa_bus_new(&d->dev.qdev);
 508     qemu_register_reset(piix3_reset, d);
 509     return 0;
 510 }
 511
 512 static PCIDeviceInfo i440fx_info[] = {
 513     {
 514         .qdev.name    = "i440FX",
 515         .qdev.desc    = "Host bridge",
 516         .qdev.size    = sizeof(PCII440FXState),
 517         .qdev.vmsd    = &vmstate_i440fx,
 518         .qdev.no_user = 1,
 519         .no_hotplug   = 1,
 520         .init         = i440fx_initfn,
 521         .config_write = i440fx_write_config,
 522         .vendor_id    = PCI_VENDOR_ID_INTEL,
 523         .device_id    = PCI_DEVICE_ID_INTEL_82441,
 524         .revision     = 0x02,
 525         .class_id     = PCI_CLASS_BRIDGE_HOST,
 526     },{
 527         .qdev.name    = "PIIX3",
 528         .qdev.desc    = "ISA bridge",
 529         .qdev.size    = sizeof(PIIX3State),
 530         .qdev.vmsd    = &vmstate_piix3,
 531         .qdev.no_user = 1,
 532         .no_hotplug   = 1,
 533         .init         = piix3_initfn,
 534         .config_write = piix3_write_config,
 535         .vendor_id    = PCI_VENDOR_ID_INTEL,
 536         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 537         .class_id     = PCI_CLASS_BRIDGE_ISA,
 538     },{
 539         .qdev.name    = "PIIX3-xen",
 540         .qdev.desc    = "ISA bridge",
 541         .qdev.size    = sizeof(PIIX3State),
 542         .qdev.vmsd    = &vmstate_piix3,
 543         .qdev.no_user = 1,
 544         .no_hotplug   = 1,
 545         .init         = piix3_initfn,
 546         .config_write = piix3_write_config_xen,
 547         .vendor_id    = PCI_VENDOR_ID_INTEL,
 548         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 549         .class_id     = PCI_CLASS_BRIDGE_ISA,
 550     },{
 551         /* end of list */
 552     }
 553 };
 554
 555 static SysBusDeviceInfo i440fx_pcihost_info = {
 556     .init         = i440fx_pcihost_initfn,
 557     .qdev.name    = "i440FX-pcihost",
 558     .qdev.fw_name = "pci",
 559     .qdev.size    = sizeof(I440FXState),
 560     .qdev.no_user = 1,
 561 };
 562
 563 static void i440fx_register(void)
 564 {
 565     sysbus_register_withprop(&i440fx_pcihost_info);
 566     pci_qdev_register_many(i440fx_info);
 567 }
 568 device_init(i440fx_register);