hw/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement boot blocs with reduced size
  33  * It does not implement software data protection as found in many real chips
  34  * It does not implement erase suspend/resume commands
  35  * It does not implement multiple sectors erase
  36  */
  37
  38 #include "hw.h"
  39 #include "flash.h"
  40 #include "qemu-timer.h"
  41 #include "block.h"
  42 #include "exec-memory.h"
  43
  44 //#define PFLASH_DEBUG
  45 #ifdef PFLASH_DEBUG
  46 #define DPRINTF(fmt, ...)                          \
  47 do {                                               \
  48     printf("PFLASH: " fmt , ## __VA_ARGS__);       \
  49 } while (0)
  50 #else
  51 #define DPRINTF(fmt, ...) do { } while (0)
  52 #endif
  53
  54 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  55
  56 struct pflash_t {
  57     BlockDriverState *bs;
  58     target_phys_addr_t base;
  59     uint32_t sector_len;
  60     uint32_t chip_len;
  61     int mappings;
  62     int width;
  63     int wcycle; /* if 0, the flash is read normally */
  64     int bypass;
  65     int ro;
  66     uint8_t cmd;
  67     uint8_t status;
  68     uint16_t ident[4];
  69     uint16_t unlock_addr[2];
  70     uint8_t cfi_len;
  71     uint8_t cfi_table[0x52];
  72     QEMUTimer *timer;
  73     /* The device replicates the flash memory across its memory space.  Emulate
  74      * that by having a container (.mem) filled with an array of aliases
  75      * (.mem_mappings) pointing to the flash memory (.orig_mem).
  76      */
  77     MemoryRegion mem;
  78     MemoryRegion *mem_mappings;    /* array; one per mapping */
  79     MemoryRegion *orig_mem;
  80     int rom_mode;
  81     int read_counter; /* used for lazy switch-back to rom mode */
  82     void *storage;
  83 };
  84
  85 /*
  86  * Set up replicated mappings of the same region.
  87  */
  88 static void pflash_setup_mappings(pflash_t *pfl, MemoryRegion *mem)
  89 {
  90     unsigned i;
  91     target_phys_addr_t size = memory_region_size(mem);
  92
  93     pfl->orig_mem = mem;
  94     memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
  95     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
  96     for (i = 0; i < pfl->mappings; ++i) {
  97         memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias", mem,
  98                                  0, size);
  99         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 100     }
 101 }
 102
 103 static void pflash_register_memory(pflash_t *pfl, int rom_mode)
 104 {
 105     memory_region_rom_device_set_readable(pfl->orig_mem, rom_mode);
 106 }
 107
 108 static void pflash_timer (void *opaque)
 109 {
 110     pflash_t *pfl = opaque;
 111
 112     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
 113     /* Reset flash */
 114     pfl->status ^= 0x80;
 115     if (pfl->bypass) {
 116         pfl->wcycle = 2;
 117     } else {
 118         pflash_register_memory(pfl, 1);
 119         pfl->wcycle = 0;
 120     }
 121     pfl->cmd = 0;
 122 }
 123
 124 static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
 125                              int width, int be)
 126 {
 127     target_phys_addr_t boff;
 128     uint32_t ret;
 129     uint8_t *p;
 130
 131     DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);
 132     ret = -1;
 133     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 134     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 135         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 136         pflash_register_memory(pfl, 1);
 137     }
 138     offset &= pfl->chip_len - 1;
 139     boff = offset & 0xFF;
 140     if (pfl->width == 2)
 141         boff = boff >> 1;
 142     else if (pfl->width == 4)
 143         boff = boff >> 2;
 144     switch (pfl->cmd) {
 145     default:
 146         /* This should never happen : reset state & treat it as a read*/
 147         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 148         pfl->wcycle = 0;
 149         pfl->cmd = 0;
 150     case 0x80:
 151         /* We accept reads during second unlock sequence... */
 152     case 0x00:
 153     flash_read:
 154         /* Flash area read */
 155         p = pfl->storage;
 156         switch (width) {
 157         case 1:
 158             ret = p[offset];
 159 //            DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
 160             break;
 161         case 2:
 162             if (be) {
 163                 ret = p[offset] << 8;
 164                 ret |= p[offset + 1];
 165             } else {
 166                 ret = p[offset];
 167                 ret |= p[offset + 1] << 8;
 168             }
 169 //            DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
 170             break;
 171         case 4:
 172             if (be) {
 173                 ret = p[offset] << 24;
 174                 ret |= p[offset + 1] << 16;
 175                 ret |= p[offset + 2] << 8;
 176                 ret |= p[offset + 3];
 177             } else {
 178                 ret = p[offset];
 179                 ret |= p[offset + 1] << 8;
 180                 ret |= p[offset + 2] << 16;
 181                 ret |= p[offset + 3] << 24;
 182             }
 183 //            DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
 184             break;
 185         }
 186         break;
 187     case 0x90:
 188         /* flash ID read */
 189         switch (boff) {
 190         case 0x00:
 191         case 0x01:
 192             ret = pfl->ident[boff & 0x01];
 193             break;
 194         case 0x02:
 195             ret = 0x00; /* Pretend all sectors are unprotected */
 196             break;
 197         case 0x0E:
 198         case 0x0F:
 199             if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
 200                 goto flash_read;
 201             ret = pfl->ident[2 + (boff & 0x01)];
 202             break;
 203         default:
 204             goto flash_read;
 205         }
 206         DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);
 207         break;
 208     case 0xA0:
 209     case 0x10:
 210     case 0x30:
 211         /* Status register read */
 212         ret = pfl->status;
 213         DPRINTF("%s: status %x\n", __func__, ret);
 214         /* Toggle bit 6 */
 215         pfl->status ^= 0x40;
 216         break;
 217     case 0x98:
 218         /* CFI query mode */
 219         if (boff > pfl->cfi_len)
 220             ret = 0;
 221         else
 222             ret = pfl->cfi_table[boff];
 223         break;
 224     }
 225
 226     return ret;
 227 }
 228
 229 /* update flash content on disk */
 230 static void pflash_update(pflash_t *pfl, int offset,
 231                           int size)
 232 {
 233     int offset_end;
 234     if (pfl->bs) {
 235         offset_end = offset + size;
 236         /* round to sectors */
 237         offset = offset >> 9;
 238         offset_end = (offset_end + 511) >> 9;
 239         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 240                    offset_end - offset);
 241     }
 242 }
 243
 244 static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
 245                           uint32_t value, int width, int be)
 246 {
 247     target_phys_addr_t boff;
 248     uint8_t *p;
 249     uint8_t cmd;
 250
 251     cmd = value;
 252     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 253 #if 0
 254         DPRINTF("%s: flash reset asked (%02x %02x)\n",
 255                 __func__, pfl->cmd, cmd);
 256 #endif
 257         goto reset_flash;
 258     }
 259     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__,
 260             offset, value, width, pfl->wcycle);
 261     offset &= pfl->chip_len - 1;
 262
 263     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
 264             offset, value, width);
 265     boff = offset & (pfl->sector_len - 1);
 266     if (pfl->width == 2)
 267         boff = boff >> 1;
 268     else if (pfl->width == 4)
 269         boff = boff >> 2;
 270     switch (pfl->wcycle) {
 271     case 0:
 272         /* Set the device in I/O access mode if required */
 273         if (pfl->rom_mode)
 274             pflash_register_memory(pfl, 0);
 275         pfl->read_counter = 0;
 276         /* We're in read mode */
 277     check_unlock0:
 278         if (boff == 0x55 && cmd == 0x98) {
 279         enter_CFI_mode:
 280             /* Enter CFI query mode */
 281             pfl->wcycle = 7;
 282             pfl->cmd = 0x98;
 283             return;
 284         }
 285         if (boff != pfl->unlock_addr[0] || cmd != 0xAA) {
 286             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 287                     __func__, boff, cmd, pfl->unlock_addr[0]);
 288             goto reset_flash;
 289         }
 290         DPRINTF("%s: unlock sequence started\n", __func__);
 291         break;
 292     case 1:
 293         /* We started an unlock sequence */
 294     check_unlock1:
 295         if (boff != pfl->unlock_addr[1] || cmd != 0x55) {
 296             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 297                     boff, cmd);
 298             goto reset_flash;
 299         }
 300         DPRINTF("%s: unlock sequence done\n", __func__);
 301         break;
 302     case 2:
 303         /* We finished an unlock sequence */
 304         if (!pfl->bypass && boff != pfl->unlock_addr[0]) {
 305             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 306                     boff, cmd);
 307             goto reset_flash;
 308         }
 309         switch (cmd) {
 310         case 0x20:
 311             pfl->bypass = 1;
 312             goto do_bypass;
 313         case 0x80:
 314         case 0x90:
 315         case 0xA0:
 316             pfl->cmd = cmd;
 317             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 318             break;
 319         default:
 320             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 321             goto reset_flash;
 322         }
 323         break;
 324     case 3:
 325         switch (pfl->cmd) {
 326         case 0x80:
 327             /* We need another unlock sequence */
 328             goto check_unlock0;
 329         case 0xA0:
 330             DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n",
 331                     __func__, offset, value, width);
 332             p = pfl->storage;
 333             switch (width) {
 334             case 1:
 335                 p[offset] &= value;
 336                 pflash_update(pfl, offset, 1);
 337                 break;
 338             case 2:
 339                 if (be) {
 340                     p[offset] &= value >> 8;
 341                     p[offset + 1] &= value;
 342                 } else {
 343                     p[offset] &= value;
 344                     p[offset + 1] &= value >> 8;
 345                 }
 346                 pflash_update(pfl, offset, 2);
 347                 break;
 348             case 4:
 349                 if (be) {
 350                     p[offset] &= value >> 24;
 351                     p[offset + 1] &= value >> 16;
 352                     p[offset + 2] &= value >> 8;
 353                     p[offset + 3] &= value;
 354                 } else {
 355                     p[offset] &= value;
 356                     p[offset + 1] &= value >> 8;
 357                     p[offset + 2] &= value >> 16;
 358                     p[offset + 3] &= value >> 24;
 359                 }
 360                 pflash_update(pfl, offset, 4);
 361                 break;
 362             }
 363             pfl->status = 0x00 | ~(value & 0x80);
 364             /* Let's pretend write is immediate */
 365             if (pfl->bypass)
 366                 goto do_bypass;
 367             goto reset_flash;
 368         case 0x90:
 369             if (pfl->bypass && cmd == 0x00) {
 370                 /* Unlock bypass reset */
 371                 goto reset_flash;
 372             }
 373             /* We can enter CFI query mode from autoselect mode */
 374             if (boff == 0x55 && cmd == 0x98)
 375                 goto enter_CFI_mode;
 376             /* No break here */
 377         default:
 378             DPRINTF("%s: invalid write for command %02x\n",
 379                     __func__, pfl->cmd);
 380             goto reset_flash;
 381         }
 382     case 4:
 383         switch (pfl->cmd) {
 384         case 0xA0:
 385             /* Ignore writes while flash data write is occurring */
 386             /* As we suppose write is immediate, this should never happen */
 387             return;
 388         case 0x80:
 389             goto check_unlock1;
 390         default:
 391             /* Should never happen */
 392             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 393                     __func__, pfl->cmd);
 394             goto reset_flash;
 395         }
 396         break;
 397     case 5:
 398         switch (cmd) {
 399         case 0x10:
 400             if (boff != pfl->unlock_addr[0]) {
 401                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 402                         __func__, offset);
 403                 goto reset_flash;
 404             }
 405             /* Chip erase */
 406             DPRINTF("%s: start chip erase\n", __func__);
 407             memset(pfl->storage, 0xFF, pfl->chip_len);
 408             pfl->status = 0x00;
 409             pflash_update(pfl, 0, pfl->chip_len);
 410             /* Let's wait 5 seconds before chip erase is done */
 411             qemu_mod_timer(pfl->timer,
 412                            qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));
 413             break;
 414         case 0x30:
 415             /* Sector erase */
 416             p = pfl->storage;
 417             offset &= ~(pfl->sector_len - 1);
 418             DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
 419                     offset);
 420             memset(p + offset, 0xFF, pfl->sector_len);
 421             pflash_update(pfl, offset, pfl->sector_len);
 422             pfl->status = 0x00;
 423             /* Let's wait 1/2 second before sector erase is done */
 424             qemu_mod_timer(pfl->timer,
 425                            qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));
 426             break;
 427         default:
 428             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 429             goto reset_flash;
 430         }
 431         pfl->cmd = cmd;
 432         break;
 433     case 6:
 434         switch (pfl->cmd) {
 435         case 0x10:
 436             /* Ignore writes during chip erase */
 437             return;
 438         case 0x30:
 439             /* Ignore writes during sector erase */
 440             return;
 441         default:
 442             /* Should never happen */
 443             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 444                     __func__, pfl->cmd);
 445             goto reset_flash;
 446         }
 447         break;
 448     case 7: /* Special value for CFI queries */
 449         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 450         goto reset_flash;
 451     default:
 452         /* Should never happen */
 453         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 454         goto reset_flash;
 455     }
 456     pfl->wcycle++;
 457
 458     return;
 459
 460     /* Reset flash */
 461  reset_flash:
 462     pfl->bypass = 0;
 463     pfl->wcycle = 0;
 464     pfl->cmd = 0;
 465     return;
 466
 467  do_bypass:
 468     pfl->wcycle = 2;
 469     pfl->cmd = 0;
 470     return;
 471 }
 472
 473
 474 static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
 475 {
 476     return pflash_read(opaque, addr, 1, 1);
 477 }
 478
 479 static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
 480 {
 481     return pflash_read(opaque, addr, 1, 0);
 482 }
 483
 484 static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
 485 {
 486     pflash_t *pfl = opaque;
 487
 488     return pflash_read(pfl, addr, 2, 1);
 489 }
 490
 491 static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
 492 {
 493     pflash_t *pfl = opaque;
 494
 495     return pflash_read(pfl, addr, 2, 0);
 496 }
 497
 498 static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
 499 {
 500     pflash_t *pfl = opaque;
 501
 502     return pflash_read(pfl, addr, 4, 1);
 503 }
 504
 505 static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
 506 {
 507     pflash_t *pfl = opaque;
 508
 509     return pflash_read(pfl, addr, 4, 0);
 510 }
 511
 512 static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
 513                              uint32_t value)
 514 {
 515     pflash_write(opaque, addr, value, 1, 1);
 516 }
 517
 518 static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
 519                              uint32_t value)
 520 {
 521     pflash_write(opaque, addr, value, 1, 0);
 522 }
 523
 524 static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
 525                              uint32_t value)
 526 {
 527     pflash_t *pfl = opaque;
 528
 529     pflash_write(pfl, addr, value, 2, 1);
 530 }
 531
 532 static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
 533                              uint32_t value)
 534 {
 535     pflash_t *pfl = opaque;
 536
 537     pflash_write(pfl, addr, value, 2, 0);
 538 }
 539
 540 static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
 541                              uint32_t value)
 542 {
 543     pflash_t *pfl = opaque;
 544
 545     pflash_write(pfl, addr, value, 4, 1);
 546 }
 547
 548 static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
 549                              uint32_t value)
 550 {
 551     pflash_t *pfl = opaque;
 552
 553     pflash_write(pfl, addr, value, 4, 0);
 554 }
 555
 556 const MemoryRegionOps pflash_cfi02_ops_be = {
 557     .old_mmio = {
 558         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
 559         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
 560     },
 561     .endianness = DEVICE_NATIVE_ENDIAN,
 562 };
 563
 564 const MemoryRegionOps pflash_cfi02_ops_le = {
 565     .old_mmio = {
 566         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
 567         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
 568     },
 569     .endianness = DEVICE_NATIVE_ENDIAN,
 570 };
 571
 572 /* Count trailing zeroes of a 32 bits quantity */
 573 static int ctz32 (uint32_t n)
 574 {
 575     int ret;
 576
 577     ret = 0;
 578     if (!(n & 0xFFFF)) {
 579         ret += 16;
 580         n = n >> 16;
 581     }
 582     if (!(n & 0xFF)) {
 583         ret += 8;
 584         n = n >> 8;
 585     }
 586     if (!(n & 0xF)) {
 587         ret += 4;
 588         n = n >> 4;
 589     }
 590     if (!(n & 0x3)) {
 591         ret += 2;
 592         n = n >> 2;
 593     }
 594     if (!(n & 0x1)) {
 595         ret++;
 596 #if 0 /* This is not necessary as n is never 0 */
 597         n = n >> 1;
 598 #endif
 599     }
 600 #if 0 /* This is not necessary as n is never 0 */
 601     if (!n)
 602         ret++;
 603 #endif
 604
 605     return ret;
 606 }
 607
 608 pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
 609                                 BlockDriverState *bs, uint32_t sector_len,
 610                                 int nb_blocs, int nb_mappings, int width,
 611                                 uint16_t id0, uint16_t id1,
 612                                 uint16_t id2, uint16_t id3,
 613                                 uint16_t unlock_addr0, uint16_t unlock_addr1)
 614 {
 615     pflash_t *pfl;
 616     int32_t chip_len;
 617     int ret;
 618
 619     chip_len = sector_len * nb_blocs;
 620     /* XXX: to be fixed */
 621 #if 0
 622     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 623         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 624         return NULL;
 625 #endif
 626     pfl = g_malloc0(sizeof(pflash_t));
 627     /* FIXME: Allocate ram ourselves.  */
 628     pfl->storage = memory_region_get_ram_ptr(mem);
 629     pfl->base = base;
 630     pfl->chip_len = chip_len;
 631     pfl->mappings = nb_mappings;
 632     pfl->bs = bs;
 633     if (pfl->bs) {
 634         /* read the initial flash content */
 635         ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
 636         if (ret < 0) {
 637             g_free(pfl);
 638             return NULL;
 639         }
 640     }
 641     pflash_setup_mappings(pfl, mem);
 642     pfl->rom_mode = 1;
 643     memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem);
 644 #if 0 /* XXX: there should be a bit to set up read-only,
 645        *      the same way the hardware does (with WP pin).
 646        */
 647     pfl->ro = 1;
 648 #else
 649     pfl->ro = 0;
 650 #endif
 651     pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
 652     pfl->sector_len = sector_len;
 653     pfl->width = width;
 654     pfl->wcycle = 0;
 655     pfl->cmd = 0;
 656     pfl->status = 0;
 657     pfl->ident[0] = id0;
 658     pfl->ident[1] = id1;
 659     pfl->ident[2] = id2;
 660     pfl->ident[3] = id3;
 661     pfl->unlock_addr[0] = unlock_addr0;
 662     pfl->unlock_addr[1] = unlock_addr1;
 663     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 664     pfl->cfi_len = 0x52;
 665     /* Standard "QRY" string */
 666     pfl->cfi_table[0x10] = 'Q';
 667     pfl->cfi_table[0x11] = 'R';
 668     pfl->cfi_table[0x12] = 'Y';
 669     /* Command set (AMD/Fujitsu) */
 670     pfl->cfi_table[0x13] = 0x02;
 671     pfl->cfi_table[0x14] = 0x00;
 672     /* Primary extended table address */
 673     pfl->cfi_table[0x15] = 0x31;
 674     pfl->cfi_table[0x16] = 0x00;
 675     /* Alternate command set (none) */
 676     pfl->cfi_table[0x17] = 0x00;
 677     pfl->cfi_table[0x18] = 0x00;
 678     /* Alternate extended table (none) */
 679     pfl->cfi_table[0x19] = 0x00;
 680     pfl->cfi_table[0x1A] = 0x00;
 681     /* Vcc min */
 682     pfl->cfi_table[0x1B] = 0x27;
 683     /* Vcc max */
 684     pfl->cfi_table[0x1C] = 0x36;
 685     /* Vpp min (no Vpp pin) */
 686     pfl->cfi_table[0x1D] = 0x00;
 687     /* Vpp max (no Vpp pin) */
 688     pfl->cfi_table[0x1E] = 0x00;
 689     /* Reserved */
 690     pfl->cfi_table[0x1F] = 0x07;
 691     /* Timeout for min size buffer write (NA) */
 692     pfl->cfi_table[0x20] = 0x00;
 693     /* Typical timeout for block erase (512 ms) */
 694     pfl->cfi_table[0x21] = 0x09;
 695     /* Typical timeout for full chip erase (4096 ms) */
 696     pfl->cfi_table[0x22] = 0x0C;
 697     /* Reserved */
 698     pfl->cfi_table[0x23] = 0x01;
 699     /* Max timeout for buffer write (NA) */
 700     pfl->cfi_table[0x24] = 0x00;
 701     /* Max timeout for block erase */
 702     pfl->cfi_table[0x25] = 0x0A;
 703     /* Max timeout for chip erase */
 704     pfl->cfi_table[0x26] = 0x0D;
 705     /* Device size */
 706     pfl->cfi_table[0x27] = ctz32(chip_len);
 707     /* Flash device interface (8 & 16 bits) */
 708     pfl->cfi_table[0x28] = 0x02;
 709     pfl->cfi_table[0x29] = 0x00;
 710     /* Max number of bytes in multi-bytes write */
 711     /* XXX: disable buffered write as it's not supported */
 712     //    pfl->cfi_table[0x2A] = 0x05;
 713     pfl->cfi_table[0x2A] = 0x00;
 714     pfl->cfi_table[0x2B] = 0x00;
 715     /* Number of erase block regions (uniform) */
 716     pfl->cfi_table[0x2C] = 0x01;
 717     /* Erase block region 1 */
 718     pfl->cfi_table[0x2D] = nb_blocs - 1;
 719     pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
 720     pfl->cfi_table[0x2F] = sector_len >> 8;
 721     pfl->cfi_table[0x30] = sector_len >> 16;
 722
 723     /* Extended */
 724     pfl->cfi_table[0x31] = 'P';
 725     pfl->cfi_table[0x32] = 'R';
 726     pfl->cfi_table[0x33] = 'I';
 727
 728     pfl->cfi_table[0x34] = '1';
 729     pfl->cfi_table[0x35] = '0';
 730
 731     pfl->cfi_table[0x36] = 0x00;
 732     pfl->cfi_table[0x37] = 0x00;
 733     pfl->cfi_table[0x38] = 0x00;
 734     pfl->cfi_table[0x39] = 0x00;
 735
 736     pfl->cfi_table[0x3a] = 0x00;
 737
 738     pfl->cfi_table[0x3b] = 0x00;
 739     pfl->cfi_table[0x3c] = 0x00;
 740
 741     return pfl;
 742 }