hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "apic.h"
  26 #include "ioapic.h"
  27 #include "qemu-timer.h"
  28 #include "host-utils.h"
  29 #include "sysbus.h"
  30
  31 //#define DEBUG_IOAPIC
  32
  33 #ifdef DEBUG_IOAPIC
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 #define MAX_IOAPICS                     1
  41
  42 #define IOAPIC_VERSION                  0x11
  43
  44 #define IOAPIC_LVT_DEST_SHIFT           56
  45 #define IOAPIC_LVT_MASKED_SHIFT         16
  46 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT   15
  47 #define IOAPIC_LVT_REMOTE_IRR_SHIFT     14
  48 #define IOAPIC_LVT_POLARITY_SHIFT       13
  49 #define IOAPIC_LVT_DELIV_STATUS_SHIFT   12
  50 #define IOAPIC_LVT_DEST_MODE_SHIFT      11
  51 #define IOAPIC_LVT_DELIV_MODE_SHIFT     8
  52
  53 #define IOAPIC_LVT_MASKED               (1 << IOAPIC_LVT_MASKED_SHIFT)
  54 #define IOAPIC_LVT_REMOTE_IRR           (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
  55
  56 #define IOAPIC_TRIGGER_EDGE             0
  57 #define IOAPIC_TRIGGER_LEVEL            1
  58
  59 /*io{apic,sapic} delivery mode*/
  60 #define IOAPIC_DM_FIXED                 0x0
  61 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  62 #define IOAPIC_DM_PMI                   0x2
  63 #define IOAPIC_DM_NMI                   0x4
  64 #define IOAPIC_DM_INIT                  0x5
  65 #define IOAPIC_DM_SIPI                  0x6
  66 #define IOAPIC_DM_EXTINT                0x7
  67 #define IOAPIC_DM_MASK                  0x7
  68
  69 #define IOAPIC_VECTOR_MASK              0xff
  70
  71 #define IOAPIC_IOREGSEL                 0x00
  72 #define IOAPIC_IOWIN                    0x10
  73
  74 #define IOAPIC_REG_ID                   0x00
  75 #define IOAPIC_REG_VER                  0x01
  76 #define IOAPIC_REG_ARB                  0x02
  77 #define IOAPIC_REG_REDTBL_BASE          0x10
  78 #define IOAPIC_ID                       0x00
  79
  80 #define IOAPIC_ID_SHIFT                 24
  81 #define IOAPIC_ID_MASK                  0xf
  82
  83 #define IOAPIC_VER_ENTRIES_SHIFT        16
  84
  85 typedef struct IOAPICState IOAPICState;
  86
  87 struct IOAPICState {
  88     SysBusDevice busdev;
  89     uint8_t id;
  90     uint8_t ioregsel;
  91     uint32_t irr;
  92     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  93 };
  94
  95 static IOAPICState *ioapics[MAX_IOAPICS];
  96
  97 static void ioapic_service(IOAPICState *s)
  98 {
  99     uint8_t i;
 100     uint8_t trig_mode;
 101     uint8_t vector;
 102     uint8_t delivery_mode;
 103     uint32_t mask;
 104     uint64_t entry;
 105     uint8_t dest;
 106     uint8_t dest_mode;
 107
 108     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 109         mask = 1 << i;
 110         if (s->irr & mask) {
 111             entry = s->ioredtbl[i];
 112             if (!(entry & IOAPIC_LVT_MASKED)) {
 113                 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
 114                 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
 115                 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
 116                 delivery_mode =
 117                     (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
 118                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
 119                     s->irr &= ~mask;
 120                 } else {
 121                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
 122                 }
 123                 if (delivery_mode == IOAPIC_DM_EXTINT) {
 124                     vector = pic_read_irq(isa_pic);
 125                 } else {
 126                     vector = entry & IOAPIC_VECTOR_MASK;
 127                 }
 128                 apic_deliver_irq(dest, dest_mode, delivery_mode,
 129                                  vector, trig_mode);
 130             }
 131         }
 132     }
 133 }
 134
 135 static void ioapic_set_irq(void *opaque, int vector, int level)
 136 {
 137     IOAPICState *s = opaque;
 138
 139     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 140      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 141      * the cleanest way of doing it but it should work. */
 142
 143     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
 144     if (vector == 0) {
 145         vector = 2;
 146     }
 147     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 148         uint32_t mask = 1 << vector;
 149         uint64_t entry = s->ioredtbl[vector];
 150
 151         if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) {
 152             level = !level;
 153         }
 154         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 155             IOAPIC_TRIGGER_LEVEL) {
 156             /* level triggered */
 157             if (level) {
 158                 s->irr |= mask;
 159                 ioapic_service(s);
 160             } else {
 161                 s->irr &= ~mask;
 162             }
 163         } else {
 164             /* According to the 82093AA manual, we must ignore edge requests
 165              * if the input pin is masked. */
 166             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 167                 s->irr |= mask;
 168                 ioapic_service(s);
 169             }
 170         }
 171     }
 172 }
 173
 174 void ioapic_eoi_broadcast(int vector)
 175 {
 176     IOAPICState *s;
 177     uint64_t entry;
 178     int i, n;
 179
 180     for (i = 0; i < MAX_IOAPICS; i++) {
 181         s = ioapics[i];
 182         if (!s) {
 183             continue;
 184         }
 185         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 186             entry = s->ioredtbl[n];
 187             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 188                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 189                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 190                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 191                     ioapic_service(s);
 192                 }
 193             }
 194         }
 195     }
 196 }
 197
 198 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 199 {
 200     IOAPICState *s = opaque;
 201     int index;
 202     uint32_t val = 0;
 203
 204     switch (addr & 0xff) {
 205     case IOAPIC_IOREGSEL:
 206         val = s->ioregsel;
 207         break;
 208     case IOAPIC_IOWIN:
 209         switch (s->ioregsel) {
 210         case IOAPIC_REG_ID:
 211             val = s->id << IOAPIC_ID_SHIFT;
 212             break;
 213         case IOAPIC_REG_VER:
 214             val = IOAPIC_VERSION |
 215                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 216             break;
 217         case IOAPIC_REG_ARB:
 218             val = 0;
 219             break;
 220         default:
 221             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 222             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 223                 if (s->ioregsel & 1) {
 224                     val = s->ioredtbl[index] >> 32;
 225                 } else {
 226                     val = s->ioredtbl[index] & 0xffffffff;
 227                 }
 228             }
 229         }
 230         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 231         break;
 232     }
 233     return val;
 234 }
 235
 236 static void
 237 ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 238 {
 239     IOAPICState *s = opaque;
 240     int index;
 241
 242     switch (addr & 0xff) {
 243     case IOAPIC_IOREGSEL:
 244         s->ioregsel = val;
 245         break;
 246     case IOAPIC_IOWIN:
 247         DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
 248         switch (s->ioregsel) {
 249         case IOAPIC_REG_ID:
 250             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 251             break;
 252         case IOAPIC_REG_VER:
 253         case IOAPIC_REG_ARB:
 254             break;
 255         default:
 256             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 257             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 258                 if (s->ioregsel & 1) {
 259                     s->ioredtbl[index] &= 0xffffffff;
 260                     s->ioredtbl[index] |= (uint64_t)val << 32;
 261                 } else {
 262                     s->ioredtbl[index] &= ~0xffffffffULL;
 263                     s->ioredtbl[index] |= val;
 264                 }
 265                 ioapic_service(s);
 266             }
 267         }
 268         break;
 269     }
 270 }
 271
 272 static int ioapic_post_load(void *opaque, int version_id)
 273 {
 274     IOAPICState *s = opaque;
 275
 276     if (version_id == 1) {
 277         /* set sane value */
 278         s->irr = 0;
 279     }
 280     return 0;
 281 }
 282
 283 static const VMStateDescription vmstate_ioapic = {
 284     .name = "ioapic",
 285     .version_id = 3,
 286     .post_load = ioapic_post_load,
 287     .minimum_version_id = 1,
 288     .minimum_version_id_old = 1,
 289     .fields = (VMStateField[]) {
 290         VMSTATE_UINT8(id, IOAPICState),
 291         VMSTATE_UINT8(ioregsel, IOAPICState),
 292         VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */
 293         VMSTATE_UINT32_V(irr, IOAPICState, 2),
 294         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 295         VMSTATE_END_OF_LIST()
 296     }
 297 };
 298
 299 static void ioapic_reset(DeviceState *d)
 300 {
 301     IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
 302     int i;
 303
 304     s->id = 0;
 305     s->ioregsel = 0;
 306     s->irr = 0;
 307     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 308         s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
 309     }
 310 }
 311
 312 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
 313     ioapic_mem_readl,
 314     ioapic_mem_readl,
 315     ioapic_mem_readl,
 316 };
 317
 318 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
 319     ioapic_mem_writel,
 320     ioapic_mem_writel,
 321     ioapic_mem_writel,
 322 };
 323
 324 static int ioapic_init1(SysBusDevice *dev)
 325 {
 326     IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
 327     int io_memory;
 328     static int ioapic_no;
 329
 330     if (ioapic_no >= MAX_IOAPICS) {
 331         return -1;
 332     }
 333
 334     io_memory = cpu_register_io_memory(ioapic_mem_read,
 335                                        ioapic_mem_write, s,
 336                                        DEVICE_NATIVE_ENDIAN);
 337     sysbus_init_mmio(dev, 0x1000, io_memory);
 338
 339     qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
 340
 341     ioapics[ioapic_no++] = s;
 342
 343     return 0;
 344 }
 345
 346 static SysBusDeviceInfo ioapic_info = {
 347     .init = ioapic_init1,
 348     .qdev.name = "ioapic",
 349     .qdev.size = sizeof(IOAPICState),
 350     .qdev.vmsd = &vmstate_ioapic,
 351     .qdev.reset = ioapic_reset,
 352     .qdev.no_user = 1,
 353 };
 354
 355 static void ioapic_register_devices(void)
 356 {
 357     sysbus_register_withprop(&ioapic_info);
 358 }
 359
 360 device_init(ioapic_register_devices)