target-arm/helper.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "internals.h"
   4 #include "exec/gdbstub.h"
   5 #include "exec/helper-proto.h"
   6 #include "qemu/host-utils.h"
   7 #include "sysemu/arch_init.h"
   8 #include "sysemu/sysemu.h"
   9 #include "qemu/bitops.h"
  10 #include "qemu/crc32c.h"
  11 #include "exec/cpu_ldst.h"
  12 #include "arm_ldst.h"
  13 #include <zlib.h> /* For crc32 */
  14 #include "exec/semihost.h"
  15 #include "sysemu/kvm.h"
  16
  17 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  18
  19 #ifndef CONFIG_USER_ONLY
  20 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  21                           int access_type, ARMMMUIdx mmu_idx,
  22                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  23                           target_ulong *page_size, uint32_t *fsr,
  24                           ARMMMUFaultInfo *fi);
  25
  26 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  27                                int access_type, ARMMMUIdx mmu_idx,
  28                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  29                                target_ulong *page_size_ptr, uint32_t *fsr,
  30                                ARMMMUFaultInfo *fi);
  31
  32 /* Definitions for the PMCCNTR and PMCR registers */
  33 #define PMCRD   0x8
  34 #define PMCRC   0x4
  35 #define PMCRE   0x1
  36 #endif
  37
  38 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  39 {
  40     int nregs;
  41
  42     /* VFP data registers are always little-endian.  */
  43     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  44     if (reg < nregs) {
  45         stfq_le_p(buf, env->vfp.regs[reg]);
  46         return 8;
  47     }
  48     if (arm_feature(env, ARM_FEATURE_NEON)) {
  49         /* Aliases for Q regs.  */
  50         nregs += 16;
  51         if (reg < nregs) {
  52             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  53             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  54             return 16;
  55         }
  56     }
  57     switch (reg - nregs) {
  58     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  59     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  60     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  61     }
  62     return 0;
  63 }
  64
  65 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  66 {
  67     int nregs;
  68
  69     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  70     if (reg < nregs) {
  71         env->vfp.regs[reg] = ldfq_le_p(buf);
  72         return 8;
  73     }
  74     if (arm_feature(env, ARM_FEATURE_NEON)) {
  75         nregs += 16;
  76         if (reg < nregs) {
  77             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  78             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  79             return 16;
  80         }
  81     }
  82     switch (reg - nregs) {
  83     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  84     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  85     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  86     }
  87     return 0;
  88 }
  89
  90 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  91 {
  92     switch (reg) {
  93     case 0 ... 31:
  94         /* 128 bit FP register */
  95         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  96         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  97         return 16;
  98     case 32:
  99         /* FPSR */
 100         stl_p(buf, vfp_get_fpsr(env));
 101         return 4;
 102     case 33:
 103         /* FPCR */
 104         stl_p(buf, vfp_get_fpcr(env));
 105         return 4;
 106     default:
 107         return 0;
 108     }
 109 }
 110
 111 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 112 {
 113     switch (reg) {
 114     case 0 ... 31:
 115         /* 128 bit FP register */
 116         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 117         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 118         return 16;
 119     case 32:
 120         /* FPSR */
 121         vfp_set_fpsr(env, ldl_p(buf));
 122         return 4;
 123     case 33:
 124         /* FPCR */
 125         vfp_set_fpcr(env, ldl_p(buf));
 126         return 4;
 127     default:
 128         return 0;
 129     }
 130 }
 131
 132 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         return CPREG_FIELD64(env, ri);
 137     } else {
 138         return CPREG_FIELD32(env, ri);
 139     }
 140 }
 141
 142 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 143                       uint64_t value)
 144 {
 145     assert(ri->fieldoffset);
 146     if (cpreg_field_is_64bit(ri)) {
 147         CPREG_FIELD64(env, ri) = value;
 148     } else {
 149         CPREG_FIELD32(env, ri) = value;
 150     }
 151 }
 152
 153 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 154 {
 155     return (char *)env + ri->fieldoffset;
 156 }
 157
 158 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 159 {
 160     /* Raw read of a coprocessor register (as needed for migration, etc). */
 161     if (ri->type & ARM_CP_CONST) {
 162         return ri->resetvalue;
 163     } else if (ri->raw_readfn) {
 164         return ri->raw_readfn(env, ri);
 165     } else if (ri->readfn) {
 166         return ri->readfn(env, ri);
 167     } else {
 168         return raw_read(env, ri);
 169     }
 170 }
 171
 172 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 173                              uint64_t v)
 174 {
 175     /* Raw write of a coprocessor register (as needed for migration, etc).
 176      * Note that constant registers are treated as write-ignored; the
 177      * caller should check for success by whether a readback gives the
 178      * value written.
 179      */
 180     if (ri->type & ARM_CP_CONST) {
 181         return;
 182     } else if (ri->raw_writefn) {
 183         ri->raw_writefn(env, ri, v);
 184     } else if (ri->writefn) {
 185         ri->writefn(env, ri, v);
 186     } else {
 187         raw_write(env, ri, v);
 188     }
 189 }
 190
 191 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 192 {
 193    /* Return true if the regdef would cause an assertion if you called
 194     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 195     * program bug for it not to have the NO_RAW flag).
 196     * NB that returning false here doesn't necessarily mean that calling
 197     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 198     * read/write access functions which are safe for raw use" from "has
 199     * read/write access functions which have side effects but has forgotten
 200     * to provide raw access functions".
 201     * The tests here line up with the conditions in read/write_raw_cp_reg()
 202     * and assertions in raw_read()/raw_write().
 203     */
 204     if ((ri->type & ARM_CP_CONST) ||
 205         ri->fieldoffset ||
 206         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 207         return false;
 208     }
 209     return true;
 210 }
 211
 212 bool write_cpustate_to_list(ARMCPU *cpu)
 213 {
 214     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 215     int i;
 216     bool ok = true;
 217
 218     for (i = 0; i < cpu->cpreg_array_len; i++) {
 219         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 220         const ARMCPRegInfo *ri;
 221
 222         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 223         if (!ri) {
 224             ok = false;
 225             continue;
 226         }
 227         if (ri->type & ARM_CP_NO_RAW) {
 228             continue;
 229         }
 230         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 231     }
 232     return ok;
 233 }
 234
 235 bool write_list_to_cpustate(ARMCPU *cpu)
 236 {
 237     int i;
 238     bool ok = true;
 239
 240     for (i = 0; i < cpu->cpreg_array_len; i++) {
 241         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 242         uint64_t v = cpu->cpreg_values[i];
 243         const ARMCPRegInfo *ri;
 244
 245         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 246         if (!ri) {
 247             ok = false;
 248             continue;
 249         }
 250         if (ri->type & ARM_CP_NO_RAW) {
 251             continue;
 252         }
 253         /* Write value and confirm it reads back as written
 254          * (to catch read-only registers and partially read-only
 255          * registers where the incoming migration value doesn't match)
 256          */
 257         write_raw_cp_reg(&cpu->env, ri, v);
 258         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 259             ok = false;
 260         }
 261     }
 262     return ok;
 263 }
 264
 265 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268     uint64_t regidx;
 269     const ARMCPRegInfo *ri;
 270
 271     regidx = *(uint32_t *)key;
 272     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 273
 274     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 275         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 276         /* The value array need not be initialized at this point */
 277         cpu->cpreg_array_len++;
 278     }
 279 }
 280
 281 static void count_cpreg(gpointer key, gpointer opaque)
 282 {
 283     ARMCPU *cpu = opaque;
 284     uint64_t regidx;
 285     const ARMCPRegInfo *ri;
 286
 287     regidx = *(uint32_t *)key;
 288     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 289
 290     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 291         cpu->cpreg_array_len++;
 292     }
 293 }
 294
 295 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 296 {
 297     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 298     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 299
 300     if (aidx > bidx) {
 301         return 1;
 302     }
 303     if (aidx < bidx) {
 304         return -1;
 305     }
 306     return 0;
 307 }
 308
 309 void init_cpreg_list(ARMCPU *cpu)
 310 {
 311     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 312      * Note that we require cpreg_tuples[] to be sorted by key ID.
 313      */
 314     GList *keys;
 315     int arraylen;
 316
 317     keys = g_hash_table_get_keys(cpu->cp_regs);
 318     keys = g_list_sort(keys, cpreg_key_compare);
 319
 320     cpu->cpreg_array_len = 0;
 321
 322     g_list_foreach(keys, count_cpreg, cpu);
 323
 324     arraylen = cpu->cpreg_array_len;
 325     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 328     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 329     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 330     cpu->cpreg_array_len = 0;
 331
 332     g_list_foreach(keys, add_cpreg_to_list, cpu);
 333
 334     assert(cpu->cpreg_array_len == arraylen);
 335
 336     g_list_free(keys);
 337 }
 338
 339 /*
 340  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 341  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 342  *
 343  * access_el3_aa32ns: Used to check AArch32 register views.
 344  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 345  */
 346 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 347                                         const ARMCPRegInfo *ri,
 348                                         bool isread)
 349 {
 350     bool secure = arm_is_secure_below_el3(env);
 351
 352     assert(!arm_el_is_aa64(env, 3));
 353     if (secure) {
 354         return CP_ACCESS_TRAP_UNCATEGORIZED;
 355     }
 356     return CP_ACCESS_OK;
 357 }
 358
 359 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 360                                                 const ARMCPRegInfo *ri,
 361                                                 bool isread)
 362 {
 363     if (!arm_el_is_aa64(env, 3)) {
 364         return access_el3_aa32ns(env, ri, isread);
 365     }
 366     return CP_ACCESS_OK;
 367 }
 368
 369 /* Some secure-only AArch32 registers trap to EL3 if used from
 370  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
 371  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
 372  * We assume that the .access field is set to PL1_RW.
 373  */
 374 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
 375                                             const ARMCPRegInfo *ri,
 376                                             bool isread)
 377 {
 378     if (arm_current_el(env) == 3) {
 379         return CP_ACCESS_OK;
 380     }
 381     if (arm_is_secure_below_el3(env)) {
 382         return CP_ACCESS_TRAP_EL3;
 383     }
 384     /* This will be EL1 NS and EL2 NS, which just UNDEF */
 385     return CP_ACCESS_TRAP_UNCATEGORIZED;
 386 }
 387
 388 /* Check for traps to "powerdown debug" registers, which are controlled
 389  * by MDCR.TDOSA
 390  */
 391 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
 392                                    bool isread)
 393 {
 394     int el = arm_current_el(env);
 395
 396     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
 397         && !arm_is_secure_below_el3(env)) {
 398         return CP_ACCESS_TRAP_EL2;
 399     }
 400     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
 401         return CP_ACCESS_TRAP_EL3;
 402     }
 403     return CP_ACCESS_OK;
 404 }
 405
 406 /* Check for traps to "debug ROM" registers, which are controlled
 407  * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
 408  */
 409 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
 410                                   bool isread)
 411 {
 412     int el = arm_current_el(env);
 413
 414     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
 415         && !arm_is_secure_below_el3(env)) {
 416         return CP_ACCESS_TRAP_EL2;
 417     }
 418     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 419         return CP_ACCESS_TRAP_EL3;
 420     }
 421     return CP_ACCESS_OK;
 422 }
 423
 424 /* Check for traps to general debug registers, which are controlled
 425  * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
 426  */
 427 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
 428                                   bool isread)
 429 {
 430     int el = arm_current_el(env);
 431
 432     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA)
 433         && !arm_is_secure_below_el3(env)) {
 434         return CP_ACCESS_TRAP_EL2;
 435     }
 436     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 437         return CP_ACCESS_TRAP_EL3;
 438     }
 439     return CP_ACCESS_OK;
 440 }
 441
 442 /* Check for traps to performance monitor registers, which are controlled
 443  * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
 444  */
 445 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 446                                  bool isread)
 447 {
 448     int el = arm_current_el(env);
 449
 450     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 451         && !arm_is_secure_below_el3(env)) {
 452         return CP_ACCESS_TRAP_EL2;
 453     }
 454     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 455         return CP_ACCESS_TRAP_EL3;
 456     }
 457     return CP_ACCESS_OK;
 458 }
 459
 460 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 461 {
 462     ARMCPU *cpu = arm_env_get_cpu(env);
 463
 464     raw_write(env, ri, value);
 465     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 466 }
 467
 468 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 469 {
 470     ARMCPU *cpu = arm_env_get_cpu(env);
 471
 472     if (raw_read(env, ri) != value) {
 473         /* Unlike real hardware the qemu TLB uses virtual addresses,
 474          * not modified virtual addresses, so this causes a TLB flush.
 475          */
 476         tlb_flush(CPU(cpu), 1);
 477         raw_write(env, ri, value);
 478     }
 479 }
 480
 481 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 482                              uint64_t value)
 483 {
 484     ARMCPU *cpu = arm_env_get_cpu(env);
 485
 486     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 487         && !extended_addresses_enabled(env)) {
 488         /* For VMSA (when not using the LPAE long descriptor page table
 489          * format) this register includes the ASID, so do a TLB flush.
 490          * For PMSA it is purely a process ID and no action is needed.
 491          */
 492         tlb_flush(CPU(cpu), 1);
 493     }
 494     raw_write(env, ri, value);
 495 }
 496
 497 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 498                           uint64_t value)
 499 {
 500     /* Invalidate all (TLBIALL) */
 501     ARMCPU *cpu = arm_env_get_cpu(env);
 502
 503     tlb_flush(CPU(cpu), 1);
 504 }
 505
 506 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 507                           uint64_t value)
 508 {
 509     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 510     ARMCPU *cpu = arm_env_get_cpu(env);
 511
 512     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 513 }
 514
 515 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 516                            uint64_t value)
 517 {
 518     /* Invalidate by ASID (TLBIASID) */
 519     ARMCPU *cpu = arm_env_get_cpu(env);
 520
 521     tlb_flush(CPU(cpu), value == 0);
 522 }
 523
 524 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 525                            uint64_t value)
 526 {
 527     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 528     ARMCPU *cpu = arm_env_get_cpu(env);
 529
 530     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 531 }
 532
 533 /* IS variants of TLB operations must affect all cores */
 534 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 535                              uint64_t value)
 536 {
 537     CPUState *other_cs;
 538
 539     CPU_FOREACH(other_cs) {
 540         tlb_flush(other_cs, 1);
 541     }
 542 }
 543
 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 545                              uint64_t value)
 546 {
 547     CPUState *other_cs;
 548
 549     CPU_FOREACH(other_cs) {
 550         tlb_flush(other_cs, value == 0);
 551     }
 552 }
 553
 554 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 555                              uint64_t value)
 556 {
 557     CPUState *other_cs;
 558
 559     CPU_FOREACH(other_cs) {
 560         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 561     }
 562 }
 563
 564 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 565                              uint64_t value)
 566 {
 567     CPUState *other_cs;
 568
 569     CPU_FOREACH(other_cs) {
 570         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 571     }
 572 }
 573
 574 static const ARMCPRegInfo cp_reginfo[] = {
 575     /* Define the secure and non-secure FCSE identifier CP registers
 576      * separately because there is no secure bank in V8 (no _EL3).  This allows
 577      * the secure register to be properly reset and migrated. There is also no
 578      * v8 EL1 version of the register so the non-secure instance stands alone.
 579      */
 580     { .name = "FCSEIDR(NS)",
 581       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 582       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 583       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 584       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 585     { .name = "FCSEIDR(S)",
 586       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 587       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 588       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 589       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 590     /* Define the secure and non-secure context identifier CP registers
 591      * separately because there is no secure bank in V8 (no _EL3).  This allows
 592      * the secure register to be properly reset and migrated.  In the
 593      * non-secure case, the 32-bit register will have reset and migration
 594      * disabled during registration as it is handled by the 64-bit instance.
 595      */
 596     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 597       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 598       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 599       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 600       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 601     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 602       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 603       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 604       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 605       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 606     REGINFO_SENTINEL
 607 };
 608
 609 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 610     /* NB: Some of these registers exist in v8 but with more precise
 611      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 612      */
 613     /* MMU Domain access control / MPU write buffer control */
 614     { .name = "DACR",
 615       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 616       .access = PL1_RW, .resetvalue = 0,
 617       .writefn = dacr_write, .raw_writefn = raw_write,
 618       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 619                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 620     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 621      * For v6 and v5, these mappings are overly broad.
 622      */
 623     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 624       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 625     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 626       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 627     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 628       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 629     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 630       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 631     /* Cache maintenance ops; some of this space may be overridden later. */
 632     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 633       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 634       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 635     REGINFO_SENTINEL
 636 };
 637
 638 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 639     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 640      * over-broad.
 641      */
 642     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 643       .access = PL1_W, .type = ARM_CP_WFI },
 644     REGINFO_SENTINEL
 645 };
 646
 647 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 648     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 649      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 650      */
 651     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 652       .access = PL1_W, .type = ARM_CP_WFI },
 653     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 654      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 655      * OMAPCP will override this space.
 656      */
 657     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 658       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 659       .resetvalue = 0 },
 660     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 661       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 662       .resetvalue = 0 },
 663     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 664     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 665       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 666       .resetvalue = 0 },
 667     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 668      * implementing it as RAZ means the "debug architecture version" bits
 669      * will read as a reserved value, which should cause Linux to not try
 670      * to use the debug hardware.
 671      */
 672     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 673       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 674     /* MMU TLB control. Note that the wildcarding means we cover not just
 675      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 676      */
 677     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 678       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 679       .type = ARM_CP_NO_RAW },
 680     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 681       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 682       .type = ARM_CP_NO_RAW },
 683     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 684       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 685       .type = ARM_CP_NO_RAW },
 686     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 687       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 688       .type = ARM_CP_NO_RAW },
 689     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 690       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 691     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 692       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 693     REGINFO_SENTINEL
 694 };
 695
 696 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 697                         uint64_t value)
 698 {
 699     uint32_t mask = 0;
 700
 701     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 702     if (!arm_feature(env, ARM_FEATURE_V8)) {
 703         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 704          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 705          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 706          */
 707         if (arm_feature(env, ARM_FEATURE_VFP)) {
 708             /* VFP coprocessor: cp10 & cp11 [23:20] */
 709             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 710
 711             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 712                 /* ASEDIS [31] bit is RAO/WI */
 713                 value |= (1 << 31);
 714             }
 715
 716             /* VFPv3 and upwards with NEON implement 32 double precision
 717              * registers (D0-D31).
 718              */
 719             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 720                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 721                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 722                 value |= (1 << 30);
 723             }
 724         }
 725         value &= mask;
 726     }
 727     env->cp15.cpacr_el1 = value;
 728 }
 729
 730 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 731                                    bool isread)
 732 {
 733     if (arm_feature(env, ARM_FEATURE_V8)) {
 734         /* Check if CPACR accesses are to be trapped to EL2 */
 735         if (arm_current_el(env) == 1 &&
 736             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 737             return CP_ACCESS_TRAP_EL2;
 738         /* Check if CPACR accesses are to be trapped to EL3 */
 739         } else if (arm_current_el(env) < 3 &&
 740                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 741             return CP_ACCESS_TRAP_EL3;
 742         }
 743     }
 744
 745     return CP_ACCESS_OK;
 746 }
 747
 748 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 749                                   bool isread)
 750 {
 751     /* Check if CPTR accesses are set to trap to EL3 */
 752     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 753         return CP_ACCESS_TRAP_EL3;
 754     }
 755
 756     return CP_ACCESS_OK;
 757 }
 758
 759 static const ARMCPRegInfo v6_cp_reginfo[] = {
 760     /* prefetch by MVA in v6, NOP in v7 */
 761     { .name = "MVA_prefetch",
 762       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 763       .access = PL1_W, .type = ARM_CP_NOP },
 764     /* We need to break the TB after ISB to execute self-modifying code
 765      * correctly and also to take any pending interrupts immediately.
 766      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 767      */
 768     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 769       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 770     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 771       .access = PL0_W, .type = ARM_CP_NOP },
 772     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 773       .access = PL0_W, .type = ARM_CP_NOP },
 774     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 775       .access = PL1_RW,
 776       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 777                              offsetof(CPUARMState, cp15.ifar_ns) },
 778       .resetvalue = 0, },
 779     /* Watchpoint Fault Address Register : should actually only be present
 780      * for 1136, 1176, 11MPCore.
 781      */
 782     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 783       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 784     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 785       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 786       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 787       .resetvalue = 0, .writefn = cpacr_write },
 788     REGINFO_SENTINEL
 789 };
 790
 791 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
 792                                    bool isread)
 793 {
 794     /* Performance monitor registers user accessibility is controlled
 795      * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
 796      * trapping to EL2 or EL3 for other accesses.
 797      */
 798     int el = arm_current_el(env);
 799
 800     if (el == 0 && !env->cp15.c9_pmuserenr) {
 801         return CP_ACCESS_TRAP;
 802     }
 803     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 804         && !arm_is_secure_below_el3(env)) {
 805         return CP_ACCESS_TRAP_EL2;
 806     }
 807     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 808         return CP_ACCESS_TRAP_EL3;
 809     }
 810
 811     return CP_ACCESS_OK;
 812 }
 813
 814 #ifndef CONFIG_USER_ONLY
 815
 816 static inline bool arm_ccnt_enabled(CPUARMState *env)
 817 {
 818     /* This does not support checking PMCCFILTR_EL0 register */
 819
 820     if (!(env->cp15.c9_pmcr & PMCRE)) {
 821         return false;
 822     }
 823
 824     return true;
 825 }
 826
 827 void pmccntr_sync(CPUARMState *env)
 828 {
 829     uint64_t temp_ticks;
 830
 831     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 832                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 833
 834     if (env->cp15.c9_pmcr & PMCRD) {
 835         /* Increment once every 64 processor clock cycles */
 836         temp_ticks /= 64;
 837     }
 838
 839     if (arm_ccnt_enabled(env)) {
 840         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 841     }
 842 }
 843
 844 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 845                        uint64_t value)
 846 {
 847     pmccntr_sync(env);
 848
 849     if (value & PMCRC) {
 850         /* The counter has been reset */
 851         env->cp15.c15_ccnt = 0;
 852     }
 853
 854     /* only the DP, X, D and E bits are writable */
 855     env->cp15.c9_pmcr &= ~0x39;
 856     env->cp15.c9_pmcr |= (value & 0x39);
 857
 858     pmccntr_sync(env);
 859 }
 860
 861 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 862 {
 863     uint64_t total_ticks;
 864
 865     if (!arm_ccnt_enabled(env)) {
 866         /* Counter is disabled, do not change value */
 867         return env->cp15.c15_ccnt;
 868     }
 869
 870     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 871                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 872
 873     if (env->cp15.c9_pmcr & PMCRD) {
 874         /* Increment once every 64 processor clock cycles */
 875         total_ticks /= 64;
 876     }
 877     return total_ticks - env->cp15.c15_ccnt;
 878 }
 879
 880 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 881                         uint64_t value)
 882 {
 883     uint64_t total_ticks;
 884
 885     if (!arm_ccnt_enabled(env)) {
 886         /* Counter is disabled, set the absolute value */
 887         env->cp15.c15_ccnt = value;
 888         return;
 889     }
 890
 891     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 892                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 893
 894     if (env->cp15.c9_pmcr & PMCRD) {
 895         /* Increment once every 64 processor clock cycles */
 896         total_ticks /= 64;
 897     }
 898     env->cp15.c15_ccnt = total_ticks - value;
 899 }
 900
 901 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 902                             uint64_t value)
 903 {
 904     uint64_t cur_val = pmccntr_read(env, NULL);
 905
 906     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 907 }
 908
 909 #else /* CONFIG_USER_ONLY */
 910
 911 void pmccntr_sync(CPUARMState *env)
 912 {
 913 }
 914
 915 #endif
 916
 917 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 918                             uint64_t value)
 919 {
 920     pmccntr_sync(env);
 921     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 922     pmccntr_sync(env);
 923 }
 924
 925 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 926                             uint64_t value)
 927 {
 928     value &= (1 << 31);
 929     env->cp15.c9_pmcnten |= value;
 930 }
 931
 932 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 933                              uint64_t value)
 934 {
 935     value &= (1 << 31);
 936     env->cp15.c9_pmcnten &= ~value;
 937 }
 938
 939 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 940                          uint64_t value)
 941 {
 942     env->cp15.c9_pmovsr &= ~value;
 943 }
 944
 945 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 946                              uint64_t value)
 947 {
 948     env->cp15.c9_pmxevtyper = value & 0xff;
 949 }
 950
 951 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 952                             uint64_t value)
 953 {
 954     env->cp15.c9_pmuserenr = value & 1;
 955 }
 956
 957 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 958                              uint64_t value)
 959 {
 960     /* We have no event counters so only the C bit can be changed */
 961     value &= (1 << 31);
 962     env->cp15.c9_pminten |= value;
 963 }
 964
 965 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 966                              uint64_t value)
 967 {
 968     value &= (1 << 31);
 969     env->cp15.c9_pminten &= ~value;
 970 }
 971
 972 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 973                        uint64_t value)
 974 {
 975     /* Note that even though the AArch64 view of this register has bits
 976      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 977      * architectural requirements for bits which are RES0 only in some
 978      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 979      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 980      */
 981     raw_write(env, ri, value & ~0x1FULL);
 982 }
 983
 984 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 985 {
 986     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 987      * For bits that vary between AArch32/64, code needs to check the
 988      * current execution mode before directly using the feature bit.
 989      */
 990     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 991
 992     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 993         valid_mask &= ~SCR_HCE;
 994
 995         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 996          * supported if EL2 exists. The bit is UNK/SBZP when
 997          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 998          * when EL2 is unavailable.
 999          * On ARMv8, this bit is always available.
1000          */
1001         if (arm_feature(env, ARM_FEATURE_V7) &&
1002             !arm_feature(env, ARM_FEATURE_V8)) {
1003             valid_mask &= ~SCR_SMD;
1004         }
1005     }
1006
1007     /* Clear all-context RES0 bits.  */
1008     value &= valid_mask;
1009     raw_write(env, ri, value);
1010 }
1011
1012 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1013 {
1014     ARMCPU *cpu = arm_env_get_cpu(env);
1015
1016     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1017      * bank
1018      */
1019     uint32_t index = A32_BANKED_REG_GET(env, csselr,
1020                                         ri->secure & ARM_CP_SECSTATE_S);
1021
1022     return cpu->ccsidr[index];
1023 }
1024
1025 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1026                          uint64_t value)
1027 {
1028     raw_write(env, ri, value & 0xf);
1029 }
1030
1031 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1032 {
1033     CPUState *cs = ENV_GET_CPU(env);
1034     uint64_t ret = 0;
1035
1036     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
1037         ret |= CPSR_I;
1038     }
1039     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
1040         ret |= CPSR_F;
1041     }
1042     /* External aborts are not possible in QEMU so A bit is always clear */
1043     return ret;
1044 }
1045
1046 static const ARMCPRegInfo v7_cp_reginfo[] = {
1047     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1048     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
1049       .access = PL1_W, .type = ARM_CP_NOP },
1050     /* Performance monitors are implementation defined in v7,
1051      * but with an ARM recommended set of registers, which we
1052      * follow (although we don't actually implement any counters)
1053      *
1054      * Performance registers fall into three categories:
1055      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1056      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1057      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1058      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1059      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1060      */
1061     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
1062       .access = PL0_RW, .type = ARM_CP_ALIAS,
1063       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1064       .writefn = pmcntenset_write,
1065       .accessfn = pmreg_access,
1066       .raw_writefn = raw_write },
1067     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
1068       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1069       .access = PL0_RW, .accessfn = pmreg_access,
1070       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1071       .writefn = pmcntenset_write, .raw_writefn = raw_write },
1072     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
1073       .access = PL0_RW,
1074       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1075       .accessfn = pmreg_access,
1076       .writefn = pmcntenclr_write,
1077       .type = ARM_CP_ALIAS },
1078     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1079       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1080       .access = PL0_RW, .accessfn = pmreg_access,
1081       .type = ARM_CP_ALIAS,
1082       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1083       .writefn = pmcntenclr_write },
1084     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1085       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1086       .accessfn = pmreg_access,
1087       .writefn = pmovsr_write,
1088       .raw_writefn = raw_write },
1089     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1090       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1091       .access = PL0_RW, .accessfn = pmreg_access,
1092       .type = ARM_CP_ALIAS,
1093       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1094       .writefn = pmovsr_write,
1095       .raw_writefn = raw_write },
1096     /* Unimplemented so WI. */
1097     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1098       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
1099     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
1100      * We choose to RAZ/WI.
1101      */
1102     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1103       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1104       .accessfn = pmreg_access },
1105 #ifndef CONFIG_USER_ONLY
1106     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1107       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
1108       .readfn = pmccntr_read, .writefn = pmccntr_write32,
1109       .accessfn = pmreg_access },
1110     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1111       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1112       .access = PL0_RW, .accessfn = pmreg_access,
1113       .type = ARM_CP_IO,
1114       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1115 #endif
1116     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1117       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1118       .writefn = pmccfiltr_write,
1119       .access = PL0_RW, .accessfn = pmreg_access,
1120       .type = ARM_CP_IO,
1121       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1122       .resetvalue = 0, },
1123     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1124       .access = PL0_RW,
1125       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1126       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1127       .raw_writefn = raw_write },
1128     /* Unimplemented, RAZ/WI. */
1129     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1130       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1131       .accessfn = pmreg_access },
1132     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1133       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
1134       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1135       .resetvalue = 0,
1136       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1137     { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
1138       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1139       .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1140       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1141       .resetvalue = 0,
1142       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1143     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1144       .access = PL1_RW, .accessfn = access_tpm,
1145       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1146       .resetvalue = 0,
1147       .writefn = pmintenset_write, .raw_writefn = raw_write },
1148     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1149       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1150       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1151       .writefn = pmintenclr_write, },
1152     { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
1153       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
1154       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1155       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1156       .writefn = pmintenclr_write },
1157     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1158       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1159       .access = PL1_RW, .writefn = vbar_write,
1160       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1161                              offsetof(CPUARMState, cp15.vbar_ns) },
1162       .resetvalue = 0 },
1163     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1164       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1165       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1166     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1167       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1168       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1169       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1170                              offsetof(CPUARMState, cp15.csselr_ns) } },
1171     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1172      * just RAZ for all cores:
1173      */
1174     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1175       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1176       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1177     /* Auxiliary fault status registers: these also are IMPDEF, and we
1178      * choose to RAZ/WI for all cores.
1179      */
1180     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1181       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1182       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1183     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1184       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1185       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1186     /* MAIR can just read-as-written because we don't implement caches
1187      * and so don't need to care about memory attributes.
1188      */
1189     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1190       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1191       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1192       .resetvalue = 0 },
1193     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1194       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1195       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1196       .resetvalue = 0 },
1197     /* For non-long-descriptor page tables these are PRRR and NMRR;
1198      * regardless they still act as reads-as-written for QEMU.
1199      */
1200      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1201       * allows them to assign the correct fieldoffset based on the endianness
1202       * handled in the field definitions.
1203       */
1204     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1205       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1206       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1207                              offsetof(CPUARMState, cp15.mair0_ns) },
1208       .resetfn = arm_cp_reset_ignore },
1209     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1210       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1211       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1212                              offsetof(CPUARMState, cp15.mair1_ns) },
1213       .resetfn = arm_cp_reset_ignore },
1214     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1215       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1216       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1217     /* 32 bit ITLB invalidates */
1218     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1219       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1220     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1221       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1222     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1223       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1224     /* 32 bit DTLB invalidates */
1225     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1226       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1227     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1228       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1229     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1230       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1231     /* 32 bit TLB invalidates */
1232     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1233       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1234     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1235       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1236     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1237       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1238     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1239       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1240     REGINFO_SENTINEL
1241 };
1242
1243 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1244     /* 32 bit TLB invalidates, Inner Shareable */
1245     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1246       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1247     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1248       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1249     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1250       .type = ARM_CP_NO_RAW, .access = PL1_W,
1251       .writefn = tlbiasid_is_write },
1252     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1253       .type = ARM_CP_NO_RAW, .access = PL1_W,
1254       .writefn = tlbimvaa_is_write },
1255     REGINFO_SENTINEL
1256 };
1257
1258 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1259                         uint64_t value)
1260 {
1261     value &= 1;
1262     env->teecr = value;
1263 }
1264
1265 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1266                                     bool isread)
1267 {
1268     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1269         return CP_ACCESS_TRAP;
1270     }
1271     return CP_ACCESS_OK;
1272 }
1273
1274 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1275     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1276       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1277       .resetvalue = 0,
1278       .writefn = teecr_write },
1279     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1280       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1281       .accessfn = teehbr_access, .resetvalue = 0 },
1282     REGINFO_SENTINEL
1283 };
1284
1285 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1286     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1287       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1288       .access = PL0_RW,
1289       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1290     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1291       .access = PL0_RW,
1292       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1293                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1294       .resetfn = arm_cp_reset_ignore },
1295     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1296       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1297       .access = PL0_R|PL1_W,
1298       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1299       .resetvalue = 0},
1300     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1301       .access = PL0_R|PL1_W,
1302       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1303                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1304       .resetfn = arm_cp_reset_ignore },
1305     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1306       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1307       .access = PL1_RW,
1308       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1309     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1310       .access = PL1_RW,
1311       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1312                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1313       .resetvalue = 0 },
1314     REGINFO_SENTINEL
1315 };
1316
1317 #ifndef CONFIG_USER_ONLY
1318
1319 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1320                                        bool isread)
1321 {
1322     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1323      * Writable only at the highest implemented exception level.
1324      */
1325     int el = arm_current_el(env);
1326
1327     switch (el) {
1328     case 0:
1329         if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
1330             return CP_ACCESS_TRAP;
1331         }
1332         break;
1333     case 1:
1334         if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1335             arm_is_secure_below_el3(env)) {
1336             /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1337             return CP_ACCESS_TRAP_UNCATEGORIZED;
1338         }
1339         break;
1340     case 2:
1341     case 3:
1342         break;
1343     }
1344
1345     if (!isread && el < arm_highest_el(env)) {
1346         return CP_ACCESS_TRAP_UNCATEGORIZED;
1347     }
1348
1349     return CP_ACCESS_OK;
1350 }
1351
1352 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1353                                         bool isread)
1354 {
1355     unsigned int cur_el = arm_current_el(env);
1356     bool secure = arm_is_secure(env);
1357
1358     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1359     if (cur_el == 0 &&
1360         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1361         return CP_ACCESS_TRAP;
1362     }
1363
1364     if (arm_feature(env, ARM_FEATURE_EL2) &&
1365         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1366         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1367         return CP_ACCESS_TRAP_EL2;
1368     }
1369     return CP_ACCESS_OK;
1370 }
1371
1372 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1373                                       bool isread)
1374 {
1375     unsigned int cur_el = arm_current_el(env);
1376     bool secure = arm_is_secure(env);
1377
1378     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1379      * EL0[PV]TEN is zero.
1380      */
1381     if (cur_el == 0 &&
1382         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1383         return CP_ACCESS_TRAP;
1384     }
1385
1386     if (arm_feature(env, ARM_FEATURE_EL2) &&
1387         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1388         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1389         return CP_ACCESS_TRAP_EL2;
1390     }
1391     return CP_ACCESS_OK;
1392 }
1393
1394 static CPAccessResult gt_pct_access(CPUARMState *env,
1395                                     const ARMCPRegInfo *ri,
1396                                     bool isread)
1397 {
1398     return gt_counter_access(env, GTIMER_PHYS, isread);
1399 }
1400
1401 static CPAccessResult gt_vct_access(CPUARMState *env,
1402                                     const ARMCPRegInfo *ri,
1403                                     bool isread)
1404 {
1405     return gt_counter_access(env, GTIMER_VIRT, isread);
1406 }
1407
1408 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1409                                        bool isread)
1410 {
1411     return gt_timer_access(env, GTIMER_PHYS, isread);
1412 }
1413
1414 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1415                                        bool isread)
1416 {
1417     return gt_timer_access(env, GTIMER_VIRT, isread);
1418 }
1419
1420 static CPAccessResult gt_stimer_access(CPUARMState *env,
1421                                        const ARMCPRegInfo *ri,
1422                                        bool isread)
1423 {
1424     /* The AArch64 register view of the secure physical timer is
1425      * always accessible from EL3, and configurably accessible from
1426      * Secure EL1.
1427      */
1428     switch (arm_current_el(env)) {
1429     case 1:
1430         if (!arm_is_secure(env)) {
1431             return CP_ACCESS_TRAP;
1432         }
1433         if (!(env->cp15.scr_el3 & SCR_ST)) {
1434             return CP_ACCESS_TRAP_EL3;
1435         }
1436         return CP_ACCESS_OK;
1437     case 0:
1438     case 2:
1439         return CP_ACCESS_TRAP;
1440     case 3:
1441         return CP_ACCESS_OK;
1442     default:
1443         g_assert_not_reached();
1444     }
1445 }
1446
1447 static uint64_t gt_get_countervalue(CPUARMState *env)
1448 {
1449     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1450 }
1451
1452 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1453 {
1454     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1455
1456     if (gt->ctl & 1) {
1457         /* Timer enabled: calculate and set current ISTATUS, irq, and
1458          * reset timer to when ISTATUS next has to change
1459          */
1460         uint64_t offset = timeridx == GTIMER_VIRT ?
1461                                       cpu->env.cp15.cntvoff_el2 : 0;
1462         uint64_t count = gt_get_countervalue(&cpu->env);
1463         /* Note that this must be unsigned 64 bit arithmetic: */
1464         int istatus = count - offset >= gt->cval;
1465         uint64_t nexttick;
1466
1467         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1468         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1469                      (istatus && !(gt->ctl & 2)));
1470         if (istatus) {
1471             /* Next transition is when count rolls back over to zero */
1472             nexttick = UINT64_MAX;
1473         } else {
1474             /* Next transition is when we hit cval */
1475             nexttick = gt->cval + offset;
1476         }
1477         /* Note that the desired next expiry time might be beyond the
1478          * signed-64-bit range of a QEMUTimer -- in this case we just
1479          * set the timer for as far in the future as possible. When the
1480          * timer expires we will reset the timer for any remaining period.
1481          */
1482         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1483             nexttick = INT64_MAX / GTIMER_SCALE;
1484         }
1485         timer_mod(cpu->gt_timer[timeridx], nexttick);
1486     } else {
1487         /* Timer disabled: ISTATUS and timer output always clear */
1488         gt->ctl &= ~4;
1489         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1490         timer_del(cpu->gt_timer[timeridx]);
1491     }
1492 }
1493
1494 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1495                            int timeridx)
1496 {
1497     ARMCPU *cpu = arm_env_get_cpu(env);
1498
1499     timer_del(cpu->gt_timer[timeridx]);
1500 }
1501
1502 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1503 {
1504     return gt_get_countervalue(env);
1505 }
1506
1507 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1508 {
1509     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1510 }
1511
1512 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1513                           int timeridx,
1514                           uint64_t value)
1515 {
1516     env->cp15.c14_timer[timeridx].cval = value;
1517     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1518 }
1519
1520 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1521                              int timeridx)
1522 {
1523     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1524
1525     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1526                       (gt_get_countervalue(env) - offset));
1527 }
1528
1529 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1530                           int timeridx,
1531                           uint64_t value)
1532 {
1533     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1534
1535     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1536                                          sextract64(value, 0, 32);
1537     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1538 }
1539
1540 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1541                          int timeridx,
1542                          uint64_t value)
1543 {
1544     ARMCPU *cpu = arm_env_get_cpu(env);
1545     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1546
1547     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1548     if ((oldval ^ value) & 1) {
1549         /* Enable toggled */
1550         gt_recalc_timer(cpu, timeridx);
1551     } else if ((oldval ^ value) & 2) {
1552         /* IMASK toggled: don't need to recalculate,
1553          * just set the interrupt line based on ISTATUS
1554          */
1555         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1556                      (oldval & 4) && !(value & 2));
1557     }
1558 }
1559
1560 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1561 {
1562     gt_timer_reset(env, ri, GTIMER_PHYS);
1563 }
1564
1565 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1566                                uint64_t value)
1567 {
1568     gt_cval_write(env, ri, GTIMER_PHYS, value);
1569 }
1570
1571 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1572 {
1573     return gt_tval_read(env, ri, GTIMER_PHYS);
1574 }
1575
1576 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1577                                uint64_t value)
1578 {
1579     gt_tval_write(env, ri, GTIMER_PHYS, value);
1580 }
1581
1582 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1583                               uint64_t value)
1584 {
1585     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1586 }
1587
1588 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1589 {
1590     gt_timer_reset(env, ri, GTIMER_VIRT);
1591 }
1592
1593 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1594                                uint64_t value)
1595 {
1596     gt_cval_write(env, ri, GTIMER_VIRT, value);
1597 }
1598
1599 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1600 {
1601     return gt_tval_read(env, ri, GTIMER_VIRT);
1602 }
1603
1604 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1605                                uint64_t value)
1606 {
1607     gt_tval_write(env, ri, GTIMER_VIRT, value);
1608 }
1609
1610 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1611                               uint64_t value)
1612 {
1613     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1614 }
1615
1616 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1617                               uint64_t value)
1618 {
1619     ARMCPU *cpu = arm_env_get_cpu(env);
1620
1621     raw_write(env, ri, value);
1622     gt_recalc_timer(cpu, GTIMER_VIRT);
1623 }
1624
1625 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1626 {
1627     gt_timer_reset(env, ri, GTIMER_HYP);
1628 }
1629
1630 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1631                               uint64_t value)
1632 {
1633     gt_cval_write(env, ri, GTIMER_HYP, value);
1634 }
1635
1636 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1637 {
1638     return gt_tval_read(env, ri, GTIMER_HYP);
1639 }
1640
1641 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1642                               uint64_t value)
1643 {
1644     gt_tval_write(env, ri, GTIMER_HYP, value);
1645 }
1646
1647 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1648                               uint64_t value)
1649 {
1650     gt_ctl_write(env, ri, GTIMER_HYP, value);
1651 }
1652
1653 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1654 {
1655     gt_timer_reset(env, ri, GTIMER_SEC);
1656 }
1657
1658 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1659                               uint64_t value)
1660 {
1661     gt_cval_write(env, ri, GTIMER_SEC, value);
1662 }
1663
1664 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1665 {
1666     return gt_tval_read(env, ri, GTIMER_SEC);
1667 }
1668
1669 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1670                               uint64_t value)
1671 {
1672     gt_tval_write(env, ri, GTIMER_SEC, value);
1673 }
1674
1675 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1676                               uint64_t value)
1677 {
1678     gt_ctl_write(env, ri, GTIMER_SEC, value);
1679 }
1680
1681 void arm_gt_ptimer_cb(void *opaque)
1682 {
1683     ARMCPU *cpu = opaque;
1684
1685     gt_recalc_timer(cpu, GTIMER_PHYS);
1686 }
1687
1688 void arm_gt_vtimer_cb(void *opaque)
1689 {
1690     ARMCPU *cpu = opaque;
1691
1692     gt_recalc_timer(cpu, GTIMER_VIRT);
1693 }
1694
1695 void arm_gt_htimer_cb(void *opaque)
1696 {
1697     ARMCPU *cpu = opaque;
1698
1699     gt_recalc_timer(cpu, GTIMER_HYP);
1700 }
1701
1702 void arm_gt_stimer_cb(void *opaque)
1703 {
1704     ARMCPU *cpu = opaque;
1705
1706     gt_recalc_timer(cpu, GTIMER_SEC);
1707 }
1708
1709 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1710     /* Note that CNTFRQ is purely reads-as-written for the benefit
1711      * of software; writing it doesn't actually change the timer frequency.
1712      * Our reset value matches the fixed frequency we implement the timer at.
1713      */
1714     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1715       .type = ARM_CP_ALIAS,
1716       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1717       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1718     },
1719     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1720       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1721       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1722       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1723       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1724     },
1725     /* overall control: mostly access permissions */
1726     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1727       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1728       .access = PL1_RW,
1729       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1730       .resetvalue = 0,
1731     },
1732     /* per-timer control */
1733     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1734       .secure = ARM_CP_SECSTATE_NS,
1735       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1736       .accessfn = gt_ptimer_access,
1737       .fieldoffset = offsetoflow32(CPUARMState,
1738                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1739       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1740     },
1741     { .name = "CNTP_CTL(S)",
1742       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1743       .secure = ARM_CP_SECSTATE_S,
1744       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1745       .accessfn = gt_ptimer_access,
1746       .fieldoffset = offsetoflow32(CPUARMState,
1747                                    cp15.c14_timer[GTIMER_SEC].ctl),
1748       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1749     },
1750     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1751       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1752       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1753       .accessfn = gt_ptimer_access,
1754       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1755       .resetvalue = 0,
1756       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1757     },
1758     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1759       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1760       .accessfn = gt_vtimer_access,
1761       .fieldoffset = offsetoflow32(CPUARMState,
1762                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1763       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1764     },
1765     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1766       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1767       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1768       .accessfn = gt_vtimer_access,
1769       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1770       .resetvalue = 0,
1771       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1772     },
1773     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1774     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1775       .secure = ARM_CP_SECSTATE_NS,
1776       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1777       .accessfn = gt_ptimer_access,
1778       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1779     },
1780     { .name = "CNTP_TVAL(S)",
1781       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1782       .secure = ARM_CP_SECSTATE_S,
1783       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1784       .accessfn = gt_ptimer_access,
1785       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1786     },
1787     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1788       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1789       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1790       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1791       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1792     },
1793     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1794       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1795       .accessfn = gt_vtimer_access,
1796       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1797     },
1798     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1799       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1800       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1801       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1802       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1803     },
1804     /* The counter itself */
1805     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1806       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1807       .accessfn = gt_pct_access,
1808       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1809     },
1810     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1811       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1812       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1813       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1814     },
1815     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1816       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1817       .accessfn = gt_vct_access,
1818       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1819     },
1820     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1821       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1822       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1823       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1824     },
1825     /* Comparison value, indicating when the timer goes off */
1826     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1827       .secure = ARM_CP_SECSTATE_NS,
1828       .access = PL1_RW | PL0_R,
1829       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1830       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1831       .accessfn = gt_ptimer_access,
1832       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1833     },
1834     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1835       .secure = ARM_CP_SECSTATE_S,
1836       .access = PL1_RW | PL0_R,
1837       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1838       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1839       .accessfn = gt_ptimer_access,
1840       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1841     },
1842     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1843       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1844       .access = PL1_RW | PL0_R,
1845       .type = ARM_CP_IO,
1846       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1847       .resetvalue = 0, .accessfn = gt_ptimer_access,
1848       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1849     },
1850     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1851       .access = PL1_RW | PL0_R,
1852       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1853       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1854       .accessfn = gt_vtimer_access,
1855       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1856     },
1857     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1858       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1859       .access = PL1_RW | PL0_R,
1860       .type = ARM_CP_IO,
1861       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1862       .resetvalue = 0, .accessfn = gt_vtimer_access,
1863       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1864     },
1865     /* Secure timer -- this is actually restricted to only EL3
1866      * and configurably Secure-EL1 via the accessfn.
1867      */
1868     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1869       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1870       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1871       .accessfn = gt_stimer_access,
1872       .readfn = gt_sec_tval_read,
1873       .writefn = gt_sec_tval_write,
1874       .resetfn = gt_sec_timer_reset,
1875     },
1876     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1877       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1878       .type = ARM_CP_IO, .access = PL1_RW,
1879       .accessfn = gt_stimer_access,
1880       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1881       .resetvalue = 0,
1882       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1883     },
1884     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1885       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1886       .type = ARM_CP_IO, .access = PL1_RW,
1887       .accessfn = gt_stimer_access,
1888       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1889       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1890     },
1891     REGINFO_SENTINEL
1892 };
1893
1894 #else
1895 /* In user-mode none of the generic timer registers are accessible,
1896  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1897  * so instead just don't register any of them.
1898  */
1899 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1900     REGINFO_SENTINEL
1901 };
1902
1903 #endif
1904
1905 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1906 {
1907     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1908         raw_write(env, ri, value);
1909     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1910         raw_write(env, ri, value & 0xfffff6ff);
1911     } else {
1912         raw_write(env, ri, value & 0xfffff1ff);
1913     }
1914 }
1915
1916 #ifndef CONFIG_USER_ONLY
1917 /* get_phys_addr() isn't present for user-mode-only targets */
1918
1919 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
1920                                  bool isread)
1921 {
1922     if (ri->opc2 & 4) {
1923         /* The ATS12NSO* operations must trap to EL3 if executed in
1924          * Secure EL1 (which can only happen if EL3 is AArch64).
1925          * They are simply UNDEF if executed from NS EL1.
1926          * They function normally from EL2 or EL3.
1927          */
1928         if (arm_current_el(env) == 1) {
1929             if (arm_is_secure_below_el3(env)) {
1930                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1931             }
1932             return CP_ACCESS_TRAP_UNCATEGORIZED;
1933         }
1934     }
1935     return CP_ACCESS_OK;
1936 }
1937
1938 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1939                              int access_type, ARMMMUIdx mmu_idx)
1940 {
1941     hwaddr phys_addr;
1942     target_ulong page_size;
1943     int prot;
1944     uint32_t fsr;
1945     bool ret;
1946     uint64_t par64;
1947     MemTxAttrs attrs = {};
1948     ARMMMUFaultInfo fi = {};
1949
1950     ret = get_phys_addr(env, value, access_type, mmu_idx,
1951                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1952     if (extended_addresses_enabled(env)) {
1953         /* fsr is a DFSR/IFSR value for the long descriptor
1954          * translation table format, but with WnR always clear.
1955          * Convert it to a 64-bit PAR.
1956          */
1957         par64 = (1 << 11); /* LPAE bit always set */
1958         if (!ret) {
1959             par64 |= phys_addr & ~0xfffULL;
1960             if (!attrs.secure) {
1961                 par64 |= (1 << 9); /* NS */
1962             }
1963             /* We don't set the ATTR or SH fields in the PAR. */
1964         } else {
1965             par64 |= 1; /* F */
1966             par64 |= (fsr & 0x3f) << 1; /* FS */
1967             /* Note that S2WLK and FSTAGE are always zero, because we don't
1968              * implement virtualization and therefore there can't be a stage 2
1969              * fault.
1970              */
1971         }
1972     } else {
1973         /* fsr is a DFSR/IFSR value for the short descriptor
1974          * translation table format (with WnR always clear).
1975          * Convert it to a 32-bit PAR.
1976          */
1977         if (!ret) {
1978             /* We do not set any attribute bits in the PAR */
1979             if (page_size == (1 << 24)
1980                 && arm_feature(env, ARM_FEATURE_V7)) {
1981                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1982             } else {
1983                 par64 = phys_addr & 0xfffff000;
1984             }
1985             if (!attrs.secure) {
1986                 par64 |= (1 << 9); /* NS */
1987             }
1988         } else {
1989             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1990                     ((fsr & 0xf) << 1) | 1;
1991         }
1992     }
1993     return par64;
1994 }
1995
1996 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1997 {
1998     int access_type = ri->opc2 & 1;
1999     uint64_t par64;
2000     ARMMMUIdx mmu_idx;
2001     int el = arm_current_el(env);
2002     bool secure = arm_is_secure_below_el3(env);
2003
2004     switch (ri->opc2 & 6) {
2005     case 0:
2006         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2007         switch (el) {
2008         case 3:
2009             mmu_idx = ARMMMUIdx_S1E3;
2010             break;
2011         case 2:
2012             mmu_idx = ARMMMUIdx_S1NSE1;
2013             break;
2014         case 1:
2015             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2016             break;
2017         default:
2018             g_assert_not_reached();
2019         }
2020         break;
2021     case 2:
2022         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2023         switch (el) {
2024         case 3:
2025             mmu_idx = ARMMMUIdx_S1SE0;
2026             break;
2027         case 2:
2028             mmu_idx = ARMMMUIdx_S1NSE0;
2029             break;
2030         case 1:
2031             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2032             break;
2033         default:
2034             g_assert_not_reached();
2035         }
2036         break;
2037     case 4:
2038         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2039         mmu_idx = ARMMMUIdx_S12NSE1;
2040         break;
2041     case 6:
2042         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2043         mmu_idx = ARMMMUIdx_S12NSE0;
2044         break;
2045     default:
2046         g_assert_not_reached();
2047     }
2048
2049     par64 = do_ats_write(env, value, access_type, mmu_idx);
2050
2051     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2052 }
2053
2054 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
2055                         uint64_t value)
2056 {
2057     int access_type = ri->opc2 & 1;
2058     uint64_t par64;
2059
2060     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
2061
2062     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2063 }
2064
2065 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
2066                                      bool isread)
2067 {
2068     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
2069         return CP_ACCESS_TRAP;
2070     }
2071     return CP_ACCESS_OK;
2072 }
2073
2074 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
2075                         uint64_t value)
2076 {
2077     int access_type = ri->opc2 & 1;
2078     ARMMMUIdx mmu_idx;
2079     int secure = arm_is_secure_below_el3(env);
2080
2081     switch (ri->opc2 & 6) {
2082     case 0:
2083         switch (ri->opc1) {
2084         case 0: /* AT S1E1R, AT S1E1W */
2085             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2086             break;
2087         case 4: /* AT S1E2R, AT S1E2W */
2088             mmu_idx = ARMMMUIdx_S1E2;
2089             break;
2090         case 6: /* AT S1E3R, AT S1E3W */
2091             mmu_idx = ARMMMUIdx_S1E3;
2092             break;
2093         default:
2094             g_assert_not_reached();
2095         }
2096         break;
2097     case 2: /* AT S1E0R, AT S1E0W */
2098         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2099         break;
2100     case 4: /* AT S12E1R, AT S12E1W */
2101         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
2102         break;
2103     case 6: /* AT S12E0R, AT S12E0W */
2104         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
2105         break;
2106     default:
2107         g_assert_not_reached();
2108     }
2109
2110     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
2111 }
2112 #endif
2113
2114 static const ARMCPRegInfo vapa_cp_reginfo[] = {
2115     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
2116       .access = PL1_RW, .resetvalue = 0,
2117       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
2118                              offsetoflow32(CPUARMState, cp15.par_ns) },
2119       .writefn = par_write },
2120 #ifndef CONFIG_USER_ONLY
2121     /* This underdecoding is safe because the reginfo is NO_RAW. */
2122     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
2123       .access = PL1_W, .accessfn = ats_access,
2124       .writefn = ats_write, .type = ARM_CP_NO_RAW },
2125 #endif
2126     REGINFO_SENTINEL
2127 };
2128
2129 /* Return basic MPU access permission bits.  */
2130 static uint32_t simple_mpu_ap_bits(uint32_t val)
2131 {
2132     uint32_t ret;
2133     uint32_t mask;
2134     int i;
2135     ret = 0;
2136     mask = 3;
2137     for (i = 0; i < 16; i += 2) {
2138         ret |= (val >> i) & mask;
2139         mask <<= 2;
2140     }
2141     return ret;
2142 }
2143
2144 /* Pad basic MPU access permission bits to extended format.  */
2145 static uint32_t extended_mpu_ap_bits(uint32_t val)
2146 {
2147     uint32_t ret;
2148     uint32_t mask;
2149     int i;
2150     ret = 0;
2151     mask = 3;
2152     for (i = 0; i < 16; i += 2) {
2153         ret |= (val & mask) << i;
2154         mask <<= 2;
2155     }
2156     return ret;
2157 }
2158
2159 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2160                                  uint64_t value)
2161 {
2162     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2163 }
2164
2165 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2166 {
2167     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2168 }
2169
2170 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2171                                  uint64_t value)
2172 {
2173     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2174 }
2175
2176 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2177 {
2178     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2179 }
2180
2181 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2182 {
2183     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2184
2185     if (!u32p) {
2186         return 0;
2187     }
2188
2189     u32p += env->cp15.c6_rgnr;
2190     return *u32p;
2191 }
2192
2193 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2194                          uint64_t value)
2195 {
2196     ARMCPU *cpu = arm_env_get_cpu(env);
2197     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2198
2199     if (!u32p) {
2200         return;
2201     }
2202
2203     u32p += env->cp15.c6_rgnr;
2204     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2205     *u32p = value;
2206 }
2207
2208 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2209 {
2210     ARMCPU *cpu = arm_env_get_cpu(env);
2211     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2212
2213     if (!u32p) {
2214         return;
2215     }
2216
2217     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2218 }
2219
2220 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2221                               uint64_t value)
2222 {
2223     ARMCPU *cpu = arm_env_get_cpu(env);
2224     uint32_t nrgs = cpu->pmsav7_dregion;
2225
2226     if (value >= nrgs) {
2227         qemu_log_mask(LOG_GUEST_ERROR,
2228                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2229                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2230         return;
2231     }
2232
2233     raw_write(env, ri, value);
2234 }
2235
2236 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2237     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2238       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2239       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2240       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2241     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2242       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2243       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2244       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2245     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2246       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2247       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2248       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2249     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2250       .access = PL1_RW,
2251       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2252       .writefn = pmsav7_rgnr_write },
2253     REGINFO_SENTINEL
2254 };
2255
2256 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2257     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2258       .access = PL1_RW, .type = ARM_CP_ALIAS,
2259       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2260       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2261     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2262       .access = PL1_RW, .type = ARM_CP_ALIAS,
2263       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2264       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2265     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2266       .access = PL1_RW,
2267       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2268       .resetvalue = 0, },
2269     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2270       .access = PL1_RW,
2271       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2272       .resetvalue = 0, },
2273     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2274       .access = PL1_RW,
2275       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2276     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2277       .access = PL1_RW,
2278       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2279     /* Protection region base and size registers */
2280     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2281       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2282       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2283     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2284       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2285       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2286     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2287       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2288       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2289     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2290       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2291       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2292     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2293       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2294       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2295     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2296       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2297       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2298     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2299       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2300       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2301     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2302       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2303       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2304     REGINFO_SENTINEL
2305 };
2306
2307 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2308                                  uint64_t value)
2309 {
2310     TCR *tcr = raw_ptr(env, ri);
2311     int maskshift = extract32(value, 0, 3);
2312
2313     if (!arm_feature(env, ARM_FEATURE_V8)) {
2314         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2315             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2316              * using Long-desciptor translation table format */
2317             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2318         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2319             /* In an implementation that includes the Security Extensions
2320              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2321              * Short-descriptor translation table format.
2322              */
2323             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2324         } else {
2325             value &= TTBCR_N;
2326         }
2327     }
2328
2329     /* Update the masks corresponding to the TCR bank being written
2330      * Note that we always calculate mask and base_mask, but
2331      * they are only used for short-descriptor tables (ie if EAE is 0);
2332      * for long-descriptor tables the TCR fields are used differently
2333      * and the mask and base_mask values are meaningless.
2334      */
2335     tcr->raw_tcr = value;
2336     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2337     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2338 }
2339
2340 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2341                              uint64_t value)
2342 {
2343     ARMCPU *cpu = arm_env_get_cpu(env);
2344
2345     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2346         /* With LPAE the TTBCR could result in a change of ASID
2347          * via the TTBCR.A1 bit, so do a TLB flush.
2348          */
2349         tlb_flush(CPU(cpu), 1);
2350     }
2351     vmsa_ttbcr_raw_write(env, ri, value);
2352 }
2353
2354 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2355 {
2356     TCR *tcr = raw_ptr(env, ri);
2357
2358     /* Reset both the TCR as well as the masks corresponding to the bank of
2359      * the TCR being reset.
2360      */
2361     tcr->raw_tcr = 0;
2362     tcr->mask = 0;
2363     tcr->base_mask = 0xffffc000u;
2364 }
2365
2366 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2367                                uint64_t value)
2368 {
2369     ARMCPU *cpu = arm_env_get_cpu(env);
2370     TCR *tcr = raw_ptr(env, ri);
2371
2372     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2373     tlb_flush(CPU(cpu), 1);
2374     tcr->raw_tcr = value;
2375 }
2376
2377 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2378                             uint64_t value)
2379 {
2380     /* 64 bit accesses to the TTBRs can change the ASID and so we
2381      * must flush the TLB.
2382      */
2383     if (cpreg_field_is_64bit(ri)) {
2384         ARMCPU *cpu = arm_env_get_cpu(env);
2385
2386         tlb_flush(CPU(cpu), 1);
2387     }
2388     raw_write(env, ri, value);
2389 }
2390
2391 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2392                         uint64_t value)
2393 {
2394     ARMCPU *cpu = arm_env_get_cpu(env);
2395     CPUState *cs = CPU(cpu);
2396
2397     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2398     if (raw_read(env, ri) != value) {
2399         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2400                             ARMMMUIdx_S2NS, -1);
2401         raw_write(env, ri, value);
2402     }
2403 }
2404
2405 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2406     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2407       .access = PL1_RW, .type = ARM_CP_ALIAS,
2408       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2409                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2410     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2411       .access = PL1_RW, .resetvalue = 0,
2412       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2413                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2414     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2415       .access = PL1_RW, .resetvalue = 0,
2416       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2417                              offsetof(CPUARMState, cp15.dfar_ns) } },
2418     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2419       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2420       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2421       .resetvalue = 0, },
2422     REGINFO_SENTINEL
2423 };
2424
2425 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2426     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2427       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2428       .access = PL1_RW,
2429       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2430     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2431       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2432       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2433       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2434                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2435     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2436       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2437       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2438       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2439                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2440     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2441       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2442       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2443       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2444       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2445     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2446       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2447       .raw_writefn = vmsa_ttbcr_raw_write,
2448       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2449                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2450     REGINFO_SENTINEL
2451 };
2452
2453 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2454                                 uint64_t value)
2455 {
2456     env->cp15.c15_ticonfig = value & 0xe7;
2457     /* The OS_TYPE bit in this register changes the reported CPUID! */
2458     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2459         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2460 }
2461
2462 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2463                                 uint64_t value)
2464 {
2465     env->cp15.c15_threadid = value & 0xffff;
2466 }
2467
2468 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2469                            uint64_t value)
2470 {
2471     /* Wait-for-interrupt (deprecated) */
2472     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2473 }
2474
2475 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2476                                   uint64_t value)
2477 {
2478     /* On OMAP there are registers indicating the max/min index of dcache lines
2479      * containing a dirty line; cache flush operations have to reset these.
2480      */
2481     env->cp15.c15_i_max = 0x000;
2482     env->cp15.c15_i_min = 0xff0;
2483 }
2484
2485 static const ARMCPRegInfo omap_cp_reginfo[] = {
2486     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2487       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2488       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2489       .resetvalue = 0, },
2490     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2491       .access = PL1_RW, .type = ARM_CP_NOP },
2492     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2493       .access = PL1_RW,
2494       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2495       .writefn = omap_ticonfig_write },
2496     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2497       .access = PL1_RW,
2498       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2499     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2500       .access = PL1_RW, .resetvalue = 0xff0,
2501       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2502     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2503       .access = PL1_RW,
2504       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2505       .writefn = omap_threadid_write },
2506     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2507       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2508       .type = ARM_CP_NO_RAW,
2509       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2510     /* TODO: Peripheral port remap register:
2511      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2512      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2513      * when MMU is off.
2514      */
2515     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2516       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2517       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2518       .writefn = omap_cachemaint_write },
2519     { .name = "C9", .cp = 15, .crn = 9,
2520       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2521       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2522     REGINFO_SENTINEL
2523 };
2524
2525 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2526                               uint64_t value)
2527 {
2528     env->cp15.c15_cpar = value & 0x3fff;
2529 }
2530
2531 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2532     { .name = "XSCALE_CPAR",
2533       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2534       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2535       .writefn = xscale_cpar_write, },
2536     { .name = "XSCALE_AUXCR",
2537       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2538       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2539       .resetvalue = 0, },
2540     /* XScale specific cache-lockdown: since we have no cache we NOP these
2541      * and hope the guest does not really rely on cache behaviour.
2542      */
2543     { .name = "XSCALE_LOCK_ICACHE_LINE",
2544       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2545       .access = PL1_W, .type = ARM_CP_NOP },
2546     { .name = "XSCALE_UNLOCK_ICACHE",
2547       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2548       .access = PL1_W, .type = ARM_CP_NOP },
2549     { .name = "XSCALE_DCACHE_LOCK",
2550       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2551       .access = PL1_RW, .type = ARM_CP_NOP },
2552     { .name = "XSCALE_UNLOCK_DCACHE",
2553       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2554       .access = PL1_W, .type = ARM_CP_NOP },
2555     REGINFO_SENTINEL
2556 };
2557
2558 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2559     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2560      * implementation of this implementation-defined space.
2561      * Ideally this should eventually disappear in favour of actually
2562      * implementing the correct behaviour for all cores.
2563      */
2564     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2565       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2566       .access = PL1_RW,
2567       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2568       .resetvalue = 0 },
2569     REGINFO_SENTINEL
2570 };
2571
2572 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2573     /* Cache status: RAZ because we have no cache so it's always clean */
2574     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2575       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2576       .resetvalue = 0 },
2577     REGINFO_SENTINEL
2578 };
2579
2580 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2581     /* We never have a a block transfer operation in progress */
2582     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2583       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2584       .resetvalue = 0 },
2585     /* The cache ops themselves: these all NOP for QEMU */
2586     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2587       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2588     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2589       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2590     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2591       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2592     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2593       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2594     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2595       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2596     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2597       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2598     REGINFO_SENTINEL
2599 };
2600
2601 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2602     /* The cache test-and-clean instructions always return (1 << 30)
2603      * to indicate that there are no dirty cache lines.
2604      */
2605     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2606       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2607       .resetvalue = (1 << 30) },
2608     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2609       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2610       .resetvalue = (1 << 30) },
2611     REGINFO_SENTINEL
2612 };
2613
2614 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2615     /* Ignore ReadBuffer accesses */
2616     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2617       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2618       .access = PL1_RW, .resetvalue = 0,
2619       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2620     REGINFO_SENTINEL
2621 };
2622
2623 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2624 {
2625     ARMCPU *cpu = arm_env_get_cpu(env);
2626     unsigned int cur_el = arm_current_el(env);
2627     bool secure = arm_is_secure(env);
2628
2629     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2630         return env->cp15.vpidr_el2;
2631     }
2632     return raw_read(env, ri);
2633 }
2634
2635 static uint64_t mpidr_read_val(CPUARMState *env)
2636 {
2637     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2638     uint64_t mpidr = cpu->mp_affinity;
2639
2640     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2641         mpidr |= (1U << 31);
2642         /* Cores which are uniprocessor (non-coherent)
2643          * but still implement the MP extensions set
2644          * bit 30. (For instance, Cortex-R5).
2645          */
2646         if (cpu->mp_is_up) {
2647             mpidr |= (1u << 30);
2648         }
2649     }
2650     return mpidr;
2651 }
2652
2653 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2654 {
2655     unsigned int cur_el = arm_current_el(env);
2656     bool secure = arm_is_secure(env);
2657
2658     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2659         return env->cp15.vmpidr_el2;
2660     }
2661     return mpidr_read_val(env);
2662 }
2663
2664 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2665     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2666       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2667       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2668     REGINFO_SENTINEL
2669 };
2670
2671 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2672     /* NOP AMAIR0/1 */
2673     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2674       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2675       .access = PL1_RW, .type = ARM_CP_CONST,
2676       .resetvalue = 0 },
2677     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2678     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2679       .access = PL1_RW, .type = ARM_CP_CONST,
2680       .resetvalue = 0 },
2681     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2682       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2683       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2684                              offsetof(CPUARMState, cp15.par_ns)} },
2685     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2686       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2687       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2688                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2689       .writefn = vmsa_ttbr_write, },
2690     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2691       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2692       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2693                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2694       .writefn = vmsa_ttbr_write, },
2695     REGINFO_SENTINEL
2696 };
2697
2698 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2699 {
2700     return vfp_get_fpcr(env);
2701 }
2702
2703 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2704                             uint64_t value)
2705 {
2706     vfp_set_fpcr(env, value);
2707 }
2708
2709 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2710 {
2711     return vfp_get_fpsr(env);
2712 }
2713
2714 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2715                             uint64_t value)
2716 {
2717     vfp_set_fpsr(env, value);
2718 }
2719
2720 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
2721                                        bool isread)
2722 {
2723     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2724         return CP_ACCESS_TRAP;
2725     }
2726     return CP_ACCESS_OK;
2727 }
2728
2729 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2730                             uint64_t value)
2731 {
2732     env->daif = value & PSTATE_DAIF;
2733 }
2734
2735 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2736                                           const ARMCPRegInfo *ri,
2737                                           bool isread)
2738 {
2739     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2740      * SCTLR_EL1.UCI is set.
2741      */
2742     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2743         return CP_ACCESS_TRAP;
2744     }
2745     return CP_ACCESS_OK;
2746 }
2747
2748 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2749  * Page D4-1736 (DDI0487A.b)
2750  */
2751
2752 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2753                                     uint64_t value)
2754 {
2755     ARMCPU *cpu = arm_env_get_cpu(env);
2756     CPUState *cs = CPU(cpu);
2757
2758     if (arm_is_secure_below_el3(env)) {
2759         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2760     } else {
2761         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2762     }
2763 }
2764
2765 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2766                                       uint64_t value)
2767 {
2768     bool sec = arm_is_secure_below_el3(env);
2769     CPUState *other_cs;
2770
2771     CPU_FOREACH(other_cs) {
2772         if (sec) {
2773             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2774         } else {
2775             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2776                                 ARMMMUIdx_S12NSE0, -1);
2777         }
2778     }
2779 }
2780
2781 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2782                                   uint64_t value)
2783 {
2784     /* Note that the 'ALL' scope must invalidate both stage 1 and
2785      * stage 2 translations, whereas most other scopes only invalidate
2786      * stage 1 translations.
2787      */
2788     ARMCPU *cpu = arm_env_get_cpu(env);
2789     CPUState *cs = CPU(cpu);
2790
2791     if (arm_is_secure_below_el3(env)) {
2792         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2793     } else {
2794         if (arm_feature(env, ARM_FEATURE_EL2)) {
2795             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2796                                 ARMMMUIdx_S2NS, -1);
2797         } else {
2798             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2799         }
2800     }
2801 }
2802
2803 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2804                                   uint64_t value)
2805 {
2806     ARMCPU *cpu = arm_env_get_cpu(env);
2807     CPUState *cs = CPU(cpu);
2808
2809     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2810 }
2811
2812 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2813                                   uint64_t value)
2814 {
2815     ARMCPU *cpu = arm_env_get_cpu(env);
2816     CPUState *cs = CPU(cpu);
2817
2818     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2819 }
2820
2821 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2822                                     uint64_t value)
2823 {
2824     /* Note that the 'ALL' scope must invalidate both stage 1 and
2825      * stage 2 translations, whereas most other scopes only invalidate
2826      * stage 1 translations.
2827      */
2828     bool sec = arm_is_secure_below_el3(env);
2829     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2830     CPUState *other_cs;
2831
2832     CPU_FOREACH(other_cs) {
2833         if (sec) {
2834             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2835         } else if (has_el2) {
2836             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2837                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2838         } else {
2839             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2840                                 ARMMMUIdx_S12NSE0, -1);
2841         }
2842     }
2843 }
2844
2845 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2846                                     uint64_t value)
2847 {
2848     CPUState *other_cs;
2849
2850     CPU_FOREACH(other_cs) {
2851         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2852     }
2853 }
2854
2855 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2856                                     uint64_t value)
2857 {
2858     CPUState *other_cs;
2859
2860     CPU_FOREACH(other_cs) {
2861         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2862     }
2863 }
2864
2865 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2866                                  uint64_t value)
2867 {
2868     /* Invalidate by VA, EL1&0 (AArch64 version).
2869      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2870      * since we don't support flush-for-specific-ASID-only or
2871      * flush-last-level-only.
2872      */
2873     ARMCPU *cpu = arm_env_get_cpu(env);
2874     CPUState *cs = CPU(cpu);
2875     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2876
2877     if (arm_is_secure_below_el3(env)) {
2878         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2879                                  ARMMMUIdx_S1SE0, -1);
2880     } else {
2881         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2882                                  ARMMMUIdx_S12NSE0, -1);
2883     }
2884 }
2885
2886 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2887                                  uint64_t value)
2888 {
2889     /* Invalidate by VA, EL2
2890      * Currently handles both VAE2 and VALE2, since we don't support
2891      * flush-last-level-only.
2892      */
2893     ARMCPU *cpu = arm_env_get_cpu(env);
2894     CPUState *cs = CPU(cpu);
2895     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2896
2897     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2898 }
2899
2900 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2901                                  uint64_t value)
2902 {
2903     /* Invalidate by VA, EL3
2904      * Currently handles both VAE3 and VALE3, since we don't support
2905      * flush-last-level-only.
2906      */
2907     ARMCPU *cpu = arm_env_get_cpu(env);
2908     CPUState *cs = CPU(cpu);
2909     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2910
2911     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2912 }
2913
2914 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2915                                    uint64_t value)
2916 {
2917     bool sec = arm_is_secure_below_el3(env);
2918     CPUState *other_cs;
2919     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2920
2921     CPU_FOREACH(other_cs) {
2922         if (sec) {
2923             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2924                                      ARMMMUIdx_S1SE0, -1);
2925         } else {
2926             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2927                                      ARMMMUIdx_S12NSE0, -1);
2928         }
2929     }
2930 }
2931
2932 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2933                                    uint64_t value)
2934 {
2935     CPUState *other_cs;
2936     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2937
2938     CPU_FOREACH(other_cs) {
2939         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2940     }
2941 }
2942
2943 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2944                                    uint64_t value)
2945 {
2946     CPUState *other_cs;
2947     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2948
2949     CPU_FOREACH(other_cs) {
2950         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2951     }
2952 }
2953
2954 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2955                                     uint64_t value)
2956 {
2957     /* Invalidate by IPA. This has to invalidate any structures that
2958      * contain only stage 2 translation information, but does not need
2959      * to apply to structures that contain combined stage 1 and stage 2
2960      * translation information.
2961      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2962      */
2963     ARMCPU *cpu = arm_env_get_cpu(env);
2964     CPUState *cs = CPU(cpu);
2965     uint64_t pageaddr;
2966
2967     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2968         return;
2969     }
2970
2971     pageaddr = sextract64(value << 12, 0, 48);
2972
2973     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2974 }
2975
2976 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2977                                       uint64_t value)
2978 {
2979     CPUState *other_cs;
2980     uint64_t pageaddr;
2981
2982     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2983         return;
2984     }
2985
2986     pageaddr = sextract64(value << 12, 0, 48);
2987
2988     CPU_FOREACH(other_cs) {
2989         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2990     }
2991 }
2992
2993 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
2994                                       bool isread)
2995 {
2996     /* We don't implement EL2, so the only control on DC ZVA is the
2997      * bit in the SCTLR which can prohibit access for EL0.
2998      */
2999     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
3000         return CP_ACCESS_TRAP;
3001     }
3002     return CP_ACCESS_OK;
3003 }
3004
3005 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3006 {
3007     ARMCPU *cpu = arm_env_get_cpu(env);
3008     int dzp_bit = 1 << 4;
3009
3010     /* DZP indicates whether DC ZVA access is allowed */
3011     if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
3012         dzp_bit = 0;
3013     }
3014     return cpu->dcz_blocksize | dzp_bit;
3015 }
3016
3017 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3018                                     bool isread)
3019 {
3020     if (!(env->pstate & PSTATE_SP)) {
3021         /* Access to SP_EL0 is undefined if it's being used as
3022          * the stack pointer.
3023          */
3024         return CP_ACCESS_TRAP_UNCATEGORIZED;
3025     }
3026     return CP_ACCESS_OK;
3027 }
3028
3029 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3030 {
3031     return env->pstate & PSTATE_SP;
3032 }
3033
3034 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3035 {
3036     update_spsel(env, val);
3037 }
3038
3039 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3040                         uint64_t value)
3041 {
3042     ARMCPU *cpu = arm_env_get_cpu(env);
3043
3044     if (raw_read(env, ri) == value) {
3045         /* Skip the TLB flush if nothing actually changed; Linux likes
3046          * to do a lot of pointless SCTLR writes.
3047          */
3048         return;
3049     }
3050
3051     raw_write(env, ri, value);
3052     /* ??? Lots of these bits are not implemented.  */
3053     /* This may enable/disable the MMU, so do a TLB flush.  */
3054     tlb_flush(CPU(cpu), 1);
3055 }
3056
3057 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
3058                                      bool isread)
3059 {
3060     if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
3061         return CP_ACCESS_TRAP_FP_EL2;
3062     }
3063     if (env->cp15.cptr_el[3] & CPTR_TFP) {
3064         return CP_ACCESS_TRAP_FP_EL3;
3065     }
3066     return CP_ACCESS_OK;
3067 }
3068
3069 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3070                        uint64_t value)
3071 {
3072     env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
3073 }
3074
3075 static const ARMCPRegInfo v8_cp_reginfo[] = {
3076     /* Minimal set of EL0-visible registers. This will need to be expanded
3077      * significantly for system emulation of AArch64 CPUs.
3078      */
3079     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
3080       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
3081       .access = PL0_RW, .type = ARM_CP_NZCV },
3082     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
3083       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
3084       .type = ARM_CP_NO_RAW,
3085       .access = PL0_RW, .accessfn = aa64_daif_access,
3086       .fieldoffset = offsetof(CPUARMState, daif),
3087       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
3088     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
3089       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
3090       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
3091     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
3092       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
3093       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
3094     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
3095       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
3096       .access = PL0_R, .type = ARM_CP_NO_RAW,
3097       .readfn = aa64_dczid_read },
3098     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
3099       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
3100       .access = PL0_W, .type = ARM_CP_DC_ZVA,
3101 #ifndef CONFIG_USER_ONLY
3102       /* Avoid overhead of an access check that always passes in user-mode */
3103       .accessfn = aa64_zva_access,
3104 #endif
3105     },
3106     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
3107       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
3108       .access = PL1_R, .type = ARM_CP_CURRENTEL },
3109     /* Cache ops: all NOPs since we don't emulate caches */
3110     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
3111       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3112       .access = PL1_W, .type = ARM_CP_NOP },
3113     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
3114       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3115       .access = PL1_W, .type = ARM_CP_NOP },
3116     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
3117       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
3118       .access = PL0_W, .type = ARM_CP_NOP,
3119       .accessfn = aa64_cacheop_access },
3120     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
3121       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3122       .access = PL1_W, .type = ARM_CP_NOP },
3123     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
3124       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3125       .access = PL1_W, .type = ARM_CP_NOP },
3126     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
3127       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
3128       .access = PL0_W, .type = ARM_CP_NOP,
3129       .accessfn = aa64_cacheop_access },
3130     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3131       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3132       .access = PL1_W, .type = ARM_CP_NOP },
3133     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3134       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3135       .access = PL0_W, .type = ARM_CP_NOP,
3136       .accessfn = aa64_cacheop_access },
3137     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3138       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3139       .access = PL0_W, .type = ARM_CP_NOP,
3140       .accessfn = aa64_cacheop_access },
3141     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3142       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3143       .access = PL1_W, .type = ARM_CP_NOP },
3144     /* TLBI operations */
3145     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3146       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3147       .access = PL1_W, .type = ARM_CP_NO_RAW,
3148       .writefn = tlbi_aa64_vmalle1is_write },
3149     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3150       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3151       .access = PL1_W, .type = ARM_CP_NO_RAW,
3152       .writefn = tlbi_aa64_vae1is_write },
3153     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3154       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3155       .access = PL1_W, .type = ARM_CP_NO_RAW,
3156       .writefn = tlbi_aa64_vmalle1is_write },
3157     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3158       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3159       .access = PL1_W, .type = ARM_CP_NO_RAW,
3160       .writefn = tlbi_aa64_vae1is_write },
3161     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3162       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3163       .access = PL1_W, .type = ARM_CP_NO_RAW,
3164       .writefn = tlbi_aa64_vae1is_write },
3165     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3166       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3167       .access = PL1_W, .type = ARM_CP_NO_RAW,
3168       .writefn = tlbi_aa64_vae1is_write },
3169     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3170       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3171       .access = PL1_W, .type = ARM_CP_NO_RAW,
3172       .writefn = tlbi_aa64_vmalle1_write },
3173     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3174       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3175       .access = PL1_W, .type = ARM_CP_NO_RAW,
3176       .writefn = tlbi_aa64_vae1_write },
3177     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3178       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3179       .access = PL1_W, .type = ARM_CP_NO_RAW,
3180       .writefn = tlbi_aa64_vmalle1_write },
3181     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3182       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3183       .access = PL1_W, .type = ARM_CP_NO_RAW,
3184       .writefn = tlbi_aa64_vae1_write },
3185     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3186       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3187       .access = PL1_W, .type = ARM_CP_NO_RAW,
3188       .writefn = tlbi_aa64_vae1_write },
3189     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3190       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3191       .access = PL1_W, .type = ARM_CP_NO_RAW,
3192       .writefn = tlbi_aa64_vae1_write },
3193     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3194       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3195       .access = PL2_W, .type = ARM_CP_NO_RAW,
3196       .writefn = tlbi_aa64_ipas2e1is_write },
3197     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3198       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3199       .access = PL2_W, .type = ARM_CP_NO_RAW,
3200       .writefn = tlbi_aa64_ipas2e1is_write },
3201     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3202       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3203       .access = PL2_W, .type = ARM_CP_NO_RAW,
3204       .writefn = tlbi_aa64_alle1is_write },
3205     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3206       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3207       .access = PL2_W, .type = ARM_CP_NO_RAW,
3208       .writefn = tlbi_aa64_alle1is_write },
3209     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3210       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3211       .access = PL2_W, .type = ARM_CP_NO_RAW,
3212       .writefn = tlbi_aa64_ipas2e1_write },
3213     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3214       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3215       .access = PL2_W, .type = ARM_CP_NO_RAW,
3216       .writefn = tlbi_aa64_ipas2e1_write },
3217     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3218       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3219       .access = PL2_W, .type = ARM_CP_NO_RAW,
3220       .writefn = tlbi_aa64_alle1_write },
3221     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3222       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3223       .access = PL2_W, .type = ARM_CP_NO_RAW,
3224       .writefn = tlbi_aa64_alle1is_write },
3225 #ifndef CONFIG_USER_ONLY
3226     /* 64 bit address translation operations */
3227     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3228       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3229       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3230     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3231       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3232       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3233     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3234       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3235       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3236     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3237       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3238       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3239     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3240       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3241       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3242     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3243       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3244       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3245     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3246       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3247       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3248     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3249       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3250       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3251     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3252     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3253       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3254       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3255     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3256       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3257       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3258     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3259       .type = ARM_CP_ALIAS,
3260       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3261       .access = PL1_RW, .resetvalue = 0,
3262       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3263       .writefn = par_write },
3264 #endif
3265     /* TLB invalidate last level of translation table walk */
3266     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3267       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3268     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3269       .type = ARM_CP_NO_RAW, .access = PL1_W,
3270       .writefn = tlbimvaa_is_write },
3271     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3272       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3273     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3274       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3275     /* 32 bit cache operations */
3276     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3277       .type = ARM_CP_NOP, .access = PL1_W },
3278     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3279       .type = ARM_CP_NOP, .access = PL1_W },
3280     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3281       .type = ARM_CP_NOP, .access = PL1_W },
3282     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3283       .type = ARM_CP_NOP, .access = PL1_W },
3284     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3285       .type = ARM_CP_NOP, .access = PL1_W },
3286     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3287       .type = ARM_CP_NOP, .access = PL1_W },
3288     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3289       .type = ARM_CP_NOP, .access = PL1_W },
3290     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3291       .type = ARM_CP_NOP, .access = PL1_W },
3292     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3293       .type = ARM_CP_NOP, .access = PL1_W },
3294     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3295       .type = ARM_CP_NOP, .access = PL1_W },
3296     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3297       .type = ARM_CP_NOP, .access = PL1_W },
3298     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3299       .type = ARM_CP_NOP, .access = PL1_W },
3300     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3301       .type = ARM_CP_NOP, .access = PL1_W },
3302     /* MMU Domain access control / MPU write buffer control */
3303     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3304       .access = PL1_RW, .resetvalue = 0,
3305       .writefn = dacr_write, .raw_writefn = raw_write,
3306       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3307                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3308     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3309       .type = ARM_CP_ALIAS,
3310       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3311       .access = PL1_RW,
3312       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3313     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3314       .type = ARM_CP_ALIAS,
3315       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3316       .access = PL1_RW,
3317       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3318     /* We rely on the access checks not allowing the guest to write to the
3319      * state field when SPSel indicates that it's being used as the stack
3320      * pointer.
3321      */
3322     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3323       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3324       .access = PL1_RW, .accessfn = sp_el0_access,
3325       .type = ARM_CP_ALIAS,
3326       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3327     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3328       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3329       .access = PL2_RW, .type = ARM_CP_ALIAS,
3330       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3331     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3332       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3333       .type = ARM_CP_NO_RAW,
3334       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3335     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3336       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3337       .type = ARM_CP_ALIAS,
3338       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3339       .access = PL2_RW, .accessfn = fpexc32_access },
3340     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3341       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3342       .access = PL2_RW, .resetvalue = 0,
3343       .writefn = dacr_write, .raw_writefn = raw_write,
3344       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3345     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3346       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3347       .access = PL2_RW, .resetvalue = 0,
3348       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3349     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3350       .type = ARM_CP_ALIAS,
3351       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3352       .access = PL2_RW,
3353       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3354     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3355       .type = ARM_CP_ALIAS,
3356       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3357       .access = PL2_RW,
3358       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3359     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3360       .type = ARM_CP_ALIAS,
3361       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3362       .access = PL2_RW,
3363       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3364     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3365       .type = ARM_CP_ALIAS,
3366       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3367       .access = PL2_RW,
3368       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3369     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3370       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3371       .resetvalue = 0,
3372       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3373     { .name = "SDCR", .type = ARM_CP_ALIAS,
3374       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3375       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3376       .writefn = sdcr_write,
3377       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3378     REGINFO_SENTINEL
3379 };
3380
3381 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3382 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3383     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3384       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3385       .access = PL2_RW,
3386       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3387     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3388       .type = ARM_CP_NO_RAW,
3389       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3390       .access = PL2_RW,
3391       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3392     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3393       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3394       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3395     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3396       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3397       .access = PL2_RW, .type = ARM_CP_CONST,
3398       .resetvalue = 0 },
3399     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3400       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3401       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3402     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3403       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3404       .access = PL2_RW, .type = ARM_CP_CONST,
3405       .resetvalue = 0 },
3406     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3407       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3408       .access = PL2_RW, .type = ARM_CP_CONST,
3409       .resetvalue = 0 },
3410     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3411       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3412       .access = PL2_RW, .type = ARM_CP_CONST,
3413       .resetvalue = 0 },
3414     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3415       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3416       .access = PL2_RW, .type = ARM_CP_CONST,
3417       .resetvalue = 0 },
3418     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3419       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3420       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3421     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3422       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3423       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3424       .type = ARM_CP_CONST, .resetvalue = 0 },
3425     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3426       .cp = 15, .opc1 = 6, .crm = 2,
3427       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3428       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3429     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3430       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3431       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3432     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3433       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3434       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3435     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3436       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3437       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3438     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3439       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3440       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3441     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3442       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3443       .resetvalue = 0 },
3444     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3445       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3446       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3447     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3448       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3449       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3450     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3451       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3452       .resetvalue = 0 },
3453     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3454       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3455       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3456     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3457       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3458       .resetvalue = 0 },
3459     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3460       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3461       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3462     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3463       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3464       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3465     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3466       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3467       .access = PL2_RW, .accessfn = access_tda,
3468       .type = ARM_CP_CONST, .resetvalue = 0 },
3469     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3470       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3471       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3472       .type = ARM_CP_CONST, .resetvalue = 0 },
3473     REGINFO_SENTINEL
3474 };
3475
3476 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3477 {
3478     ARMCPU *cpu = arm_env_get_cpu(env);
3479     uint64_t valid_mask = HCR_MASK;
3480
3481     if (arm_feature(env, ARM_FEATURE_EL3)) {
3482         valid_mask &= ~HCR_HCD;
3483     } else {
3484         valid_mask &= ~HCR_TSC;
3485     }
3486
3487     /* Clear RES0 bits.  */
3488     value &= valid_mask;
3489
3490     /* These bits change the MMU setup:
3491      * HCR_VM enables stage 2 translation
3492      * HCR_PTW forbids certain page-table setups
3493      * HCR_DC Disables stage1 and enables stage2 translation
3494      */
3495     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3496         tlb_flush(CPU(cpu), 1);
3497     }
3498     raw_write(env, ri, value);
3499 }
3500
3501 static const ARMCPRegInfo el2_cp_reginfo[] = {
3502     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3503       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3504       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3505       .writefn = hcr_write },
3506     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3507       .type = ARM_CP_ALIAS,
3508       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3509       .access = PL2_RW,
3510       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3511     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3512       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3513       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3514     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3515       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3516       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3517     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3518       .type = ARM_CP_ALIAS,
3519       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3520       .access = PL2_RW,
3521       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3522     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3523       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3524       .access = PL2_RW, .writefn = vbar_write,
3525       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3526       .resetvalue = 0 },
3527     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3528       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3529       .access = PL3_RW, .type = ARM_CP_ALIAS,
3530       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3531     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3532       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3533       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3534       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3535     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3536       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3537       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3538       .resetvalue = 0 },
3539     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3540       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3541       .access = PL2_RW, .type = ARM_CP_ALIAS,
3542       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3543     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3544       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3545       .access = PL2_RW, .type = ARM_CP_CONST,
3546       .resetvalue = 0 },
3547     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3548     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3549       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3550       .access = PL2_RW, .type = ARM_CP_CONST,
3551       .resetvalue = 0 },
3552     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3553       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3554       .access = PL2_RW, .type = ARM_CP_CONST,
3555       .resetvalue = 0 },
3556     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3557       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3558       .access = PL2_RW, .type = ARM_CP_CONST,
3559       .resetvalue = 0 },
3560     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3561       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3562       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3563       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3564       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3565     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3566       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3567       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3568       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3569     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3570       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3571       .access = PL2_RW, .type = ARM_CP_ALIAS,
3572       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3573     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3574       .cp = 15, .opc1 = 6, .crm = 2,
3575       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3576       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3577       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3578       .writefn = vttbr_write },
3579     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3580       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3581       .access = PL2_RW, .writefn = vttbr_write,
3582       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3583     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3584       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3585       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3586       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3587     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3588       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3589       .access = PL2_RW, .resetvalue = 0,
3590       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3591     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3592       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3593       .access = PL2_RW, .resetvalue = 0,
3594       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3595     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3596       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3597       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3598     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3599       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3600       .type = ARM_CP_NO_RAW, .access = PL2_W,
3601       .writefn = tlbi_aa64_alle2_write },
3602     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3603       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3604       .type = ARM_CP_NO_RAW, .access = PL2_W,
3605       .writefn = tlbi_aa64_vae2_write },
3606     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3607       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3608       .access = PL2_W, .type = ARM_CP_NO_RAW,
3609       .writefn = tlbi_aa64_vae2_write },
3610     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3611       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3612       .access = PL2_W, .type = ARM_CP_NO_RAW,
3613       .writefn = tlbi_aa64_alle2is_write },
3614     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3615       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3616       .type = ARM_CP_NO_RAW, .access = PL2_W,
3617       .writefn = tlbi_aa64_vae2is_write },
3618     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3619       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3620       .access = PL2_W, .type = ARM_CP_NO_RAW,
3621       .writefn = tlbi_aa64_vae2is_write },
3622 #ifndef CONFIG_USER_ONLY
3623     /* Unlike the other EL2-related AT operations, these must
3624      * UNDEF from EL3 if EL2 is not implemented, which is why we
3625      * define them here rather than with the rest of the AT ops.
3626      */
3627     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3628       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3629       .access = PL2_W, .accessfn = at_s1e2_access,
3630       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3631     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3632       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3633       .access = PL2_W, .accessfn = at_s1e2_access,
3634       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3635     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3636      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3637      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3638      * to behave as if SCR.NS was 1.
3639      */
3640     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3641       .access = PL2_W,
3642       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3643     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3644       .access = PL2_W,
3645       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3646     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3647       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3648       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3649        * reset values as IMPDEF. We choose to reset to 3 to comply with
3650        * both ARMv7 and ARMv8.
3651        */
3652       .access = PL2_RW, .resetvalue = 3,
3653       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3654     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3655       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3656       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3657       .writefn = gt_cntvoff_write,
3658       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3659     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3660       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3661       .writefn = gt_cntvoff_write,
3662       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3663     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3664       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3665       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3666       .type = ARM_CP_IO, .access = PL2_RW,
3667       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3668     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3669       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3670       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3671       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3672     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3673       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3674       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
3675       .resetfn = gt_hyp_timer_reset,
3676       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3677     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3678       .type = ARM_CP_IO,
3679       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3680       .access = PL2_RW,
3681       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3682       .resetvalue = 0,
3683       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3684 #endif
3685     /* The only field of MDCR_EL2 that has a defined architectural reset value
3686      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3687      * don't impelment any PMU event counters, so using zero as a reset
3688      * value for MDCR_EL2 is okay
3689      */
3690     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3691       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3692       .access = PL2_RW, .resetvalue = 0,
3693       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3694     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3695       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3696       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3697       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3698     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3699       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3700       .access = PL2_RW,
3701       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3702     REGINFO_SENTINEL
3703 };
3704
3705 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
3706                                    bool isread)
3707 {
3708     /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3709      * At Secure EL1 it traps to EL3.
3710      */
3711     if (arm_current_el(env) == 3) {
3712         return CP_ACCESS_OK;
3713     }
3714     if (arm_is_secure_below_el3(env)) {
3715         return CP_ACCESS_TRAP_EL3;
3716     }
3717     /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3718     if (isread) {
3719         return CP_ACCESS_OK;
3720     }
3721     return CP_ACCESS_TRAP_UNCATEGORIZED;
3722 }
3723
3724 static const ARMCPRegInfo el3_cp_reginfo[] = {
3725     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3726       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3727       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3728       .resetvalue = 0, .writefn = scr_write },
3729     { .name = "SCR",  .type = ARM_CP_ALIAS,
3730       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3731       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3732       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3733       .writefn = scr_write },
3734     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3735       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3736       .access = PL3_RW, .resetvalue = 0,
3737       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3738     { .name = "SDER",
3739       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3740       .access = PL3_RW, .resetvalue = 0,
3741       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3742     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3743       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3744       .writefn = vbar_write, .resetvalue = 0,
3745       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3746     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3747       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3748       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3749       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3750     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3751       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3752       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3753       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3754       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3755     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3756       .type = ARM_CP_ALIAS,
3757       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3758       .access = PL3_RW,
3759       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3760     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3761       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3762       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3763     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3764       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3765       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3766     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3767       .type = ARM_CP_ALIAS,
3768       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3769       .access = PL3_RW,
3770       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3771     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3772       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3773       .access = PL3_RW, .writefn = vbar_write,
3774       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3775       .resetvalue = 0 },
3776     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3777       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3778       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3779       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3780     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3781       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3782       .access = PL3_RW, .resetvalue = 0,
3783       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3784     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3785       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3786       .access = PL3_RW, .type = ARM_CP_CONST,
3787       .resetvalue = 0 },
3788     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3789       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3790       .access = PL3_RW, .type = ARM_CP_CONST,
3791       .resetvalue = 0 },
3792     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3793       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3794       .access = PL3_RW, .type = ARM_CP_CONST,
3795       .resetvalue = 0 },
3796     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3797       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3798       .access = PL3_W, .type = ARM_CP_NO_RAW,
3799       .writefn = tlbi_aa64_alle3is_write },
3800     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3801       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3802       .access = PL3_W, .type = ARM_CP_NO_RAW,
3803       .writefn = tlbi_aa64_vae3is_write },
3804     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3805       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3806       .access = PL3_W, .type = ARM_CP_NO_RAW,
3807       .writefn = tlbi_aa64_vae3is_write },
3808     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3809       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3810       .access = PL3_W, .type = ARM_CP_NO_RAW,
3811       .writefn = tlbi_aa64_alle3_write },
3812     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3813       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3814       .access = PL3_W, .type = ARM_CP_NO_RAW,
3815       .writefn = tlbi_aa64_vae3_write },
3816     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3817       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3818       .access = PL3_W, .type = ARM_CP_NO_RAW,
3819       .writefn = tlbi_aa64_vae3_write },
3820     REGINFO_SENTINEL
3821 };
3822
3823 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3824                                      bool isread)
3825 {
3826     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3827      * but the AArch32 CTR has its own reginfo struct)
3828      */
3829     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3830         return CP_ACCESS_TRAP;
3831     }
3832     return CP_ACCESS_OK;
3833 }
3834
3835 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3836                         uint64_t value)
3837 {
3838     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3839      * read via a bit in OSLSR_EL1.
3840      */
3841     int oslock;
3842
3843     if (ri->state == ARM_CP_STATE_AA32) {
3844         oslock = (value == 0xC5ACCE55);
3845     } else {
3846         oslock = value & 1;
3847     }
3848
3849     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3850 }
3851
3852 static const ARMCPRegInfo debug_cp_reginfo[] = {
3853     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3854      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3855      * unlike DBGDRAR it is never accessible from EL0.
3856      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3857      * accessor.
3858      */
3859     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3860       .access = PL0_R, .accessfn = access_tdra,
3861       .type = ARM_CP_CONST, .resetvalue = 0 },
3862     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3863       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3864       .access = PL1_R, .accessfn = access_tdra,
3865       .type = ARM_CP_CONST, .resetvalue = 0 },
3866     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3867       .access = PL0_R, .accessfn = access_tdra,
3868       .type = ARM_CP_CONST, .resetvalue = 0 },
3869     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3870     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3871       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3872       .access = PL1_RW, .accessfn = access_tda,
3873       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3874       .resetvalue = 0 },
3875     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3876      * We don't implement the configurable EL0 access.
3877      */
3878     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3879       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3880       .type = ARM_CP_ALIAS,
3881       .access = PL1_R, .accessfn = access_tda,
3882       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3883     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3884       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3885       .access = PL1_W, .type = ARM_CP_NO_RAW,
3886       .accessfn = access_tdosa,
3887       .writefn = oslar_write },
3888     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3889       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3890       .access = PL1_R, .resetvalue = 10,
3891       .accessfn = access_tdosa,
3892       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3893     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3894     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3895       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3896       .access = PL1_RW, .accessfn = access_tdosa,
3897       .type = ARM_CP_NOP },
3898     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3899      * implement vector catch debug events yet.
3900      */
3901     { .name = "DBGVCR",
3902       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3903       .access = PL1_RW, .accessfn = access_tda,
3904       .type = ARM_CP_NOP },
3905     REGINFO_SENTINEL
3906 };
3907
3908 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3909     /* 64 bit access versions of the (dummy) debug registers */
3910     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3911       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3912     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3913       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3914     REGINFO_SENTINEL
3915 };
3916
3917 void hw_watchpoint_update(ARMCPU *cpu, int n)
3918 {
3919     CPUARMState *env = &cpu->env;
3920     vaddr len = 0;
3921     vaddr wvr = env->cp15.dbgwvr[n];
3922     uint64_t wcr = env->cp15.dbgwcr[n];
3923     int mask;
3924     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3925
3926     if (env->cpu_watchpoint[n]) {
3927         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3928         env->cpu_watchpoint[n] = NULL;
3929     }
3930
3931     if (!extract64(wcr, 0, 1)) {
3932         /* E bit clear : watchpoint disabled */
3933         return;
3934     }
3935
3936     switch (extract64(wcr, 3, 2)) {
3937     case 0:
3938         /* LSC 00 is reserved and must behave as if the wp is disabled */
3939         return;
3940     case 1:
3941         flags |= BP_MEM_READ;
3942         break;
3943     case 2:
3944         flags |= BP_MEM_WRITE;
3945         break;
3946     case 3:
3947         flags |= BP_MEM_ACCESS;
3948         break;
3949     }
3950
3951     /* Attempts to use both MASK and BAS fields simultaneously are
3952      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3953      * thus generating a watchpoint for every byte in the masked region.
3954      */
3955     mask = extract64(wcr, 24, 4);
3956     if (mask == 1 || mask == 2) {
3957         /* Reserved values of MASK; we must act as if the mask value was
3958          * some non-reserved value, or as if the watchpoint were disabled.
3959          * We choose the latter.
3960          */
3961         return;
3962     } else if (mask) {
3963         /* Watchpoint covers an aligned area up to 2GB in size */
3964         len = 1ULL << mask;
3965         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3966          * whether the watchpoint fires when the unmasked bits match; we opt
3967          * to generate the exceptions.
3968          */
3969         wvr &= ~(len - 1);
3970     } else {
3971         /* Watchpoint covers bytes defined by the byte address select bits */
3972         int bas = extract64(wcr, 5, 8);
3973         int basstart;
3974
3975         if (bas == 0) {
3976             /* This must act as if the watchpoint is disabled */
3977             return;
3978         }
3979
3980         if (extract64(wvr, 2, 1)) {
3981             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3982              * ignored, and BAS[3:0] define which bytes to watch.
3983              */
3984             bas &= 0xf;
3985         }
3986         /* The BAS bits are supposed to be programmed to indicate a contiguous
3987          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3988          * we fire for each byte in the word/doubleword addressed by the WVR.
3989          * We choose to ignore any non-zero bits after the first range of 1s.
3990          */
3991         basstart = ctz32(bas);
3992         len = cto32(bas >> basstart);
3993         wvr += basstart;
3994     }
3995
3996     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3997                           &env->cpu_watchpoint[n]);
3998 }
3999
4000 void hw_watchpoint_update_all(ARMCPU *cpu)
4001 {
4002     int i;
4003     CPUARMState *env = &cpu->env;
4004
4005     /* Completely clear out existing QEMU watchpoints and our array, to
4006      * avoid possible stale entries following migration load.
4007      */
4008     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
4009     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
4010
4011     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
4012         hw_watchpoint_update(cpu, i);
4013     }
4014 }
4015
4016 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4017                          uint64_t value)
4018 {
4019     ARMCPU *cpu = arm_env_get_cpu(env);
4020     int i = ri->crm;
4021
4022     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4023      * register reads and behaves as if values written are sign extended.
4024      * Bits [1:0] are RES0.
4025      */
4026     value = sextract64(value, 0, 49) & ~3ULL;
4027
4028     raw_write(env, ri, value);
4029     hw_watchpoint_update(cpu, i);
4030 }
4031
4032 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4033                          uint64_t value)
4034 {
4035     ARMCPU *cpu = arm_env_get_cpu(env);
4036     int i = ri->crm;
4037
4038     raw_write(env, ri, value);
4039     hw_watchpoint_update(cpu, i);
4040 }
4041
4042 void hw_breakpoint_update(ARMCPU *cpu, int n)
4043 {
4044     CPUARMState *env = &cpu->env;
4045     uint64_t bvr = env->cp15.dbgbvr[n];
4046     uint64_t bcr = env->cp15.dbgbcr[n];
4047     vaddr addr;
4048     int bt;
4049     int flags = BP_CPU;
4050
4051     if (env->cpu_breakpoint[n]) {
4052         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
4053         env->cpu_breakpoint[n] = NULL;
4054     }
4055
4056     if (!extract64(bcr, 0, 1)) {
4057         /* E bit clear : watchpoint disabled */
4058         return;
4059     }
4060
4061     bt = extract64(bcr, 20, 4);
4062
4063     switch (bt) {
4064     case 4: /* unlinked address mismatch (reserved if AArch64) */
4065     case 5: /* linked address mismatch (reserved if AArch64) */
4066         qemu_log_mask(LOG_UNIMP,
4067                       "arm: address mismatch breakpoint types not implemented");
4068         return;
4069     case 0: /* unlinked address match */
4070     case 1: /* linked address match */
4071     {
4072         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4073          * we behave as if the register was sign extended. Bits [1:0] are
4074          * RES0. The BAS field is used to allow setting breakpoints on 16
4075          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4076          * a bp will fire if the addresses covered by the bp and the addresses
4077          * covered by the insn overlap but the insn doesn't start at the
4078          * start of the bp address range. We choose to require the insn and
4079          * the bp to have the same address. The constraints on writing to
4080          * BAS enforced in dbgbcr_write mean we have only four cases:
4081          *  0b0000  => no breakpoint
4082          *  0b0011  => breakpoint on addr
4083          *  0b1100  => breakpoint on addr + 2
4084          *  0b1111  => breakpoint on addr
4085          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4086          */
4087         int bas = extract64(bcr, 5, 4);
4088         addr = sextract64(bvr, 0, 49) & ~3ULL;
4089         if (bas == 0) {
4090             return;
4091         }
4092         if (bas == 0xc) {
4093             addr += 2;
4094         }
4095         break;
4096     }
4097     case 2: /* unlinked context ID match */
4098     case 8: /* unlinked VMID match (reserved if no EL2) */
4099     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4100         qemu_log_mask(LOG_UNIMP,
4101                       "arm: unlinked context breakpoint types not implemented");
4102         return;
4103     case 9: /* linked VMID match (reserved if no EL2) */
4104     case 11: /* linked context ID and VMID match (reserved if no EL2) */
4105     case 3: /* linked context ID match */
4106     default:
4107         /* We must generate no events for Linked context matches (unless
4108          * they are linked to by some other bp/wp, which is handled in
4109          * updates for the linking bp/wp). We choose to also generate no events
4110          * for reserved values.
4111          */
4112         return;
4113     }
4114
4115     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
4116 }
4117
4118 void hw_breakpoint_update_all(ARMCPU *cpu)
4119 {
4120     int i;
4121     CPUARMState *env = &cpu->env;
4122
4123     /* Completely clear out existing QEMU breakpoints and our array, to
4124      * avoid possible stale entries following migration load.
4125      */
4126     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
4127     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
4128
4129     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
4130         hw_breakpoint_update(cpu, i);
4131     }
4132 }
4133
4134 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4135                          uint64_t value)
4136 {
4137     ARMCPU *cpu = arm_env_get_cpu(env);
4138     int i = ri->crm;
4139
4140     raw_write(env, ri, value);
4141     hw_breakpoint_update(cpu, i);
4142 }
4143
4144 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4145                          uint64_t value)
4146 {
4147     ARMCPU *cpu = arm_env_get_cpu(env);
4148     int i = ri->crm;
4149
4150     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4151      * copy of BAS[0].
4152      */
4153     value = deposit64(value, 6, 1, extract64(value, 5, 1));
4154     value = deposit64(value, 8, 1, extract64(value, 7, 1));
4155
4156     raw_write(env, ri, value);
4157     hw_breakpoint_update(cpu, i);
4158 }
4159
4160 static void define_debug_regs(ARMCPU *cpu)
4161 {
4162     /* Define v7 and v8 architectural debug registers.
4163      * These are just dummy implementations for now.
4164      */
4165     int i;
4166     int wrps, brps, ctx_cmps;
4167     ARMCPRegInfo dbgdidr = {
4168         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4169         .access = PL0_R, .accessfn = access_tda,
4170         .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4171     };
4172
4173     /* Note that all these register fields hold "number of Xs minus 1". */
4174     brps = extract32(cpu->dbgdidr, 24, 4);
4175     wrps = extract32(cpu->dbgdidr, 28, 4);
4176     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4177
4178     assert(ctx_cmps <= brps);
4179
4180     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4181      * of the debug registers such as number of breakpoints;
4182      * check that if they both exist then they agree.
4183      */
4184     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4185         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4186         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4187         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4188     }
4189
4190     define_one_arm_cp_reg(cpu, &dbgdidr);
4191     define_arm_cp_regs(cpu, debug_cp_reginfo);
4192
4193     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4194         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4195     }
4196
4197     for (i = 0; i < brps + 1; i++) {
4198         ARMCPRegInfo dbgregs[] = {
4199             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4200               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4201               .access = PL1_RW, .accessfn = access_tda,
4202               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4203               .writefn = dbgbvr_write, .raw_writefn = raw_write
4204             },
4205             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4206               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4207               .access = PL1_RW, .accessfn = access_tda,
4208               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4209               .writefn = dbgbcr_write, .raw_writefn = raw_write
4210             },
4211             REGINFO_SENTINEL
4212         };
4213         define_arm_cp_regs(cpu, dbgregs);
4214     }
4215
4216     for (i = 0; i < wrps + 1; i++) {
4217         ARMCPRegInfo dbgregs[] = {
4218             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4219               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4220               .access = PL1_RW, .accessfn = access_tda,
4221               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4222               .writefn = dbgwvr_write, .raw_writefn = raw_write
4223             },
4224             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4225               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4226               .access = PL1_RW, .accessfn = access_tda,
4227               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4228               .writefn = dbgwcr_write, .raw_writefn = raw_write
4229             },
4230             REGINFO_SENTINEL
4231         };
4232         define_arm_cp_regs(cpu, dbgregs);
4233     }
4234 }
4235
4236 void register_cp_regs_for_features(ARMCPU *cpu)
4237 {
4238     /* Register all the coprocessor registers based on feature bits */
4239     CPUARMState *env = &cpu->env;
4240     if (arm_feature(env, ARM_FEATURE_M)) {
4241         /* M profile has no coprocessor registers */
4242         return;
4243     }
4244
4245     define_arm_cp_regs(cpu, cp_reginfo);
4246     if (!arm_feature(env, ARM_FEATURE_V8)) {
4247         /* Must go early as it is full of wildcards that may be
4248          * overridden by later definitions.
4249          */
4250         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4251     }
4252
4253     if (arm_feature(env, ARM_FEATURE_V6)) {
4254         /* The ID registers all have impdef reset values */
4255         ARMCPRegInfo v6_idregs[] = {
4256             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4257               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4258               .access = PL1_R, .type = ARM_CP_CONST,
4259               .resetvalue = cpu->id_pfr0 },
4260             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4261               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4262               .access = PL1_R, .type = ARM_CP_CONST,
4263               .resetvalue = cpu->id_pfr1 },
4264             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4265               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4266               .access = PL1_R, .type = ARM_CP_CONST,
4267               .resetvalue = cpu->id_dfr0 },
4268             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4269               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4270               .access = PL1_R, .type = ARM_CP_CONST,
4271               .resetvalue = cpu->id_afr0 },
4272             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4273               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4274               .access = PL1_R, .type = ARM_CP_CONST,
4275               .resetvalue = cpu->id_mmfr0 },
4276             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4277               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4278               .access = PL1_R, .type = ARM_CP_CONST,
4279               .resetvalue = cpu->id_mmfr1 },
4280             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4281               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4282               .access = PL1_R, .type = ARM_CP_CONST,
4283               .resetvalue = cpu->id_mmfr2 },
4284             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4285               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4286               .access = PL1_R, .type = ARM_CP_CONST,
4287               .resetvalue = cpu->id_mmfr3 },
4288             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4289               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4290               .access = PL1_R, .type = ARM_CP_CONST,
4291               .resetvalue = cpu->id_isar0 },
4292             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4293               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4294               .access = PL1_R, .type = ARM_CP_CONST,
4295               .resetvalue = cpu->id_isar1 },
4296             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4297               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4298               .access = PL1_R, .type = ARM_CP_CONST,
4299               .resetvalue = cpu->id_isar2 },
4300             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4301               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4302               .access = PL1_R, .type = ARM_CP_CONST,
4303               .resetvalue = cpu->id_isar3 },
4304             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4305               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4306               .access = PL1_R, .type = ARM_CP_CONST,
4307               .resetvalue = cpu->id_isar4 },
4308             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4309               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4310               .access = PL1_R, .type = ARM_CP_CONST,
4311               .resetvalue = cpu->id_isar5 },
4312             { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
4313               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
4314               .access = PL1_R, .type = ARM_CP_CONST,
4315               .resetvalue = cpu->id_mmfr4 },
4316             /* 7 is as yet unallocated and must RAZ */
4317             { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
4318               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
4319               .access = PL1_R, .type = ARM_CP_CONST,
4320               .resetvalue = 0 },
4321             REGINFO_SENTINEL
4322         };
4323         define_arm_cp_regs(cpu, v6_idregs);
4324         define_arm_cp_regs(cpu, v6_cp_reginfo);
4325     } else {
4326         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4327     }
4328     if (arm_feature(env, ARM_FEATURE_V6K)) {
4329         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4330     }
4331     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4332         !arm_feature(env, ARM_FEATURE_MPU)) {
4333         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4334     }
4335     if (arm_feature(env, ARM_FEATURE_V7)) {
4336         /* v7 performance monitor control register: same implementor
4337          * field as main ID register, and we implement only the cycle
4338          * count register.
4339          */
4340 #ifndef CONFIG_USER_ONLY
4341         ARMCPRegInfo pmcr = {
4342             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4343             .access = PL0_RW,
4344             .type = ARM_CP_IO | ARM_CP_ALIAS,
4345             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4346             .accessfn = pmreg_access, .writefn = pmcr_write,
4347             .raw_writefn = raw_write,
4348         };
4349         ARMCPRegInfo pmcr64 = {
4350             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4351             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4352             .access = PL0_RW, .accessfn = pmreg_access,
4353             .type = ARM_CP_IO,
4354             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4355             .resetvalue = cpu->midr & 0xff000000,
4356             .writefn = pmcr_write, .raw_writefn = raw_write,
4357         };
4358         define_one_arm_cp_reg(cpu, &pmcr);
4359         define_one_arm_cp_reg(cpu, &pmcr64);
4360 #endif
4361         ARMCPRegInfo clidr = {
4362             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4363             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4364             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4365         };
4366         define_one_arm_cp_reg(cpu, &clidr);
4367         define_arm_cp_regs(cpu, v7_cp_reginfo);
4368         define_debug_regs(cpu);
4369     } else {
4370         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4371     }
4372     if (arm_feature(env, ARM_FEATURE_V8)) {
4373         /* AArch64 ID registers, which all have impdef reset values.
4374          * Note that within the ID register ranges the unused slots
4375          * must all RAZ, not UNDEF; future architecture versions may
4376          * define new registers here.
4377          */
4378         ARMCPRegInfo v8_idregs[] = {
4379             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4380               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4381               .access = PL1_R, .type = ARM_CP_CONST,
4382               .resetvalue = cpu->id_aa64pfr0 },
4383             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4384               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4385               .access = PL1_R, .type = ARM_CP_CONST,
4386               .resetvalue = cpu->id_aa64pfr1},
4387             { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4388               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
4389               .access = PL1_R, .type = ARM_CP_CONST,
4390               .resetvalue = 0 },
4391             { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4392               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
4393               .access = PL1_R, .type = ARM_CP_CONST,
4394               .resetvalue = 0 },
4395             { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4396               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
4397               .access = PL1_R, .type = ARM_CP_CONST,
4398               .resetvalue = 0 },
4399             { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4400               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
4401               .access = PL1_R, .type = ARM_CP_CONST,
4402               .resetvalue = 0 },
4403             { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4404               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
4405               .access = PL1_R, .type = ARM_CP_CONST,
4406               .resetvalue = 0 },
4407             { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4408               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
4409               .access = PL1_R, .type = ARM_CP_CONST,
4410               .resetvalue = 0 },
4411             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4412               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4413               .access = PL1_R, .type = ARM_CP_CONST,
4414               /* We mask out the PMUVer field, because we don't currently
4415                * implement the PMU. Not advertising it prevents the guest
4416                * from trying to use it and getting UNDEFs on registers we
4417                * don't implement.
4418                */
4419               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4420             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4421               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4422               .access = PL1_R, .type = ARM_CP_CONST,
4423               .resetvalue = cpu->id_aa64dfr1 },
4424             { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4425               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
4426               .access = PL1_R, .type = ARM_CP_CONST,
4427               .resetvalue = 0 },
4428             { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4429               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
4430               .access = PL1_R, .type = ARM_CP_CONST,
4431               .resetvalue = 0 },
4432             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4433               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4434               .access = PL1_R, .type = ARM_CP_CONST,
4435               .resetvalue = cpu->id_aa64afr0 },
4436             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4437               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4438               .access = PL1_R, .type = ARM_CP_CONST,
4439               .resetvalue = cpu->id_aa64afr1 },
4440             { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4441               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
4442               .access = PL1_R, .type = ARM_CP_CONST,
4443               .resetvalue = 0 },
4444             { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4445               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
4446               .access = PL1_R, .type = ARM_CP_CONST,
4447               .resetvalue = 0 },
4448             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4449               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4450               .access = PL1_R, .type = ARM_CP_CONST,
4451               .resetvalue = cpu->id_aa64isar0 },
4452             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4453               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4454               .access = PL1_R, .type = ARM_CP_CONST,
4455               .resetvalue = cpu->id_aa64isar1 },
4456             { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4457               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
4458               .access = PL1_R, .type = ARM_CP_CONST,
4459               .resetvalue = 0 },
4460             { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4461               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
4462               .access = PL1_R, .type = ARM_CP_CONST,
4463               .resetvalue = 0 },
4464             { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4465               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
4466               .access = PL1_R, .type = ARM_CP_CONST,
4467               .resetvalue = 0 },
4468             { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4469               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
4470               .access = PL1_R, .type = ARM_CP_CONST,
4471               .resetvalue = 0 },
4472             { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4473               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
4474               .access = PL1_R, .type = ARM_CP_CONST,
4475               .resetvalue = 0 },
4476             { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4477               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
4478               .access = PL1_R, .type = ARM_CP_CONST,
4479               .resetvalue = 0 },
4480             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4481               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4482               .access = PL1_R, .type = ARM_CP_CONST,
4483               .resetvalue = cpu->id_aa64mmfr0 },
4484             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4485               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4486               .access = PL1_R, .type = ARM_CP_CONST,
4487               .resetvalue = cpu->id_aa64mmfr1 },
4488             { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4489               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
4490               .access = PL1_R, .type = ARM_CP_CONST,
4491               .resetvalue = 0 },
4492             { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4493               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
4494               .access = PL1_R, .type = ARM_CP_CONST,
4495               .resetvalue = 0 },
4496             { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4497               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
4498               .access = PL1_R, .type = ARM_CP_CONST,
4499               .resetvalue = 0 },
4500             { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4501               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
4502               .access = PL1_R, .type = ARM_CP_CONST,
4503               .resetvalue = 0 },
4504             { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4505               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
4506               .access = PL1_R, .type = ARM_CP_CONST,
4507               .resetvalue = 0 },
4508             { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4509               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
4510               .access = PL1_R, .type = ARM_CP_CONST,
4511               .resetvalue = 0 },
4512             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4513               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4514               .access = PL1_R, .type = ARM_CP_CONST,
4515               .resetvalue = cpu->mvfr0 },
4516             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4517               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4518               .access = PL1_R, .type = ARM_CP_CONST,
4519               .resetvalue = cpu->mvfr1 },
4520             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4521               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4522               .access = PL1_R, .type = ARM_CP_CONST,
4523               .resetvalue = cpu->mvfr2 },
4524             { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4525               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
4526               .access = PL1_R, .type = ARM_CP_CONST,
4527               .resetvalue = 0 },
4528             { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4529               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
4530               .access = PL1_R, .type = ARM_CP_CONST,
4531               .resetvalue = 0 },
4532             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4533               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
4534               .access = PL1_R, .type = ARM_CP_CONST,
4535               .resetvalue = 0 },
4536             { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4537               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
4538               .access = PL1_R, .type = ARM_CP_CONST,
4539               .resetvalue = 0 },
4540             { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4541               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
4542               .access = PL1_R, .type = ARM_CP_CONST,
4543               .resetvalue = 0 },
4544             { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
4545               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
4546               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4547               .resetvalue = cpu->pmceid0 },
4548             { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
4549               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
4550               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4551               .resetvalue = cpu->pmceid0 },
4552             { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
4553               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
4554               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4555               .resetvalue = cpu->pmceid1 },
4556             { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
4557               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
4558               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4559               .resetvalue = cpu->pmceid1 },
4560             REGINFO_SENTINEL
4561         };
4562         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4563         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4564             !arm_feature(env, ARM_FEATURE_EL2)) {
4565             ARMCPRegInfo rvbar = {
4566                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4567                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4568                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4569             };
4570             define_one_arm_cp_reg(cpu, &rvbar);
4571         }
4572         define_arm_cp_regs(cpu, v8_idregs);
4573         define_arm_cp_regs(cpu, v8_cp_reginfo);
4574     }
4575     if (arm_feature(env, ARM_FEATURE_EL2)) {
4576         uint64_t vmpidr_def = mpidr_read_val(env);
4577         ARMCPRegInfo vpidr_regs[] = {
4578             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4579               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4580               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4581               .resetvalue = cpu->midr,
4582               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4583             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4584               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4585               .access = PL2_RW, .resetvalue = cpu->midr,
4586               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4587             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4588               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4589               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4590               .resetvalue = vmpidr_def,
4591               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4592             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4593               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4594               .access = PL2_RW,
4595               .resetvalue = vmpidr_def,
4596               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4597             REGINFO_SENTINEL
4598         };
4599         define_arm_cp_regs(cpu, vpidr_regs);
4600         define_arm_cp_regs(cpu, el2_cp_reginfo);
4601         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4602         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4603             ARMCPRegInfo rvbar = {
4604                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4605                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4606                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4607             };
4608             define_one_arm_cp_reg(cpu, &rvbar);
4609         }
4610     } else {
4611         /* If EL2 is missing but higher ELs are enabled, we need to
4612          * register the no_el2 reginfos.
4613          */
4614         if (arm_feature(env, ARM_FEATURE_EL3)) {
4615             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4616              * of MIDR_EL1 and MPIDR_EL1.
4617              */
4618             ARMCPRegInfo vpidr_regs[] = {
4619                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4620                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4621                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4622                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4623                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4624                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4625                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4626                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4627                   .type = ARM_CP_NO_RAW,
4628                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4629                 REGINFO_SENTINEL
4630             };
4631             define_arm_cp_regs(cpu, vpidr_regs);
4632             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4633         }
4634     }
4635     if (arm_feature(env, ARM_FEATURE_EL3)) {
4636         define_arm_cp_regs(cpu, el3_cp_reginfo);
4637         ARMCPRegInfo el3_regs[] = {
4638             { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4639               .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4640               .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
4641             { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
4642               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
4643               .access = PL3_RW,
4644               .raw_writefn = raw_write, .writefn = sctlr_write,
4645               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
4646               .resetvalue = cpu->reset_sctlr },
4647             REGINFO_SENTINEL
4648         };
4649
4650         define_arm_cp_regs(cpu, el3_regs);
4651     }
4652     /* The behaviour of NSACR is sufficiently various that we don't
4653      * try to describe it in a single reginfo:
4654      *  if EL3 is 64 bit, then trap to EL3 from S EL1,
4655      *     reads as constant 0xc00 from NS EL1 and NS EL2
4656      *  if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4657      *  if v7 without EL3, register doesn't exist
4658      *  if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4659      */
4660     if (arm_feature(env, ARM_FEATURE_EL3)) {
4661         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4662             ARMCPRegInfo nsacr = {
4663                 .name = "NSACR", .type = ARM_CP_CONST,
4664                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4665                 .access = PL1_RW, .accessfn = nsacr_access,
4666                 .resetvalue = 0xc00
4667             };
4668             define_one_arm_cp_reg(cpu, &nsacr);
4669         } else {
4670             ARMCPRegInfo nsacr = {
4671                 .name = "NSACR",
4672                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4673                 .access = PL3_RW | PL1_R,
4674                 .resetvalue = 0,
4675                 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
4676             };
4677             define_one_arm_cp_reg(cpu, &nsacr);
4678         }
4679     } else {
4680         if (arm_feature(env, ARM_FEATURE_V8)) {
4681             ARMCPRegInfo nsacr = {
4682                 .name = "NSACR", .type = ARM_CP_CONST,
4683                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4684                 .access = PL1_R,
4685                 .resetvalue = 0xc00
4686             };
4687             define_one_arm_cp_reg(cpu, &nsacr);
4688         }
4689     }
4690
4691     if (arm_feature(env, ARM_FEATURE_MPU)) {
4692         if (arm_feature(env, ARM_FEATURE_V6)) {
4693             /* PMSAv6 not implemented */
4694             assert(arm_feature(env, ARM_FEATURE_V7));
4695             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4696             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4697         } else {
4698             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4699         }
4700     } else {
4701         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4702         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4703     }
4704     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4705         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4706     }
4707     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4708         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4709     }
4710     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4711         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4712     }
4713     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4714         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4715     }
4716     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4717         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4718     }
4719     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4720         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4721     }
4722     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4723         define_arm_cp_regs(cpu, omap_cp_reginfo);
4724     }
4725     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4726         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4727     }
4728     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4729         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4730     }
4731     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4732         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4733     }
4734     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4735         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4736     }
4737     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4738      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4739      * be read-only (ie write causes UNDEF exception).
4740      */
4741     {
4742         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4743             /* Pre-v8 MIDR space.
4744              * Note that the MIDR isn't a simple constant register because
4745              * of the TI925 behaviour where writes to another register can
4746              * cause the MIDR value to change.
4747              *
4748              * Unimplemented registers in the c15 0 0 0 space default to
4749              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4750              * and friends override accordingly.
4751              */
4752             { .name = "MIDR",
4753               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4754               .access = PL1_R, .resetvalue = cpu->midr,
4755               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4756               .readfn = midr_read,
4757               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4758               .type = ARM_CP_OVERRIDE },
4759             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4760             { .name = "DUMMY",
4761               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4762               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4763             { .name = "DUMMY",
4764               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4765               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4766             { .name = "DUMMY",
4767               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4768               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4769             { .name = "DUMMY",
4770               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4771               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4772             { .name = "DUMMY",
4773               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4774               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4775             REGINFO_SENTINEL
4776         };
4777         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4778             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4779               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4780               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4781               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4782               .readfn = midr_read },
4783             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4784             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4785               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4786               .access = PL1_R, .resetvalue = cpu->midr },
4787             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4788               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4789               .access = PL1_R, .resetvalue = cpu->midr },
4790             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4791               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4792               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4793             REGINFO_SENTINEL
4794         };
4795         ARMCPRegInfo id_cp_reginfo[] = {
4796             /* These are common to v8 and pre-v8 */
4797             { .name = "CTR",
4798               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4799               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4800             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4801               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4802               .access = PL0_R, .accessfn = ctr_el0_access,
4803               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4804             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4805             { .name = "TCMTR",
4806               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4807               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4808             REGINFO_SENTINEL
4809         };
4810         /* TLBTR is specific to VMSA */
4811         ARMCPRegInfo id_tlbtr_reginfo = {
4812               .name = "TLBTR",
4813               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4814               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4815         };
4816         /* MPUIR is specific to PMSA V6+ */
4817         ARMCPRegInfo id_mpuir_reginfo = {
4818               .name = "MPUIR",
4819               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4820               .access = PL1_R, .type = ARM_CP_CONST,
4821               .resetvalue = cpu->pmsav7_dregion << 8
4822         };
4823         ARMCPRegInfo crn0_wi_reginfo = {
4824             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4825             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4826             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4827         };
4828         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4829             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4830             ARMCPRegInfo *r;
4831             /* Register the blanket "writes ignored" value first to cover the
4832              * whole space. Then update the specific ID registers to allow write
4833              * access, so that they ignore writes rather than causing them to
4834              * UNDEF.
4835              */
4836             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4837             for (r = id_pre_v8_midr_cp_reginfo;
4838                  r->type != ARM_CP_SENTINEL; r++) {
4839                 r->access = PL1_RW;
4840             }
4841             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4842                 r->access = PL1_RW;
4843             }
4844             id_tlbtr_reginfo.access = PL1_RW;
4845             id_tlbtr_reginfo.access = PL1_RW;
4846         }
4847         if (arm_feature(env, ARM_FEATURE_V8)) {
4848             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4849         } else {
4850             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4851         }
4852         define_arm_cp_regs(cpu, id_cp_reginfo);
4853         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4854             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4855         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4856             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4857         }
4858     }
4859
4860     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4861         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4862     }
4863
4864     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4865         ARMCPRegInfo auxcr_reginfo[] = {
4866             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4867               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4868               .access = PL1_RW, .type = ARM_CP_CONST,
4869               .resetvalue = cpu->reset_auxcr },
4870             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4871               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4872               .access = PL2_RW, .type = ARM_CP_CONST,
4873               .resetvalue = 0 },
4874             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4875               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4876               .access = PL3_RW, .type = ARM_CP_CONST,
4877               .resetvalue = 0 },
4878             REGINFO_SENTINEL
4879         };
4880         define_arm_cp_regs(cpu, auxcr_reginfo);
4881     }
4882
4883     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4884         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4885             /* 32 bit view is [31:18] 0...0 [43:32]. */
4886             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4887                 | extract64(cpu->reset_cbar, 32, 12);
4888             ARMCPRegInfo cbar_reginfo[] = {
4889                 { .name = "CBAR",
4890                   .type = ARM_CP_CONST,
4891                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4892                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4893                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4894                   .type = ARM_CP_CONST,
4895                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4896                   .access = PL1_R, .resetvalue = cbar32 },
4897                 REGINFO_SENTINEL
4898             };
4899             /* We don't implement a r/w 64 bit CBAR currently */
4900             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4901             define_arm_cp_regs(cpu, cbar_reginfo);
4902         } else {
4903             ARMCPRegInfo cbar = {
4904                 .name = "CBAR",
4905                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4906                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4907                 .fieldoffset = offsetof(CPUARMState,
4908                                         cp15.c15_config_base_address)
4909             };
4910             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4911                 cbar.access = PL1_R;
4912                 cbar.fieldoffset = 0;
4913                 cbar.type = ARM_CP_CONST;
4914             }
4915             define_one_arm_cp_reg(cpu, &cbar);
4916         }
4917     }
4918
4919     /* Generic registers whose values depend on the implementation */
4920     {
4921         ARMCPRegInfo sctlr = {
4922             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4923             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4924             .access = PL1_RW,
4925             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4926                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4927             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4928             .raw_writefn = raw_write,
4929         };
4930         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4931             /* Normally we would always end the TB on an SCTLR write, but Linux
4932              * arch/arm/mach-pxa/sleep.S expects two instructions following
4933              * an MMU enable to execute from cache.  Imitate this behaviour.
4934              */
4935             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4936         }
4937         define_one_arm_cp_reg(cpu, &sctlr);
4938     }
4939 }
4940
4941 ARMCPU *cpu_arm_init(const char *cpu_model)
4942 {
4943     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4944 }
4945
4946 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4947 {
4948     CPUState *cs = CPU(cpu);
4949     CPUARMState *env = &cpu->env;
4950
4951     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4952         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4953                                  aarch64_fpu_gdb_set_reg,
4954                                  34, "aarch64-fpu.xml", 0);
4955     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4956         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4957                                  51, "arm-neon.xml", 0);
4958     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4959         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4960                                  35, "arm-vfp3.xml", 0);
4961     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4962         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4963                                  19, "arm-vfp.xml", 0);
4964     }
4965 }
4966
4967 /* Sort alphabetically by type name, except for "any". */
4968 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4969 {
4970     ObjectClass *class_a = (ObjectClass *)a;
4971     ObjectClass *class_b = (ObjectClass *)b;
4972     const char *name_a, *name_b;
4973
4974     name_a = object_class_get_name(class_a);
4975     name_b = object_class_get_name(class_b);
4976     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4977         return 1;
4978     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4979         return -1;
4980     } else {
4981         return strcmp(name_a, name_b);
4982     }
4983 }
4984
4985 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4986 {
4987     ObjectClass *oc = data;
4988     CPUListState *s = user_data;
4989     const char *typename;
4990     char *name;
4991
4992     typename = object_class_get_name(oc);
4993     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4994     (*s->cpu_fprintf)(s->file, "  %s\n",
4995                       name);
4996     g_free(name);
4997 }
4998
4999 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5000 {
5001     CPUListState s = {
5002         .file = f,
5003         .cpu_fprintf = cpu_fprintf,
5004     };
5005     GSList *list;
5006
5007     list = object_class_get_list(TYPE_ARM_CPU, false);
5008     list = g_slist_sort(list, arm_cpu_list_compare);
5009     (*cpu_fprintf)(f, "Available CPUs:\n");
5010     g_slist_foreach(list, arm_cpu_list_entry, &s);
5011     g_slist_free(list);
5012 #ifdef CONFIG_KVM
5013     /* The 'host' CPU type is dynamically registered only if KVM is
5014      * enabled, so we have to special-case it here:
5015      */
5016     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
5017 #endif
5018 }
5019
5020 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
5021 {
5022     ObjectClass *oc = data;
5023     CpuDefinitionInfoList **cpu_list = user_data;
5024     CpuDefinitionInfoList *entry;
5025     CpuDefinitionInfo *info;
5026     const char *typename;
5027
5028     typename = object_class_get_name(oc);
5029     info = g_malloc0(sizeof(*info));
5030     info->name = g_strndup(typename,
5031                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
5032
5033     entry = g_malloc0(sizeof(*entry));
5034     entry->value = info;
5035     entry->next = *cpu_list;
5036     *cpu_list = entry;
5037 }
5038
5039 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
5040 {
5041     CpuDefinitionInfoList *cpu_list = NULL;
5042     GSList *list;
5043
5044     list = object_class_get_list(TYPE_ARM_CPU, false);
5045     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
5046     g_slist_free(list);
5047
5048     return cpu_list;
5049 }
5050
5051 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
5052                                    void *opaque, int state, int secstate,
5053                                    int crm, int opc1, int opc2)
5054 {
5055     /* Private utility function for define_one_arm_cp_reg_with_opaque():
5056      * add a single reginfo struct to the hash table.
5057      */
5058     uint32_t *key = g_new(uint32_t, 1);
5059     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
5060     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
5061     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
5062
5063     /* Reset the secure state to the specific incoming state.  This is
5064      * necessary as the register may have been defined with both states.
5065      */
5066     r2->secure = secstate;
5067
5068     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5069         /* Register is banked (using both entries in array).
5070          * Overwriting fieldoffset as the array is only used to define
5071          * banked registers but later only fieldoffset is used.
5072          */
5073         r2->fieldoffset = r->bank_fieldoffsets[ns];
5074     }
5075
5076     if (state == ARM_CP_STATE_AA32) {
5077         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5078             /* If the register is banked then we don't need to migrate or
5079              * reset the 32-bit instance in certain cases:
5080              *
5081              * 1) If the register has both 32-bit and 64-bit instances then we
5082              *    can count on the 64-bit instance taking care of the
5083              *    non-secure bank.
5084              * 2) If ARMv8 is enabled then we can count on a 64-bit version
5085              *    taking care of the secure bank.  This requires that separate
5086              *    32 and 64-bit definitions are provided.
5087              */
5088             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
5089                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
5090                 r2->type |= ARM_CP_ALIAS;
5091             }
5092         } else if ((secstate != r->secure) && !ns) {
5093             /* The register is not banked so we only want to allow migration of
5094              * the non-secure instance.
5095              */
5096             r2->type |= ARM_CP_ALIAS;
5097         }
5098
5099         if (r->state == ARM_CP_STATE_BOTH) {
5100             /* We assume it is a cp15 register if the .cp field is left unset.
5101              */
5102             if (r2->cp == 0) {
5103                 r2->cp = 15;
5104             }
5105
5106 #ifdef HOST_WORDS_BIGENDIAN
5107             if (r2->fieldoffset) {
5108                 r2->fieldoffset += sizeof(uint32_t);
5109             }
5110 #endif
5111         }
5112     }
5113     if (state == ARM_CP_STATE_AA64) {
5114         /* To allow abbreviation of ARMCPRegInfo
5115          * definitions, we treat cp == 0 as equivalent to
5116          * the value for "standard guest-visible sysreg".
5117          * STATE_BOTH definitions are also always "standard
5118          * sysreg" in their AArch64 view (the .cp value may
5119          * be non-zero for the benefit of the AArch32 view).
5120          */
5121         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
5122             r2->cp = CP_REG_ARM64_SYSREG_CP;
5123         }
5124         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
5125                                   r2->opc0, opc1, opc2);
5126     } else {
5127         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
5128     }
5129     if (opaque) {
5130         r2->opaque = opaque;
5131     }
5132     /* reginfo passed to helpers is correct for the actual access,
5133      * and is never ARM_CP_STATE_BOTH:
5134      */
5135     r2->state = state;
5136     /* Make sure reginfo passed to helpers for wildcarded regs
5137      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5138      */
5139     r2->crm = crm;
5140     r2->opc1 = opc1;
5141     r2->opc2 = opc2;
5142     /* By convention, for wildcarded registers only the first
5143      * entry is used for migration; the others are marked as
5144      * ALIAS so we don't try to transfer the register
5145      * multiple times. Special registers (ie NOP/WFI) are
5146      * never migratable and not even raw-accessible.
5147      */
5148     if ((r->type & ARM_CP_SPECIAL)) {
5149         r2->type |= ARM_CP_NO_RAW;
5150     }
5151     if (((r->crm == CP_ANY) && crm != 0) ||
5152         ((r->opc1 == CP_ANY) && opc1 != 0) ||
5153         ((r->opc2 == CP_ANY) && opc2 != 0)) {
5154         r2->type |= ARM_CP_ALIAS;
5155     }
5156
5157     /* Check that raw accesses are either forbidden or handled. Note that
5158      * we can't assert this earlier because the setup of fieldoffset for
5159      * banked registers has to be done first.
5160      */
5161     if (!(r2->type & ARM_CP_NO_RAW)) {
5162         assert(!raw_accessors_invalid(r2));
5163     }
5164
5165     /* Overriding of an existing definition must be explicitly
5166      * requested.
5167      */
5168     if (!(r->type & ARM_CP_OVERRIDE)) {
5169         ARMCPRegInfo *oldreg;
5170         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
5171         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
5172             fprintf(stderr, "Register redefined: cp=%d %d bit "
5173                     "crn=%d crm=%d opc1=%d opc2=%d, "
5174                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
5175                     r2->crn, r2->crm, r2->opc1, r2->opc2,
5176                     oldreg->name, r2->name);
5177             g_assert_not_reached();
5178         }
5179     }
5180     g_hash_table_insert(cpu->cp_regs, key, r2);
5181 }
5182
5183
5184 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
5185                                        const ARMCPRegInfo *r, void *opaque)
5186 {
5187     /* Define implementations of coprocessor registers.
5188      * We store these in a hashtable because typically
5189      * there are less than 150 registers in a space which
5190      * is 16*16*16*8*8 = 262144 in size.
5191      * Wildcarding is supported for the crm, opc1 and opc2 fields.
5192      * If a register is defined twice then the second definition is
5193      * used, so this can be used to define some generic registers and
5194      * then override them with implementation specific variations.
5195      * At least one of the original and the second definition should
5196      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5197      * against accidental use.
5198      *
5199      * The state field defines whether the register is to be
5200      * visible in the AArch32 or AArch64 execution state. If the
5201      * state is set to ARM_CP_STATE_BOTH then we synthesise a
5202      * reginfo structure for the AArch32 view, which sees the lower
5203      * 32 bits of the 64 bit register.
5204      *
5205      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5206      * be wildcarded. AArch64 registers are always considered to be 64
5207      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5208      * the register, if any.
5209      */
5210     int crm, opc1, opc2, state;
5211     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
5212     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
5213     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
5214     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
5215     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
5216     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
5217     /* 64 bit registers have only CRm and Opc1 fields */
5218     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
5219     /* op0 only exists in the AArch64 encodings */
5220     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
5221     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5222     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
5223     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5224      * encodes a minimum access level for the register. We roll this
5225      * runtime check into our general permission check code, so check
5226      * here that the reginfo's specified permissions are strict enough
5227      * to encompass the generic architectural permission check.
5228      */
5229     if (r->state != ARM_CP_STATE_AA32) {
5230         int mask = 0;
5231         switch (r->opc1) {
5232         case 0: case 1: case 2:
5233             /* min_EL EL1 */
5234             mask = PL1_RW;
5235             break;
5236         case 3:
5237             /* min_EL EL0 */
5238             mask = PL0_RW;
5239             break;
5240         case 4:
5241             /* min_EL EL2 */
5242             mask = PL2_RW;
5243             break;
5244         case 5:
5245             /* unallocated encoding, so not possible */
5246             assert(false);
5247             break;
5248         case 6:
5249             /* min_EL EL3 */
5250             mask = PL3_RW;
5251             break;
5252         case 7:
5253             /* min_EL EL1, secure mode only (we don't check the latter) */
5254             mask = PL1_RW;
5255             break;
5256         default:
5257             /* broken reginfo with out-of-range opc1 */
5258             assert(false);
5259             break;
5260         }
5261         /* assert our permissions are not too lax (stricter is fine) */
5262         assert((r->access & ~mask) == 0);
5263     }
5264
5265     /* Check that the register definition has enough info to handle
5266      * reads and writes if they are permitted.
5267      */
5268     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
5269         if (r->access & PL3_R) {
5270             assert((r->fieldoffset ||
5271                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5272                    r->readfn);
5273         }
5274         if (r->access & PL3_W) {
5275             assert((r->fieldoffset ||
5276                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5277                    r->writefn);
5278         }
5279     }
5280     /* Bad type field probably means missing sentinel at end of reg list */
5281     assert(cptype_valid(r->type));
5282     for (crm = crmmin; crm <= crmmax; crm++) {
5283         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5284             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5285                 for (state = ARM_CP_STATE_AA32;
5286                      state <= ARM_CP_STATE_AA64; state++) {
5287                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5288                         continue;
5289                     }
5290                     if (state == ARM_CP_STATE_AA32) {
5291                         /* Under AArch32 CP registers can be common
5292                          * (same for secure and non-secure world) or banked.
5293                          */
5294                         switch (r->secure) {
5295                         case ARM_CP_SECSTATE_S:
5296                         case ARM_CP_SECSTATE_NS:
5297                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5298                                                    r->secure, crm, opc1, opc2);
5299                             break;
5300                         default:
5301                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5302                                                    ARM_CP_SECSTATE_S,
5303                                                    crm, opc1, opc2);
5304                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5305                                                    ARM_CP_SECSTATE_NS,
5306                                                    crm, opc1, opc2);
5307                             break;
5308                         }
5309                     } else {
5310                         /* AArch64 registers get mapped to non-secure instance
5311                          * of AArch32 */
5312                         add_cpreg_to_hashtable(cpu, r, opaque, state,
5313                                                ARM_CP_SECSTATE_NS,
5314                                                crm, opc1, opc2);
5315                     }
5316                 }
5317             }
5318         }
5319     }
5320 }
5321
5322 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
5323                                     const ARMCPRegInfo *regs, void *opaque)
5324 {
5325     /* Define a whole list of registers */
5326     const ARMCPRegInfo *r;
5327     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
5328         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
5329     }
5330 }
5331
5332 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
5333 {
5334     return g_hash_table_lookup(cpregs, &encoded_cp);
5335 }
5336
5337 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
5338                          uint64_t value)
5339 {
5340     /* Helper coprocessor write function for write-ignore registers */
5341 }
5342
5343 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
5344 {
5345     /* Helper coprocessor write function for read-as-zero registers */
5346     return 0;
5347 }
5348
5349 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
5350 {
5351     /* Helper coprocessor reset function for do-nothing-on-reset registers */
5352 }
5353
5354 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
5355 {
5356     /* Return true if it is not valid for us to switch to
5357      * this CPU mode (ie all the UNPREDICTABLE cases in
5358      * the ARM ARM CPSRWriteByInstr pseudocode).
5359      */
5360
5361     /* Changes to or from Hyp via MSR and CPS are illegal. */
5362     if (write_type == CPSRWriteByInstr &&
5363         ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
5364          mode == ARM_CPU_MODE_HYP)) {
5365         return 1;
5366     }
5367
5368     switch (mode) {
5369     case ARM_CPU_MODE_USR:
5370         return 0;
5371     case ARM_CPU_MODE_SYS:
5372     case ARM_CPU_MODE_SVC:
5373     case ARM_CPU_MODE_ABT:
5374     case ARM_CPU_MODE_UND:
5375     case ARM_CPU_MODE_IRQ:
5376     case ARM_CPU_MODE_FIQ:
5377         /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5378          * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5379          */
5380         /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5381          * and CPS are treated as illegal mode changes.
5382          */
5383         if (write_type == CPSRWriteByInstr &&
5384             (env->cp15.hcr_el2 & HCR_TGE) &&
5385             (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
5386             !arm_is_secure_below_el3(env)) {
5387             return 1;
5388         }
5389         return 0;
5390     case ARM_CPU_MODE_HYP:
5391         return !arm_feature(env, ARM_FEATURE_EL2)
5392             || arm_current_el(env) < 2 || arm_is_secure(env);
5393     case ARM_CPU_MODE_MON:
5394         return arm_current_el(env) < 3;
5395     default:
5396         return 1;
5397     }
5398 }
5399
5400 uint32_t cpsr_read(CPUARMState *env)
5401 {
5402     int ZF;
5403     ZF = (env->ZF == 0);
5404     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5405         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5406         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5407         | ((env->condexec_bits & 0xfc) << 8)
5408         | (env->GE << 16) | (env->daif & CPSR_AIF);
5409 }
5410
5411 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
5412                 CPSRWriteType write_type)
5413 {
5414     uint32_t changed_daif;
5415
5416     if (mask & CPSR_NZCV) {
5417         env->ZF = (~val) & CPSR_Z;
5418         env->NF = val;
5419         env->CF = (val >> 29) & 1;
5420         env->VF = (val << 3) & 0x80000000;
5421     }
5422     if (mask & CPSR_Q)
5423         env->QF = ((val & CPSR_Q) != 0);
5424     if (mask & CPSR_T)
5425         env->thumb = ((val & CPSR_T) != 0);
5426     if (mask & CPSR_IT_0_1) {
5427         env->condexec_bits &= ~3;
5428         env->condexec_bits |= (val >> 25) & 3;
5429     }
5430     if (mask & CPSR_IT_2_7) {
5431         env->condexec_bits &= 3;
5432         env->condexec_bits |= (val >> 8) & 0xfc;
5433     }
5434     if (mask & CPSR_GE) {
5435         env->GE = (val >> 16) & 0xf;
5436     }
5437
5438     /* In a V7 implementation that includes the security extensions but does
5439      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5440      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5441      * bits respectively.
5442      *
5443      * In a V8 implementation, it is permitted for privileged software to
5444      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5445      */
5446     if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
5447         arm_feature(env, ARM_FEATURE_EL3) &&
5448         !arm_feature(env, ARM_FEATURE_EL2) &&
5449         !arm_is_secure(env)) {
5450
5451         changed_daif = (env->daif ^ val) & mask;
5452
5453         if (changed_daif & CPSR_A) {
5454             /* Check to see if we are allowed to change the masking of async
5455              * abort exceptions from a non-secure state.
5456              */
5457             if (!(env->cp15.scr_el3 & SCR_AW)) {
5458                 qemu_log_mask(LOG_GUEST_ERROR,
5459                               "Ignoring attempt to switch CPSR_A flag from "
5460                               "non-secure world with SCR.AW bit clear\n");
5461                 mask &= ~CPSR_A;
5462             }
5463         }
5464
5465         if (changed_daif & CPSR_F) {
5466             /* Check to see if we are allowed to change the masking of FIQ
5467              * exceptions from a non-secure state.
5468              */
5469             if (!(env->cp15.scr_el3 & SCR_FW)) {
5470                 qemu_log_mask(LOG_GUEST_ERROR,
5471                               "Ignoring attempt to switch CPSR_F flag from "
5472                               "non-secure world with SCR.FW bit clear\n");
5473                 mask &= ~CPSR_F;
5474             }
5475
5476             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5477              * If this bit is set software is not allowed to mask
5478              * FIQs, but is allowed to set CPSR_F to 0.
5479              */
5480             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5481                 (val & CPSR_F)) {
5482                 qemu_log_mask(LOG_GUEST_ERROR,
5483                               "Ignoring attempt to enable CPSR_F flag "
5484                               "(non-maskable FIQ [NMFI] support enabled)\n");
5485                 mask &= ~CPSR_F;
5486             }
5487         }
5488     }
5489
5490     env->daif &= ~(CPSR_AIF & mask);
5491     env->daif |= val & CPSR_AIF & mask;
5492
5493     if (write_type != CPSRWriteRaw &&
5494         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
5495         if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
5496             /* Note that we can only get here in USR mode if this is a
5497              * gdb stub write; for this case we follow the architectural
5498              * behaviour for guest writes in USR mode of ignoring an attempt
5499              * to switch mode. (Those are caught by translate.c for writes
5500              * triggered by guest instructions.)
5501              */
5502             mask &= ~CPSR_M;
5503         } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
5504             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5505              * v7, and has defined behaviour in v8:
5506              *  + leave CPSR.M untouched
5507              *  + allow changes to the other CPSR fields
5508              *  + set PSTATE.IL
5509              * For user changes via the GDB stub, we don't set PSTATE.IL,
5510              * as this would be unnecessarily harsh for a user error.
5511              */
5512             mask &= ~CPSR_M;
5513             if (write_type != CPSRWriteByGDBStub &&
5514                 arm_feature(env, ARM_FEATURE_V8)) {
5515                 mask |= CPSR_IL;
5516                 val |= CPSR_IL;
5517             }
5518         } else {
5519             switch_mode(env, val & CPSR_M);
5520         }
5521     }
5522     mask &= ~CACHED_CPSR_BITS;
5523     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5524 }
5525
5526 /* Sign/zero extend */
5527 uint32_t HELPER(sxtb16)(uint32_t x)
5528 {
5529     uint32_t res;
5530     res = (uint16_t)(int8_t)x;
5531     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5532     return res;
5533 }
5534
5535 uint32_t HELPER(uxtb16)(uint32_t x)
5536 {
5537     uint32_t res;
5538     res = (uint16_t)(uint8_t)x;
5539     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5540     return res;
5541 }
5542
5543 uint32_t HELPER(clz)(uint32_t x)
5544 {
5545     return clz32(x);
5546 }
5547
5548 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5549 {
5550     if (den == 0)
5551       return 0;
5552     if (num == INT_MIN && den == -1)
5553       return INT_MIN;
5554     return num / den;
5555 }
5556
5557 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5558 {
5559     if (den == 0)
5560       return 0;
5561     return num / den;
5562 }
5563
5564 uint32_t HELPER(rbit)(uint32_t x)
5565 {
5566     return revbit32(x);
5567 }
5568
5569 #if defined(CONFIG_USER_ONLY)
5570
5571 /* These should probably raise undefined insn exceptions.  */
5572 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5573 {
5574     ARMCPU *cpu = arm_env_get_cpu(env);
5575
5576     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5577 }
5578
5579 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5580 {
5581     ARMCPU *cpu = arm_env_get_cpu(env);
5582
5583     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5584     return 0;
5585 }
5586
5587 void switch_mode(CPUARMState *env, int mode)
5588 {
5589     ARMCPU *cpu = arm_env_get_cpu(env);
5590
5591     if (mode != ARM_CPU_MODE_USR) {
5592         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5593     }
5594 }
5595
5596 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5597                                  uint32_t cur_el, bool secure)
5598 {
5599     return 1;
5600 }
5601
5602 void aarch64_sync_64_to_32(CPUARMState *env)
5603 {
5604     g_assert_not_reached();
5605 }
5606
5607 #else
5608
5609 void switch_mode(CPUARMState *env, int mode)
5610 {
5611     int old_mode;
5612     int i;
5613
5614     old_mode = env->uncached_cpsr & CPSR_M;
5615     if (mode == old_mode)
5616         return;
5617
5618     if (old_mode == ARM_CPU_MODE_FIQ) {
5619         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5620         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5621     } else if (mode == ARM_CPU_MODE_FIQ) {
5622         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5623         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5624     }
5625
5626     i = bank_number(old_mode);
5627     env->banked_r13[i] = env->regs[13];
5628     env->banked_r14[i] = env->regs[14];
5629     env->banked_spsr[i] = env->spsr;
5630
5631     i = bank_number(mode);
5632     env->regs[13] = env->banked_r13[i];
5633     env->regs[14] = env->banked_r14[i];
5634     env->spsr = env->banked_spsr[i];
5635 }
5636
5637 /* Physical Interrupt Target EL Lookup Table
5638  *
5639  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5640  *
5641  * The below multi-dimensional table is used for looking up the target
5642  * exception level given numerous condition criteria.  Specifically, the
5643  * target EL is based on SCR and HCR routing controls as well as the
5644  * currently executing EL and secure state.
5645  *
5646  *    Dimensions:
5647  *    target_el_table[2][2][2][2][2][4]
5648  *                    |  |  |  |  |  +--- Current EL
5649  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5650  *                    |  |  |  +--------- HCR mask override
5651  *                    |  |  +------------ SCR exec state control
5652  *                    |  +--------------- SCR mask override
5653  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5654  *
5655  *    The table values are as such:
5656  *    0-3 = EL0-EL3
5657  *     -1 = Cannot occur
5658  *
5659  * The ARM ARM target EL table includes entries indicating that an "exception
5660  * is not taken".  The two cases where this is applicable are:
5661  *    1) An exception is taken from EL3 but the SCR does not have the exception
5662  *    routed to EL3.
5663  *    2) An exception is taken from EL2 but the HCR does not have the exception
5664  *    routed to EL2.
5665  * In these two cases, the below table contain a target of EL1.  This value is
5666  * returned as it is expected that the consumer of the table data will check
5667  * for "target EL >= current EL" to ensure the exception is not taken.
5668  *
5669  *            SCR     HCR
5670  *         64  EA     AMO                 From
5671  *        BIT IRQ     IMO      Non-secure         Secure
5672  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5673  */
5674 static const int8_t target_el_table[2][2][2][2][2][4] = {
5675     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5676        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5677       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5678        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5679      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5680        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5681       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5682        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5683     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5684        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5685       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5686        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5687      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5688        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5689       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5690        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5691 };
5692
5693 /*
5694  * Determine the target EL for physical exceptions
5695  */
5696 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5697                                  uint32_t cur_el, bool secure)
5698 {
5699     CPUARMState *env = cs->env_ptr;
5700     int rw;
5701     int scr;
5702     int hcr;
5703     int target_el;
5704     /* Is the highest EL AArch64? */
5705     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5706
5707     if (arm_feature(env, ARM_FEATURE_EL3)) {
5708         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5709     } else {
5710         /* Either EL2 is the highest EL (and so the EL2 register width
5711          * is given by is64); or there is no EL2 or EL3, in which case
5712          * the value of 'rw' does not affect the table lookup anyway.
5713          */
5714         rw = is64;
5715     }
5716
5717     switch (excp_idx) {
5718     case EXCP_IRQ:
5719         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5720         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5721         break;
5722     case EXCP_FIQ:
5723         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5724         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5725         break;
5726     default:
5727         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5728         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5729         break;
5730     };
5731
5732     /* If HCR.TGE is set then HCR is treated as being 1 */
5733     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5734
5735     /* Perform a table-lookup for the target EL given the current state */
5736     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5737
5738     assert(target_el > 0);
5739
5740     return target_el;
5741 }
5742
5743 static void v7m_push(CPUARMState *env, uint32_t val)
5744 {
5745     CPUState *cs = CPU(arm_env_get_cpu(env));
5746
5747     env->regs[13] -= 4;
5748     stl_phys(cs->as, env->regs[13], val);
5749 }
5750
5751 static uint32_t v7m_pop(CPUARMState *env)
5752 {
5753     CPUState *cs = CPU(arm_env_get_cpu(env));
5754     uint32_t val;
5755
5756     val = ldl_phys(cs->as, env->regs[13]);
5757     env->regs[13] += 4;
5758     return val;
5759 }
5760
5761 /* Switch to V7M main or process stack pointer.  */
5762 static void switch_v7m_sp(CPUARMState *env, int process)
5763 {
5764     uint32_t tmp;
5765     if (env->v7m.current_sp != process) {
5766         tmp = env->v7m.other_sp;
5767         env->v7m.other_sp = env->regs[13];
5768         env->regs[13] = tmp;
5769         env->v7m.current_sp = process;
5770     }
5771 }
5772
5773 static void do_v7m_exception_exit(CPUARMState *env)
5774 {
5775     uint32_t type;
5776     uint32_t xpsr;
5777
5778     type = env->regs[15];
5779     if (env->v7m.exception != 0)
5780         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5781
5782     /* Switch to the target stack.  */
5783     switch_v7m_sp(env, (type & 4) != 0);
5784     /* Pop registers.  */
5785     env->regs[0] = v7m_pop(env);
5786     env->regs[1] = v7m_pop(env);
5787     env->regs[2] = v7m_pop(env);
5788     env->regs[3] = v7m_pop(env);
5789     env->regs[12] = v7m_pop(env);
5790     env->regs[14] = v7m_pop(env);
5791     env->regs[15] = v7m_pop(env);
5792     if (env->regs[15] & 1) {
5793         qemu_log_mask(LOG_GUEST_ERROR,
5794                       "M profile return from interrupt with misaligned "
5795                       "PC is UNPREDICTABLE\n");
5796         /* Actual hardware seems to ignore the lsbit, and there are several
5797          * RTOSes out there which incorrectly assume the r15 in the stack
5798          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5799          */
5800         env->regs[15] &= ~1U;
5801     }
5802     xpsr = v7m_pop(env);
5803     xpsr_write(env, xpsr, 0xfffffdff);
5804     /* Undo stack alignment.  */
5805     if (xpsr & 0x200)
5806         env->regs[13] |= 4;
5807     /* ??? The exception return type specifies Thread/Handler mode.  However
5808        this is also implied by the xPSR value. Not sure what to do
5809        if there is a mismatch.  */
5810     /* ??? Likewise for mismatches between the CONTROL register and the stack
5811        pointer.  */
5812 }
5813
5814 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5815 {
5816     ARMCPU *cpu = ARM_CPU(cs);
5817     CPUARMState *env = &cpu->env;
5818     uint32_t xpsr = xpsr_read(env);
5819     uint32_t lr;
5820     uint32_t addr;
5821
5822     arm_log_exception(cs->exception_index);
5823
5824     lr = 0xfffffff1;
5825     if (env->v7m.current_sp)
5826         lr |= 4;
5827     if (env->v7m.exception == 0)
5828         lr |= 8;
5829
5830     /* For exceptions we just mark as pending on the NVIC, and let that
5831        handle it.  */
5832     /* TODO: Need to escalate if the current priority is higher than the
5833        one we're raising.  */
5834     switch (cs->exception_index) {
5835     case EXCP_UDEF:
5836         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5837         return;
5838     case EXCP_SWI:
5839         /* The PC already points to the next instruction.  */
5840         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5841         return;
5842     case EXCP_PREFETCH_ABORT:
5843     case EXCP_DATA_ABORT:
5844         /* TODO: if we implemented the MPU registers, this is where we
5845          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5846          */
5847         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5848         return;
5849     case EXCP_BKPT:
5850         if (semihosting_enabled()) {
5851             int nr;
5852             nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
5853             if (nr == 0xab) {
5854                 env->regs[15] += 2;
5855                 qemu_log_mask(CPU_LOG_INT,
5856                               "...handling as semihosting call 0x%x\n",
5857                               env->regs[0]);
5858                 env->regs[0] = do_arm_semihosting(env);
5859                 return;
5860             }
5861         }
5862         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5863         return;
5864     case EXCP_IRQ:
5865         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5866         break;
5867     case EXCP_EXCEPTION_EXIT:
5868         do_v7m_exception_exit(env);
5869         return;
5870     default:
5871         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5872         return; /* Never happens.  Keep compiler happy.  */
5873     }
5874
5875     /* Align stack pointer.  */
5876     /* ??? Should only do this if Configuration Control Register
5877        STACKALIGN bit is set.  */
5878     if (env->regs[13] & 4) {
5879         env->regs[13] -= 4;
5880         xpsr |= 0x200;
5881     }
5882     /* Switch to the handler mode.  */
5883     v7m_push(env, xpsr);
5884     v7m_push(env, env->regs[15]);
5885     v7m_push(env, env->regs[14]);
5886     v7m_push(env, env->regs[12]);
5887     v7m_push(env, env->regs[3]);
5888     v7m_push(env, env->regs[2]);
5889     v7m_push(env, env->regs[1]);
5890     v7m_push(env, env->regs[0]);
5891     switch_v7m_sp(env, 0);
5892     /* Clear IT bits */
5893     env->condexec_bits = 0;
5894     env->regs[14] = lr;
5895     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5896     env->regs[15] = addr & 0xfffffffe;
5897     env->thumb = addr & 1;
5898 }
5899
5900 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5901  * register set.  This is necessary when switching between AArch32 and AArch64
5902  * execution state.
5903  */
5904 void aarch64_sync_32_to_64(CPUARMState *env)
5905 {
5906     int i;
5907     uint32_t mode = env->uncached_cpsr & CPSR_M;
5908
5909     /* We can blanket copy R[0:7] to X[0:7] */
5910     for (i = 0; i < 8; i++) {
5911         env->xregs[i] = env->regs[i];
5912     }
5913
5914     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5915      * Otherwise, they come from the banked user regs.
5916      */
5917     if (mode == ARM_CPU_MODE_FIQ) {
5918         for (i = 8; i < 13; i++) {
5919             env->xregs[i] = env->usr_regs[i - 8];
5920         }
5921     } else {
5922         for (i = 8; i < 13; i++) {
5923             env->xregs[i] = env->regs[i];
5924         }
5925     }
5926
5927     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5928      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5929      * from the mode banked register.
5930      */
5931     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5932         env->xregs[13] = env->regs[13];
5933         env->xregs[14] = env->regs[14];
5934     } else {
5935         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5936         /* HYP is an exception in that it is copied from r14 */
5937         if (mode == ARM_CPU_MODE_HYP) {
5938             env->xregs[14] = env->regs[14];
5939         } else {
5940             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5941         }
5942     }
5943
5944     if (mode == ARM_CPU_MODE_HYP) {
5945         env->xregs[15] = env->regs[13];
5946     } else {
5947         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5948     }
5949
5950     if (mode == ARM_CPU_MODE_IRQ) {
5951         env->xregs[16] = env->regs[14];
5952         env->xregs[17] = env->regs[13];
5953     } else {
5954         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5955         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5956     }
5957
5958     if (mode == ARM_CPU_MODE_SVC) {
5959         env->xregs[18] = env->regs[14];
5960         env->xregs[19] = env->regs[13];
5961     } else {
5962         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5963         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5964     }
5965
5966     if (mode == ARM_CPU_MODE_ABT) {
5967         env->xregs[20] = env->regs[14];
5968         env->xregs[21] = env->regs[13];
5969     } else {
5970         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5971         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5972     }
5973
5974     if (mode == ARM_CPU_MODE_UND) {
5975         env->xregs[22] = env->regs[14];
5976         env->xregs[23] = env->regs[13];
5977     } else {
5978         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5979         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5980     }
5981
5982     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5983      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5984      * FIQ bank for r8-r14.
5985      */
5986     if (mode == ARM_CPU_MODE_FIQ) {
5987         for (i = 24; i < 31; i++) {
5988             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5989         }
5990     } else {
5991         for (i = 24; i < 29; i++) {
5992             env->xregs[i] = env->fiq_regs[i - 24];
5993         }
5994         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5995         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5996     }
5997
5998     env->pc = env->regs[15];
5999 }
6000
6001 /* Function used to synchronize QEMU's AArch32 register set with AArch64
6002  * register set.  This is necessary when switching between AArch32 and AArch64
6003  * execution state.
6004  */
6005 void aarch64_sync_64_to_32(CPUARMState *env)
6006 {
6007     int i;
6008     uint32_t mode = env->uncached_cpsr & CPSR_M;
6009
6010     /* We can blanket copy X[0:7] to R[0:7] */
6011     for (i = 0; i < 8; i++) {
6012         env->regs[i] = env->xregs[i];
6013     }
6014
6015     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6016      * Otherwise, we copy x8-x12 into the banked user regs.
6017      */
6018     if (mode == ARM_CPU_MODE_FIQ) {
6019         for (i = 8; i < 13; i++) {
6020             env->usr_regs[i - 8] = env->xregs[i];
6021         }
6022     } else {
6023         for (i = 8; i < 13; i++) {
6024             env->regs[i] = env->xregs[i];
6025         }
6026     }
6027
6028     /* Registers r13 & r14 depend on the current mode.
6029      * If we are in a given mode, we copy the corresponding x registers to r13
6030      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
6031      * for the mode.
6032      */
6033     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
6034         env->regs[13] = env->xregs[13];
6035         env->regs[14] = env->xregs[14];
6036     } else {
6037         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
6038
6039         /* HYP is an exception in that it does not have its own banked r14 but
6040          * shares the USR r14
6041          */
6042         if (mode == ARM_CPU_MODE_HYP) {
6043             env->regs[14] = env->xregs[14];
6044         } else {
6045             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
6046         }
6047     }
6048
6049     if (mode == ARM_CPU_MODE_HYP) {
6050         env->regs[13] = env->xregs[15];
6051     } else {
6052         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
6053     }
6054
6055     if (mode == ARM_CPU_MODE_IRQ) {
6056         env->regs[14] = env->xregs[16];
6057         env->regs[13] = env->xregs[17];
6058     } else {
6059         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
6060         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
6061     }
6062
6063     if (mode == ARM_CPU_MODE_SVC) {
6064         env->regs[14] = env->xregs[18];
6065         env->regs[13] = env->xregs[19];
6066     } else {
6067         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
6068         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
6069     }
6070
6071     if (mode == ARM_CPU_MODE_ABT) {
6072         env->regs[14] = env->xregs[20];
6073         env->regs[13] = env->xregs[21];
6074     } else {
6075         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
6076         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
6077     }
6078
6079     if (mode == ARM_CPU_MODE_UND) {
6080         env->regs[14] = env->xregs[22];
6081         env->regs[13] = env->xregs[23];
6082     } else {
6083         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
6084         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
6085     }
6086
6087     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
6088      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
6089      * FIQ bank for r8-r14.
6090      */
6091     if (mode == ARM_CPU_MODE_FIQ) {
6092         for (i = 24; i < 31; i++) {
6093             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
6094         }
6095     } else {
6096         for (i = 24; i < 29; i++) {
6097             env->fiq_regs[i - 24] = env->xregs[i];
6098         }
6099         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
6100         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
6101     }
6102
6103     env->regs[15] = env->pc;
6104 }
6105
6106 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
6107 {
6108     ARMCPU *cpu = ARM_CPU(cs);
6109     CPUARMState *env = &cpu->env;
6110     uint32_t addr;
6111     uint32_t mask;
6112     int new_mode;
6113     uint32_t offset;
6114     uint32_t moe;
6115
6116     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6117     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
6118     case EC_BREAKPOINT:
6119     case EC_BREAKPOINT_SAME_EL:
6120         moe = 1;
6121         break;
6122     case EC_WATCHPOINT:
6123     case EC_WATCHPOINT_SAME_EL:
6124         moe = 10;
6125         break;
6126     case EC_AA32_BKPT:
6127         moe = 3;
6128         break;
6129     case EC_VECTORCATCH:
6130         moe = 5;
6131         break;
6132     default:
6133         moe = 0;
6134         break;
6135     }
6136
6137     if (moe) {
6138         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
6139     }
6140
6141     /* TODO: Vectored interrupt controller.  */
6142     switch (cs->exception_index) {
6143     case EXCP_UDEF:
6144         new_mode = ARM_CPU_MODE_UND;
6145         addr = 0x04;
6146         mask = CPSR_I;
6147         if (env->thumb)
6148             offset = 2;
6149         else
6150             offset = 4;
6151         break;
6152     case EXCP_SWI:
6153         new_mode = ARM_CPU_MODE_SVC;
6154         addr = 0x08;
6155         mask = CPSR_I;
6156         /* The PC already points to the next instruction.  */
6157         offset = 0;
6158         break;
6159     case EXCP_BKPT:
6160         env->exception.fsr = 2;
6161         /* Fall through to prefetch abort.  */
6162     case EXCP_PREFETCH_ABORT:
6163         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
6164         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
6165         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
6166                       env->exception.fsr, (uint32_t)env->exception.vaddress);
6167         new_mode = ARM_CPU_MODE_ABT;
6168         addr = 0x0c;
6169         mask = CPSR_A | CPSR_I;
6170         offset = 4;
6171         break;
6172     case EXCP_DATA_ABORT:
6173         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
6174         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
6175         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
6176                       env->exception.fsr,
6177                       (uint32_t)env->exception.vaddress);
6178         new_mode = ARM_CPU_MODE_ABT;
6179         addr = 0x10;
6180         mask = CPSR_A | CPSR_I;
6181         offset = 8;
6182         break;
6183     case EXCP_IRQ:
6184         new_mode = ARM_CPU_MODE_IRQ;
6185         addr = 0x18;
6186         /* Disable IRQ and imprecise data aborts.  */
6187         mask = CPSR_A | CPSR_I;
6188         offset = 4;
6189         if (env->cp15.scr_el3 & SCR_IRQ) {
6190             /* IRQ routed to monitor mode */
6191             new_mode = ARM_CPU_MODE_MON;
6192             mask |= CPSR_F;
6193         }
6194         break;
6195     case EXCP_FIQ:
6196         new_mode = ARM_CPU_MODE_FIQ;
6197         addr = 0x1c;
6198         /* Disable FIQ, IRQ and imprecise data aborts.  */
6199         mask = CPSR_A | CPSR_I | CPSR_F;
6200         if (env->cp15.scr_el3 & SCR_FIQ) {
6201             /* FIQ routed to monitor mode */
6202             new_mode = ARM_CPU_MODE_MON;
6203         }
6204         offset = 4;
6205         break;
6206     case EXCP_SMC:
6207         new_mode = ARM_CPU_MODE_MON;
6208         addr = 0x08;
6209         mask = CPSR_A | CPSR_I | CPSR_F;
6210         offset = 0;
6211         break;
6212     default:
6213         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6214         return; /* Never happens.  Keep compiler happy.  */
6215     }
6216
6217     if (new_mode == ARM_CPU_MODE_MON) {
6218         addr += env->cp15.mvbar;
6219     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
6220         /* High vectors. When enabled, base address cannot be remapped. */
6221         addr += 0xffff0000;
6222     } else {
6223         /* ARM v7 architectures provide a vector base address register to remap
6224          * the interrupt vector table.
6225          * This register is only followed in non-monitor mode, and is banked.
6226          * Note: only bits 31:5 are valid.
6227          */
6228         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
6229     }
6230
6231     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
6232         env->cp15.scr_el3 &= ~SCR_NS;
6233     }
6234
6235     switch_mode (env, new_mode);
6236     /* For exceptions taken to AArch32 we must clear the SS bit in both
6237      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
6238      */
6239     env->uncached_cpsr &= ~PSTATE_SS;
6240     env->spsr = cpsr_read(env);
6241     /* Clear IT bits.  */
6242     env->condexec_bits = 0;
6243     /* Switch to the new mode, and to the correct instruction set.  */
6244     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
6245     /* Set new mode endianness */
6246     env->uncached_cpsr &= ~CPSR_E;
6247     if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
6248         env->uncached_cpsr |= ~CPSR_E;
6249     }
6250     env->daif |= mask;
6251     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
6252      * and we should just guard the thumb mode on V4 */
6253     if (arm_feature(env, ARM_FEATURE_V4T)) {
6254         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
6255     }
6256     env->regs[14] = env->regs[15] + offset;
6257     env->regs[15] = addr;
6258 }
6259
6260 /* Handle exception entry to a target EL which is using AArch64 */
6261 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
6262 {
6263     ARMCPU *cpu = ARM_CPU(cs);
6264     CPUARMState *env = &cpu->env;
6265     unsigned int new_el = env->exception.target_el;
6266     target_ulong addr = env->cp15.vbar_el[new_el];
6267     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
6268
6269     if (arm_current_el(env) < new_el) {
6270         /* Entry vector offset depends on whether the implemented EL
6271          * immediately lower than the target level is using AArch32 or AArch64
6272          */
6273         bool is_aa64;
6274
6275         switch (new_el) {
6276         case 3:
6277             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
6278             break;
6279         case 2:
6280             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
6281             break;
6282         case 1:
6283             is_aa64 = is_a64(env);
6284             break;
6285         default:
6286             g_assert_not_reached();
6287         }
6288
6289         if (is_aa64) {
6290             addr += 0x400;
6291         } else {
6292             addr += 0x600;
6293         }
6294     } else if (pstate_read(env) & PSTATE_SP) {
6295         addr += 0x200;
6296     }
6297
6298     switch (cs->exception_index) {
6299     case EXCP_PREFETCH_ABORT:
6300     case EXCP_DATA_ABORT:
6301         env->cp15.far_el[new_el] = env->exception.vaddress;
6302         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
6303                       env->cp15.far_el[new_el]);
6304         /* fall through */
6305     case EXCP_BKPT:
6306     case EXCP_UDEF:
6307     case EXCP_SWI:
6308     case EXCP_HVC:
6309     case EXCP_HYP_TRAP:
6310     case EXCP_SMC:
6311         env->cp15.esr_el[new_el] = env->exception.syndrome;
6312         break;
6313     case EXCP_IRQ:
6314     case EXCP_VIRQ:
6315         addr += 0x80;
6316         break;
6317     case EXCP_FIQ:
6318     case EXCP_VFIQ:
6319         addr += 0x100;
6320         break;
6321     case EXCP_SEMIHOST:
6322         qemu_log_mask(CPU_LOG_INT,
6323                       "...handling as semihosting call 0x%" PRIx64 "\n",
6324                       env->xregs[0]);
6325         env->xregs[0] = do_arm_semihosting(env);
6326         return;
6327     default:
6328         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6329     }
6330
6331     if (is_a64(env)) {
6332         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
6333         aarch64_save_sp(env, arm_current_el(env));
6334         env->elr_el[new_el] = env->pc;
6335     } else {
6336         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
6337         if (!env->thumb) {
6338             env->cp15.esr_el[new_el] |= 1 << 25;
6339         }
6340         env->elr_el[new_el] = env->regs[15];
6341
6342         aarch64_sync_32_to_64(env);
6343
6344         env->condexec_bits = 0;
6345     }
6346     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
6347                   env->elr_el[new_el]);
6348
6349     pstate_write(env, PSTATE_DAIF | new_mode);
6350     env->aarch64 = 1;
6351     aarch64_restore_sp(env, new_el);
6352
6353     env->pc = addr;
6354
6355     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
6356                   new_el, env->pc, pstate_read(env));
6357 }
6358
6359 static inline bool check_for_semihosting(CPUState *cs)
6360 {
6361     /* Check whether this exception is a semihosting call; if so
6362      * then handle it and return true; otherwise return false.
6363      */
6364     ARMCPU *cpu = ARM_CPU(cs);
6365     CPUARMState *env = &cpu->env;
6366
6367     if (is_a64(env)) {
6368         if (cs->exception_index == EXCP_SEMIHOST) {
6369             /* This is always the 64-bit semihosting exception.
6370              * The "is this usermode" and "is semihosting enabled"
6371              * checks have been done at translate time.
6372              */
6373             qemu_log_mask(CPU_LOG_INT,
6374                           "...handling as semihosting call 0x%" PRIx64 "\n",
6375                           env->xregs[0]);
6376             env->xregs[0] = do_arm_semihosting(env);
6377             return true;
6378         }
6379         return false;
6380     } else {
6381         uint32_t imm;
6382
6383         /* Only intercept calls from privileged modes, to provide some
6384          * semblance of security.
6385          */
6386         if (!semihosting_enabled() ||
6387             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
6388             return false;
6389         }
6390
6391         switch (cs->exception_index) {
6392         case EXCP_SWI:
6393             /* Check for semihosting interrupt.  */
6394             if (env->thumb) {
6395                 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
6396                     & 0xff;
6397                 if (imm == 0xab) {
6398                     break;
6399                 }
6400             } else {
6401                 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
6402                     & 0xffffff;
6403                 if (imm == 0x123456) {
6404                     break;
6405                 }
6406             }
6407             return false;
6408         case EXCP_BKPT:
6409             /* See if this is a semihosting syscall.  */
6410             if (env->thumb) {
6411                 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
6412                     & 0xff;
6413                 if (imm == 0xab) {
6414                     env->regs[15] += 2;
6415                     break;
6416                 }
6417             }
6418             return false;
6419         default:
6420             return false;
6421         }
6422
6423         qemu_log_mask(CPU_LOG_INT,
6424                       "...handling as semihosting call 0x%x\n",
6425                       env->regs[0]);
6426         env->regs[0] = do_arm_semihosting(env);
6427         return true;
6428     }
6429 }
6430
6431 /* Handle a CPU exception for A and R profile CPUs.
6432  * Do any appropriate logging, handle PSCI calls, and then hand off
6433  * to the AArch64-entry or AArch32-entry function depending on the
6434  * target exception level's register width.
6435  */
6436 void arm_cpu_do_interrupt(CPUState *cs)
6437 {
6438     ARMCPU *cpu = ARM_CPU(cs);
6439     CPUARMState *env = &cpu->env;
6440     unsigned int new_el = env->exception.target_el;
6441
6442     assert(!IS_M(env));
6443
6444     arm_log_exception(cs->exception_index);
6445     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6446                   new_el);
6447     if (qemu_loglevel_mask(CPU_LOG_INT)
6448         && !excp_is_internal(cs->exception_index)) {
6449         qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6450                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
6451                       env->exception.syndrome);
6452     }
6453
6454     if (arm_is_psci_call(cpu, cs->exception_index)) {
6455         arm_handle_psci_call(cpu);
6456         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6457         return;
6458     }
6459
6460     /* Semihosting semantics depend on the register width of the
6461      * code that caused the exception, not the target exception level,
6462      * so must be handled here.
6463      */
6464     if (check_for_semihosting(cs)) {
6465         return;
6466     }
6467
6468     assert(!excp_is_internal(cs->exception_index));
6469     if (arm_el_is_aa64(env, new_el)) {
6470         arm_cpu_do_interrupt_aarch64(cs);
6471     } else {
6472         arm_cpu_do_interrupt_aarch32(cs);
6473     }
6474
6475     if (!kvm_enabled()) {
6476         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6477     }
6478 }
6479
6480 /* Return the exception level which controls this address translation regime */
6481 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6482 {
6483     switch (mmu_idx) {
6484     case ARMMMUIdx_S2NS:
6485     case ARMMMUIdx_S1E2:
6486         return 2;
6487     case ARMMMUIdx_S1E3:
6488         return 3;
6489     case ARMMMUIdx_S1SE0:
6490         return arm_el_is_aa64(env, 3) ? 1 : 3;
6491     case ARMMMUIdx_S1SE1:
6492     case ARMMMUIdx_S1NSE0:
6493     case ARMMMUIdx_S1NSE1:
6494         return 1;
6495     default:
6496         g_assert_not_reached();
6497     }
6498 }
6499
6500 /* Return true if this address translation regime is secure */
6501 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6502 {
6503     switch (mmu_idx) {
6504     case ARMMMUIdx_S12NSE0:
6505     case ARMMMUIdx_S12NSE1:
6506     case ARMMMUIdx_S1NSE0:
6507     case ARMMMUIdx_S1NSE1:
6508     case ARMMMUIdx_S1E2:
6509     case ARMMMUIdx_S2NS:
6510         return false;
6511     case ARMMMUIdx_S1E3:
6512     case ARMMMUIdx_S1SE0:
6513     case ARMMMUIdx_S1SE1:
6514         return true;
6515     default:
6516         g_assert_not_reached();
6517     }
6518 }
6519
6520 /* Return the SCTLR value which controls this address translation regime */
6521 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6522 {
6523     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6524 }
6525
6526 /* Return true if the specified stage of address translation is disabled */
6527 static inline bool regime_translation_disabled(CPUARMState *env,
6528                                                ARMMMUIdx mmu_idx)
6529 {
6530     if (mmu_idx == ARMMMUIdx_S2NS) {
6531         return (env->cp15.hcr_el2 & HCR_VM) == 0;
6532     }
6533     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6534 }
6535
6536 static inline bool regime_translation_big_endian(CPUARMState *env,
6537                                                  ARMMMUIdx mmu_idx)
6538 {
6539     return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
6540 }
6541
6542 /* Return the TCR controlling this translation regime */
6543 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6544 {
6545     if (mmu_idx == ARMMMUIdx_S2NS) {
6546         return &env->cp15.vtcr_el2;
6547     }
6548     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6549 }
6550
6551 /* Return the TTBR associated with this translation regime */
6552 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6553                                    int ttbrn)
6554 {
6555     if (mmu_idx == ARMMMUIdx_S2NS) {
6556         return env->cp15.vttbr_el2;
6557     }
6558     if (ttbrn == 0) {
6559         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6560     } else {
6561         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6562     }
6563 }
6564
6565 /* Return true if the translation regime is using LPAE format page tables */
6566 static inline bool regime_using_lpae_format(CPUARMState *env,
6567                                             ARMMMUIdx mmu_idx)
6568 {
6569     int el = regime_el(env, mmu_idx);
6570     if (el == 2 || arm_el_is_aa64(env, el)) {
6571         return true;
6572     }
6573     if (arm_feature(env, ARM_FEATURE_LPAE)
6574         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6575         return true;
6576     }
6577     return false;
6578 }
6579
6580 /* Returns true if the stage 1 translation regime is using LPAE format page
6581  * tables. Used when raising alignment exceptions, whose FSR changes depending
6582  * on whether the long or short descriptor format is in use. */
6583 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6584 {
6585     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6586         mmu_idx += ARMMMUIdx_S1NSE0;
6587     }
6588
6589     return regime_using_lpae_format(env, mmu_idx);
6590 }
6591
6592 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6593 {
6594     switch (mmu_idx) {
6595     case ARMMMUIdx_S1SE0:
6596     case ARMMMUIdx_S1NSE0:
6597         return true;
6598     default:
6599         return false;
6600     case ARMMMUIdx_S12NSE0:
6601     case ARMMMUIdx_S12NSE1:
6602         g_assert_not_reached();
6603     }
6604 }
6605
6606 /* Translate section/page access permissions to page
6607  * R/W protection flags
6608  *
6609  * @env:         CPUARMState
6610  * @mmu_idx:     MMU index indicating required translation regime
6611  * @ap:          The 3-bit access permissions (AP[2:0])
6612  * @domain_prot: The 2-bit domain access permissions
6613  */
6614 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6615                                 int ap, int domain_prot)
6616 {
6617     bool is_user = regime_is_user(env, mmu_idx);
6618
6619     if (domain_prot == 3) {
6620         return PAGE_READ | PAGE_WRITE;
6621     }
6622
6623     switch (ap) {
6624     case 0:
6625         if (arm_feature(env, ARM_FEATURE_V7)) {
6626             return 0;
6627         }
6628         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6629         case SCTLR_S:
6630             return is_user ? 0 : PAGE_READ;
6631         case SCTLR_R:
6632             return PAGE_READ;
6633         default:
6634             return 0;
6635         }
6636     case 1:
6637         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6638     case 2:
6639         if (is_user) {
6640             return PAGE_READ;
6641         } else {
6642             return PAGE_READ | PAGE_WRITE;
6643         }
6644     case 3:
6645         return PAGE_READ | PAGE_WRITE;
6646     case 4: /* Reserved.  */
6647         return 0;
6648     case 5:
6649         return is_user ? 0 : PAGE_READ;
6650     case 6:
6651         return PAGE_READ;
6652     case 7:
6653         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6654             return 0;
6655         }
6656         return PAGE_READ;
6657     default:
6658         g_assert_not_reached();
6659     }
6660 }
6661
6662 /* Translate section/page access permissions to page
6663  * R/W protection flags.
6664  *
6665  * @ap:      The 2-bit simple AP (AP[2:1])
6666  * @is_user: TRUE if accessing from PL0
6667  */
6668 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6669 {
6670     switch (ap) {
6671     case 0:
6672         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6673     case 1:
6674         return PAGE_READ | PAGE_WRITE;
6675     case 2:
6676         return is_user ? 0 : PAGE_READ;
6677     case 3:
6678         return PAGE_READ;
6679     default:
6680         g_assert_not_reached();
6681     }
6682 }
6683
6684 static inline int
6685 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6686 {
6687     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6688 }
6689
6690 /* Translate S2 section/page access permissions to protection flags
6691  *
6692  * @env:     CPUARMState
6693  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6694  * @xn:      XN (execute-never) bit
6695  */
6696 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6697 {
6698     int prot = 0;
6699
6700     if (s2ap & 1) {
6701         prot |= PAGE_READ;
6702     }
6703     if (s2ap & 2) {
6704         prot |= PAGE_WRITE;
6705     }
6706     if (!xn) {
6707         prot |= PAGE_EXEC;
6708     }
6709     return prot;
6710 }
6711
6712 /* Translate section/page access permissions to protection flags
6713  *
6714  * @env:     CPUARMState
6715  * @mmu_idx: MMU index indicating required translation regime
6716  * @is_aa64: TRUE if AArch64
6717  * @ap:      The 2-bit simple AP (AP[2:1])
6718  * @ns:      NS (non-secure) bit
6719  * @xn:      XN (execute-never) bit
6720  * @pxn:     PXN (privileged execute-never) bit
6721  */
6722 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6723                       int ap, int ns, int xn, int pxn)
6724 {
6725     bool is_user = regime_is_user(env, mmu_idx);
6726     int prot_rw, user_rw;
6727     bool have_wxn;
6728     int wxn = 0;
6729
6730     assert(mmu_idx != ARMMMUIdx_S2NS);
6731
6732     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6733     if (is_user) {
6734         prot_rw = user_rw;
6735     } else {
6736         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6737     }
6738
6739     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6740         return prot_rw;
6741     }
6742
6743     /* TODO have_wxn should be replaced with
6744      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6745      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6746      * compatible processors have EL2, which is required for [U]WXN.
6747      */
6748     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6749
6750     if (have_wxn) {
6751         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6752     }
6753
6754     if (is_aa64) {
6755         switch (regime_el(env, mmu_idx)) {
6756         case 1:
6757             if (!is_user) {
6758                 xn = pxn || (user_rw & PAGE_WRITE);
6759             }
6760             break;
6761         case 2:
6762         case 3:
6763             break;
6764         }
6765     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6766         switch (regime_el(env, mmu_idx)) {
6767         case 1:
6768         case 3:
6769             if (is_user) {
6770                 xn = xn || !(user_rw & PAGE_READ);
6771             } else {
6772                 int uwxn = 0;
6773                 if (have_wxn) {
6774                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6775                 }
6776                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6777                      (uwxn && (user_rw & PAGE_WRITE));
6778             }
6779             break;
6780         case 2:
6781             break;
6782         }
6783     } else {
6784         xn = wxn = 0;
6785     }
6786
6787     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6788         return prot_rw;
6789     }
6790     return prot_rw | PAGE_EXEC;
6791 }
6792
6793 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6794                                      uint32_t *table, uint32_t address)
6795 {
6796     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6797     TCR *tcr = regime_tcr(env, mmu_idx);
6798
6799     if (address & tcr->mask) {
6800         if (tcr->raw_tcr & TTBCR_PD1) {
6801             /* Translation table walk disabled for TTBR1 */
6802             return false;
6803         }
6804         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6805     } else {
6806         if (tcr->raw_tcr & TTBCR_PD0) {
6807             /* Translation table walk disabled for TTBR0 */
6808             return false;
6809         }
6810         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6811     }
6812     *table |= (address >> 18) & 0x3ffc;
6813     return true;
6814 }
6815
6816 /* Translate a S1 pagetable walk through S2 if needed.  */
6817 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6818                                hwaddr addr, MemTxAttrs txattrs,
6819                                uint32_t *fsr,
6820                                ARMMMUFaultInfo *fi)
6821 {
6822     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6823         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6824         target_ulong s2size;
6825         hwaddr s2pa;
6826         int s2prot;
6827         int ret;
6828
6829         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6830                                  &txattrs, &s2prot, &s2size, fsr, fi);
6831         if (ret) {
6832             fi->s2addr = addr;
6833             fi->stage2 = true;
6834             fi->s1ptw = true;
6835             return ~0;
6836         }
6837         addr = s2pa;
6838     }
6839     return addr;
6840 }
6841
6842 /* All loads done in the course of a page table walk go through here.
6843  * TODO: rather than ignoring errors from physical memory reads (which
6844  * are external aborts in ARM terminology) we should propagate this
6845  * error out so that we can turn it into a Data Abort if this walk
6846  * was being done for a CPU load/store or an address translation instruction
6847  * (but not if it was for a debug access).
6848  */
6849 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6850                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6851                             ARMMMUFaultInfo *fi)
6852 {
6853     ARMCPU *cpu = ARM_CPU(cs);
6854     CPUARMState *env = &cpu->env;
6855     MemTxAttrs attrs = {};
6856     AddressSpace *as;
6857
6858     attrs.secure = is_secure;
6859     as = arm_addressspace(cs, attrs);
6860     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6861     if (fi->s1ptw) {
6862         return 0;
6863     }
6864     if (regime_translation_big_endian(env, mmu_idx)) {
6865         return address_space_ldl_be(as, addr, attrs, NULL);
6866     } else {
6867         return address_space_ldl_le(as, addr, attrs, NULL);
6868     }
6869 }
6870
6871 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6872                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6873                             ARMMMUFaultInfo *fi)
6874 {
6875     ARMCPU *cpu = ARM_CPU(cs);
6876     CPUARMState *env = &cpu->env;
6877     MemTxAttrs attrs = {};
6878     AddressSpace *as;
6879
6880     attrs.secure = is_secure;
6881     as = arm_addressspace(cs, attrs);
6882     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6883     if (fi->s1ptw) {
6884         return 0;
6885     }
6886     if (regime_translation_big_endian(env, mmu_idx)) {
6887         return address_space_ldq_be(as, addr, attrs, NULL);
6888     } else {
6889         return address_space_ldq_le(as, addr, attrs, NULL);
6890     }
6891 }
6892
6893 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6894                              int access_type, ARMMMUIdx mmu_idx,
6895                              hwaddr *phys_ptr, int *prot,
6896                              target_ulong *page_size, uint32_t *fsr,
6897                              ARMMMUFaultInfo *fi)
6898 {
6899     CPUState *cs = CPU(arm_env_get_cpu(env));
6900     int code;
6901     uint32_t table;
6902     uint32_t desc;
6903     int type;
6904     int ap;
6905     int domain = 0;
6906     int domain_prot;
6907     hwaddr phys_addr;
6908     uint32_t dacr;
6909
6910     /* Pagetable walk.  */
6911     /* Lookup l1 descriptor.  */
6912     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6913         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6914         code = 5;
6915         goto do_fault;
6916     }
6917     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6918                        mmu_idx, fsr, fi);
6919     type = (desc & 3);
6920     domain = (desc >> 5) & 0x0f;
6921     if (regime_el(env, mmu_idx) == 1) {
6922         dacr = env->cp15.dacr_ns;
6923     } else {
6924         dacr = env->cp15.dacr_s;
6925     }
6926     domain_prot = (dacr >> (domain * 2)) & 3;
6927     if (type == 0) {
6928         /* Section translation fault.  */
6929         code = 5;
6930         goto do_fault;
6931     }
6932     if (domain_prot == 0 || domain_prot == 2) {
6933         if (type == 2)
6934             code = 9; /* Section domain fault.  */
6935         else
6936             code = 11; /* Page domain fault.  */
6937         goto do_fault;
6938     }
6939     if (type == 2) {
6940         /* 1Mb section.  */
6941         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6942         ap = (desc >> 10) & 3;
6943         code = 13;
6944         *page_size = 1024 * 1024;
6945     } else {
6946         /* Lookup l2 entry.  */
6947         if (type == 1) {
6948             /* Coarse pagetable.  */
6949             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6950         } else {
6951             /* Fine pagetable.  */
6952             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6953         }
6954         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6955                            mmu_idx, fsr, fi);
6956         switch (desc & 3) {
6957         case 0: /* Page translation fault.  */
6958             code = 7;
6959             goto do_fault;
6960         case 1: /* 64k page.  */
6961             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6962             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6963             *page_size = 0x10000;
6964             break;
6965         case 2: /* 4k page.  */
6966             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6967             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6968             *page_size = 0x1000;
6969             break;
6970         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6971             if (type == 1) {
6972                 /* ARMv6/XScale extended small page format */
6973                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6974                     || arm_feature(env, ARM_FEATURE_V6)) {
6975                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6976                     *page_size = 0x1000;
6977                 } else {
6978                     /* UNPREDICTABLE in ARMv5; we choose to take a
6979                      * page translation fault.
6980                      */
6981                     code = 7;
6982                     goto do_fault;
6983                 }
6984             } else {
6985                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6986                 *page_size = 0x400;
6987             }
6988             ap = (desc >> 4) & 3;
6989             break;
6990         default:
6991             /* Never happens, but compiler isn't smart enough to tell.  */
6992             abort();
6993         }
6994         code = 15;
6995     }
6996     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6997     *prot |= *prot ? PAGE_EXEC : 0;
6998     if (!(*prot & (1 << access_type))) {
6999         /* Access permission fault.  */
7000         goto do_fault;
7001     }
7002     *phys_ptr = phys_addr;
7003     return false;
7004 do_fault:
7005     *fsr = code | (domain << 4);
7006     return true;
7007 }
7008
7009 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
7010                              int access_type, ARMMMUIdx mmu_idx,
7011                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7012                              target_ulong *page_size, uint32_t *fsr,
7013                              ARMMMUFaultInfo *fi)
7014 {
7015     CPUState *cs = CPU(arm_env_get_cpu(env));
7016     int code;
7017     uint32_t table;
7018     uint32_t desc;
7019     uint32_t xn;
7020     uint32_t pxn = 0;
7021     int type;
7022     int ap;
7023     int domain = 0;
7024     int domain_prot;
7025     hwaddr phys_addr;
7026     uint32_t dacr;
7027     bool ns;
7028
7029     /* Pagetable walk.  */
7030     /* Lookup l1 descriptor.  */
7031     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
7032         /* Section translation fault if page walk is disabled by PD0 or PD1 */
7033         code = 5;
7034         goto do_fault;
7035     }
7036     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7037                        mmu_idx, fsr, fi);
7038     type = (desc & 3);
7039     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
7040         /* Section translation fault, or attempt to use the encoding
7041          * which is Reserved on implementations without PXN.
7042          */
7043         code = 5;
7044         goto do_fault;
7045     }
7046     if ((type == 1) || !(desc & (1 << 18))) {
7047         /* Page or Section.  */
7048         domain = (desc >> 5) & 0x0f;
7049     }
7050     if (regime_el(env, mmu_idx) == 1) {
7051         dacr = env->cp15.dacr_ns;
7052     } else {
7053         dacr = env->cp15.dacr_s;
7054     }
7055     domain_prot = (dacr >> (domain * 2)) & 3;
7056     if (domain_prot == 0 || domain_prot == 2) {
7057         if (type != 1) {
7058             code = 9; /* Section domain fault.  */
7059         } else {
7060             code = 11; /* Page domain fault.  */
7061         }
7062         goto do_fault;
7063     }
7064     if (type != 1) {
7065         if (desc & (1 << 18)) {
7066             /* Supersection.  */
7067             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
7068             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
7069             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
7070             *page_size = 0x1000000;
7071         } else {
7072             /* Section.  */
7073             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
7074             *page_size = 0x100000;
7075         }
7076         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
7077         xn = desc & (1 << 4);
7078         pxn = desc & 1;
7079         code = 13;
7080         ns = extract32(desc, 19, 1);
7081     } else {
7082         if (arm_feature(env, ARM_FEATURE_PXN)) {
7083             pxn = (desc >> 2) & 1;
7084         }
7085         ns = extract32(desc, 3, 1);
7086         /* Lookup l2 entry.  */
7087         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
7088         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7089                            mmu_idx, fsr, fi);
7090         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
7091         switch (desc & 3) {
7092         case 0: /* Page translation fault.  */
7093             code = 7;
7094             goto do_fault;
7095         case 1: /* 64k page.  */
7096             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
7097             xn = desc & (1 << 15);
7098             *page_size = 0x10000;
7099             break;
7100         case 2: case 3: /* 4k page.  */
7101             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7102             xn = desc & 1;
7103             *page_size = 0x1000;
7104             break;
7105         default:
7106             /* Never happens, but compiler isn't smart enough to tell.  */
7107             abort();
7108         }
7109         code = 15;
7110     }
7111     if (domain_prot == 3) {
7112         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7113     } else {
7114         if (pxn && !regime_is_user(env, mmu_idx)) {
7115             xn = 1;
7116         }
7117         if (xn && access_type == 2)
7118             goto do_fault;
7119
7120         if (arm_feature(env, ARM_FEATURE_V6K) &&
7121                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
7122             /* The simplified model uses AP[0] as an access control bit.  */
7123             if ((ap & 1) == 0) {
7124                 /* Access flag fault.  */
7125                 code = (code == 15) ? 6 : 3;
7126                 goto do_fault;
7127             }
7128             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
7129         } else {
7130             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7131         }
7132         if (*prot && !xn) {
7133             *prot |= PAGE_EXEC;
7134         }
7135         if (!(*prot & (1 << access_type))) {
7136             /* Access permission fault.  */
7137             goto do_fault;
7138         }
7139     }
7140     if (ns) {
7141         /* The NS bit will (as required by the architecture) have no effect if
7142          * the CPU doesn't support TZ or this is a non-secure translation
7143          * regime, because the attribute will already be non-secure.
7144          */
7145         attrs->secure = false;
7146     }
7147     *phys_ptr = phys_addr;
7148     return false;
7149 do_fault:
7150     *fsr = code | (domain << 4);
7151     return true;
7152 }
7153
7154 /* Fault type for long-descriptor MMU fault reporting; this corresponds
7155  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
7156  */
7157 typedef enum {
7158     translation_fault = 1,
7159     access_fault = 2,
7160     permission_fault = 3,
7161 } MMUFaultType;
7162
7163 /*
7164  * check_s2_mmu_setup
7165  * @cpu:        ARMCPU
7166  * @is_aa64:    True if the translation regime is in AArch64 state
7167  * @startlevel: Suggested starting level
7168  * @inputsize:  Bitsize of IPAs
7169  * @stride:     Page-table stride (See the ARM ARM)
7170  *
7171  * Returns true if the suggested S2 translation parameters are OK and
7172  * false otherwise.
7173  */
7174 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
7175                                int inputsize, int stride)
7176 {
7177     const int grainsize = stride + 3;
7178     int startsizecheck;
7179
7180     /* Negative levels are never allowed.  */
7181     if (level < 0) {
7182         return false;
7183     }
7184
7185     startsizecheck = inputsize - ((3 - level) * stride + grainsize);
7186     if (startsizecheck < 1 || startsizecheck > stride + 4) {
7187         return false;
7188     }
7189
7190     if (is_aa64) {
7191         CPUARMState *env = &cpu->env;
7192         unsigned int pamax = arm_pamax(cpu);
7193
7194         switch (stride) {
7195         case 13: /* 64KB Pages.  */
7196             if (level == 0 || (level == 1 && pamax <= 42)) {
7197                 return false;
7198             }
7199             break;
7200         case 11: /* 16KB Pages.  */
7201             if (level == 0 || (level == 1 && pamax <= 40)) {
7202                 return false;
7203             }
7204             break;
7205         case 9: /* 4KB Pages.  */
7206             if (level == 0 && pamax <= 42) {
7207                 return false;
7208             }
7209             break;
7210         default:
7211             g_assert_not_reached();
7212         }
7213
7214         /* Inputsize checks.  */
7215         if (inputsize > pamax &&
7216             (arm_el_is_aa64(env, 1) || inputsize > 40)) {
7217             /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
7218             return false;
7219         }
7220     } else {
7221         /* AArch32 only supports 4KB pages. Assert on that.  */
7222         assert(stride == 9);
7223
7224         if (level == 0) {
7225             return false;
7226         }
7227     }
7228     return true;
7229 }
7230
7231 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
7232                                int access_type, ARMMMUIdx mmu_idx,
7233                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
7234                                target_ulong *page_size_ptr, uint32_t *fsr,
7235                                ARMMMUFaultInfo *fi)
7236 {
7237     ARMCPU *cpu = arm_env_get_cpu(env);
7238     CPUState *cs = CPU(cpu);
7239     /* Read an LPAE long-descriptor translation table. */
7240     MMUFaultType fault_type = translation_fault;
7241     uint32_t level;
7242     uint32_t epd = 0;
7243     int32_t t0sz, t1sz;
7244     uint32_t tg;
7245     uint64_t ttbr;
7246     int ttbr_select;
7247     hwaddr descaddr, descmask;
7248     uint32_t tableattrs;
7249     target_ulong page_size;
7250     uint32_t attrs;
7251     int32_t stride = 9;
7252     int32_t va_size;
7253     int inputsize;
7254     int32_t tbi = 0;
7255     TCR *tcr = regime_tcr(env, mmu_idx);
7256     int ap, ns, xn, pxn;
7257     uint32_t el = regime_el(env, mmu_idx);
7258     bool ttbr1_valid = true;
7259     uint64_t descaddrmask;
7260
7261     /* TODO:
7262      * This code does not handle the different format TCR for VTCR_EL2.
7263      * This code also does not support shareability levels.
7264      * Attribute and permission bit handling should also be checked when adding
7265      * support for those page table walks.
7266      */
7267     if (arm_el_is_aa64(env, el)) {
7268         level = 0;
7269         va_size = 64;
7270         if (el > 1) {
7271             if (mmu_idx != ARMMMUIdx_S2NS) {
7272                 tbi = extract64(tcr->raw_tcr, 20, 1);
7273             }
7274         } else {
7275             if (extract64(address, 55, 1)) {
7276                 tbi = extract64(tcr->raw_tcr, 38, 1);
7277             } else {
7278                 tbi = extract64(tcr->raw_tcr, 37, 1);
7279             }
7280         }
7281         tbi *= 8;
7282
7283         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
7284          * invalid.
7285          */
7286         if (el > 1) {
7287             ttbr1_valid = false;
7288         }
7289     } else {
7290         level = 1;
7291         va_size = 32;
7292         /* There is no TTBR1 for EL2 */
7293         if (el == 2) {
7294             ttbr1_valid = false;
7295         }
7296     }
7297
7298     /* Determine whether this address is in the region controlled by
7299      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7300      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7301      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7302      */
7303     if (va_size == 64) {
7304         /* AArch64 translation.  */
7305         t0sz = extract32(tcr->raw_tcr, 0, 6);
7306         t0sz = MIN(t0sz, 39);
7307         t0sz = MAX(t0sz, 16);
7308     } else if (mmu_idx != ARMMMUIdx_S2NS) {
7309         /* AArch32 stage 1 translation.  */
7310         t0sz = extract32(tcr->raw_tcr, 0, 3);
7311     } else {
7312         /* AArch32 stage 2 translation.  */
7313         bool sext = extract32(tcr->raw_tcr, 4, 1);
7314         bool sign = extract32(tcr->raw_tcr, 3, 1);
7315         t0sz = sextract32(tcr->raw_tcr, 0, 4);
7316
7317         /* If the sign-extend bit is not the same as t0sz[3], the result
7318          * is unpredictable. Flag this as a guest error.  */
7319         if (sign != sext) {
7320             qemu_log_mask(LOG_GUEST_ERROR,
7321                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
7322         }
7323     }
7324     t1sz = extract32(tcr->raw_tcr, 16, 6);
7325     if (va_size == 64) {
7326         t1sz = MIN(t1sz, 39);
7327         t1sz = MAX(t1sz, 16);
7328     }
7329     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
7330         /* there is a ttbr0 region and we are in it (high bits all zero) */
7331         ttbr_select = 0;
7332     } else if (ttbr1_valid && t1sz &&
7333                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
7334         /* there is a ttbr1 region and we are in it (high bits all one) */
7335         ttbr_select = 1;
7336     } else if (!t0sz) {
7337         /* ttbr0 region is "everything not in the ttbr1 region" */
7338         ttbr_select = 0;
7339     } else if (!t1sz && ttbr1_valid) {
7340         /* ttbr1 region is "everything not in the ttbr0 region" */
7341         ttbr_select = 1;
7342     } else {
7343         /* in the gap between the two regions, this is a Translation fault */
7344         fault_type = translation_fault;
7345         goto do_fault;
7346     }
7347
7348     /* Note that QEMU ignores shareability and cacheability attributes,
7349      * so we don't need to do anything with the SH, ORGN, IRGN fields
7350      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
7351      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7352      * implement any ASID-like capability so we can ignore it (instead
7353      * we will always flush the TLB any time the ASID is changed).
7354      */
7355     if (ttbr_select == 0) {
7356         ttbr = regime_ttbr(env, mmu_idx, 0);
7357         if (el < 2) {
7358             epd = extract32(tcr->raw_tcr, 7, 1);
7359         }
7360         inputsize = va_size - t0sz;
7361
7362         tg = extract32(tcr->raw_tcr, 14, 2);
7363         if (tg == 1) { /* 64KB pages */
7364             stride = 13;
7365         }
7366         if (tg == 2) { /* 16KB pages */
7367             stride = 11;
7368         }
7369     } else {
7370         /* We should only be here if TTBR1 is valid */
7371         assert(ttbr1_valid);
7372
7373         ttbr = regime_ttbr(env, mmu_idx, 1);
7374         epd = extract32(tcr->raw_tcr, 23, 1);
7375         inputsize = va_size - t1sz;
7376
7377         tg = extract32(tcr->raw_tcr, 30, 2);
7378         if (tg == 3)  { /* 64KB pages */
7379             stride = 13;
7380         }
7381         if (tg == 1) { /* 16KB pages */
7382             stride = 11;
7383         }
7384     }
7385
7386     /* Here we should have set up all the parameters for the translation:
7387      * va_size, inputsize, ttbr, epd, stride, tbi
7388      */
7389
7390     if (epd) {
7391         /* Translation table walk disabled => Translation fault on TLB miss
7392          * Note: This is always 0 on 64-bit EL2 and EL3.
7393          */
7394         goto do_fault;
7395     }
7396
7397     if (mmu_idx != ARMMMUIdx_S2NS) {
7398         /* The starting level depends on the virtual address size (which can
7399          * be up to 48 bits) and the translation granule size. It indicates
7400          * the number of strides (stride bits at a time) needed to
7401          * consume the bits of the input address. In the pseudocode this is:
7402          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
7403          * where their 'inputsize' is our 'inputsize', 'grainsize' is
7404          * our 'stride + 3' and 'stride' is our 'stride'.
7405          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
7406          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
7407          * = 4 - (inputsize - 4) / stride;
7408          */
7409         level = 4 - (inputsize - 4) / stride;
7410     } else {
7411         /* For stage 2 translations the starting level is specified by the
7412          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7413          */
7414         uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
7415         uint32_t startlevel;
7416         bool ok;
7417
7418         if (va_size == 32 || stride == 9) {
7419             /* AArch32 or 4KB pages */
7420             startlevel = 2 - sl0;
7421         } else {
7422             /* 16KB or 64KB pages */
7423             startlevel = 3 - sl0;
7424         }
7425
7426         /* Check that the starting level is valid. */
7427         ok = check_s2_mmu_setup(cpu, va_size == 64, startlevel,
7428                                 inputsize, stride);
7429         if (!ok) {
7430             fault_type = translation_fault;
7431             goto do_fault;
7432         }
7433         level = startlevel;
7434     }
7435
7436     /* Clear the vaddr bits which aren't part of the within-region address,
7437      * so that we don't have to special case things when calculating the
7438      * first descriptor address.
7439      */
7440     if (va_size != inputsize) {
7441         address &= (1ULL << inputsize) - 1;
7442     }
7443
7444     descmask = (1ULL << (stride + 3)) - 1;
7445
7446     /* Now we can extract the actual base address from the TTBR */
7447     descaddr = extract64(ttbr, 0, 48);
7448     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
7449
7450     /* The address field in the descriptor goes up to bit 39 for ARMv7
7451      * but up to bit 47 for ARMv8.
7452      */
7453     if (arm_feature(env, ARM_FEATURE_V8)) {
7454         descaddrmask = 0xfffffffff000ULL;
7455     } else {
7456         descaddrmask = 0xfffffff000ULL;
7457     }
7458
7459     /* Secure accesses start with the page table in secure memory and
7460      * can be downgraded to non-secure at any step. Non-secure accesses
7461      * remain non-secure. We implement this by just ORing in the NSTable/NS
7462      * bits at each step.
7463      */
7464     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7465     for (;;) {
7466         uint64_t descriptor;
7467         bool nstable;
7468
7469         descaddr |= (address >> (stride * (4 - level))) & descmask;
7470         descaddr &= ~7ULL;
7471         nstable = extract32(tableattrs, 4, 1);
7472         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7473         if (fi->s1ptw) {
7474             goto do_fault;
7475         }
7476
7477         if (!(descriptor & 1) ||
7478             (!(descriptor & 2) && (level == 3))) {
7479             /* Invalid, or the Reserved level 3 encoding */
7480             goto do_fault;
7481         }
7482         descaddr = descriptor & descaddrmask;
7483
7484         if ((descriptor & 2) && (level < 3)) {
7485             /* Table entry. The top five bits are attributes which  may
7486              * propagate down through lower levels of the table (and
7487              * which are all arranged so that 0 means "no effect", so
7488              * we can gather them up by ORing in the bits at each level).
7489              */
7490             tableattrs |= extract64(descriptor, 59, 5);
7491             level++;
7492             continue;
7493         }
7494         /* Block entry at level 1 or 2, or page entry at level 3.
7495          * These are basically the same thing, although the number
7496          * of bits we pull in from the vaddr varies.
7497          */
7498         page_size = (1ULL << ((stride * (4 - level)) + 3));
7499         descaddr |= (address & (page_size - 1));
7500         /* Extract attributes from the descriptor */
7501         attrs = extract64(descriptor, 2, 10)
7502             | (extract64(descriptor, 52, 12) << 10);
7503
7504         if (mmu_idx == ARMMMUIdx_S2NS) {
7505             /* Stage 2 table descriptors do not include any attribute fields */
7506             break;
7507         }
7508         /* Merge in attributes from table descriptors */
7509         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7510         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7511         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7512          * means "force PL1 access only", which means forcing AP[1] to 0.
7513          */
7514         if (extract32(tableattrs, 2, 1)) {
7515             attrs &= ~(1 << 4);
7516         }
7517         attrs |= nstable << 3; /* NS */
7518         break;
7519     }
7520     /* Here descaddr is the final physical address, and attributes
7521      * are all in attrs.
7522      */
7523     fault_type = access_fault;
7524     if ((attrs & (1 << 8)) == 0) {
7525         /* Access flag */
7526         goto do_fault;
7527     }
7528
7529     ap = extract32(attrs, 4, 2);
7530     xn = extract32(attrs, 12, 1);
7531
7532     if (mmu_idx == ARMMMUIdx_S2NS) {
7533         ns = true;
7534         *prot = get_S2prot(env, ap, xn);
7535     } else {
7536         ns = extract32(attrs, 3, 1);
7537         pxn = extract32(attrs, 11, 1);
7538         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
7539     }
7540
7541     fault_type = permission_fault;
7542     if (!(*prot & (1 << access_type))) {
7543         goto do_fault;
7544     }
7545
7546     if (ns) {
7547         /* The NS bit will (as required by the architecture) have no effect if
7548          * the CPU doesn't support TZ or this is a non-secure translation
7549          * regime, because the attribute will already be non-secure.
7550          */
7551         txattrs->secure = false;
7552     }
7553     *phys_ptr = descaddr;
7554     *page_size_ptr = page_size;
7555     return false;
7556
7557 do_fault:
7558     /* Long-descriptor format IFSR/DFSR value */
7559     *fsr = (1 << 9) | (fault_type << 2) | level;
7560     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
7561     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7562     return true;
7563 }
7564
7565 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7566                                                 ARMMMUIdx mmu_idx,
7567                                                 int32_t address, int *prot)
7568 {
7569     *prot = PAGE_READ | PAGE_WRITE;
7570     switch (address) {
7571     case 0xF0000000 ... 0xFFFFFFFF:
7572         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7573             *prot |= PAGE_EXEC;
7574         }
7575         break;
7576     case 0x00000000 ... 0x7FFFFFFF:
7577         *prot |= PAGE_EXEC;
7578         break;
7579     }
7580
7581 }
7582
7583 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7584                                  int access_type, ARMMMUIdx mmu_idx,
7585                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7586 {
7587     ARMCPU *cpu = arm_env_get_cpu(env);
7588     int n;
7589     bool is_user = regime_is_user(env, mmu_idx);
7590
7591     *phys_ptr = address;
7592     *prot = 0;
7593
7594     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7595         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7596     } else { /* MPU enabled */
7597         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7598             /* region search */
7599             uint32_t base = env->pmsav7.drbar[n];
7600             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7601             uint32_t rmask;
7602             bool srdis = false;
7603
7604             if (!(env->pmsav7.drsr[n] & 0x1)) {
7605                 continue;
7606             }
7607
7608             if (!rsize) {
7609                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7610                 continue;
7611             }
7612             rsize++;
7613             rmask = (1ull << rsize) - 1;
7614
7615             if (base & rmask) {
7616                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7617                               "to DRSR region size, mask = %" PRIx32,
7618                               base, rmask);
7619                 continue;
7620             }
7621
7622             if (address < base || address > base + rmask) {
7623                 continue;
7624             }
7625
7626             /* Region matched */
7627
7628             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7629                 int i, snd;
7630                 uint32_t srdis_mask;
7631
7632                 rsize -= 3; /* sub region size (power of 2) */
7633                 snd = ((address - base) >> rsize) & 0x7;
7634                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7635
7636                 srdis_mask = srdis ? 0x3 : 0x0;
7637                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7638                     /* This will check in groups of 2, 4 and then 8, whether
7639                      * the subregion bits are consistent. rsize is incremented
7640                      * back up to give the region size, considering consistent
7641                      * adjacent subregions as one region. Stop testing if rsize
7642                      * is already big enough for an entire QEMU page.
7643                      */
7644                     int snd_rounded = snd & ~(i - 1);
7645                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7646                                                      snd_rounded + 8, i);
7647                     if (srdis_mask ^ srdis_multi) {
7648                         break;
7649                     }
7650                     srdis_mask = (srdis_mask << i) | srdis_mask;
7651                     rsize++;
7652                 }
7653             }
7654             if (rsize < TARGET_PAGE_BITS) {
7655                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7656                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7657                               rsize, TARGET_PAGE_BITS);
7658                 continue;
7659             }
7660             if (srdis) {
7661                 continue;
7662             }
7663             break;
7664         }
7665
7666         if (n == -1) { /* no hits */
7667             if (cpu->pmsav7_dregion &&
7668                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7669                 /* background fault */
7670                 *fsr = 0;
7671                 return true;
7672             }
7673             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7674         } else { /* a MPU hit! */
7675             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7676
7677             if (is_user) { /* User mode AP bit decoding */
7678                 switch (ap) {
7679                 case 0:
7680                 case 1:
7681                 case 5:
7682                     break; /* no access */
7683                 case 3:
7684                     *prot |= PAGE_WRITE;
7685                     /* fall through */
7686                 case 2:
7687                 case 6:
7688                     *prot |= PAGE_READ | PAGE_EXEC;
7689                     break;
7690                 default:
7691                     qemu_log_mask(LOG_GUEST_ERROR,
7692                                   "Bad value for AP bits in DRACR %"
7693                                   PRIx32 "\n", ap);
7694                 }
7695             } else { /* Priv. mode AP bits decoding */
7696                 switch (ap) {
7697                 case 0:
7698                     break; /* no access */
7699                 case 1:
7700                 case 2:
7701                 case 3:
7702                     *prot |= PAGE_WRITE;
7703                     /* fall through */
7704                 case 5:
7705                 case 6:
7706                     *prot |= PAGE_READ | PAGE_EXEC;
7707                     break;
7708                 default:
7709                     qemu_log_mask(LOG_GUEST_ERROR,
7710                                   "Bad value for AP bits in DRACR %"
7711                                   PRIx32 "\n", ap);
7712                 }
7713             }
7714
7715             /* execute never */
7716             if (env->pmsav7.dracr[n] & (1 << 12)) {
7717                 *prot &= ~PAGE_EXEC;
7718             }
7719         }
7720     }
7721
7722     *fsr = 0x00d; /* Permission fault */
7723     return !(*prot & (1 << access_type));
7724 }
7725
7726 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7727                                  int access_type, ARMMMUIdx mmu_idx,
7728                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7729 {
7730     int n;
7731     uint32_t mask;
7732     uint32_t base;
7733     bool is_user = regime_is_user(env, mmu_idx);
7734
7735     *phys_ptr = address;
7736     for (n = 7; n >= 0; n--) {
7737         base = env->cp15.c6_region[n];
7738         if ((base & 1) == 0) {
7739             continue;
7740         }
7741         mask = 1 << ((base >> 1) & 0x1f);
7742         /* Keep this shift separate from the above to avoid an
7743            (undefined) << 32.  */
7744         mask = (mask << 1) - 1;
7745         if (((base ^ address) & ~mask) == 0) {
7746             break;
7747         }
7748     }
7749     if (n < 0) {
7750         *fsr = 2;
7751         return true;
7752     }
7753
7754     if (access_type == 2) {
7755         mask = env->cp15.pmsav5_insn_ap;
7756     } else {
7757         mask = env->cp15.pmsav5_data_ap;
7758     }
7759     mask = (mask >> (n * 4)) & 0xf;
7760     switch (mask) {
7761     case 0:
7762         *fsr = 1;
7763         return true;
7764     case 1:
7765         if (is_user) {
7766             *fsr = 1;
7767             return true;
7768         }
7769         *prot = PAGE_READ | PAGE_WRITE;
7770         break;
7771     case 2:
7772         *prot = PAGE_READ;
7773         if (!is_user) {
7774             *prot |= PAGE_WRITE;
7775         }
7776         break;
7777     case 3:
7778         *prot = PAGE_READ | PAGE_WRITE;
7779         break;
7780     case 5:
7781         if (is_user) {
7782             *fsr = 1;
7783             return true;
7784         }
7785         *prot = PAGE_READ;
7786         break;
7787     case 6:
7788         *prot = PAGE_READ;
7789         break;
7790     default:
7791         /* Bad permission.  */
7792         *fsr = 1;
7793         return true;
7794     }
7795     *prot |= PAGE_EXEC;
7796     return false;
7797 }
7798
7799 /* get_phys_addr - get the physical address for this virtual address
7800  *
7801  * Find the physical address corresponding to the given virtual address,
7802  * by doing a translation table walk on MMU based systems or using the
7803  * MPU state on MPU based systems.
7804  *
7805  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7806  * prot and page_size may not be filled in, and the populated fsr value provides
7807  * information on why the translation aborted, in the format of a
7808  * DFSR/IFSR fault register, with the following caveats:
7809  *  * we honour the short vs long DFSR format differences.
7810  *  * the WnR bit is never set (the caller must do this).
7811  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7812  *    value.
7813  *
7814  * @env: CPUARMState
7815  * @address: virtual address to get physical address for
7816  * @access_type: 0 for read, 1 for write, 2 for execute
7817  * @mmu_idx: MMU index indicating required translation regime
7818  * @phys_ptr: set to the physical address corresponding to the virtual address
7819  * @attrs: set to the memory transaction attributes to use
7820  * @prot: set to the permissions for the page containing phys_ptr
7821  * @page_size: set to the size of the page containing phys_ptr
7822  * @fsr: set to the DFSR/IFSR value on failure
7823  */
7824 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7825                           int access_type, ARMMMUIdx mmu_idx,
7826                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7827                           target_ulong *page_size, uint32_t *fsr,
7828                           ARMMMUFaultInfo *fi)
7829 {
7830     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7831         /* Call ourselves recursively to do the stage 1 and then stage 2
7832          * translations.
7833          */
7834         if (arm_feature(env, ARM_FEATURE_EL2)) {
7835             hwaddr ipa;
7836             int s2_prot;
7837             int ret;
7838
7839             ret = get_phys_addr(env, address, access_type,
7840                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7841                                 prot, page_size, fsr, fi);
7842
7843             /* If S1 fails or S2 is disabled, return early.  */
7844             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7845                 *phys_ptr = ipa;
7846                 return ret;
7847             }
7848
7849             /* S1 is done. Now do S2 translation.  */
7850             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7851                                      phys_ptr, attrs, &s2_prot,
7852                                      page_size, fsr, fi);
7853             fi->s2addr = ipa;
7854             /* Combine the S1 and S2 perms.  */
7855             *prot &= s2_prot;
7856             return ret;
7857         } else {
7858             /*
7859              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7860              */
7861             mmu_idx += ARMMMUIdx_S1NSE0;
7862         }
7863     }
7864
7865     /* The page table entries may downgrade secure to non-secure, but
7866      * cannot upgrade an non-secure translation regime's attributes
7867      * to secure.
7868      */
7869     attrs->secure = regime_is_secure(env, mmu_idx);
7870     attrs->user = regime_is_user(env, mmu_idx);
7871
7872     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7873      * In v7 and earlier it affects all stage 1 translations.
7874      */
7875     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7876         && !arm_feature(env, ARM_FEATURE_V8)) {
7877         if (regime_el(env, mmu_idx) == 3) {
7878             address += env->cp15.fcseidr_s;
7879         } else {
7880             address += env->cp15.fcseidr_ns;
7881         }
7882     }
7883
7884     /* pmsav7 has special handling for when MPU is disabled so call it before
7885      * the common MMU/MPU disabled check below.
7886      */
7887     if (arm_feature(env, ARM_FEATURE_MPU) &&
7888         arm_feature(env, ARM_FEATURE_V7)) {
7889         *page_size = TARGET_PAGE_SIZE;
7890         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7891                                     phys_ptr, prot, fsr);
7892     }
7893
7894     if (regime_translation_disabled(env, mmu_idx)) {
7895         /* MMU/MPU disabled.  */
7896         *phys_ptr = address;
7897         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7898         *page_size = TARGET_PAGE_SIZE;
7899         return 0;
7900     }
7901
7902     if (arm_feature(env, ARM_FEATURE_MPU)) {
7903         /* Pre-v7 MPU */
7904         *page_size = TARGET_PAGE_SIZE;
7905         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7906                                     phys_ptr, prot, fsr);
7907     }
7908
7909     if (regime_using_lpae_format(env, mmu_idx)) {
7910         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7911                                   attrs, prot, page_size, fsr, fi);
7912     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7913         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7914                                 attrs, prot, page_size, fsr, fi);
7915     } else {
7916         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7917                                 prot, page_size, fsr, fi);
7918     }
7919 }
7920
7921 /* Walk the page table and (if the mapping exists) add the page
7922  * to the TLB. Return false on success, or true on failure. Populate
7923  * fsr with ARM DFSR/IFSR fault register format value on failure.
7924  */
7925 bool arm_tlb_fill(CPUState *cs, vaddr address,
7926                   int access_type, int mmu_idx, uint32_t *fsr,
7927                   ARMMMUFaultInfo *fi)
7928 {
7929     ARMCPU *cpu = ARM_CPU(cs);
7930     CPUARMState *env = &cpu->env;
7931     hwaddr phys_addr;
7932     target_ulong page_size;
7933     int prot;
7934     int ret;
7935     MemTxAttrs attrs = {};
7936
7937     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7938                         &attrs, &prot, &page_size, fsr, fi);
7939     if (!ret) {
7940         /* Map a single [sub]page.  */
7941         phys_addr &= TARGET_PAGE_MASK;
7942         address &= TARGET_PAGE_MASK;
7943         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7944                                 prot, mmu_idx, page_size);
7945         return 0;
7946     }
7947
7948     return ret;
7949 }
7950
7951 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7952                                          MemTxAttrs *attrs)
7953 {
7954     ARMCPU *cpu = ARM_CPU(cs);
7955     CPUARMState *env = &cpu->env;
7956     hwaddr phys_addr;
7957     target_ulong page_size;
7958     int prot;
7959     bool ret;
7960     uint32_t fsr;
7961     ARMMMUFaultInfo fi = {};
7962
7963     *attrs = (MemTxAttrs) {};
7964
7965     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7966                         attrs, &prot, &page_size, &fsr, &fi);
7967
7968     if (ret) {
7969         return -1;
7970     }
7971     return phys_addr;
7972 }
7973
7974 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7975 {
7976     ARMCPU *cpu = arm_env_get_cpu(env);
7977
7978     switch (reg) {
7979     case 0: /* APSR */
7980         return xpsr_read(env) & 0xf8000000;
7981     case 1: /* IAPSR */
7982         return xpsr_read(env) & 0xf80001ff;
7983     case 2: /* EAPSR */
7984         return xpsr_read(env) & 0xff00fc00;
7985     case 3: /* xPSR */
7986         return xpsr_read(env) & 0xff00fdff;
7987     case 5: /* IPSR */
7988         return xpsr_read(env) & 0x000001ff;
7989     case 6: /* EPSR */
7990         return xpsr_read(env) & 0x0700fc00;
7991     case 7: /* IEPSR */
7992         return xpsr_read(env) & 0x0700edff;
7993     case 8: /* MSP */
7994         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7995     case 9: /* PSP */
7996         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7997     case 16: /* PRIMASK */
7998         return (env->daif & PSTATE_I) != 0;
7999     case 17: /* BASEPRI */
8000     case 18: /* BASEPRI_MAX */
8001         return env->v7m.basepri;
8002     case 19: /* FAULTMASK */
8003         return (env->daif & PSTATE_F) != 0;
8004     case 20: /* CONTROL */
8005         return env->v7m.control;
8006     default:
8007         /* ??? For debugging only.  */
8008         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
8009         return 0;
8010     }
8011 }
8012
8013 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
8014 {
8015     ARMCPU *cpu = arm_env_get_cpu(env);
8016
8017     switch (reg) {
8018     case 0: /* APSR */
8019         xpsr_write(env, val, 0xf8000000);
8020         break;
8021     case 1: /* IAPSR */
8022         xpsr_write(env, val, 0xf8000000);
8023         break;
8024     case 2: /* EAPSR */
8025         xpsr_write(env, val, 0xfe00fc00);
8026         break;
8027     case 3: /* xPSR */
8028         xpsr_write(env, val, 0xfe00fc00);
8029         break;
8030     case 5: /* IPSR */
8031         /* IPSR bits are readonly.  */
8032         break;
8033     case 6: /* EPSR */
8034         xpsr_write(env, val, 0x0600fc00);
8035         break;
8036     case 7: /* IEPSR */
8037         xpsr_write(env, val, 0x0600fc00);
8038         break;
8039     case 8: /* MSP */
8040         if (env->v7m.current_sp)
8041             env->v7m.other_sp = val;
8042         else
8043             env->regs[13] = val;
8044         break;
8045     case 9: /* PSP */
8046         if (env->v7m.current_sp)
8047             env->regs[13] = val;
8048         else
8049             env->v7m.other_sp = val;
8050         break;
8051     case 16: /* PRIMASK */
8052         if (val & 1) {
8053             env->daif |= PSTATE_I;
8054         } else {
8055             env->daif &= ~PSTATE_I;
8056         }
8057         break;
8058     case 17: /* BASEPRI */
8059         env->v7m.basepri = val & 0xff;
8060         break;
8061     case 18: /* BASEPRI_MAX */
8062         val &= 0xff;
8063         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
8064             env->v7m.basepri = val;
8065         break;
8066     case 19: /* FAULTMASK */
8067         if (val & 1) {
8068             env->daif |= PSTATE_F;
8069         } else {
8070             env->daif &= ~PSTATE_F;
8071         }
8072         break;
8073     case 20: /* CONTROL */
8074         env->v7m.control = val & 3;
8075         switch_v7m_sp(env, (val & 2) != 0);
8076         break;
8077     default:
8078         /* ??? For debugging only.  */
8079         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
8080         return;
8081     }
8082 }
8083
8084 #endif
8085
8086 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
8087 {
8088     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
8089      * Note that we do not implement the (architecturally mandated)
8090      * alignment fault for attempts to use this on Device memory
8091      * (which matches the usual QEMU behaviour of not implementing either
8092      * alignment faults or any memory attribute handling).
8093      */
8094
8095     ARMCPU *cpu = arm_env_get_cpu(env);
8096     uint64_t blocklen = 4 << cpu->dcz_blocksize;
8097     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
8098
8099 #ifndef CONFIG_USER_ONLY
8100     {
8101         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
8102          * the block size so we might have to do more than one TLB lookup.
8103          * We know that in fact for any v8 CPU the page size is at least 4K
8104          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
8105          * 1K as an artefact of legacy v5 subpage support being present in the
8106          * same QEMU executable.
8107          */
8108         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
8109         void *hostaddr[maxidx];
8110         int try, i;
8111         unsigned mmu_idx = cpu_mmu_index(env, false);
8112         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
8113
8114         for (try = 0; try < 2; try++) {
8115
8116             for (i = 0; i < maxidx; i++) {
8117                 hostaddr[i] = tlb_vaddr_to_host(env,
8118                                                 vaddr + TARGET_PAGE_SIZE * i,
8119                                                 1, mmu_idx);
8120                 if (!hostaddr[i]) {
8121                     break;
8122                 }
8123             }
8124             if (i == maxidx) {
8125                 /* If it's all in the TLB it's fair game for just writing to;
8126                  * we know we don't need to update dirty status, etc.
8127                  */
8128                 for (i = 0; i < maxidx - 1; i++) {
8129                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
8130                 }
8131                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
8132                 return;
8133             }
8134             /* OK, try a store and see if we can populate the tlb. This
8135              * might cause an exception if the memory isn't writable,
8136              * in which case we will longjmp out of here. We must for
8137              * this purpose use the actual register value passed to us
8138              * so that we get the fault address right.
8139              */
8140             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
8141             /* Now we can populate the other TLB entries, if any */
8142             for (i = 0; i < maxidx; i++) {
8143                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
8144                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
8145                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
8146                 }
8147             }
8148         }
8149
8150         /* Slow path (probably attempt to do this to an I/O device or
8151          * similar, or clearing of a block of code we have translations
8152          * cached for). Just do a series of byte writes as the architecture
8153          * demands. It's not worth trying to use a cpu_physical_memory_map(),
8154          * memset(), unmap() sequence here because:
8155          *  + we'd need to account for the blocksize being larger than a page
8156          *  + the direct-RAM access case is almost always going to be dealt
8157          *    with in the fastpath code above, so there's no speed benefit
8158          *  + we would have to deal with the map returning NULL because the
8159          *    bounce buffer was in use
8160          */
8161         for (i = 0; i < blocklen; i++) {
8162             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
8163         }
8164     }
8165 #else
8166     memset(g2h(vaddr), 0, blocklen);
8167 #endif
8168 }
8169
8170 /* Note that signed overflow is undefined in C.  The following routines are
8171    careful to use unsigned types where modulo arithmetic is required.
8172    Failure to do so _will_ break on newer gcc.  */
8173
8174 /* Signed saturating arithmetic.  */
8175
8176 /* Perform 16-bit signed saturating addition.  */
8177 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
8178 {
8179     uint16_t res;
8180
8181     res = a + b;
8182     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
8183         if (a & 0x8000)
8184             res = 0x8000;
8185         else
8186             res = 0x7fff;
8187     }
8188     return res;
8189 }
8190
8191 /* Perform 8-bit signed saturating addition.  */
8192 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
8193 {
8194     uint8_t res;
8195
8196     res = a + b;
8197     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
8198         if (a & 0x80)
8199             res = 0x80;
8200         else
8201             res = 0x7f;
8202     }
8203     return res;
8204 }
8205
8206 /* Perform 16-bit signed saturating subtraction.  */
8207 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
8208 {
8209     uint16_t res;
8210
8211     res = a - b;
8212     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
8213         if (a & 0x8000)
8214             res = 0x8000;
8215         else
8216             res = 0x7fff;
8217     }
8218     return res;
8219 }
8220
8221 /* Perform 8-bit signed saturating subtraction.  */
8222 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
8223 {
8224     uint8_t res;
8225
8226     res = a - b;
8227     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
8228         if (a & 0x80)
8229             res = 0x80;
8230         else
8231             res = 0x7f;
8232     }
8233     return res;
8234 }
8235
8236 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
8237 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
8238 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
8239 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
8240 #define PFX q
8241
8242 #include "op_addsub.h"
8243
8244 /* Unsigned saturating arithmetic.  */
8245 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
8246 {
8247     uint16_t res;
8248     res = a + b;
8249     if (res < a)
8250         res = 0xffff;
8251     return res;
8252 }
8253
8254 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
8255 {
8256     if (a > b)
8257         return a - b;
8258     else
8259         return 0;
8260 }
8261
8262 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
8263 {
8264     uint8_t res;
8265     res = a + b;
8266     if (res < a)
8267         res = 0xff;
8268     return res;
8269 }
8270
8271 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
8272 {
8273     if (a > b)
8274         return a - b;
8275     else
8276         return 0;
8277 }
8278
8279 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
8280 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
8281 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
8282 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
8283 #define PFX uq
8284
8285 #include "op_addsub.h"
8286
8287 /* Signed modulo arithmetic.  */
8288 #define SARITH16(a, b, n, op) do { \
8289     int32_t sum; \
8290     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
8291     RESULT(sum, n, 16); \
8292     if (sum >= 0) \
8293         ge |= 3 << (n * 2); \
8294     } while(0)
8295
8296 #define SARITH8(a, b, n, op) do { \
8297     int32_t sum; \
8298     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
8299     RESULT(sum, n, 8); \
8300     if (sum >= 0) \
8301         ge |= 1 << n; \
8302     } while(0)
8303
8304
8305 #define ADD16(a, b, n) SARITH16(a, b, n, +)
8306 #define SUB16(a, b, n) SARITH16(a, b, n, -)
8307 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
8308 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
8309 #define PFX s
8310 #define ARITH_GE
8311
8312 #include "op_addsub.h"
8313
8314 /* Unsigned modulo arithmetic.  */
8315 #define ADD16(a, b, n) do { \
8316     uint32_t sum; \
8317     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
8318     RESULT(sum, n, 16); \
8319     if ((sum >> 16) == 1) \
8320         ge |= 3 << (n * 2); \
8321     } while(0)
8322
8323 #define ADD8(a, b, n) do { \
8324     uint32_t sum; \
8325     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
8326     RESULT(sum, n, 8); \
8327     if ((sum >> 8) == 1) \
8328         ge |= 1 << n; \
8329     } while(0)
8330
8331 #define SUB16(a, b, n) do { \
8332     uint32_t sum; \
8333     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
8334     RESULT(sum, n, 16); \
8335     if ((sum >> 16) == 0) \
8336         ge |= 3 << (n * 2); \
8337     } while(0)
8338
8339 #define SUB8(a, b, n) do { \
8340     uint32_t sum; \
8341     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
8342     RESULT(sum, n, 8); \
8343     if ((sum >> 8) == 0) \
8344         ge |= 1 << n; \
8345     } while(0)
8346
8347 #define PFX u
8348 #define ARITH_GE
8349
8350 #include "op_addsub.h"
8351
8352 /* Halved signed arithmetic.  */
8353 #define ADD16(a, b, n) \
8354   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
8355 #define SUB16(a, b, n) \
8356   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
8357 #define ADD8(a, b, n) \
8358   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
8359 #define SUB8(a, b, n) \
8360   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
8361 #define PFX sh
8362
8363 #include "op_addsub.h"
8364
8365 /* Halved unsigned arithmetic.  */
8366 #define ADD16(a, b, n) \
8367   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8368 #define SUB16(a, b, n) \
8369   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8370 #define ADD8(a, b, n) \
8371   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8372 #define SUB8(a, b, n) \
8373   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8374 #define PFX uh
8375
8376 #include "op_addsub.h"
8377
8378 static inline uint8_t do_usad(uint8_t a, uint8_t b)
8379 {
8380     if (a > b)
8381         return a - b;
8382     else
8383         return b - a;
8384 }
8385
8386 /* Unsigned sum of absolute byte differences.  */
8387 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
8388 {
8389     uint32_t sum;
8390     sum = do_usad(a, b);
8391     sum += do_usad(a >> 8, b >> 8);
8392     sum += do_usad(a >> 16, b >>16);
8393     sum += do_usad(a >> 24, b >> 24);
8394     return sum;
8395 }
8396
8397 /* For ARMv6 SEL instruction.  */
8398 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
8399 {
8400     uint32_t mask;
8401
8402     mask = 0;
8403     if (flags & 1)
8404         mask |= 0xff;
8405     if (flags & 2)
8406         mask |= 0xff00;
8407     if (flags & 4)
8408         mask |= 0xff0000;
8409     if (flags & 8)
8410         mask |= 0xff000000;
8411     return (a & mask) | (b & ~mask);
8412 }
8413
8414 /* VFP support.  We follow the convention used for VFP instructions:
8415    Single precision routines have a "s" suffix, double precision a
8416    "d" suffix.  */
8417
8418 /* Convert host exception flags to vfp form.  */
8419 static inline int vfp_exceptbits_from_host(int host_bits)
8420 {
8421     int target_bits = 0;
8422
8423     if (host_bits & float_flag_invalid)
8424         target_bits |= 1;
8425     if (host_bits & float_flag_divbyzero)
8426         target_bits |= 2;
8427     if (host_bits & float_flag_overflow)
8428         target_bits |= 4;
8429     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8430         target_bits |= 8;
8431     if (host_bits & float_flag_inexact)
8432         target_bits |= 0x10;
8433     if (host_bits & float_flag_input_denormal)
8434         target_bits |= 0x80;
8435     return target_bits;
8436 }
8437
8438 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8439 {
8440     int i;
8441     uint32_t fpscr;
8442
8443     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8444             | (env->vfp.vec_len << 16)
8445             | (env->vfp.vec_stride << 20);
8446     i = get_float_exception_flags(&env->vfp.fp_status);
8447     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8448     fpscr |= vfp_exceptbits_from_host(i);
8449     return fpscr;
8450 }
8451
8452 uint32_t vfp_get_fpscr(CPUARMState *env)
8453 {
8454     return HELPER(vfp_get_fpscr)(env);
8455 }
8456
8457 /* Convert vfp exception flags to target form.  */
8458 static inline int vfp_exceptbits_to_host(int target_bits)
8459 {
8460     int host_bits = 0;
8461
8462     if (target_bits & 1)
8463         host_bits |= float_flag_invalid;
8464     if (target_bits & 2)
8465         host_bits |= float_flag_divbyzero;
8466     if (target_bits & 4)
8467         host_bits |= float_flag_overflow;
8468     if (target_bits & 8)
8469         host_bits |= float_flag_underflow;
8470     if (target_bits & 0x10)
8471         host_bits |= float_flag_inexact;
8472     if (target_bits & 0x80)
8473         host_bits |= float_flag_input_denormal;
8474     return host_bits;
8475 }
8476
8477 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8478 {
8479     int i;
8480     uint32_t changed;
8481
8482     changed = env->vfp.xregs[ARM_VFP_FPSCR];
8483     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8484     env->vfp.vec_len = (val >> 16) & 7;
8485     env->vfp.vec_stride = (val >> 20) & 3;
8486
8487     changed ^= val;
8488     if (changed & (3 << 22)) {
8489         i = (val >> 22) & 3;
8490         switch (i) {
8491         case FPROUNDING_TIEEVEN:
8492             i = float_round_nearest_even;
8493             break;
8494         case FPROUNDING_POSINF:
8495             i = float_round_up;
8496             break;
8497         case FPROUNDING_NEGINF:
8498             i = float_round_down;
8499             break;
8500         case FPROUNDING_ZERO:
8501             i = float_round_to_zero;
8502             break;
8503         }
8504         set_float_rounding_mode(i, &env->vfp.fp_status);
8505     }
8506     if (changed & (1 << 24)) {
8507         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8508         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8509     }
8510     if (changed & (1 << 25))
8511         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8512
8513     i = vfp_exceptbits_to_host(val);
8514     set_float_exception_flags(i, &env->vfp.fp_status);
8515     set_float_exception_flags(0, &env->vfp.standard_fp_status);
8516 }
8517
8518 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8519 {
8520     HELPER(vfp_set_fpscr)(env, val);
8521 }
8522
8523 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8524
8525 #define VFP_BINOP(name) \
8526 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8527 { \
8528     float_status *fpst = fpstp; \
8529     return float32_ ## name(a, b, fpst); \
8530 } \
8531 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8532 { \
8533     float_status *fpst = fpstp; \
8534     return float64_ ## name(a, b, fpst); \
8535 }
8536 VFP_BINOP(add)
8537 VFP_BINOP(sub)
8538 VFP_BINOP(mul)
8539 VFP_BINOP(div)
8540 VFP_BINOP(min)
8541 VFP_BINOP(max)
8542 VFP_BINOP(minnum)
8543 VFP_BINOP(maxnum)
8544 #undef VFP_BINOP
8545
8546 float32 VFP_HELPER(neg, s)(float32 a)
8547 {
8548     return float32_chs(a);
8549 }
8550
8551 float64 VFP_HELPER(neg, d)(float64 a)
8552 {
8553     return float64_chs(a);
8554 }
8555
8556 float32 VFP_HELPER(abs, s)(float32 a)
8557 {
8558     return float32_abs(a);
8559 }
8560
8561 float64 VFP_HELPER(abs, d)(float64 a)
8562 {
8563     return float64_abs(a);
8564 }
8565
8566 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8567 {
8568     return float32_sqrt(a, &env->vfp.fp_status);
8569 }
8570
8571 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8572 {
8573     return float64_sqrt(a, &env->vfp.fp_status);
8574 }
8575
8576 /* XXX: check quiet/signaling case */
8577 #define DO_VFP_cmp(p, type) \
8578 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
8579 { \
8580     uint32_t flags; \
8581     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8582     case 0: flags = 0x6; break; \
8583     case -1: flags = 0x8; break; \
8584     case 1: flags = 0x2; break; \
8585     default: case 2: flags = 0x3; break; \
8586     } \
8587     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8588         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8589 } \
8590 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8591 { \
8592     uint32_t flags; \
8593     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8594     case 0: flags = 0x6; break; \
8595     case -1: flags = 0x8; break; \
8596     case 1: flags = 0x2; break; \
8597     default: case 2: flags = 0x3; break; \
8598     } \
8599     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8600         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8601 }
8602 DO_VFP_cmp(s, float32)
8603 DO_VFP_cmp(d, float64)
8604 #undef DO_VFP_cmp
8605
8606 /* Integer to float and float to integer conversions */
8607
8608 #define CONV_ITOF(name, fsz, sign) \
8609     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8610 { \
8611     float_status *fpst = fpstp; \
8612     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8613 }
8614
8615 #define CONV_FTOI(name, fsz, sign, round) \
8616 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8617 { \
8618     float_status *fpst = fpstp; \
8619     if (float##fsz##_is_any_nan(x)) { \
8620         float_raise(float_flag_invalid, fpst); \
8621         return 0; \
8622     } \
8623     return float##fsz##_to_##sign##int32##round(x, fpst); \
8624 }
8625
8626 #define FLOAT_CONVS(name, p, fsz, sign) \
8627 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8628 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8629 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8630
8631 FLOAT_CONVS(si, s, 32, )
8632 FLOAT_CONVS(si, d, 64, )
8633 FLOAT_CONVS(ui, s, 32, u)
8634 FLOAT_CONVS(ui, d, 64, u)
8635
8636 #undef CONV_ITOF
8637 #undef CONV_FTOI
8638 #undef FLOAT_CONVS
8639
8640 /* floating point conversion */
8641 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8642 {
8643     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8644     /* ARM requires that S<->D conversion of any kind of NaN generates
8645      * a quiet NaN by forcing the most significant frac bit to 1.
8646      */
8647     return float64_maybe_silence_nan(r);
8648 }
8649
8650 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8651 {
8652     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8653     /* ARM requires that S<->D conversion of any kind of NaN generates
8654      * a quiet NaN by forcing the most significant frac bit to 1.
8655      */
8656     return float32_maybe_silence_nan(r);
8657 }
8658
8659 /* VFP3 fixed point conversion.  */
8660 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8661 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8662                                      void *fpstp) \
8663 { \
8664     float_status *fpst = fpstp; \
8665     float##fsz tmp; \
8666     tmp = itype##_to_##float##fsz(x, fpst); \
8667     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8668 }
8669
8670 /* Notice that we want only input-denormal exception flags from the
8671  * scalbn operation: the other possible flags (overflow+inexact if
8672  * we overflow to infinity, output-denormal) aren't correct for the
8673  * complete scale-and-convert operation.
8674  */
8675 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8676 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8677                                              uint32_t shift, \
8678                                              void *fpstp) \
8679 { \
8680     float_status *fpst = fpstp; \
8681     int old_exc_flags = get_float_exception_flags(fpst); \
8682     float##fsz tmp; \
8683     if (float##fsz##_is_any_nan(x)) { \
8684         float_raise(float_flag_invalid, fpst); \
8685         return 0; \
8686     } \
8687     tmp = float##fsz##_scalbn(x, shift, fpst); \
8688     old_exc_flags |= get_float_exception_flags(fpst) \
8689         & float_flag_input_denormal; \
8690     set_float_exception_flags(old_exc_flags, fpst); \
8691     return float##fsz##_to_##itype##round(tmp, fpst); \
8692 }
8693
8694 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8695 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8696 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8697 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8698
8699 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8700 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8701 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8702
8703 VFP_CONV_FIX(sh, d, 64, 64, int16)
8704 VFP_CONV_FIX(sl, d, 64, 64, int32)
8705 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8706 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8707 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8708 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8709 VFP_CONV_FIX(sh, s, 32, 32, int16)
8710 VFP_CONV_FIX(sl, s, 32, 32, int32)
8711 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8712 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8713 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8714 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8715 #undef VFP_CONV_FIX
8716 #undef VFP_CONV_FIX_FLOAT
8717 #undef VFP_CONV_FLOAT_FIX_ROUND
8718
8719 /* Set the current fp rounding mode and return the old one.
8720  * The argument is a softfloat float_round_ value.
8721  */
8722 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8723 {
8724     float_status *fp_status = &env->vfp.fp_status;
8725
8726     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8727     set_float_rounding_mode(rmode, fp_status);
8728
8729     return prev_rmode;
8730 }
8731
8732 /* Set the current fp rounding mode in the standard fp status and return
8733  * the old one. This is for NEON instructions that need to change the
8734  * rounding mode but wish to use the standard FPSCR values for everything
8735  * else. Always set the rounding mode back to the correct value after
8736  * modifying it.
8737  * The argument is a softfloat float_round_ value.
8738  */
8739 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8740 {
8741     float_status *fp_status = &env->vfp.standard_fp_status;
8742
8743     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8744     set_float_rounding_mode(rmode, fp_status);
8745
8746     return prev_rmode;
8747 }
8748
8749 /* Half precision conversions.  */
8750 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8751 {
8752     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8753     float32 r = float16_to_float32(make_float16(a), ieee, s);
8754     if (ieee) {
8755         return float32_maybe_silence_nan(r);
8756     }
8757     return r;
8758 }
8759
8760 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8761 {
8762     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8763     float16 r = float32_to_float16(a, ieee, s);
8764     if (ieee) {
8765         r = float16_maybe_silence_nan(r);
8766     }
8767     return float16_val(r);
8768 }
8769
8770 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8771 {
8772     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8773 }
8774
8775 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8776 {
8777     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8778 }
8779
8780 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8781 {
8782     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8783 }
8784
8785 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8786 {
8787     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8788 }
8789
8790 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8791 {
8792     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8793     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8794     if (ieee) {
8795         return float64_maybe_silence_nan(r);
8796     }
8797     return r;
8798 }
8799
8800 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8801 {
8802     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8803     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8804     if (ieee) {
8805         r = float16_maybe_silence_nan(r);
8806     }
8807     return float16_val(r);
8808 }
8809
8810 #define float32_two make_float32(0x40000000)
8811 #define float32_three make_float32(0x40400000)
8812 #define float32_one_point_five make_float32(0x3fc00000)
8813
8814 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8815 {
8816     float_status *s = &env->vfp.standard_fp_status;
8817     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8818         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8819         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8820             float_raise(float_flag_input_denormal, s);
8821         }
8822         return float32_two;
8823     }
8824     return float32_sub(float32_two, float32_mul(a, b, s), s);
8825 }
8826
8827 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8828 {
8829     float_status *s = &env->vfp.standard_fp_status;
8830     float32 product;
8831     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8832         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8833         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8834             float_raise(float_flag_input_denormal, s);
8835         }
8836         return float32_one_point_five;
8837     }
8838     product = float32_mul(a, b, s);
8839     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8840 }
8841
8842 /* NEON helpers.  */
8843
8844 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8845  * int->float conversions at run-time.  */
8846 #define float64_256 make_float64(0x4070000000000000LL)
8847 #define float64_512 make_float64(0x4080000000000000LL)
8848 #define float32_maxnorm make_float32(0x7f7fffff)
8849 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8850
8851 /* Reciprocal functions
8852  *
8853  * The algorithm that must be used to calculate the estimate
8854  * is specified by the ARM ARM, see FPRecipEstimate()
8855  */
8856
8857 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8858 {
8859     /* These calculations mustn't set any fp exception flags,
8860      * so we use a local copy of the fp_status.
8861      */
8862     float_status dummy_status = *real_fp_status;
8863     float_status *s = &dummy_status;
8864     /* q = (int)(a * 512.0) */
8865     float64 q = float64_mul(float64_512, a, s);
8866     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8867
8868     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8869     q = int64_to_float64(q_int, s);
8870     q = float64_add(q, float64_half, s);
8871     q = float64_div(q, float64_512, s);
8872     q = float64_div(float64_one, q, s);
8873
8874     /* s = (int)(256.0 * r + 0.5) */
8875     q = float64_mul(q, float64_256, s);
8876     q = float64_add(q, float64_half, s);
8877     q_int = float64_to_int64_round_to_zero(q, s);
8878
8879     /* return (double)s / 256.0 */
8880     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8881 }
8882
8883 /* Common wrapper to call recip_estimate */
8884 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8885 {
8886     uint64_t val64 = float64_val(num);
8887     uint64_t frac = extract64(val64, 0, 52);
8888     int64_t exp = extract64(val64, 52, 11);
8889     uint64_t sbit;
8890     float64 scaled, estimate;
8891
8892     /* Generate the scaled number for the estimate function */
8893     if (exp == 0) {
8894         if (extract64(frac, 51, 1) == 0) {
8895             exp = -1;
8896             frac = extract64(frac, 0, 50) << 2;
8897         } else {
8898             frac = extract64(frac, 0, 51) << 1;
8899         }
8900     }
8901
8902     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8903     scaled = make_float64((0x3feULL << 52)
8904                           | extract64(frac, 44, 8) << 44);
8905
8906     estimate = recip_estimate(scaled, fpst);
8907
8908     /* Build new result */
8909     val64 = float64_val(estimate);
8910     sbit = 0x8000000000000000ULL & val64;
8911     exp = off - exp;
8912     frac = extract64(val64, 0, 52);
8913
8914     if (exp == 0) {
8915         frac = 1ULL << 51 | extract64(frac, 1, 51);
8916     } else if (exp == -1) {
8917         frac = 1ULL << 50 | extract64(frac, 2, 50);
8918         exp = 0;
8919     }
8920
8921     return make_float64(sbit | (exp << 52) | frac);
8922 }
8923
8924 static bool round_to_inf(float_status *fpst, bool sign_bit)
8925 {
8926     switch (fpst->float_rounding_mode) {
8927     case float_round_nearest_even: /* Round to Nearest */
8928         return true;
8929     case float_round_up: /* Round to +Inf */
8930         return !sign_bit;
8931     case float_round_down: /* Round to -Inf */
8932         return sign_bit;
8933     case float_round_to_zero: /* Round to Zero */
8934         return false;
8935     }
8936
8937     g_assert_not_reached();
8938 }
8939
8940 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8941 {
8942     float_status *fpst = fpstp;
8943     float32 f32 = float32_squash_input_denormal(input, fpst);
8944     uint32_t f32_val = float32_val(f32);
8945     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8946     int32_t f32_exp = extract32(f32_val, 23, 8);
8947     uint32_t f32_frac = extract32(f32_val, 0, 23);
8948     float64 f64, r64;
8949     uint64_t r64_val;
8950     int64_t r64_exp;
8951     uint64_t r64_frac;
8952
8953     if (float32_is_any_nan(f32)) {
8954         float32 nan = f32;
8955         if (float32_is_signaling_nan(f32)) {
8956             float_raise(float_flag_invalid, fpst);
8957             nan = float32_maybe_silence_nan(f32);
8958         }
8959         if (fpst->default_nan_mode) {
8960             nan =  float32_default_nan;
8961         }
8962         return nan;
8963     } else if (float32_is_infinity(f32)) {
8964         return float32_set_sign(float32_zero, float32_is_neg(f32));
8965     } else if (float32_is_zero(f32)) {
8966         float_raise(float_flag_divbyzero, fpst);
8967         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8968     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8969         /* Abs(value) < 2.0^-128 */
8970         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8971         if (round_to_inf(fpst, f32_sbit)) {
8972             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8973         } else {
8974             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8975         }
8976     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8977         float_raise(float_flag_underflow, fpst);
8978         return float32_set_sign(float32_zero, float32_is_neg(f32));
8979     }
8980
8981
8982     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8983     r64 = call_recip_estimate(f64, 253, fpst);
8984     r64_val = float64_val(r64);
8985     r64_exp = extract64(r64_val, 52, 11);
8986     r64_frac = extract64(r64_val, 0, 52);
8987
8988     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8989     return make_float32(f32_sbit |
8990                         (r64_exp & 0xff) << 23 |
8991                         extract64(r64_frac, 29, 24));
8992 }
8993
8994 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8995 {
8996     float_status *fpst = fpstp;
8997     float64 f64 = float64_squash_input_denormal(input, fpst);
8998     uint64_t f64_val = float64_val(f64);
8999     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
9000     int64_t f64_exp = extract64(f64_val, 52, 11);
9001     float64 r64;
9002     uint64_t r64_val;
9003     int64_t r64_exp;
9004     uint64_t r64_frac;
9005
9006     /* Deal with any special cases */
9007     if (float64_is_any_nan(f64)) {
9008         float64 nan = f64;
9009         if (float64_is_signaling_nan(f64)) {
9010             float_raise(float_flag_invalid, fpst);
9011             nan = float64_maybe_silence_nan(f64);
9012         }
9013         if (fpst->default_nan_mode) {
9014             nan =  float64_default_nan;
9015         }
9016         return nan;
9017     } else if (float64_is_infinity(f64)) {
9018         return float64_set_sign(float64_zero, float64_is_neg(f64));
9019     } else if (float64_is_zero(f64)) {
9020         float_raise(float_flag_divbyzero, fpst);
9021         return float64_set_sign(float64_infinity, float64_is_neg(f64));
9022     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
9023         /* Abs(value) < 2.0^-1024 */
9024         float_raise(float_flag_overflow | float_flag_inexact, fpst);
9025         if (round_to_inf(fpst, f64_sbit)) {
9026             return float64_set_sign(float64_infinity, float64_is_neg(f64));
9027         } else {
9028             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
9029         }
9030     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
9031         float_raise(float_flag_underflow, fpst);
9032         return float64_set_sign(float64_zero, float64_is_neg(f64));
9033     }
9034
9035     r64 = call_recip_estimate(f64, 2045, fpst);
9036     r64_val = float64_val(r64);
9037     r64_exp = extract64(r64_val, 52, 11);
9038     r64_frac = extract64(r64_val, 0, 52);
9039
9040     /* result = sign : result_exp<10:0> : fraction<51:0> */
9041     return make_float64(f64_sbit |
9042                         ((r64_exp & 0x7ff) << 52) |
9043                         r64_frac);
9044 }
9045
9046 /* The algorithm that must be used to calculate the estimate
9047  * is specified by the ARM ARM.
9048  */
9049 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
9050 {
9051     /* These calculations mustn't set any fp exception flags,
9052      * so we use a local copy of the fp_status.
9053      */
9054     float_status dummy_status = *real_fp_status;
9055     float_status *s = &dummy_status;
9056     float64 q;
9057     int64_t q_int;
9058
9059     if (float64_lt(a, float64_half, s)) {
9060         /* range 0.25 <= a < 0.5 */
9061
9062         /* a in units of 1/512 rounded down */
9063         /* q0 = (int)(a * 512.0);  */
9064         q = float64_mul(float64_512, a, s);
9065         q_int = float64_to_int64_round_to_zero(q, s);
9066
9067         /* reciprocal root r */
9068         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
9069         q = int64_to_float64(q_int, s);
9070         q = float64_add(q, float64_half, s);
9071         q = float64_div(q, float64_512, s);
9072         q = float64_sqrt(q, s);
9073         q = float64_div(float64_one, q, s);
9074     } else {
9075         /* range 0.5 <= a < 1.0 */
9076
9077         /* a in units of 1/256 rounded down */
9078         /* q1 = (int)(a * 256.0); */
9079         q = float64_mul(float64_256, a, s);
9080         int64_t q_int = float64_to_int64_round_to_zero(q, s);
9081
9082         /* reciprocal root r */
9083         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
9084         q = int64_to_float64(q_int, s);
9085         q = float64_add(q, float64_half, s);
9086         q = float64_div(q, float64_256, s);
9087         q = float64_sqrt(q, s);
9088         q = float64_div(float64_one, q, s);
9089     }
9090     /* r in units of 1/256 rounded to nearest */
9091     /* s = (int)(256.0 * r + 0.5); */
9092
9093     q = float64_mul(q, float64_256,s );
9094     q = float64_add(q, float64_half, s);
9095     q_int = float64_to_int64_round_to_zero(q, s);
9096
9097     /* return (double)s / 256.0;*/
9098     return float64_div(int64_to_float64(q_int, s), float64_256, s);
9099 }
9100
9101 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
9102 {
9103     float_status *s = fpstp;
9104     float32 f32 = float32_squash_input_denormal(input, s);
9105     uint32_t val = float32_val(f32);
9106     uint32_t f32_sbit = 0x80000000 & val;
9107     int32_t f32_exp = extract32(val, 23, 8);
9108     uint32_t f32_frac = extract32(val, 0, 23);
9109     uint64_t f64_frac;
9110     uint64_t val64;
9111     int result_exp;
9112     float64 f64;
9113
9114     if (float32_is_any_nan(f32)) {
9115         float32 nan = f32;
9116         if (float32_is_signaling_nan(f32)) {
9117             float_raise(float_flag_invalid, s);
9118             nan = float32_maybe_silence_nan(f32);
9119         }
9120         if (s->default_nan_mode) {
9121             nan =  float32_default_nan;
9122         }
9123         return nan;
9124     } else if (float32_is_zero(f32)) {
9125         float_raise(float_flag_divbyzero, s);
9126         return float32_set_sign(float32_infinity, float32_is_neg(f32));
9127     } else if (float32_is_neg(f32)) {
9128         float_raise(float_flag_invalid, s);
9129         return float32_default_nan;
9130     } else if (float32_is_infinity(f32)) {
9131         return float32_zero;
9132     }
9133
9134     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9135      * preserving the parity of the exponent.  */
9136
9137     f64_frac = ((uint64_t) f32_frac) << 29;
9138     if (f32_exp == 0) {
9139         while (extract64(f64_frac, 51, 1) == 0) {
9140             f64_frac = f64_frac << 1;
9141             f32_exp = f32_exp-1;
9142         }
9143         f64_frac = extract64(f64_frac, 0, 51) << 1;
9144     }
9145
9146     if (extract64(f32_exp, 0, 1) == 0) {
9147         f64 = make_float64(((uint64_t) f32_sbit) << 32
9148                            | (0x3feULL << 52)
9149                            | f64_frac);
9150     } else {
9151         f64 = make_float64(((uint64_t) f32_sbit) << 32
9152                            | (0x3fdULL << 52)
9153                            | f64_frac);
9154     }
9155
9156     result_exp = (380 - f32_exp) / 2;
9157
9158     f64 = recip_sqrt_estimate(f64, s);
9159
9160     val64 = float64_val(f64);
9161
9162     val = ((result_exp & 0xff) << 23)
9163         | ((val64 >> 29)  & 0x7fffff);
9164     return make_float32(val);
9165 }
9166
9167 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
9168 {
9169     float_status *s = fpstp;
9170     float64 f64 = float64_squash_input_denormal(input, s);
9171     uint64_t val = float64_val(f64);
9172     uint64_t f64_sbit = 0x8000000000000000ULL & val;
9173     int64_t f64_exp = extract64(val, 52, 11);
9174     uint64_t f64_frac = extract64(val, 0, 52);
9175     int64_t result_exp;
9176     uint64_t result_frac;
9177
9178     if (float64_is_any_nan(f64)) {
9179         float64 nan = f64;
9180         if (float64_is_signaling_nan(f64)) {
9181             float_raise(float_flag_invalid, s);
9182             nan = float64_maybe_silence_nan(f64);
9183         }
9184         if (s->default_nan_mode) {
9185             nan =  float64_default_nan;
9186         }
9187         return nan;
9188     } else if (float64_is_zero(f64)) {
9189         float_raise(float_flag_divbyzero, s);
9190         return float64_set_sign(float64_infinity, float64_is_neg(f64));
9191     } else if (float64_is_neg(f64)) {
9192         float_raise(float_flag_invalid, s);
9193         return float64_default_nan;
9194     } else if (float64_is_infinity(f64)) {
9195         return float64_zero;
9196     }
9197
9198     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9199      * preserving the parity of the exponent.  */
9200
9201     if (f64_exp == 0) {
9202         while (extract64(f64_frac, 51, 1) == 0) {
9203             f64_frac = f64_frac << 1;
9204             f64_exp = f64_exp - 1;
9205         }
9206         f64_frac = extract64(f64_frac, 0, 51) << 1;
9207     }
9208
9209     if (extract64(f64_exp, 0, 1) == 0) {
9210         f64 = make_float64(f64_sbit
9211                            | (0x3feULL << 52)
9212                            | f64_frac);
9213     } else {
9214         f64 = make_float64(f64_sbit
9215                            | (0x3fdULL << 52)
9216                            | f64_frac);
9217     }
9218
9219     result_exp = (3068 - f64_exp) / 2;
9220
9221     f64 = recip_sqrt_estimate(f64, s);
9222
9223     result_frac = extract64(float64_val(f64), 0, 52);
9224
9225     return make_float64(f64_sbit |
9226                         ((result_exp & 0x7ff) << 52) |
9227                         result_frac);
9228 }
9229
9230 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
9231 {
9232     float_status *s = fpstp;
9233     float64 f64;
9234
9235     if ((a & 0x80000000) == 0) {
9236         return 0xffffffff;
9237     }
9238
9239     f64 = make_float64((0x3feULL << 52)
9240                        | ((int64_t)(a & 0x7fffffff) << 21));
9241
9242     f64 = recip_estimate(f64, s);
9243
9244     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9245 }
9246
9247 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
9248 {
9249     float_status *fpst = fpstp;
9250     float64 f64;
9251
9252     if ((a & 0xc0000000) == 0) {
9253         return 0xffffffff;
9254     }
9255
9256     if (a & 0x80000000) {
9257         f64 = make_float64((0x3feULL << 52)
9258                            | ((uint64_t)(a & 0x7fffffff) << 21));
9259     } else { /* bits 31-30 == '01' */
9260         f64 = make_float64((0x3fdULL << 52)
9261                            | ((uint64_t)(a & 0x3fffffff) << 22));
9262     }
9263
9264     f64 = recip_sqrt_estimate(f64, fpst);
9265
9266     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9267 }
9268
9269 /* VFPv4 fused multiply-accumulate */
9270 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
9271 {
9272     float_status *fpst = fpstp;
9273     return float32_muladd(a, b, c, 0, fpst);
9274 }
9275
9276 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
9277 {
9278     float_status *fpst = fpstp;
9279     return float64_muladd(a, b, c, 0, fpst);
9280 }
9281
9282 /* ARMv8 round to integral */
9283 float32 HELPER(rints_exact)(float32 x, void *fp_status)
9284 {
9285     return float32_round_to_int(x, fp_status);
9286 }
9287
9288 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
9289 {
9290     return float64_round_to_int(x, fp_status);
9291 }
9292
9293 float32 HELPER(rints)(float32 x, void *fp_status)
9294 {
9295     int old_flags = get_float_exception_flags(fp_status), new_flags;
9296     float32 ret;
9297
9298     ret = float32_round_to_int(x, fp_status);
9299
9300     /* Suppress any inexact exceptions the conversion produced */
9301     if (!(old_flags & float_flag_inexact)) {
9302         new_flags = get_float_exception_flags(fp_status);
9303         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9304     }
9305
9306     return ret;
9307 }
9308
9309 float64 HELPER(rintd)(float64 x, void *fp_status)
9310 {
9311     int old_flags = get_float_exception_flags(fp_status), new_flags;
9312     float64 ret;
9313
9314     ret = float64_round_to_int(x, fp_status);
9315
9316     new_flags = get_float_exception_flags(fp_status);
9317
9318     /* Suppress any inexact exceptions the conversion produced */
9319     if (!(old_flags & float_flag_inexact)) {
9320         new_flags = get_float_exception_flags(fp_status);
9321         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9322     }
9323
9324     return ret;
9325 }
9326
9327 /* Convert ARM rounding mode to softfloat */
9328 int arm_rmode_to_sf(int rmode)
9329 {
9330     switch (rmode) {
9331     case FPROUNDING_TIEAWAY:
9332         rmode = float_round_ties_away;
9333         break;
9334     case FPROUNDING_ODD:
9335         /* FIXME: add support for TIEAWAY and ODD */
9336         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
9337                       rmode);
9338     case FPROUNDING_TIEEVEN:
9339     default:
9340         rmode = float_round_nearest_even;
9341         break;
9342     case FPROUNDING_POSINF:
9343         rmode = float_round_up;
9344         break;
9345     case FPROUNDING_NEGINF:
9346         rmode = float_round_down;
9347         break;
9348     case FPROUNDING_ZERO:
9349         rmode = float_round_to_zero;
9350         break;
9351     }
9352     return rmode;
9353 }
9354
9355 /* CRC helpers.
9356  * The upper bytes of val (above the number specified by 'bytes') must have
9357  * been zeroed out by the caller.
9358  */
9359 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
9360 {
9361     uint8_t buf[4];
9362
9363     stl_le_p(buf, val);
9364
9365     /* zlib crc32 converts the accumulator and output to one's complement.  */
9366     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
9367 }
9368
9369 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
9370 {
9371     uint8_t buf[4];
9372
9373     stl_le_p(buf, val);
9374
9375     /* Linux crc32c converts the output to one's complement.  */
9376     return crc32c(acc, buf, bytes) ^ 0xffffffff;
9377 }