2 * SuperH interrupt controller module
4 * Copyright (c) 2007 Magnus Damm
5 * Based on sh_timer.c and arm_timer.c by Paul Brook
6 * Copyright (c) 2005-2006 CodeSourcery.
8 * This code is licensed under the GPL.
16 //#define DEBUG_INTC_SOURCES
18 #define INTC_A7(x) ((x) & 0x1fffffff)
20 void sh_intc_toggle_source(struct intc_source
*source
,
21 int enable_adj
, int assert_adj
)
23 int enable_changed
= 0;
24 int pending_changed
= 0;
27 if ((source
->enable_count
== source
->enable_max
) && (enable_adj
== -1))
30 source
->enable_count
+= enable_adj
;
32 if (source
->enable_count
== source
->enable_max
)
35 source
->asserted
+= assert_adj
;
37 old_pending
= source
->pending
;
38 source
->pending
= source
->asserted
&&
39 (source
->enable_count
== source
->enable_max
);
41 if (old_pending
!= source
->pending
)
44 if (pending_changed
) {
45 if (source
->pending
) {
46 source
->parent
->pending
++;
47 if (source
->parent
->pending
== 1)
48 cpu_interrupt(first_cpu
, CPU_INTERRUPT_HARD
);
51 source
->parent
->pending
--;
52 if (source
->parent
->pending
== 0)
53 cpu_reset_interrupt(first_cpu
, CPU_INTERRUPT_HARD
);
57 if (enable_changed
|| assert_adj
|| pending_changed
) {
58 #ifdef DEBUG_INTC_SOURCES
59 printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
60 source
->parent
->pending
,
65 source
->asserted
? "asserted " :
66 assert_adj
? "deasserted" : "",
67 enable_changed
== 1 ? "enabled " :
68 enable_changed
== -1 ? "disabled " : "",
69 source
->pending
? "pending" : "");
74 static void sh_intc_set_irq (void *opaque
, int n
, int level
)
76 struct intc_desc
*desc
= opaque
;
77 struct intc_source
*source
= &(desc
->sources
[n
]);
79 if (level
&& !source
->asserted
)
80 sh_intc_toggle_source(source
, 0, 1);
81 else if (!level
&& source
->asserted
)
82 sh_intc_toggle_source(source
, 0, -1);
85 int sh_intc_get_pending_vector(struct intc_desc
*desc
, int imask
)
89 /* slow: use a linked lists of pending sources instead */
90 /* wrong: take interrupt priority into account (one list per priority) */
93 return -1; /* FIXME, update code to include priority per source */
96 for (i
= 0; i
< desc
->nr_sources
; i
++) {
97 struct intc_source
*source
= desc
->sources
+ i
;
99 if (source
->pending
) {
100 #ifdef DEBUG_INTC_SOURCES
101 printf("sh_intc: (%d) returning interrupt source 0x%x\n",
102 desc
->pending
, source
->vect
);
111 #define INTC_MODE_NONE 0
112 #define INTC_MODE_DUAL_SET 1
113 #define INTC_MODE_DUAL_CLR 2
114 #define INTC_MODE_ENABLE_REG 3
115 #define INTC_MODE_MASK_REG 4
116 #define INTC_MODE_IS_PRIO 8
118 static unsigned int sh_intc_mode(unsigned long address
,
119 unsigned long set_reg
, unsigned long clr_reg
)
121 if ((address
!= INTC_A7(set_reg
)) &&
122 (address
!= INTC_A7(clr_reg
)))
123 return INTC_MODE_NONE
;
125 if (set_reg
&& clr_reg
) {
126 if (address
== INTC_A7(set_reg
))
127 return INTC_MODE_DUAL_SET
;
129 return INTC_MODE_DUAL_CLR
;
133 return INTC_MODE_ENABLE_REG
;
135 return INTC_MODE_MASK_REG
;
138 static void sh_intc_locate(struct intc_desc
*desc
,
139 unsigned long address
,
140 unsigned long **datap
,
146 unsigned int i
, mode
;
148 /* this is slow but works for now */
150 if (desc
->mask_regs
) {
151 for (i
= 0; i
< desc
->nr_mask_regs
; i
++) {
152 struct intc_mask_reg
*mr
= desc
->mask_regs
+ i
;
154 mode
= sh_intc_mode(address
, mr
->set_reg
, mr
->clr_reg
);
155 if (mode
== INTC_MODE_NONE
)
160 *enums
= mr
->enum_ids
;
161 *first
= mr
->reg_width
- 1;
167 if (desc
->prio_regs
) {
168 for (i
= 0; i
< desc
->nr_prio_regs
; i
++) {
169 struct intc_prio_reg
*pr
= desc
->prio_regs
+ i
;
171 mode
= sh_intc_mode(address
, pr
->set_reg
, pr
->clr_reg
);
172 if (mode
== INTC_MODE_NONE
)
175 *modep
= mode
| INTC_MODE_IS_PRIO
;
177 *enums
= pr
->enum_ids
;
178 *first
= (pr
->reg_width
/ pr
->field_width
) - 1;
179 *width
= pr
->field_width
;
187 static void sh_intc_toggle_mask(struct intc_desc
*desc
, intc_enum id
,
188 int enable
, int is_group
)
190 struct intc_source
*source
= desc
->sources
+ id
;
195 if (!source
->next_enum_id
&& (!source
->enable_max
|| !source
->vect
)) {
196 #ifdef DEBUG_INTC_SOURCES
197 printf("sh_intc: reserved interrupt source %d modified\n", id
);
203 sh_intc_toggle_source(source
, enable
? 1 : -1, 0);
207 printf("setting interrupt group %d to %d\n", id
, !!enable
);
211 if ((is_group
|| !source
->vect
) && source
->next_enum_id
) {
212 sh_intc_toggle_mask(desc
, source
->next_enum_id
, enable
, 1);
217 printf("setting interrupt group %d to %d - done\n", id
, !!enable
);
222 static uint64_t sh_intc_read(void *opaque
, target_phys_addr_t offset
,
225 struct intc_desc
*desc
= opaque
;
226 intc_enum
*enum_ids
= NULL
;
227 unsigned int first
= 0;
228 unsigned int width
= 0;
229 unsigned int mode
= 0;
230 unsigned long *valuep
;
233 printf("sh_intc_read 0x%lx\n", (unsigned long) offset
);
236 sh_intc_locate(desc
, (unsigned long)offset
, &valuep
,
237 &enum_ids
, &first
, &width
, &mode
);
241 static void sh_intc_write(void *opaque
, target_phys_addr_t offset
,
242 uint64_t value
, unsigned size
)
244 struct intc_desc
*desc
= opaque
;
245 intc_enum
*enum_ids
= NULL
;
246 unsigned int first
= 0;
247 unsigned int width
= 0;
248 unsigned int mode
= 0;
250 unsigned long *valuep
;
254 printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset
, value
);
257 sh_intc_locate(desc
, (unsigned long)offset
, &valuep
,
258 &enum_ids
, &first
, &width
, &mode
);
261 case INTC_MODE_ENABLE_REG
| INTC_MODE_IS_PRIO
: break;
262 case INTC_MODE_DUAL_SET
: value
|= *valuep
; break;
263 case INTC_MODE_DUAL_CLR
: value
= *valuep
& ~value
; break;
267 for (k
= 0; k
<= first
; k
++) {
268 mask
= ((1 << width
) - 1) << ((first
- k
) * width
);
270 if ((*valuep
& mask
) == (value
& mask
))
273 printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
274 k
, first
, enum_ids
[k
], (unsigned int)mask
);
276 sh_intc_toggle_mask(desc
, enum_ids
[k
], value
& mask
, 0);
282 printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset
, value
);
286 static const MemoryRegionOps sh_intc_ops
= {
287 .read
= sh_intc_read
,
288 .write
= sh_intc_write
,
289 .endianness
= DEVICE_NATIVE_ENDIAN
,
292 struct intc_source
*sh_intc_source(struct intc_desc
*desc
, intc_enum id
)
295 return desc
->sources
+ id
;
300 static unsigned int sh_intc_register(MemoryRegion
*sysmem
,
301 struct intc_desc
*desc
,
302 const unsigned long address
,
305 const unsigned int index
)
308 MemoryRegion
*iomem
, *iomem_p4
, *iomem_a7
;
314 iomem
= &desc
->iomem
;
315 iomem_p4
= desc
->iomem_aliases
+ index
;
316 iomem_a7
= iomem_p4
+ 1;
318 #define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
319 snprintf(name
, sizeof(name
), SH_INTC_IOMEM_FORMAT
, type
, action
, "p4");
320 memory_region_init_alias(iomem_p4
, name
, iomem
, INTC_A7(address
), 4);
321 memory_region_add_subregion(sysmem
, P4ADDR(address
), iomem_p4
);
323 snprintf(name
, sizeof(name
), SH_INTC_IOMEM_FORMAT
, type
, action
, "a7");
324 memory_region_init_alias(iomem_a7
, name
, iomem
, INTC_A7(address
), 4);
325 memory_region_add_subregion(sysmem
, A7ADDR(address
), iomem_a7
);
326 #undef SH_INTC_IOMEM_FORMAT
328 /* used to increment aliases index */
332 static void sh_intc_register_source(struct intc_desc
*desc
,
334 struct intc_group
*groups
,
338 struct intc_source
*s
;
340 if (desc
->mask_regs
) {
341 for (i
= 0; i
< desc
->nr_mask_regs
; i
++) {
342 struct intc_mask_reg
*mr
= desc
->mask_regs
+ i
;
344 for (k
= 0; k
< ARRAY_SIZE(mr
->enum_ids
); k
++) {
345 if (mr
->enum_ids
[k
] != source
)
348 s
= sh_intc_source(desc
, mr
->enum_ids
[k
]);
355 if (desc
->prio_regs
) {
356 for (i
= 0; i
< desc
->nr_prio_regs
; i
++) {
357 struct intc_prio_reg
*pr
= desc
->prio_regs
+ i
;
359 for (k
= 0; k
< ARRAY_SIZE(pr
->enum_ids
); k
++) {
360 if (pr
->enum_ids
[k
] != source
)
363 s
= sh_intc_source(desc
, pr
->enum_ids
[k
]);
371 for (i
= 0; i
< nr_groups
; i
++) {
372 struct intc_group
*gr
= groups
+ i
;
374 for (k
= 0; k
< ARRAY_SIZE(gr
->enum_ids
); k
++) {
375 if (gr
->enum_ids
[k
] != source
)
378 s
= sh_intc_source(desc
, gr
->enum_ids
[k
]);
387 void sh_intc_register_sources(struct intc_desc
*desc
,
388 struct intc_vect
*vectors
,
390 struct intc_group
*groups
,
394 struct intc_source
*s
;
396 for (i
= 0; i
< nr_vectors
; i
++) {
397 struct intc_vect
*vect
= vectors
+ i
;
399 sh_intc_register_source(desc
, vect
->enum_id
, groups
, nr_groups
);
400 s
= sh_intc_source(desc
, vect
->enum_id
);
402 s
->vect
= vect
->vect
;
404 #ifdef DEBUG_INTC_SOURCES
405 printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
406 vect
->enum_id
, s
->vect
, s
->enable_count
, s
->enable_max
);
412 for (i
= 0; i
< nr_groups
; i
++) {
413 struct intc_group
*gr
= groups
+ i
;
415 s
= sh_intc_source(desc
, gr
->enum_id
);
416 s
->next_enum_id
= gr
->enum_ids
[0];
418 for (k
= 1; k
< ARRAY_SIZE(gr
->enum_ids
); k
++) {
419 if (!gr
->enum_ids
[k
])
422 s
= sh_intc_source(desc
, gr
->enum_ids
[k
- 1]);
423 s
->next_enum_id
= gr
->enum_ids
[k
];
426 #ifdef DEBUG_INTC_SOURCES
427 printf("sh_intc: registered group %d (%d/%d)\n",
428 gr
->enum_id
, s
->enable_count
, s
->enable_max
);
434 int sh_intc_init(MemoryRegion
*sysmem
,
435 struct intc_desc
*desc
,
437 struct intc_mask_reg
*mask_regs
,
439 struct intc_prio_reg
*prio_regs
,
445 desc
->nr_sources
= nr_sources
;
446 desc
->mask_regs
= mask_regs
;
447 desc
->nr_mask_regs
= nr_mask_regs
;
448 desc
->prio_regs
= prio_regs
;
449 desc
->nr_prio_regs
= nr_prio_regs
;
450 /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases).
452 desc
->iomem_aliases
= g_new0(MemoryRegion
,
453 (nr_mask_regs
+ nr_prio_regs
) * 4);
456 i
= sizeof(struct intc_source
) * nr_sources
;
457 desc
->sources
= g_malloc0(i
);
459 for (i
= 0; i
< desc
->nr_sources
; i
++) {
460 struct intc_source
*source
= desc
->sources
+ i
;
462 source
->parent
= desc
;
465 desc
->irqs
= qemu_allocate_irqs(sh_intc_set_irq
, desc
, nr_sources
);
467 memory_region_init_io(&desc
->iomem
, &sh_intc_ops
, desc
,
468 "interrupt-controller", 0x100000000ULL
);
470 #define INT_REG_PARAMS(reg_struct, type, action, j) \
471 reg_struct->action##_reg, #type, #action, j
472 if (desc
->mask_regs
) {
473 for (i
= 0; i
< desc
->nr_mask_regs
; i
++) {
474 struct intc_mask_reg
*mr
= desc
->mask_regs
+ i
;
476 j
+= sh_intc_register(sysmem
, desc
,
477 INT_REG_PARAMS(mr
, mask
, set
, j
));
478 j
+= sh_intc_register(sysmem
, desc
,
479 INT_REG_PARAMS(mr
, mask
, clr
, j
));
483 if (desc
->prio_regs
) {
484 for (i
= 0; i
< desc
->nr_prio_regs
; i
++) {
485 struct intc_prio_reg
*pr
= desc
->prio_regs
+ i
;
487 j
+= sh_intc_register(sysmem
, desc
,
488 INT_REG_PARAMS(pr
, prio
, set
, j
));
489 j
+= sh_intc_register(sysmem
, desc
,
490 INT_REG_PARAMS(pr
, prio
, clr
, j
));
493 #undef INT_REG_PARAMS
498 /* Assert level <n> IRL interrupt.
499 0:deassert. 1:lowest priority,... 15:highest priority. */
500 void sh_intc_set_irl(void *opaque
, int n
, int level
)
502 struct intc_source
*s
= opaque
;
503 int i
, irl
= level
^ 15;
504 for (i
= 0; (s
= sh_intc_source(s
->parent
, s
->next_enum_id
)); i
++) {
506 sh_intc_toggle_source(s
, s
->enable_count
?0:1, s
->asserted
?0:1);
509 sh_intc_toggle_source(s
, 0, -1);