4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
109 switch (s
->mmu_idx
) {
110 case ARMMMUIdx_S12NSE1
:
111 return ARMMMUIdx_S12NSE0
;
112 case ARMMMUIdx_S1SE1
:
113 return ARMMMUIdx_S1SE0
;
115 g_assert_not_reached();
121 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
122 fprintf_function cpu_fprintf
, int flags
)
124 ARMCPU
*cpu
= ARM_CPU(cs
);
125 CPUARMState
*env
= &cpu
->env
;
126 uint32_t psr
= pstate_read(env
);
128 int el
= arm_current_el(env
);
129 const char *ns_status
;
131 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
132 env
->pc
, env
->xregs
[31]);
133 for (i
= 0; i
< 31; i
++) {
134 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
136 cpu_fprintf(f
, "\n");
142 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
143 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
148 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
150 psr
& PSTATE_N
? 'N' : '-',
151 psr
& PSTATE_Z
? 'Z' : '-',
152 psr
& PSTATE_C
? 'C' : '-',
153 psr
& PSTATE_V
? 'V' : '-',
156 psr
& PSTATE_SP
? 'h' : 't');
158 if (flags
& CPU_DUMP_FPU
) {
160 for (i
= 0; i
< numvfpregs
; i
+= 2) {
161 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
162 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
163 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
165 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
166 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
167 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
170 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
171 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
175 void gen_a64_set_pc_im(uint64_t val
)
177 tcg_gen_movi_i64(cpu_pc
, val
);
180 /* Load the PC from a generic TCG variable.
182 * If address tagging is enabled via the TCR TBI bits, then loading
183 * an address into the PC will clear out any tag in the it:
184 * + for EL2 and EL3 there is only one TBI bit, and if it is set
185 * then the address is zero-extended, clearing bits [63:56]
186 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
187 * and TBI1 controls addressses with bit 55 == 1.
188 * If the appropriate TBI bit is set for the address then
189 * the address is sign-extended from bit 55 into bits [63:56]
191 * We can avoid doing this for relative-branches, because the
192 * PC + offset can never overflow into the tag bits (assuming
193 * that virtual addresses are less than 56 bits wide, as they
194 * are currently), but we must handle it for branch-to-register.
196 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
199 if (s
->current_el
<= 1) {
200 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
201 * examine bit 55 of address, can just generate code.
202 * If mixed, then test via generated code
204 if (s
->tbi0
&& s
->tbi1
) {
205 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
206 /* Both bits set, sign extension from bit 55 into [63:56] will
209 tcg_gen_shli_i64(tmp_reg
, src
, 8);
210 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
211 tcg_temp_free_i64(tmp_reg
);
212 } else if (!s
->tbi0
&& !s
->tbi1
) {
213 /* Neither bit set, just load it as-is */
214 tcg_gen_mov_i64(cpu_pc
, src
);
216 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
217 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
218 TCGv_i64 tcg_zero
= tcg_const_i64(0);
220 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
223 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
224 tcg_gen_andi_i64(tcg_tmpval
, src
,
225 0x00FFFFFFFFFFFFFFull
);
226 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
229 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
230 tcg_gen_ori_i64(tcg_tmpval
, src
,
231 0xFF00000000000000ull
);
232 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 tcg_temp_free_i64(tcg_zero
);
236 tcg_temp_free_i64(tcg_bit55
);
237 tcg_temp_free_i64(tcg_tmpval
);
239 } else { /* EL > 1 */
241 /* Force tag byte to all zero */
242 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
244 /* Load unmodified address */
245 tcg_gen_mov_i64(cpu_pc
, src
);
250 typedef struct DisasCompare64
{
255 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
259 arm_test_cc(&c32
, cc
);
261 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
262 * properly. The NE/EQ comparisons are also fine with this choice. */
263 c64
->cond
= c32
.cond
;
264 c64
->value
= tcg_temp_new_i64();
265 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
270 static void a64_free_cc(DisasCompare64
*c64
)
272 tcg_temp_free_i64(c64
->value
);
275 static void gen_exception_internal(int excp
)
277 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
279 assert(excp_is_internal(excp
));
280 gen_helper_exception_internal(cpu_env
, tcg_excp
);
281 tcg_temp_free_i32(tcg_excp
);
284 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
286 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
287 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
288 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
290 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
292 tcg_temp_free_i32(tcg_el
);
293 tcg_temp_free_i32(tcg_syn
);
294 tcg_temp_free_i32(tcg_excp
);
297 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
299 gen_a64_set_pc_im(s
->pc
- offset
);
300 gen_exception_internal(excp
);
301 s
->is_jmp
= DISAS_EXC
;
304 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
305 uint32_t syndrome
, uint32_t target_el
)
307 gen_a64_set_pc_im(s
->pc
- offset
);
308 gen_exception(excp
, syndrome
, target_el
);
309 s
->is_jmp
= DISAS_EXC
;
312 static void gen_ss_advance(DisasContext
*s
)
314 /* If the singlestep state is Active-not-pending, advance to
319 gen_helper_clear_pstate_ss(cpu_env
);
323 static void gen_step_complete_exception(DisasContext
*s
)
325 /* We just completed step of an insn. Move from Active-not-pending
326 * to Active-pending, and then also take the swstep exception.
327 * This corresponds to making the (IMPDEF) choice to prioritize
328 * swstep exceptions over asynchronous exceptions taken to an exception
329 * level where debug is disabled. This choice has the advantage that
330 * we do not need to maintain internal state corresponding to the
331 * ISV/EX syndrome bits between completion of the step and generation
332 * of the exception, and our syndrome information is always correct.
335 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
336 default_exception_el(s
));
337 s
->is_jmp
= DISAS_EXC
;
340 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
342 /* No direct tb linking with singlestep (either QEMU's or the ARM
343 * debug architecture kind) or deterministic io
345 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
349 #ifndef CONFIG_USER_ONLY
350 /* Only link tbs from inside the same guest page */
351 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
359 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
361 TranslationBlock
*tb
;
364 if (use_goto_tb(s
, n
, dest
)) {
366 gen_a64_set_pc_im(dest
);
367 tcg_gen_exit_tb((intptr_t)tb
+ n
);
368 s
->is_jmp
= DISAS_TB_JUMP
;
370 gen_a64_set_pc_im(dest
);
372 gen_step_complete_exception(s
);
373 } else if (s
->singlestep_enabled
) {
374 gen_exception_internal(EXCP_DEBUG
);
377 s
->is_jmp
= DISAS_TB_JUMP
;
382 static void disas_set_insn_syndrome(DisasContext
*s
, uint32_t syn
)
384 /* We don't need to save all of the syndrome so we mask and shift
385 * out uneeded bits to help the sleb128 encoder do a better job.
387 syn
&= ARM_INSN_START_WORD2_MASK
;
388 syn
>>= ARM_INSN_START_WORD2_SHIFT
;
390 /* We check and clear insn_start_idx to catch multiple updates. */
391 assert(s
->insn_start_idx
!= 0);
392 tcg_set_insn_param(s
->insn_start_idx
, 2, syn
);
393 s
->insn_start_idx
= 0;
396 static void unallocated_encoding(DisasContext
*s
)
398 /* Unallocated and reserved encodings are uncategorized */
399 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
400 default_exception_el(s
));
403 #define unsupported_encoding(s, insn) \
405 qemu_log_mask(LOG_UNIMP, \
406 "%s:%d: unsupported instruction encoding 0x%08x " \
407 "at pc=%016" PRIx64 "\n", \
408 __FILE__, __LINE__, insn, s->pc - 4); \
409 unallocated_encoding(s); \
412 static void init_tmp_a64_array(DisasContext
*s
)
414 #ifdef CONFIG_DEBUG_TCG
416 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
417 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
420 s
->tmp_a64_count
= 0;
423 static void free_tmp_a64(DisasContext
*s
)
426 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
427 tcg_temp_free_i64(s
->tmp_a64
[i
]);
429 init_tmp_a64_array(s
);
432 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
434 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
435 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
438 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
440 TCGv_i64 t
= new_tmp_a64(s
);
441 tcg_gen_movi_i64(t
, 0);
446 * Register access functions
448 * These functions are used for directly accessing a register in where
449 * changes to the final register value are likely to be made. If you
450 * need to use a register for temporary calculation (e.g. index type
451 * operations) use the read_* form.
453 * B1.2.1 Register mappings
455 * In instruction register encoding 31 can refer to ZR (zero register) or
456 * the SP (stack pointer) depending on context. In QEMU's case we map SP
457 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
458 * This is the point of the _sp forms.
460 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
463 return new_tmp_a64_zero(s
);
469 /* register access for when 31 == SP */
470 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
475 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
476 * representing the register contents. This TCGv is an auto-freed
477 * temporary so it need not be explicitly freed, and may be modified.
479 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
481 TCGv_i64 v
= new_tmp_a64(s
);
484 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
486 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
489 tcg_gen_movi_i64(v
, 0);
494 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
496 TCGv_i64 v
= new_tmp_a64(s
);
498 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
500 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
505 /* We should have at some point before trying to access an FP register
506 * done the necessary access check, so assert that
507 * (a) we did the check and
508 * (b) we didn't then just plough ahead anyway if it failed.
509 * Print the instruction pattern in the abort message so we can figure
510 * out what we need to fix if a user encounters this problem in the wild.
512 static inline void assert_fp_access_checked(DisasContext
*s
)
514 #ifdef CONFIG_DEBUG_TCG
515 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
516 fprintf(stderr
, "target-arm: FP access check missing for "
517 "instruction 0x%08x\n", s
->insn
);
523 /* Return the offset into CPUARMState of an element of specified
524 * size, 'element' places in from the least significant end of
525 * the FP/vector register Qn.
527 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
528 int element
, TCGMemOp size
)
530 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
531 #ifdef HOST_WORDS_BIGENDIAN
532 /* This is complicated slightly because vfp.regs[2n] is
533 * still the low half and vfp.regs[2n+1] the high half
534 * of the 128 bit vector, even on big endian systems.
535 * Calculate the offset assuming a fully bigendian 128 bits,
536 * then XOR to account for the order of the two 64 bit halves.
538 offs
+= (16 - ((element
+ 1) * (1 << size
)));
541 offs
+= element
* (1 << size
);
543 assert_fp_access_checked(s
);
547 /* Return the offset into CPUARMState of a slice (from
548 * the least significant end) of FP register Qn (ie
550 * (Note that this is not the same mapping as for A32; see cpu.h)
552 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
554 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
555 #ifdef HOST_WORDS_BIGENDIAN
556 offs
+= (8 - (1 << size
));
558 assert_fp_access_checked(s
);
562 /* Offset of the high half of the 128 bit vector Qn */
563 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
565 assert_fp_access_checked(s
);
566 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
569 /* Convenience accessors for reading and writing single and double
570 * FP registers. Writing clears the upper parts of the associated
571 * 128 bit vector register, as required by the architecture.
572 * Note that unlike the GP register accessors, the values returned
573 * by the read functions must be manually freed.
575 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
577 TCGv_i64 v
= tcg_temp_new_i64();
579 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
583 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
585 TCGv_i32 v
= tcg_temp_new_i32();
587 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
591 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
593 TCGv_i64 tcg_zero
= tcg_const_i64(0);
595 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
596 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
597 tcg_temp_free_i64(tcg_zero
);
600 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
602 TCGv_i64 tmp
= tcg_temp_new_i64();
604 tcg_gen_extu_i32_i64(tmp
, v
);
605 write_fp_dreg(s
, reg
, tmp
);
606 tcg_temp_free_i64(tmp
);
609 static TCGv_ptr
get_fpstatus_ptr(void)
611 TCGv_ptr statusptr
= tcg_temp_new_ptr();
614 /* In A64 all instructions (both FP and Neon) use the FPCR;
615 * there is no equivalent of the A32 Neon "standard FPSCR value"
616 * and all operations use vfp.fp_status.
618 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
619 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
623 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
624 * than the 32 bit equivalent.
626 static inline void gen_set_NZ64(TCGv_i64 result
)
628 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
629 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
632 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
633 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
636 gen_set_NZ64(result
);
638 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
639 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
641 tcg_gen_movi_i32(cpu_CF
, 0);
642 tcg_gen_movi_i32(cpu_VF
, 0);
645 /* dest = T0 + T1; compute C, N, V and Z flags */
646 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
649 TCGv_i64 result
, flag
, tmp
;
650 result
= tcg_temp_new_i64();
651 flag
= tcg_temp_new_i64();
652 tmp
= tcg_temp_new_i64();
654 tcg_gen_movi_i64(tmp
, 0);
655 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
657 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
659 gen_set_NZ64(result
);
661 tcg_gen_xor_i64(flag
, result
, t0
);
662 tcg_gen_xor_i64(tmp
, t0
, t1
);
663 tcg_gen_andc_i64(flag
, flag
, tmp
);
664 tcg_temp_free_i64(tmp
);
665 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
667 tcg_gen_mov_i64(dest
, result
);
668 tcg_temp_free_i64(result
);
669 tcg_temp_free_i64(flag
);
671 /* 32 bit arithmetic */
672 TCGv_i32 t0_32
= tcg_temp_new_i32();
673 TCGv_i32 t1_32
= tcg_temp_new_i32();
674 TCGv_i32 tmp
= tcg_temp_new_i32();
676 tcg_gen_movi_i32(tmp
, 0);
677 tcg_gen_extrl_i64_i32(t0_32
, t0
);
678 tcg_gen_extrl_i64_i32(t1_32
, t1
);
679 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
680 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
681 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
682 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
683 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
684 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
686 tcg_temp_free_i32(tmp
);
687 tcg_temp_free_i32(t0_32
);
688 tcg_temp_free_i32(t1_32
);
692 /* dest = T0 - T1; compute C, N, V and Z flags */
693 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
696 /* 64 bit arithmetic */
697 TCGv_i64 result
, flag
, tmp
;
699 result
= tcg_temp_new_i64();
700 flag
= tcg_temp_new_i64();
701 tcg_gen_sub_i64(result
, t0
, t1
);
703 gen_set_NZ64(result
);
705 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
706 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
708 tcg_gen_xor_i64(flag
, result
, t0
);
709 tmp
= tcg_temp_new_i64();
710 tcg_gen_xor_i64(tmp
, t0
, t1
);
711 tcg_gen_and_i64(flag
, flag
, tmp
);
712 tcg_temp_free_i64(tmp
);
713 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
714 tcg_gen_mov_i64(dest
, result
);
715 tcg_temp_free_i64(flag
);
716 tcg_temp_free_i64(result
);
718 /* 32 bit arithmetic */
719 TCGv_i32 t0_32
= tcg_temp_new_i32();
720 TCGv_i32 t1_32
= tcg_temp_new_i32();
723 tcg_gen_extrl_i64_i32(t0_32
, t0
);
724 tcg_gen_extrl_i64_i32(t1_32
, t1
);
725 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
726 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
727 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
728 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
729 tmp
= tcg_temp_new_i32();
730 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
731 tcg_temp_free_i32(t0_32
);
732 tcg_temp_free_i32(t1_32
);
733 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
734 tcg_temp_free_i32(tmp
);
735 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
739 /* dest = T0 + T1 + CF; do not compute flags. */
740 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
742 TCGv_i64 flag
= tcg_temp_new_i64();
743 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
744 tcg_gen_add_i64(dest
, t0
, t1
);
745 tcg_gen_add_i64(dest
, dest
, flag
);
746 tcg_temp_free_i64(flag
);
749 tcg_gen_ext32u_i64(dest
, dest
);
753 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
754 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
757 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
758 result
= tcg_temp_new_i64();
759 cf_64
= tcg_temp_new_i64();
760 vf_64
= tcg_temp_new_i64();
761 tmp
= tcg_const_i64(0);
763 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
764 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
765 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
766 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
767 gen_set_NZ64(result
);
769 tcg_gen_xor_i64(vf_64
, result
, t0
);
770 tcg_gen_xor_i64(tmp
, t0
, t1
);
771 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
772 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
774 tcg_gen_mov_i64(dest
, result
);
776 tcg_temp_free_i64(tmp
);
777 tcg_temp_free_i64(vf_64
);
778 tcg_temp_free_i64(cf_64
);
779 tcg_temp_free_i64(result
);
781 TCGv_i32 t0_32
, t1_32
, tmp
;
782 t0_32
= tcg_temp_new_i32();
783 t1_32
= tcg_temp_new_i32();
784 tmp
= tcg_const_i32(0);
786 tcg_gen_extrl_i64_i32(t0_32
, t0
);
787 tcg_gen_extrl_i64_i32(t1_32
, t1
);
788 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
789 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
791 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
792 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
793 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
794 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
795 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
797 tcg_temp_free_i32(tmp
);
798 tcg_temp_free_i32(t1_32
);
799 tcg_temp_free_i32(t0_32
);
804 * Load/Store generators
808 * Store from GPR register to memory.
810 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
811 TCGv_i64 tcg_addr
, int size
, int memidx
,
813 unsigned int iss_srt
,
814 bool iss_sf
, bool iss_ar
)
817 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
822 syn
= syn_data_abort_with_iss(0,
828 0, 0, 0, 0, 0, false);
829 disas_set_insn_syndrome(s
, syn
);
833 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
834 TCGv_i64 tcg_addr
, int size
,
836 unsigned int iss_srt
,
837 bool iss_sf
, bool iss_ar
)
839 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
840 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
844 * Load from memory to GPR register
846 static void do_gpr_ld_memidx(DisasContext
*s
,
847 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
848 int size
, bool is_signed
,
849 bool extend
, int memidx
,
850 bool iss_valid
, unsigned int iss_srt
,
851 bool iss_sf
, bool iss_ar
)
853 TCGMemOp memop
= s
->be_data
+ size
;
861 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
863 if (extend
&& is_signed
) {
865 tcg_gen_ext32u_i64(dest
, dest
);
871 syn
= syn_data_abort_with_iss(0,
877 0, 0, 0, 0, 0, false);
878 disas_set_insn_syndrome(s
, syn
);
882 static void do_gpr_ld(DisasContext
*s
,
883 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
884 int size
, bool is_signed
, bool extend
,
885 bool iss_valid
, unsigned int iss_srt
,
886 bool iss_sf
, bool iss_ar
)
888 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
890 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
894 * Store from FP register to memory
896 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
898 /* This writes the bottom N bits of a 128 bit wide vector to memory */
899 TCGv_i64 tmp
= tcg_temp_new_i64();
900 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
902 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
905 bool be
= s
->be_data
== MO_BE
;
906 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
908 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
909 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
911 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
912 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
914 tcg_temp_free_i64(tcg_hiaddr
);
917 tcg_temp_free_i64(tmp
);
921 * Load from memory to FP register
923 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
925 /* This always zero-extends and writes to a full 128 bit wide vector */
926 TCGv_i64 tmplo
= tcg_temp_new_i64();
930 TCGMemOp memop
= s
->be_data
+ size
;
931 tmphi
= tcg_const_i64(0);
932 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
934 bool be
= s
->be_data
== MO_BE
;
937 tmphi
= tcg_temp_new_i64();
938 tcg_hiaddr
= tcg_temp_new_i64();
940 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
941 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
943 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
945 tcg_temp_free_i64(tcg_hiaddr
);
948 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
949 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
951 tcg_temp_free_i64(tmplo
);
952 tcg_temp_free_i64(tmphi
);
956 * Vector load/store helpers.
958 * The principal difference between this and a FP load is that we don't
959 * zero extend as we are filling a partial chunk of the vector register.
960 * These functions don't support 128 bit loads/stores, which would be
961 * normal load/store operations.
963 * The _i32 versions are useful when operating on 32 bit quantities
964 * (eg for floating point single or using Neon helper functions).
967 /* Get value of an element within a vector register */
968 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
969 int element
, TCGMemOp memop
)
971 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
974 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
977 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
980 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
983 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
986 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
989 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
993 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
996 g_assert_not_reached();
1000 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1001 int element
, TCGMemOp memop
)
1003 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1006 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1009 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1015 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1019 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1022 g_assert_not_reached();
1026 /* Set value of an element within a vector register */
1027 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1028 int element
, TCGMemOp memop
)
1030 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1033 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1036 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1039 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1042 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1045 g_assert_not_reached();
1049 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1050 int destidx
, int element
, TCGMemOp memop
)
1052 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1055 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1058 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1061 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1064 g_assert_not_reached();
1068 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1069 * vector ops all need to do this).
1071 static void clear_vec_high(DisasContext
*s
, int rd
)
1073 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1075 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1076 tcg_temp_free_i64(tcg_zero
);
1079 /* Store from vector register to memory */
1080 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1081 TCGv_i64 tcg_addr
, int size
)
1083 TCGMemOp memop
= s
->be_data
+ size
;
1084 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1086 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1087 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1089 tcg_temp_free_i64(tcg_tmp
);
1092 /* Load from memory to vector register */
1093 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1094 TCGv_i64 tcg_addr
, int size
)
1096 TCGMemOp memop
= s
->be_data
+ size
;
1097 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1099 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1100 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1102 tcg_temp_free_i64(tcg_tmp
);
1105 /* Check that FP/Neon access is enabled. If it is, return
1106 * true. If not, emit code to generate an appropriate exception,
1107 * and return false; the caller should not emit any code for
1108 * the instruction. Note that this check must happen after all
1109 * unallocated-encoding checks (otherwise the syndrome information
1110 * for the resulting exception will be incorrect).
1112 static inline bool fp_access_check(DisasContext
*s
)
1114 assert(!s
->fp_access_checked
);
1115 s
->fp_access_checked
= true;
1117 if (!s
->fp_excp_el
) {
1121 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1127 * This utility function is for doing register extension with an
1128 * optional shift. You will likely want to pass a temporary for the
1129 * destination register. See DecodeRegExtend() in the ARM ARM.
1131 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1132 int option
, unsigned int shift
)
1134 int extsize
= extract32(option
, 0, 2);
1135 bool is_signed
= extract32(option
, 2, 1);
1140 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1143 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1146 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1149 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1155 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1158 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1161 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1164 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1170 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1174 static inline void gen_check_sp_alignment(DisasContext
*s
)
1176 /* The AArch64 architecture mandates that (if enabled via PSTATE
1177 * or SCTLR bits) there is a check that SP is 16-aligned on every
1178 * SP-relative load or store (with an exception generated if it is not).
1179 * In line with general QEMU practice regarding misaligned accesses,
1180 * we omit these checks for the sake of guest program performance.
1181 * This function is provided as a hook so we can more easily add these
1182 * checks in future (possibly as a "favour catching guest program bugs
1183 * over speed" user selectable option).
1188 * This provides a simple table based table lookup decoder. It is
1189 * intended to be used when the relevant bits for decode are too
1190 * awkwardly placed and switch/if based logic would be confusing and
1191 * deeply nested. Since it's a linear search through the table, tables
1192 * should be kept small.
1194 * It returns the first handler where insn & mask == pattern, or
1195 * NULL if there is no match.
1196 * The table is terminated by an empty mask (i.e. 0)
1198 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1201 const AArch64DecodeTable
*tptr
= table
;
1203 while (tptr
->mask
) {
1204 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1205 return tptr
->disas_fn
;
1213 * the instruction disassembly implemented here matches
1214 * the instruction encoding classifications in chapter 3 (C3)
1215 * of the ARM Architecture Reference Manual (DDI0487A_a)
1218 /* C3.2.7 Unconditional branch (immediate)
1220 * +----+-----------+-------------------------------------+
1221 * | op | 0 0 1 0 1 | imm26 |
1222 * +----+-----------+-------------------------------------+
1224 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1226 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1228 if (insn
& (1U << 31)) {
1229 /* C5.6.26 BL Branch with link */
1230 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1233 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1234 gen_goto_tb(s
, 0, addr
);
1237 /* C3.2.1 Compare & branch (immediate)
1238 * 31 30 25 24 23 5 4 0
1239 * +----+-------------+----+---------------------+--------+
1240 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1241 * +----+-------------+----+---------------------+--------+
1243 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1245 unsigned int sf
, op
, rt
;
1247 TCGLabel
*label_match
;
1250 sf
= extract32(insn
, 31, 1);
1251 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1252 rt
= extract32(insn
, 0, 5);
1253 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1255 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1256 label_match
= gen_new_label();
1258 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1259 tcg_cmp
, 0, label_match
);
1261 gen_goto_tb(s
, 0, s
->pc
);
1262 gen_set_label(label_match
);
1263 gen_goto_tb(s
, 1, addr
);
1266 /* C3.2.5 Test & branch (immediate)
1267 * 31 30 25 24 23 19 18 5 4 0
1268 * +----+-------------+----+-------+-------------+------+
1269 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1270 * +----+-------------+----+-------+-------------+------+
1272 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1274 unsigned int bit_pos
, op
, rt
;
1276 TCGLabel
*label_match
;
1279 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1280 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1281 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1282 rt
= extract32(insn
, 0, 5);
1284 tcg_cmp
= tcg_temp_new_i64();
1285 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1286 label_match
= gen_new_label();
1287 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1288 tcg_cmp
, 0, label_match
);
1289 tcg_temp_free_i64(tcg_cmp
);
1290 gen_goto_tb(s
, 0, s
->pc
);
1291 gen_set_label(label_match
);
1292 gen_goto_tb(s
, 1, addr
);
1295 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1296 * 31 25 24 23 5 4 3 0
1297 * +---------------+----+---------------------+----+------+
1298 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1299 * +---------------+----+---------------------+----+------+
1301 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1306 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1307 unallocated_encoding(s
);
1310 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1311 cond
= extract32(insn
, 0, 4);
1314 /* genuinely conditional branches */
1315 TCGLabel
*label_match
= gen_new_label();
1316 arm_gen_test_cc(cond
, label_match
);
1317 gen_goto_tb(s
, 0, s
->pc
);
1318 gen_set_label(label_match
);
1319 gen_goto_tb(s
, 1, addr
);
1321 /* 0xe and 0xf are both "always" conditions */
1322 gen_goto_tb(s
, 0, addr
);
1327 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1328 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1330 unsigned int selector
= crm
<< 3 | op2
;
1333 unallocated_encoding(s
);
1341 s
->is_jmp
= DISAS_WFI
;
1344 s
->is_jmp
= DISAS_YIELD
;
1347 s
->is_jmp
= DISAS_WFE
;
1351 /* we treat all as NOP at least for now */
1354 /* default specified as NOP equivalent */
1359 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1361 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1364 /* CLREX, DSB, DMB, ISB */
1365 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1366 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1371 unallocated_encoding(s
);
1382 case 1: /* MBReqTypes_Reads */
1383 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1385 case 2: /* MBReqTypes_Writes */
1386 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1388 default: /* MBReqTypes_All */
1389 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1395 /* We need to break the TB after this insn to execute
1396 * a self-modified code correctly and also to take
1397 * any pending interrupts immediately.
1399 s
->is_jmp
= DISAS_UPDATE
;
1402 unallocated_encoding(s
);
1407 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1408 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1409 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1411 int op
= op1
<< 3 | op2
;
1413 case 0x05: /* SPSel */
1414 if (s
->current_el
== 0) {
1415 unallocated_encoding(s
);
1419 case 0x1e: /* DAIFSet */
1420 case 0x1f: /* DAIFClear */
1422 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1423 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1424 gen_a64_set_pc_im(s
->pc
- 4);
1425 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1426 tcg_temp_free_i32(tcg_imm
);
1427 tcg_temp_free_i32(tcg_op
);
1428 s
->is_jmp
= DISAS_UPDATE
;
1432 unallocated_encoding(s
);
1437 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1439 TCGv_i32 tmp
= tcg_temp_new_i32();
1440 TCGv_i32 nzcv
= tcg_temp_new_i32();
1442 /* build bit 31, N */
1443 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1444 /* build bit 30, Z */
1445 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1446 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1447 /* build bit 29, C */
1448 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1449 /* build bit 28, V */
1450 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1451 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1452 /* generate result */
1453 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1455 tcg_temp_free_i32(nzcv
);
1456 tcg_temp_free_i32(tmp
);
1459 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1462 TCGv_i32 nzcv
= tcg_temp_new_i32();
1464 /* take NZCV from R[t] */
1465 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1468 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1470 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1471 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1473 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1474 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1476 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1477 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1478 tcg_temp_free_i32(nzcv
);
1481 /* C5.6.129 MRS - move from system register
1482 * C5.6.131 MSR (register) - move to system register
1485 * These are all essentially the same insn in 'read' and 'write'
1486 * versions, with varying op0 fields.
1488 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1489 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1490 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1492 const ARMCPRegInfo
*ri
;
1495 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1496 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1497 crn
, crm
, op0
, op1
, op2
));
1500 /* Unknown register; this might be a guest error or a QEMU
1501 * unimplemented feature.
1503 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1504 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1505 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1506 unallocated_encoding(s
);
1510 /* Check access permissions */
1511 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1512 unallocated_encoding(s
);
1517 /* Emit code to perform further access permissions checks at
1518 * runtime; this may result in an exception.
1521 TCGv_i32 tcg_syn
, tcg_isread
;
1524 gen_a64_set_pc_im(s
->pc
- 4);
1525 tmpptr
= tcg_const_ptr(ri
);
1526 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1527 tcg_syn
= tcg_const_i32(syndrome
);
1528 tcg_isread
= tcg_const_i32(isread
);
1529 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1530 tcg_temp_free_ptr(tmpptr
);
1531 tcg_temp_free_i32(tcg_syn
);
1532 tcg_temp_free_i32(tcg_isread
);
1535 /* Handle special cases first */
1536 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1540 tcg_rt
= cpu_reg(s
, rt
);
1542 gen_get_nzcv(tcg_rt
);
1544 gen_set_nzcv(tcg_rt
);
1547 case ARM_CP_CURRENTEL
:
1548 /* Reads as current EL value from pstate, which is
1549 * guaranteed to be constant by the tb flags.
1551 tcg_rt
= cpu_reg(s
, rt
);
1552 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1555 /* Writes clear the aligned block of memory which rt points into. */
1556 tcg_rt
= cpu_reg(s
, rt
);
1557 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1563 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1567 tcg_rt
= cpu_reg(s
, rt
);
1570 if (ri
->type
& ARM_CP_CONST
) {
1571 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1572 } else if (ri
->readfn
) {
1574 tmpptr
= tcg_const_ptr(ri
);
1575 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1576 tcg_temp_free_ptr(tmpptr
);
1578 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1581 if (ri
->type
& ARM_CP_CONST
) {
1582 /* If not forbidden by access permissions, treat as WI */
1584 } else if (ri
->writefn
) {
1586 tmpptr
= tcg_const_ptr(ri
);
1587 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1588 tcg_temp_free_ptr(tmpptr
);
1590 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1594 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1595 /* I/O operations must end the TB here (whether read or write) */
1597 s
->is_jmp
= DISAS_UPDATE
;
1598 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1599 /* We default to ending the TB on a coprocessor register write,
1600 * but allow this to be suppressed by the register definition
1601 * (usually only necessary to work around guest bugs).
1603 s
->is_jmp
= DISAS_UPDATE
;
1608 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1609 * +---------------------+---+-----+-----+-------+-------+-----+------+
1610 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1611 * +---------------------+---+-----+-----+-------+-------+-----+------+
1613 static void disas_system(DisasContext
*s
, uint32_t insn
)
1615 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1616 l
= extract32(insn
, 21, 1);
1617 op0
= extract32(insn
, 19, 2);
1618 op1
= extract32(insn
, 16, 3);
1619 crn
= extract32(insn
, 12, 4);
1620 crm
= extract32(insn
, 8, 4);
1621 op2
= extract32(insn
, 5, 3);
1622 rt
= extract32(insn
, 0, 5);
1625 if (l
|| rt
!= 31) {
1626 unallocated_encoding(s
);
1630 case 2: /* C5.6.68 HINT */
1631 handle_hint(s
, insn
, op1
, op2
, crm
);
1633 case 3: /* CLREX, DSB, DMB, ISB */
1634 handle_sync(s
, insn
, op1
, op2
, crm
);
1636 case 4: /* C5.6.130 MSR (immediate) */
1637 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1640 unallocated_encoding(s
);
1645 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1648 /* C3.2.3 Exception generation
1650 * 31 24 23 21 20 5 4 2 1 0
1651 * +-----------------+-----+------------------------+-----+----+
1652 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1653 * +-----------------------+------------------------+----------+
1655 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1657 int opc
= extract32(insn
, 21, 3);
1658 int op2_ll
= extract32(insn
, 0, 5);
1659 int imm16
= extract32(insn
, 5, 16);
1664 /* For SVC, HVC and SMC we advance the single-step state
1665 * machine before taking the exception. This is architecturally
1666 * mandated, to ensure that single-stepping a system call
1667 * instruction works properly.
1672 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1673 default_exception_el(s
));
1676 if (s
->current_el
== 0) {
1677 unallocated_encoding(s
);
1680 /* The pre HVC helper handles cases when HVC gets trapped
1681 * as an undefined insn by runtime configuration.
1683 gen_a64_set_pc_im(s
->pc
- 4);
1684 gen_helper_pre_hvc(cpu_env
);
1686 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1689 if (s
->current_el
== 0) {
1690 unallocated_encoding(s
);
1693 gen_a64_set_pc_im(s
->pc
- 4);
1694 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1695 gen_helper_pre_smc(cpu_env
, tmp
);
1696 tcg_temp_free_i32(tmp
);
1698 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1701 unallocated_encoding(s
);
1707 unallocated_encoding(s
);
1711 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1712 default_exception_el(s
));
1716 unallocated_encoding(s
);
1719 /* HLT. This has two purposes.
1720 * Architecturally, it is an external halting debug instruction.
1721 * Since QEMU doesn't implement external debug, we treat this as
1722 * it is required for halting debug disabled: it will UNDEF.
1723 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1725 if (semihosting_enabled() && imm16
== 0xf000) {
1726 #ifndef CONFIG_USER_ONLY
1727 /* In system mode, don't allow userspace access to semihosting,
1728 * to provide some semblance of security (and for consistency
1729 * with our 32-bit semihosting).
1731 if (s
->current_el
== 0) {
1732 unsupported_encoding(s
, insn
);
1736 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1738 unsupported_encoding(s
, insn
);
1742 if (op2_ll
< 1 || op2_ll
> 3) {
1743 unallocated_encoding(s
);
1746 /* DCPS1, DCPS2, DCPS3 */
1747 unsupported_encoding(s
, insn
);
1750 unallocated_encoding(s
);
1755 /* C3.2.7 Unconditional branch (register)
1756 * 31 25 24 21 20 16 15 10 9 5 4 0
1757 * +---------------+-------+-------+-------+------+-------+
1758 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1759 * +---------------+-------+-------+-------+------+-------+
1761 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1763 unsigned int opc
, op2
, op3
, rn
, op4
;
1765 opc
= extract32(insn
, 21, 4);
1766 op2
= extract32(insn
, 16, 5);
1767 op3
= extract32(insn
, 10, 6);
1768 rn
= extract32(insn
, 5, 5);
1769 op4
= extract32(insn
, 0, 5);
1771 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1772 unallocated_encoding(s
);
1780 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1781 /* BLR also needs to load return address */
1783 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1787 if (s
->current_el
== 0) {
1788 unallocated_encoding(s
);
1791 gen_helper_exception_return(cpu_env
);
1792 s
->is_jmp
= DISAS_JUMP
;
1796 unallocated_encoding(s
);
1798 unsupported_encoding(s
, insn
);
1802 unallocated_encoding(s
);
1806 s
->is_jmp
= DISAS_JUMP
;
1809 /* C3.2 Branches, exception generating and system instructions */
1810 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1812 switch (extract32(insn
, 25, 7)) {
1813 case 0x0a: case 0x0b:
1814 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1815 disas_uncond_b_imm(s
, insn
);
1817 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1818 disas_comp_b_imm(s
, insn
);
1820 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1821 disas_test_b_imm(s
, insn
);
1823 case 0x2a: /* Conditional branch (immediate) */
1824 disas_cond_b_imm(s
, insn
);
1826 case 0x6a: /* Exception generation / System */
1827 if (insn
& (1 << 24)) {
1828 disas_system(s
, insn
);
1833 case 0x6b: /* Unconditional branch (register) */
1834 disas_uncond_b_reg(s
, insn
);
1837 unallocated_encoding(s
);
1843 * Load/Store exclusive instructions are implemented by remembering
1844 * the value/address loaded, and seeing if these are the same
1845 * when the store is performed. This is not actually the architecturally
1846 * mandated semantics, but it works for typical guest code sequences
1847 * and avoids having to monitor regular stores.
1849 * In system emulation mode only one CPU will be running at once, so
1850 * this sequence is effectively atomic. In user emulation mode we
1851 * throw an exception and handle the atomic operation elsewhere.
1853 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1854 TCGv_i64 addr
, int size
, bool is_pair
)
1856 TCGv_i64 tmp
= tcg_temp_new_i64();
1857 TCGMemOp memop
= s
->be_data
+ size
;
1859 g_assert(size
<= 3);
1860 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1863 TCGv_i64 addr2
= tcg_temp_new_i64();
1864 TCGv_i64 hitmp
= tcg_temp_new_i64();
1866 g_assert(size
>= 2);
1867 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1868 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1869 tcg_temp_free_i64(addr2
);
1870 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1871 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1872 tcg_temp_free_i64(hitmp
);
1875 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1876 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1878 tcg_temp_free_i64(tmp
);
1879 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1882 #ifdef CONFIG_USER_ONLY
1883 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1884 TCGv_i64 addr
, int size
, int is_pair
)
1886 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1887 tcg_gen_movi_i32(cpu_exclusive_info
,
1888 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1889 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1892 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1893 TCGv_i64 inaddr
, int size
, int is_pair
)
1895 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1896 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1899 * [addr + datasize] = {Rt2};
1905 * env->exclusive_addr = -1;
1907 TCGLabel
*fail_label
= gen_new_label();
1908 TCGLabel
*done_label
= gen_new_label();
1909 TCGv_i64 addr
= tcg_temp_local_new_i64();
1912 /* Copy input into a local temp so it is not trashed when the
1913 * basic block ends at the branch insn.
1915 tcg_gen_mov_i64(addr
, inaddr
);
1916 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1918 tmp
= tcg_temp_new_i64();
1919 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), s
->be_data
+ size
);
1920 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1921 tcg_temp_free_i64(tmp
);
1924 TCGv_i64 addrhi
= tcg_temp_new_i64();
1925 TCGv_i64 tmphi
= tcg_temp_new_i64();
1927 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1928 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
),
1930 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1932 tcg_temp_free_i64(tmphi
);
1933 tcg_temp_free_i64(addrhi
);
1936 /* We seem to still have the exclusive monitor, so do the store */
1937 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
),
1940 TCGv_i64 addrhi
= tcg_temp_new_i64();
1942 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1943 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1944 get_mem_index(s
), s
->be_data
+ size
);
1945 tcg_temp_free_i64(addrhi
);
1948 tcg_temp_free_i64(addr
);
1950 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1951 tcg_gen_br(done_label
);
1952 gen_set_label(fail_label
);
1953 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1954 gen_set_label(done_label
);
1955 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1960 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1961 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1963 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1965 int opc0
= extract32(opc
, 0, 1);
1969 regsize
= opc0
? 32 : 64;
1971 regsize
= size
== 3 ? 64 : 32;
1973 return regsize
== 64;
1976 /* C3.3.6 Load/store exclusive
1978 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1979 * +-----+-------------+----+---+----+------+----+-------+------+------+
1980 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1981 * +-----+-------------+----+---+----+------+----+-------+------+------+
1983 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1984 * L: 0 -> store, 1 -> load
1985 * o2: 0 -> exclusive, 1 -> not
1986 * o1: 0 -> single register, 1 -> register pair
1987 * o0: 1 -> load-acquire/store-release, 0 -> not
1989 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1991 int rt
= extract32(insn
, 0, 5);
1992 int rn
= extract32(insn
, 5, 5);
1993 int rt2
= extract32(insn
, 10, 5);
1994 int is_lasr
= extract32(insn
, 15, 1);
1995 int rs
= extract32(insn
, 16, 5);
1996 int is_pair
= extract32(insn
, 21, 1);
1997 int is_store
= !extract32(insn
, 22, 1);
1998 int is_excl
= !extract32(insn
, 23, 1);
1999 int size
= extract32(insn
, 30, 2);
2002 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
2003 (!is_excl
&& is_pair
) ||
2004 (is_pair
&& size
< 2)) {
2005 unallocated_encoding(s
);
2010 gen_check_sp_alignment(s
);
2012 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2014 /* Note that since TCG is single threaded load-acquire/store-release
2015 * semantics require no extra if (is_lasr) { ... } handling.
2021 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2023 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2027 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2029 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2032 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2033 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2035 /* Generate ISS for non-exclusive accesses including LASR. */
2038 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2040 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2041 true, rt
, iss_sf
, is_lasr
);
2043 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2044 true, rt
, iss_sf
, is_lasr
);
2046 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2053 * C3.3.5 Load register (literal)
2055 * 31 30 29 27 26 25 24 23 5 4 0
2056 * +-----+-------+---+-----+-------------------+-------+
2057 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2058 * +-----+-------+---+-----+-------------------+-------+
2060 * V: 1 -> vector (simd/fp)
2061 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2062 * 10-> 32 bit signed, 11 -> prefetch
2063 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2065 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2067 int rt
= extract32(insn
, 0, 5);
2068 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2069 bool is_vector
= extract32(insn
, 26, 1);
2070 int opc
= extract32(insn
, 30, 2);
2071 bool is_signed
= false;
2073 TCGv_i64 tcg_rt
, tcg_addr
;
2077 unallocated_encoding(s
);
2081 if (!fp_access_check(s
)) {
2086 /* PRFM (literal) : prefetch */
2089 size
= 2 + extract32(opc
, 0, 1);
2090 is_signed
= extract32(opc
, 1, 1);
2093 tcg_rt
= cpu_reg(s
, rt
);
2095 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2097 do_fp_ld(s
, rt
, tcg_addr
, size
);
2099 /* Only unsigned 32bit loads target 32bit registers. */
2100 bool iss_sf
= opc
!= 0;
2102 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2103 true, rt
, iss_sf
, false);
2105 tcg_temp_free_i64(tcg_addr
);
2109 * C5.6.80 LDNP (Load Pair - non-temporal hint)
2110 * C5.6.81 LDP (Load Pair - non vector)
2111 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
2112 * C5.6.176 STNP (Store Pair - non-temporal hint)
2113 * C5.6.177 STP (Store Pair - non vector)
2114 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
2115 * C6.3.165 LDP (Load Pair of SIMD&FP)
2116 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
2117 * C6.3.284 STP (Store Pair of SIMD&FP)
2119 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2120 * +-----+-------+---+---+-------+---+-----------------------------+
2121 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2122 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2124 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2126 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2127 * V: 0 -> GPR, 1 -> Vector
2128 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2129 * 10 -> signed offset, 11 -> pre-index
2130 * L: 0 -> Store 1 -> Load
2132 * Rt, Rt2 = GPR or SIMD registers to be stored
2133 * Rn = general purpose register containing address
2134 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2136 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2138 int rt
= extract32(insn
, 0, 5);
2139 int rn
= extract32(insn
, 5, 5);
2140 int rt2
= extract32(insn
, 10, 5);
2141 uint64_t offset
= sextract64(insn
, 15, 7);
2142 int index
= extract32(insn
, 23, 2);
2143 bool is_vector
= extract32(insn
, 26, 1);
2144 bool is_load
= extract32(insn
, 22, 1);
2145 int opc
= extract32(insn
, 30, 2);
2147 bool is_signed
= false;
2148 bool postindex
= false;
2151 TCGv_i64 tcg_addr
; /* calculated address */
2155 unallocated_encoding(s
);
2162 size
= 2 + extract32(opc
, 1, 1);
2163 is_signed
= extract32(opc
, 0, 1);
2164 if (!is_load
&& is_signed
) {
2165 unallocated_encoding(s
);
2171 case 1: /* post-index */
2176 /* signed offset with "non-temporal" hint. Since we don't emulate
2177 * caches we don't care about hints to the cache system about
2178 * data access patterns, and handle this identically to plain
2182 /* There is no non-temporal-hint version of LDPSW */
2183 unallocated_encoding(s
);
2188 case 2: /* signed offset, rn not updated */
2191 case 3: /* pre-index */
2197 if (is_vector
&& !fp_access_check(s
)) {
2204 gen_check_sp_alignment(s
);
2207 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2210 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2215 do_fp_ld(s
, rt
, tcg_addr
, size
);
2217 do_fp_st(s
, rt
, tcg_addr
, size
);
2220 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2222 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2223 false, 0, false, false);
2225 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2226 false, 0, false, false);
2229 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2232 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2234 do_fp_st(s
, rt2
, tcg_addr
, size
);
2237 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2239 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2240 false, 0, false, false);
2242 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2243 false, 0, false, false);
2249 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2251 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2253 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2258 * C3.3.8 Load/store (immediate post-indexed)
2259 * C3.3.9 Load/store (immediate pre-indexed)
2260 * C3.3.12 Load/store (unscaled immediate)
2262 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2263 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2264 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2265 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2267 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2269 * V = 0 -> non-vector
2270 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2271 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2273 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2279 int rn
= extract32(insn
, 5, 5);
2280 int imm9
= sextract32(insn
, 12, 9);
2281 int idx
= extract32(insn
, 10, 2);
2282 bool is_signed
= false;
2283 bool is_store
= false;
2284 bool is_extended
= false;
2285 bool is_unpriv
= (idx
== 2);
2286 bool iss_valid
= !is_vector
;
2293 size
|= (opc
& 2) << 1;
2294 if (size
> 4 || is_unpriv
) {
2295 unallocated_encoding(s
);
2298 is_store
= ((opc
& 1) == 0);
2299 if (!fp_access_check(s
)) {
2303 if (size
== 3 && opc
== 2) {
2304 /* PRFM - prefetch */
2306 unallocated_encoding(s
);
2311 if (opc
== 3 && size
> 1) {
2312 unallocated_encoding(s
);
2315 is_store
= (opc
== 0);
2316 is_signed
= extract32(opc
, 1, 1);
2317 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2337 gen_check_sp_alignment(s
);
2339 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2342 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2347 do_fp_st(s
, rt
, tcg_addr
, size
);
2349 do_fp_ld(s
, rt
, tcg_addr
, size
);
2352 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2353 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2354 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2357 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2358 iss_valid
, rt
, iss_sf
, false);
2360 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2361 is_signed
, is_extended
, memidx
,
2362 iss_valid
, rt
, iss_sf
, false);
2367 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2369 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2371 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2376 * C3.3.10 Load/store (register offset)
2378 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2379 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2380 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2381 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2384 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2385 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2387 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2388 * opc<0>: 0 -> store, 1 -> load
2389 * V: 1 -> vector/simd
2390 * opt: extend encoding (see DecodeRegExtend)
2391 * S: if S=1 then scale (essentially index by sizeof(size))
2392 * Rt: register to transfer into/out of
2393 * Rn: address register or SP for base
2394 * Rm: offset register or ZR for offset
2396 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2402 int rn
= extract32(insn
, 5, 5);
2403 int shift
= extract32(insn
, 12, 1);
2404 int rm
= extract32(insn
, 16, 5);
2405 int opt
= extract32(insn
, 13, 3);
2406 bool is_signed
= false;
2407 bool is_store
= false;
2408 bool is_extended
= false;
2413 if (extract32(opt
, 1, 1) == 0) {
2414 unallocated_encoding(s
);
2419 size
|= (opc
& 2) << 1;
2421 unallocated_encoding(s
);
2424 is_store
= !extract32(opc
, 0, 1);
2425 if (!fp_access_check(s
)) {
2429 if (size
== 3 && opc
== 2) {
2430 /* PRFM - prefetch */
2433 if (opc
== 3 && size
> 1) {
2434 unallocated_encoding(s
);
2437 is_store
= (opc
== 0);
2438 is_signed
= extract32(opc
, 1, 1);
2439 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2443 gen_check_sp_alignment(s
);
2445 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2447 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2448 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2450 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2454 do_fp_st(s
, rt
, tcg_addr
, size
);
2456 do_fp_ld(s
, rt
, tcg_addr
, size
);
2459 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2460 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2462 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2463 true, rt
, iss_sf
, false);
2465 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2466 is_signed
, is_extended
,
2467 true, rt
, iss_sf
, false);
2473 * C3.3.13 Load/store (unsigned immediate)
2475 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2476 * +----+-------+---+-----+-----+------------+-------+------+
2477 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2478 * +----+-------+---+-----+-----+------------+-------+------+
2481 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2482 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2484 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2485 * opc<0>: 0 -> store, 1 -> load
2486 * Rn: base address register (inc SP)
2487 * Rt: target register
2489 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2495 int rn
= extract32(insn
, 5, 5);
2496 unsigned int imm12
= extract32(insn
, 10, 12);
2497 unsigned int offset
;
2502 bool is_signed
= false;
2503 bool is_extended
= false;
2506 size
|= (opc
& 2) << 1;
2508 unallocated_encoding(s
);
2511 is_store
= !extract32(opc
, 0, 1);
2512 if (!fp_access_check(s
)) {
2516 if (size
== 3 && opc
== 2) {
2517 /* PRFM - prefetch */
2520 if (opc
== 3 && size
> 1) {
2521 unallocated_encoding(s
);
2524 is_store
= (opc
== 0);
2525 is_signed
= extract32(opc
, 1, 1);
2526 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2530 gen_check_sp_alignment(s
);
2532 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2533 offset
= imm12
<< size
;
2534 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2538 do_fp_st(s
, rt
, tcg_addr
, size
);
2540 do_fp_ld(s
, rt
, tcg_addr
, size
);
2543 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2544 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2546 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2547 true, rt
, iss_sf
, false);
2549 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2550 true, rt
, iss_sf
, false);
2555 /* Load/store register (all forms) */
2556 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2558 int rt
= extract32(insn
, 0, 5);
2559 int opc
= extract32(insn
, 22, 2);
2560 bool is_vector
= extract32(insn
, 26, 1);
2561 int size
= extract32(insn
, 30, 2);
2563 switch (extract32(insn
, 24, 2)) {
2565 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2566 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2568 /* Load/store register (unscaled immediate)
2569 * Load/store immediate pre/post-indexed
2570 * Load/store register unprivileged
2572 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2576 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2579 unallocated_encoding(s
);
2584 /* C3.3.1 AdvSIMD load/store multiple structures
2586 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2587 * +---+---+---------------+---+-------------+--------+------+------+------+
2588 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2589 * +---+---+---------------+---+-------------+--------+------+------+------+
2591 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2593 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2594 * +---+---+---------------+---+---+---------+--------+------+------+------+
2595 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2596 * +---+---+---------------+---+---+---------+--------+------+------+------+
2598 * Rt: first (or only) SIMD&FP register to be transferred
2599 * Rn: base address or SP
2600 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2602 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2604 int rt
= extract32(insn
, 0, 5);
2605 int rn
= extract32(insn
, 5, 5);
2606 int size
= extract32(insn
, 10, 2);
2607 int opcode
= extract32(insn
, 12, 4);
2608 bool is_store
= !extract32(insn
, 22, 1);
2609 bool is_postidx
= extract32(insn
, 23, 1);
2610 bool is_q
= extract32(insn
, 30, 1);
2611 TCGv_i64 tcg_addr
, tcg_rn
;
2613 int ebytes
= 1 << size
;
2614 int elements
= (is_q
? 128 : 64) / (8 << size
);
2615 int rpt
; /* num iterations */
2616 int selem
; /* structure elements */
2619 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2620 unallocated_encoding(s
);
2624 /* From the shared decode logic */
2655 unallocated_encoding(s
);
2659 if (size
== 3 && !is_q
&& selem
!= 1) {
2661 unallocated_encoding(s
);
2665 if (!fp_access_check(s
)) {
2670 gen_check_sp_alignment(s
);
2673 tcg_rn
= cpu_reg_sp(s
, rn
);
2674 tcg_addr
= tcg_temp_new_i64();
2675 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2677 for (r
= 0; r
< rpt
; r
++) {
2679 for (e
= 0; e
< elements
; e
++) {
2680 int tt
= (rt
+ r
) % 32;
2682 for (xs
= 0; xs
< selem
; xs
++) {
2684 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2686 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2688 /* For non-quad operations, setting a slice of the low
2689 * 64 bits of the register clears the high 64 bits (in
2690 * the ARM ARM pseudocode this is implicit in the fact
2691 * that 'rval' is a 64 bit wide variable). We optimize
2692 * by noticing that we only need to do this the first
2693 * time we touch a register.
2695 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2696 clear_vec_high(s
, tt
);
2699 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2706 int rm
= extract32(insn
, 16, 5);
2708 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2710 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2713 tcg_temp_free_i64(tcg_addr
);
2716 /* C3.3.3 AdvSIMD load/store single structure
2718 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2719 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2720 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2721 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2723 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2725 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2726 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2727 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2728 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2730 * Rt: first (or only) SIMD&FP register to be transferred
2731 * Rn: base address or SP
2732 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2733 * index = encoded in Q:S:size dependent on size
2735 * lane_size = encoded in R, opc
2736 * transfer width = encoded in opc, S, size
2738 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2740 int rt
= extract32(insn
, 0, 5);
2741 int rn
= extract32(insn
, 5, 5);
2742 int size
= extract32(insn
, 10, 2);
2743 int S
= extract32(insn
, 12, 1);
2744 int opc
= extract32(insn
, 13, 3);
2745 int R
= extract32(insn
, 21, 1);
2746 int is_load
= extract32(insn
, 22, 1);
2747 int is_postidx
= extract32(insn
, 23, 1);
2748 int is_q
= extract32(insn
, 30, 1);
2750 int scale
= extract32(opc
, 1, 2);
2751 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2752 bool replicate
= false;
2753 int index
= is_q
<< 3 | S
<< 2 | size
;
2755 TCGv_i64 tcg_addr
, tcg_rn
;
2759 if (!is_load
|| S
) {
2760 unallocated_encoding(s
);
2769 if (extract32(size
, 0, 1)) {
2770 unallocated_encoding(s
);
2776 if (extract32(size
, 1, 1)) {
2777 unallocated_encoding(s
);
2780 if (!extract32(size
, 0, 1)) {
2784 unallocated_encoding(s
);
2792 g_assert_not_reached();
2795 if (!fp_access_check(s
)) {
2799 ebytes
= 1 << scale
;
2802 gen_check_sp_alignment(s
);
2805 tcg_rn
= cpu_reg_sp(s
, rn
);
2806 tcg_addr
= tcg_temp_new_i64();
2807 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2809 for (xs
= 0; xs
< selem
; xs
++) {
2811 /* Load and replicate to all elements */
2813 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2815 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2816 get_mem_index(s
), s
->be_data
+ scale
);
2819 mulconst
= 0x0101010101010101ULL
;
2822 mulconst
= 0x0001000100010001ULL
;
2825 mulconst
= 0x0000000100000001ULL
;
2831 g_assert_not_reached();
2834 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2836 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2838 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2840 clear_vec_high(s
, rt
);
2842 tcg_temp_free_i64(tcg_tmp
);
2844 /* Load/store one element per register */
2846 do_vec_ld(s
, rt
, index
, tcg_addr
, s
->be_data
+ scale
);
2848 do_vec_st(s
, rt
, index
, tcg_addr
, s
->be_data
+ scale
);
2851 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2856 int rm
= extract32(insn
, 16, 5);
2858 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2860 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2863 tcg_temp_free_i64(tcg_addr
);
2866 /* C3.3 Loads and stores */
2867 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2869 switch (extract32(insn
, 24, 6)) {
2870 case 0x08: /* Load/store exclusive */
2871 disas_ldst_excl(s
, insn
);
2873 case 0x18: case 0x1c: /* Load register (literal) */
2874 disas_ld_lit(s
, insn
);
2876 case 0x28: case 0x29:
2877 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2878 disas_ldst_pair(s
, insn
);
2880 case 0x38: case 0x39:
2881 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2882 disas_ldst_reg(s
, insn
);
2884 case 0x0c: /* AdvSIMD load/store multiple structures */
2885 disas_ldst_multiple_struct(s
, insn
);
2887 case 0x0d: /* AdvSIMD load/store single structure */
2888 disas_ldst_single_struct(s
, insn
);
2891 unallocated_encoding(s
);
2896 /* C3.4.6 PC-rel. addressing
2897 * 31 30 29 28 24 23 5 4 0
2898 * +----+-------+-----------+-------------------+------+
2899 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2900 * +----+-------+-----------+-------------------+------+
2902 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2904 unsigned int page
, rd
;
2908 page
= extract32(insn
, 31, 1);
2909 /* SignExtend(immhi:immlo) -> offset */
2910 offset
= sextract64(insn
, 5, 19);
2911 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2912 rd
= extract32(insn
, 0, 5);
2916 /* ADRP (page based) */
2921 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2925 * C3.4.1 Add/subtract (immediate)
2927 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2928 * +--+--+--+-----------+-----+-------------+-----+-----+
2929 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2930 * +--+--+--+-----------+-----+-------------+-----+-----+
2932 * sf: 0 -> 32bit, 1 -> 64bit
2933 * op: 0 -> add , 1 -> sub
2935 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2937 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2939 int rd
= extract32(insn
, 0, 5);
2940 int rn
= extract32(insn
, 5, 5);
2941 uint64_t imm
= extract32(insn
, 10, 12);
2942 int shift
= extract32(insn
, 22, 2);
2943 bool setflags
= extract32(insn
, 29, 1);
2944 bool sub_op
= extract32(insn
, 30, 1);
2945 bool is_64bit
= extract32(insn
, 31, 1);
2947 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2948 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2949 TCGv_i64 tcg_result
;
2958 unallocated_encoding(s
);
2962 tcg_result
= tcg_temp_new_i64();
2965 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2967 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2970 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2972 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2974 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2976 tcg_temp_free_i64(tcg_imm
);
2980 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2982 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2985 tcg_temp_free_i64(tcg_result
);
2988 /* The input should be a value in the bottom e bits (with higher
2989 * bits zero); returns that value replicated into every element
2990 * of size e in a 64 bit integer.
2992 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3002 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3003 static inline uint64_t bitmask64(unsigned int length
)
3005 assert(length
> 0 && length
<= 64);
3006 return ~0ULL >> (64 - length
);
3009 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3010 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3011 * value (ie should cause a guest UNDEF exception), and true if they are
3012 * valid, in which case the decoded bit pattern is written to result.
3014 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3015 unsigned int imms
, unsigned int immr
)
3018 unsigned e
, levels
, s
, r
;
3021 assert(immn
< 2 && imms
< 64 && immr
< 64);
3023 /* The bit patterns we create here are 64 bit patterns which
3024 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3025 * 64 bits each. Each element contains the same value: a run
3026 * of between 1 and e-1 non-zero bits, rotated within the
3027 * element by between 0 and e-1 bits.
3029 * The element size and run length are encoded into immn (1 bit)
3030 * and imms (6 bits) as follows:
3031 * 64 bit elements: immn = 1, imms = <length of run - 1>
3032 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3033 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3034 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3035 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3036 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3037 * Notice that immn = 0, imms = 11111x is the only combination
3038 * not covered by one of the above options; this is reserved.
3039 * Further, <length of run - 1> all-ones is a reserved pattern.
3041 * In all cases the rotation is by immr % e (and immr is 6 bits).
3044 /* First determine the element size */
3045 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3047 /* This is the immn == 0, imms == 0x11111x case */
3057 /* <length of run - 1> mustn't be all-ones. */
3061 /* Create the value of one element: s+1 set bits rotated
3062 * by r within the element (which is e bits wide)...
3064 mask
= bitmask64(s
+ 1);
3066 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3067 mask
&= bitmask64(e
);
3069 /* ...then replicate the element over the whole 64 bit value */
3070 mask
= bitfield_replicate(mask
, e
);
3075 /* C3.4.4 Logical (immediate)
3076 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3077 * +----+-----+-------------+---+------+------+------+------+
3078 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3079 * +----+-----+-------------+---+------+------+------+------+
3081 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3083 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3084 TCGv_i64 tcg_rd
, tcg_rn
;
3086 bool is_and
= false;
3088 sf
= extract32(insn
, 31, 1);
3089 opc
= extract32(insn
, 29, 2);
3090 is_n
= extract32(insn
, 22, 1);
3091 immr
= extract32(insn
, 16, 6);
3092 imms
= extract32(insn
, 10, 6);
3093 rn
= extract32(insn
, 5, 5);
3094 rd
= extract32(insn
, 0, 5);
3097 unallocated_encoding(s
);
3101 if (opc
== 0x3) { /* ANDS */
3102 tcg_rd
= cpu_reg(s
, rd
);
3104 tcg_rd
= cpu_reg_sp(s
, rd
);
3106 tcg_rn
= cpu_reg(s
, rn
);
3108 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3109 /* some immediate field values are reserved */
3110 unallocated_encoding(s
);
3115 wmask
&= 0xffffffff;
3119 case 0x3: /* ANDS */
3121 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3125 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3128 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3131 assert(FALSE
); /* must handle all above */
3135 if (!sf
&& !is_and
) {
3136 /* zero extend final result; we know we can skip this for AND
3137 * since the immediate had the high 32 bits clear.
3139 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3142 if (opc
== 3) { /* ANDS */
3143 gen_logic_CC(sf
, tcg_rd
);
3148 * C3.4.5 Move wide (immediate)
3150 * 31 30 29 28 23 22 21 20 5 4 0
3151 * +--+-----+-------------+-----+----------------+------+
3152 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3153 * +--+-----+-------------+-----+----------------+------+
3155 * sf: 0 -> 32 bit, 1 -> 64 bit
3156 * opc: 00 -> N, 10 -> Z, 11 -> K
3157 * hw: shift/16 (0,16, and sf only 32, 48)
3159 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3161 int rd
= extract32(insn
, 0, 5);
3162 uint64_t imm
= extract32(insn
, 5, 16);
3163 int sf
= extract32(insn
, 31, 1);
3164 int opc
= extract32(insn
, 29, 2);
3165 int pos
= extract32(insn
, 21, 2) << 4;
3166 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3169 if (!sf
&& (pos
>= 32)) {
3170 unallocated_encoding(s
);
3184 tcg_gen_movi_i64(tcg_rd
, imm
);
3187 tcg_imm
= tcg_const_i64(imm
);
3188 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3189 tcg_temp_free_i64(tcg_imm
);
3191 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3195 unallocated_encoding(s
);
3201 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3202 * +----+-----+-------------+---+------+------+------+------+
3203 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3204 * +----+-----+-------------+---+------+------+------+------+
3206 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3208 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3209 TCGv_i64 tcg_rd
, tcg_tmp
;
3211 sf
= extract32(insn
, 31, 1);
3212 opc
= extract32(insn
, 29, 2);
3213 n
= extract32(insn
, 22, 1);
3214 ri
= extract32(insn
, 16, 6);
3215 si
= extract32(insn
, 10, 6);
3216 rn
= extract32(insn
, 5, 5);
3217 rd
= extract32(insn
, 0, 5);
3218 bitsize
= sf
? 64 : 32;
3220 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3221 unallocated_encoding(s
);
3225 tcg_rd
= cpu_reg(s
, rd
);
3227 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3228 to be smaller than bitsize, we'll never reference data outside the
3229 low 32-bits anyway. */
3230 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3232 /* Recognize the common aliases. */
3233 if (opc
== 0) { /* SBFM */
3235 if (si
== 7) { /* SXTB */
3236 tcg_gen_ext8s_i64(tcg_rd
, tcg_tmp
);
3238 } else if (si
== 15) { /* SXTH */
3239 tcg_gen_ext16s_i64(tcg_rd
, tcg_tmp
);
3241 } else if (si
== 31) { /* SXTW */
3242 tcg_gen_ext32s_i64(tcg_rd
, tcg_tmp
);
3246 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* ASR */
3248 tcg_gen_ext32s_i64(tcg_tmp
, tcg_tmp
);
3250 tcg_gen_sari_i64(tcg_rd
, tcg_tmp
, ri
);
3253 } else if (opc
== 2) { /* UBFM */
3254 if (ri
== 0) { /* UXTB, UXTH, plus non-canonical AND */
3255 tcg_gen_andi_i64(tcg_rd
, tcg_tmp
, bitmask64(si
+ 1));
3258 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* LSR */
3260 tcg_gen_ext32u_i64(tcg_tmp
, tcg_tmp
);
3262 tcg_gen_shri_i64(tcg_rd
, tcg_tmp
, ri
);
3265 if (si
+ 1 == ri
&& si
!= bitsize
- 1) { /* LSL */
3266 int shift
= bitsize
- 1 - si
;
3267 tcg_gen_shli_i64(tcg_rd
, tcg_tmp
, shift
);
3272 if (opc
!= 1) { /* SBFM or UBFM */
3273 tcg_gen_movi_i64(tcg_rd
, 0);
3276 /* do the bit move operation */
3278 /* Wd<s-r:0> = Wn<s:r> */
3279 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
3281 len
= (si
- ri
) + 1;
3283 /* Wd<32+s-r,32-r> = Wn<s:0> */
3288 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3290 if (opc
== 0) { /* SBFM - sign extend the destination field */
3291 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3292 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3296 if (!sf
) { /* zero extend final result */
3297 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3302 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3303 * +----+------+-------------+---+----+------+--------+------+------+
3304 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3305 * +----+------+-------------+---+----+------+--------+------+------+
3307 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3309 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3311 sf
= extract32(insn
, 31, 1);
3312 n
= extract32(insn
, 22, 1);
3313 rm
= extract32(insn
, 16, 5);
3314 imm
= extract32(insn
, 10, 6);
3315 rn
= extract32(insn
, 5, 5);
3316 rd
= extract32(insn
, 0, 5);
3317 op21
= extract32(insn
, 29, 2);
3318 op0
= extract32(insn
, 21, 1);
3319 bitsize
= sf
? 64 : 32;
3321 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3322 unallocated_encoding(s
);
3324 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3326 tcg_rd
= cpu_reg(s
, rd
);
3328 if (unlikely(imm
== 0)) {
3329 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3330 * so an extract from bit 0 is a special case.
3333 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3335 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3337 } else if (rm
== rn
) { /* ROR */
3338 tcg_rm
= cpu_reg(s
, rm
);
3340 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3342 TCGv_i32 tmp
= tcg_temp_new_i32();
3343 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3344 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3345 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3346 tcg_temp_free_i32(tmp
);
3349 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3350 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3351 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3352 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3353 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3355 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3361 /* C3.4 Data processing - immediate */
3362 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3364 switch (extract32(insn
, 23, 6)) {
3365 case 0x20: case 0x21: /* PC-rel. addressing */
3366 disas_pc_rel_adr(s
, insn
);
3368 case 0x22: case 0x23: /* Add/subtract (immediate) */
3369 disas_add_sub_imm(s
, insn
);
3371 case 0x24: /* Logical (immediate) */
3372 disas_logic_imm(s
, insn
);
3374 case 0x25: /* Move wide (immediate) */
3375 disas_movw_imm(s
, insn
);
3377 case 0x26: /* Bitfield */
3378 disas_bitfield(s
, insn
);
3380 case 0x27: /* Extract */
3381 disas_extract(s
, insn
);
3384 unallocated_encoding(s
);
3389 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3390 * Note that it is the caller's responsibility to ensure that the
3391 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3392 * mandated semantics for out of range shifts.
3394 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3395 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3397 switch (shift_type
) {
3398 case A64_SHIFT_TYPE_LSL
:
3399 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3401 case A64_SHIFT_TYPE_LSR
:
3402 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3404 case A64_SHIFT_TYPE_ASR
:
3406 tcg_gen_ext32s_i64(dst
, src
);
3408 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3410 case A64_SHIFT_TYPE_ROR
:
3412 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3415 t0
= tcg_temp_new_i32();
3416 t1
= tcg_temp_new_i32();
3417 tcg_gen_extrl_i64_i32(t0
, src
);
3418 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3419 tcg_gen_rotr_i32(t0
, t0
, t1
);
3420 tcg_gen_extu_i32_i64(dst
, t0
);
3421 tcg_temp_free_i32(t0
);
3422 tcg_temp_free_i32(t1
);
3426 assert(FALSE
); /* all shift types should be handled */
3430 if (!sf
) { /* zero extend final result */
3431 tcg_gen_ext32u_i64(dst
, dst
);
3435 /* Shift a TCGv src by immediate, put result in dst.
3436 * The shift amount must be in range (this should always be true as the
3437 * relevant instructions will UNDEF on bad shift immediates).
3439 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3440 enum a64_shift_type shift_type
, unsigned int shift_i
)
3442 assert(shift_i
< (sf
? 64 : 32));
3445 tcg_gen_mov_i64(dst
, src
);
3447 TCGv_i64 shift_const
;
3449 shift_const
= tcg_const_i64(shift_i
);
3450 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3451 tcg_temp_free_i64(shift_const
);
3455 /* C3.5.10 Logical (shifted register)
3456 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3457 * +----+-----+-----------+-------+---+------+--------+------+------+
3458 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3459 * +----+-----+-----------+-------+---+------+--------+------+------+
3461 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3463 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3464 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3466 sf
= extract32(insn
, 31, 1);
3467 opc
= extract32(insn
, 29, 2);
3468 shift_type
= extract32(insn
, 22, 2);
3469 invert
= extract32(insn
, 21, 1);
3470 rm
= extract32(insn
, 16, 5);
3471 shift_amount
= extract32(insn
, 10, 6);
3472 rn
= extract32(insn
, 5, 5);
3473 rd
= extract32(insn
, 0, 5);
3475 if (!sf
&& (shift_amount
& (1 << 5))) {
3476 unallocated_encoding(s
);
3480 tcg_rd
= cpu_reg(s
, rd
);
3482 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3483 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3484 * register-register MOV and MVN, so it is worth special casing.
3486 tcg_rm
= cpu_reg(s
, rm
);
3488 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3490 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3494 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3496 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3502 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3505 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3508 tcg_rn
= cpu_reg(s
, rn
);
3510 switch (opc
| (invert
<< 2)) {
3513 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3516 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3519 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3523 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3526 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3529 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3537 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3541 gen_logic_CC(sf
, tcg_rd
);
3546 * C3.5.1 Add/subtract (extended register)
3548 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3549 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3550 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3551 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3553 * sf: 0 -> 32bit, 1 -> 64bit
3554 * op: 0 -> add , 1 -> sub
3557 * option: extension type (see DecodeRegExtend)
3558 * imm3: optional shift to Rm
3560 * Rd = Rn + LSL(extend(Rm), amount)
3562 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3564 int rd
= extract32(insn
, 0, 5);
3565 int rn
= extract32(insn
, 5, 5);
3566 int imm3
= extract32(insn
, 10, 3);
3567 int option
= extract32(insn
, 13, 3);
3568 int rm
= extract32(insn
, 16, 5);
3569 bool setflags
= extract32(insn
, 29, 1);
3570 bool sub_op
= extract32(insn
, 30, 1);
3571 bool sf
= extract32(insn
, 31, 1);
3573 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3575 TCGv_i64 tcg_result
;
3578 unallocated_encoding(s
);
3582 /* non-flag setting ops may use SP */
3584 tcg_rd
= cpu_reg_sp(s
, rd
);
3586 tcg_rd
= cpu_reg(s
, rd
);
3588 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3590 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3591 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3593 tcg_result
= tcg_temp_new_i64();
3597 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3599 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3603 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3605 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3610 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3612 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3615 tcg_temp_free_i64(tcg_result
);
3619 * C3.5.2 Add/subtract (shifted register)
3621 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3622 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3623 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3624 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3626 * sf: 0 -> 32bit, 1 -> 64bit
3627 * op: 0 -> add , 1 -> sub
3629 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3630 * imm6: Shift amount to apply to Rm before the add/sub
3632 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3634 int rd
= extract32(insn
, 0, 5);
3635 int rn
= extract32(insn
, 5, 5);
3636 int imm6
= extract32(insn
, 10, 6);
3637 int rm
= extract32(insn
, 16, 5);
3638 int shift_type
= extract32(insn
, 22, 2);
3639 bool setflags
= extract32(insn
, 29, 1);
3640 bool sub_op
= extract32(insn
, 30, 1);
3641 bool sf
= extract32(insn
, 31, 1);
3643 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3644 TCGv_i64 tcg_rn
, tcg_rm
;
3645 TCGv_i64 tcg_result
;
3647 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3648 unallocated_encoding(s
);
3652 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3653 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3655 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3657 tcg_result
= tcg_temp_new_i64();
3661 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3663 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3667 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3669 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3674 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3676 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3679 tcg_temp_free_i64(tcg_result
);
3682 /* C3.5.9 Data-processing (3 source)
3684 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3685 +--+------+-----------+------+------+----+------+------+------+
3686 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3687 +--+------+-----------+------+------+----+------+------+------+
3690 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3692 int rd
= extract32(insn
, 0, 5);
3693 int rn
= extract32(insn
, 5, 5);
3694 int ra
= extract32(insn
, 10, 5);
3695 int rm
= extract32(insn
, 16, 5);
3696 int op_id
= (extract32(insn
, 29, 3) << 4) |
3697 (extract32(insn
, 21, 3) << 1) |
3698 extract32(insn
, 15, 1);
3699 bool sf
= extract32(insn
, 31, 1);
3700 bool is_sub
= extract32(op_id
, 0, 1);
3701 bool is_high
= extract32(op_id
, 2, 1);
3702 bool is_signed
= false;
3707 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3709 case 0x42: /* SMADDL */
3710 case 0x43: /* SMSUBL */
3711 case 0x44: /* SMULH */
3714 case 0x0: /* MADD (32bit) */
3715 case 0x1: /* MSUB (32bit) */
3716 case 0x40: /* MADD (64bit) */
3717 case 0x41: /* MSUB (64bit) */
3718 case 0x4a: /* UMADDL */
3719 case 0x4b: /* UMSUBL */
3720 case 0x4c: /* UMULH */
3723 unallocated_encoding(s
);
3728 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3729 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3730 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3731 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3734 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3736 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3739 tcg_temp_free_i64(low_bits
);
3743 tcg_op1
= tcg_temp_new_i64();
3744 tcg_op2
= tcg_temp_new_i64();
3745 tcg_tmp
= tcg_temp_new_i64();
3748 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3749 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3752 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3753 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3755 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3756 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3760 if (ra
== 31 && !is_sub
) {
3761 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3762 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3764 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3766 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3768 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3773 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3776 tcg_temp_free_i64(tcg_op1
);
3777 tcg_temp_free_i64(tcg_op2
);
3778 tcg_temp_free_i64(tcg_tmp
);
3781 /* C3.5.3 - Add/subtract (with carry)
3782 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3783 * +--+--+--+------------------------+------+---------+------+-----+
3784 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3785 * +--+--+--+------------------------+------+---------+------+-----+
3789 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3791 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3792 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3794 if (extract32(insn
, 10, 6) != 0) {
3795 unallocated_encoding(s
);
3799 sf
= extract32(insn
, 31, 1);
3800 op
= extract32(insn
, 30, 1);
3801 setflags
= extract32(insn
, 29, 1);
3802 rm
= extract32(insn
, 16, 5);
3803 rn
= extract32(insn
, 5, 5);
3804 rd
= extract32(insn
, 0, 5);
3806 tcg_rd
= cpu_reg(s
, rd
);
3807 tcg_rn
= cpu_reg(s
, rn
);
3810 tcg_y
= new_tmp_a64(s
);
3811 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3813 tcg_y
= cpu_reg(s
, rm
);
3817 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3819 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3823 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3824 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3825 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3826 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3827 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3830 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3832 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3833 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3834 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3837 if (!extract32(insn
, 29, 1)) {
3838 unallocated_encoding(s
);
3841 if (insn
& (1 << 10 | 1 << 4)) {
3842 unallocated_encoding(s
);
3845 sf
= extract32(insn
, 31, 1);
3846 op
= extract32(insn
, 30, 1);
3847 is_imm
= extract32(insn
, 11, 1);
3848 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3849 cond
= extract32(insn
, 12, 4);
3850 rn
= extract32(insn
, 5, 5);
3851 nzcv
= extract32(insn
, 0, 4);
3853 /* Set T0 = !COND. */
3854 tcg_t0
= tcg_temp_new_i32();
3855 arm_test_cc(&c
, cond
);
3856 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3859 /* Load the arguments for the new comparison. */
3861 tcg_y
= new_tmp_a64(s
);
3862 tcg_gen_movi_i64(tcg_y
, y
);
3864 tcg_y
= cpu_reg(s
, y
);
3866 tcg_rn
= cpu_reg(s
, rn
);
3868 /* Set the flags for the new comparison. */
3869 tcg_tmp
= tcg_temp_new_i64();
3871 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3873 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3875 tcg_temp_free_i64(tcg_tmp
);
3877 /* If COND was false, force the flags to #nzcv. Compute two masks
3878 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3879 * For tcg hosts that support ANDC, we can make do with just T1.
3880 * In either case, allow the tcg optimizer to delete any unused mask.
3882 tcg_t1
= tcg_temp_new_i32();
3883 tcg_t2
= tcg_temp_new_i32();
3884 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3885 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3887 if (nzcv
& 8) { /* N */
3888 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3890 if (TCG_TARGET_HAS_andc_i32
) {
3891 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3893 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3896 if (nzcv
& 4) { /* Z */
3897 if (TCG_TARGET_HAS_andc_i32
) {
3898 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3900 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3903 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3905 if (nzcv
& 2) { /* C */
3906 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3908 if (TCG_TARGET_HAS_andc_i32
) {
3909 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3911 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3914 if (nzcv
& 1) { /* V */
3915 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3917 if (TCG_TARGET_HAS_andc_i32
) {
3918 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3920 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3923 tcg_temp_free_i32(tcg_t0
);
3924 tcg_temp_free_i32(tcg_t1
);
3925 tcg_temp_free_i32(tcg_t2
);
3928 /* C3.5.6 Conditional select
3929 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3930 * +----+----+---+-----------------+------+------+-----+------+------+
3931 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3932 * +----+----+---+-----------------+------+------+-----+------+------+
3934 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3936 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3937 TCGv_i64 tcg_rd
, zero
;
3940 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3941 /* S == 1 or op2<1> == 1 */
3942 unallocated_encoding(s
);
3945 sf
= extract32(insn
, 31, 1);
3946 else_inv
= extract32(insn
, 30, 1);
3947 rm
= extract32(insn
, 16, 5);
3948 cond
= extract32(insn
, 12, 4);
3949 else_inc
= extract32(insn
, 10, 1);
3950 rn
= extract32(insn
, 5, 5);
3951 rd
= extract32(insn
, 0, 5);
3953 tcg_rd
= cpu_reg(s
, rd
);
3955 a64_test_cc(&c
, cond
);
3956 zero
= tcg_const_i64(0);
3958 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3960 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3962 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3965 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3966 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3967 if (else_inv
&& else_inc
) {
3968 tcg_gen_neg_i64(t_false
, t_false
);
3969 } else if (else_inv
) {
3970 tcg_gen_not_i64(t_false
, t_false
);
3971 } else if (else_inc
) {
3972 tcg_gen_addi_i64(t_false
, t_false
, 1);
3974 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3977 tcg_temp_free_i64(zero
);
3981 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3985 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3986 unsigned int rn
, unsigned int rd
)
3988 TCGv_i64 tcg_rd
, tcg_rn
;
3989 tcg_rd
= cpu_reg(s
, rd
);
3990 tcg_rn
= cpu_reg(s
, rn
);
3993 gen_helper_clz64(tcg_rd
, tcg_rn
);
3995 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3996 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3997 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3998 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3999 tcg_temp_free_i32(tcg_tmp32
);
4003 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4004 unsigned int rn
, unsigned int rd
)
4006 TCGv_i64 tcg_rd
, tcg_rn
;
4007 tcg_rd
= cpu_reg(s
, rd
);
4008 tcg_rn
= cpu_reg(s
, rn
);
4011 gen_helper_cls64(tcg_rd
, tcg_rn
);
4013 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4014 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4015 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
4016 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4017 tcg_temp_free_i32(tcg_tmp32
);
4021 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4022 unsigned int rn
, unsigned int rd
)
4024 TCGv_i64 tcg_rd
, tcg_rn
;
4025 tcg_rd
= cpu_reg(s
, rd
);
4026 tcg_rn
= cpu_reg(s
, rn
);
4029 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4031 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4032 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4033 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4034 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4035 tcg_temp_free_i32(tcg_tmp32
);
4039 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
4040 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4041 unsigned int rn
, unsigned int rd
)
4044 unallocated_encoding(s
);
4047 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4050 /* C5.6.149 REV with sf==0, opcode==2
4051 * C5.6.151 REV32 (sf==1, opcode==2)
4053 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4054 unsigned int rn
, unsigned int rd
)
4056 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4059 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4060 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4062 /* bswap32_i64 requires zero high word */
4063 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4064 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4065 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4066 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4067 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4069 tcg_temp_free_i64(tcg_tmp
);
4071 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4072 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4076 /* C5.6.150 REV16 (opcode==1) */
4077 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4078 unsigned int rn
, unsigned int rd
)
4080 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4081 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4082 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4084 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
4085 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
4087 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
4088 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4089 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4090 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
4093 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4094 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4095 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4096 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
4098 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
4099 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4100 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
4103 tcg_temp_free_i64(tcg_tmp
);
4106 /* C3.5.7 Data-processing (1 source)
4107 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4108 * +----+---+---+-----------------+---------+--------+------+------+
4109 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4110 * +----+---+---+-----------------+---------+--------+------+------+
4112 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4114 unsigned int sf
, opcode
, rn
, rd
;
4116 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4117 unallocated_encoding(s
);
4121 sf
= extract32(insn
, 31, 1);
4122 opcode
= extract32(insn
, 10, 6);
4123 rn
= extract32(insn
, 5, 5);
4124 rd
= extract32(insn
, 0, 5);
4128 handle_rbit(s
, sf
, rn
, rd
);
4131 handle_rev16(s
, sf
, rn
, rd
);
4134 handle_rev32(s
, sf
, rn
, rd
);
4137 handle_rev64(s
, sf
, rn
, rd
);
4140 handle_clz(s
, sf
, rn
, rd
);
4143 handle_cls(s
, sf
, rn
, rd
);
4148 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4149 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4151 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4152 tcg_rd
= cpu_reg(s
, rd
);
4154 if (!sf
&& is_signed
) {
4155 tcg_n
= new_tmp_a64(s
);
4156 tcg_m
= new_tmp_a64(s
);
4157 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4158 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4160 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4161 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4165 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4167 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4170 if (!sf
) { /* zero extend final result */
4171 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4175 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
4176 static void handle_shift_reg(DisasContext
*s
,
4177 enum a64_shift_type shift_type
, unsigned int sf
,
4178 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4180 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4181 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4182 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4184 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4185 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4186 tcg_temp_free_i64(tcg_shift
);
4189 /* CRC32[BHWX], CRC32C[BHWX] */
4190 static void handle_crc32(DisasContext
*s
,
4191 unsigned int sf
, unsigned int sz
, bool crc32c
,
4192 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4194 TCGv_i64 tcg_acc
, tcg_val
;
4197 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4198 || (sf
== 1 && sz
!= 3)
4199 || (sf
== 0 && sz
== 3)) {
4200 unallocated_encoding(s
);
4205 tcg_val
= cpu_reg(s
, rm
);
4219 g_assert_not_reached();
4221 tcg_val
= new_tmp_a64(s
);
4222 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4225 tcg_acc
= cpu_reg(s
, rn
);
4226 tcg_bytes
= tcg_const_i32(1 << sz
);
4229 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4231 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4234 tcg_temp_free_i32(tcg_bytes
);
4237 /* C3.5.8 Data-processing (2 source)
4238 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4239 * +----+---+---+-----------------+------+--------+------+------+
4240 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4241 * +----+---+---+-----------------+------+--------+------+------+
4243 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4245 unsigned int sf
, rm
, opcode
, rn
, rd
;
4246 sf
= extract32(insn
, 31, 1);
4247 rm
= extract32(insn
, 16, 5);
4248 opcode
= extract32(insn
, 10, 6);
4249 rn
= extract32(insn
, 5, 5);
4250 rd
= extract32(insn
, 0, 5);
4252 if (extract32(insn
, 29, 1)) {
4253 unallocated_encoding(s
);
4259 handle_div(s
, false, sf
, rm
, rn
, rd
);
4262 handle_div(s
, true, sf
, rm
, rn
, rd
);
4265 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4268 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4271 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4274 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4283 case 23: /* CRC32 */
4285 int sz
= extract32(opcode
, 0, 2);
4286 bool crc32c
= extract32(opcode
, 2, 1);
4287 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4291 unallocated_encoding(s
);
4296 /* C3.5 Data processing - register */
4297 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4299 switch (extract32(insn
, 24, 5)) {
4300 case 0x0a: /* Logical (shifted register) */
4301 disas_logic_reg(s
, insn
);
4303 case 0x0b: /* Add/subtract */
4304 if (insn
& (1 << 21)) { /* (extended register) */
4305 disas_add_sub_ext_reg(s
, insn
);
4307 disas_add_sub_reg(s
, insn
);
4310 case 0x1b: /* Data-processing (3 source) */
4311 disas_data_proc_3src(s
, insn
);
4314 switch (extract32(insn
, 21, 3)) {
4315 case 0x0: /* Add/subtract (with carry) */
4316 disas_adc_sbc(s
, insn
);
4318 case 0x2: /* Conditional compare */
4319 disas_cc(s
, insn
); /* both imm and reg forms */
4321 case 0x4: /* Conditional select */
4322 disas_cond_select(s
, insn
);
4324 case 0x6: /* Data-processing */
4325 if (insn
& (1 << 30)) { /* (1 source) */
4326 disas_data_proc_1src(s
, insn
);
4327 } else { /* (2 source) */
4328 disas_data_proc_2src(s
, insn
);
4332 unallocated_encoding(s
);
4337 unallocated_encoding(s
);
4342 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4343 unsigned int rn
, unsigned int rm
,
4344 bool cmp_with_zero
, bool signal_all_nans
)
4346 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4347 TCGv_ptr fpst
= get_fpstatus_ptr();
4350 TCGv_i64 tcg_vn
, tcg_vm
;
4352 tcg_vn
= read_fp_dreg(s
, rn
);
4353 if (cmp_with_zero
) {
4354 tcg_vm
= tcg_const_i64(0);
4356 tcg_vm
= read_fp_dreg(s
, rm
);
4358 if (signal_all_nans
) {
4359 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4361 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4363 tcg_temp_free_i64(tcg_vn
);
4364 tcg_temp_free_i64(tcg_vm
);
4366 TCGv_i32 tcg_vn
, tcg_vm
;
4368 tcg_vn
= read_fp_sreg(s
, rn
);
4369 if (cmp_with_zero
) {
4370 tcg_vm
= tcg_const_i32(0);
4372 tcg_vm
= read_fp_sreg(s
, rm
);
4374 if (signal_all_nans
) {
4375 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4377 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4379 tcg_temp_free_i32(tcg_vn
);
4380 tcg_temp_free_i32(tcg_vm
);
4383 tcg_temp_free_ptr(fpst
);
4385 gen_set_nzcv(tcg_flags
);
4387 tcg_temp_free_i64(tcg_flags
);
4390 /* C3.6.22 Floating point compare
4391 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4392 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4393 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4394 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4396 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4398 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4400 mos
= extract32(insn
, 29, 3);
4401 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4402 rm
= extract32(insn
, 16, 5);
4403 op
= extract32(insn
, 14, 2);
4404 rn
= extract32(insn
, 5, 5);
4405 opc
= extract32(insn
, 3, 2);
4406 op2r
= extract32(insn
, 0, 3);
4408 if (mos
|| op
|| op2r
|| type
> 1) {
4409 unallocated_encoding(s
);
4413 if (!fp_access_check(s
)) {
4417 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4420 /* C3.6.23 Floating point conditional compare
4421 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4422 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4423 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4424 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4426 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4428 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4430 TCGLabel
*label_continue
= NULL
;
4432 mos
= extract32(insn
, 29, 3);
4433 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4434 rm
= extract32(insn
, 16, 5);
4435 cond
= extract32(insn
, 12, 4);
4436 rn
= extract32(insn
, 5, 5);
4437 op
= extract32(insn
, 4, 1);
4438 nzcv
= extract32(insn
, 0, 4);
4440 if (mos
|| type
> 1) {
4441 unallocated_encoding(s
);
4445 if (!fp_access_check(s
)) {
4449 if (cond
< 0x0e) { /* not always */
4450 TCGLabel
*label_match
= gen_new_label();
4451 label_continue
= gen_new_label();
4452 arm_gen_test_cc(cond
, label_match
);
4454 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4455 gen_set_nzcv(tcg_flags
);
4456 tcg_temp_free_i64(tcg_flags
);
4457 tcg_gen_br(label_continue
);
4458 gen_set_label(label_match
);
4461 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4464 gen_set_label(label_continue
);
4468 /* C3.6.24 Floating point conditional select
4469 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4470 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4471 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4472 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4474 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4476 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4477 TCGv_i64 t_true
, t_false
, t_zero
;
4480 mos
= extract32(insn
, 29, 3);
4481 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4482 rm
= extract32(insn
, 16, 5);
4483 cond
= extract32(insn
, 12, 4);
4484 rn
= extract32(insn
, 5, 5);
4485 rd
= extract32(insn
, 0, 5);
4487 if (mos
|| type
> 1) {
4488 unallocated_encoding(s
);
4492 if (!fp_access_check(s
)) {
4496 /* Zero extend sreg inputs to 64 bits now. */
4497 t_true
= tcg_temp_new_i64();
4498 t_false
= tcg_temp_new_i64();
4499 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4500 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4502 a64_test_cc(&c
, cond
);
4503 t_zero
= tcg_const_i64(0);
4504 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4505 tcg_temp_free_i64(t_zero
);
4506 tcg_temp_free_i64(t_false
);
4509 /* Note that sregs write back zeros to the high bits,
4510 and we've already done the zero-extension. */
4511 write_fp_dreg(s
, rd
, t_true
);
4512 tcg_temp_free_i64(t_true
);
4515 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4516 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4522 fpst
= get_fpstatus_ptr();
4523 tcg_op
= read_fp_sreg(s
, rn
);
4524 tcg_res
= tcg_temp_new_i32();
4527 case 0x0: /* FMOV */
4528 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4530 case 0x1: /* FABS */
4531 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4533 case 0x2: /* FNEG */
4534 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4536 case 0x3: /* FSQRT */
4537 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4539 case 0x8: /* FRINTN */
4540 case 0x9: /* FRINTP */
4541 case 0xa: /* FRINTM */
4542 case 0xb: /* FRINTZ */
4543 case 0xc: /* FRINTA */
4545 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4547 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4548 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4550 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4551 tcg_temp_free_i32(tcg_rmode
);
4554 case 0xe: /* FRINTX */
4555 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4557 case 0xf: /* FRINTI */
4558 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4564 write_fp_sreg(s
, rd
, tcg_res
);
4566 tcg_temp_free_ptr(fpst
);
4567 tcg_temp_free_i32(tcg_op
);
4568 tcg_temp_free_i32(tcg_res
);
4571 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4572 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4578 fpst
= get_fpstatus_ptr();
4579 tcg_op
= read_fp_dreg(s
, rn
);
4580 tcg_res
= tcg_temp_new_i64();
4583 case 0x0: /* FMOV */
4584 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4586 case 0x1: /* FABS */
4587 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4589 case 0x2: /* FNEG */
4590 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4592 case 0x3: /* FSQRT */
4593 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4595 case 0x8: /* FRINTN */
4596 case 0x9: /* FRINTP */
4597 case 0xa: /* FRINTM */
4598 case 0xb: /* FRINTZ */
4599 case 0xc: /* FRINTA */
4601 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4603 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4604 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4606 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4607 tcg_temp_free_i32(tcg_rmode
);
4610 case 0xe: /* FRINTX */
4611 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4613 case 0xf: /* FRINTI */
4614 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4620 write_fp_dreg(s
, rd
, tcg_res
);
4622 tcg_temp_free_ptr(fpst
);
4623 tcg_temp_free_i64(tcg_op
);
4624 tcg_temp_free_i64(tcg_res
);
4627 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4628 int rd
, int rn
, int dtype
, int ntype
)
4633 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4635 /* Single to double */
4636 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4637 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4638 write_fp_dreg(s
, rd
, tcg_rd
);
4639 tcg_temp_free_i64(tcg_rd
);
4641 /* Single to half */
4642 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4643 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4644 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4645 write_fp_sreg(s
, rd
, tcg_rd
);
4646 tcg_temp_free_i32(tcg_rd
);
4648 tcg_temp_free_i32(tcg_rn
);
4653 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4654 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4656 /* Double to single */
4657 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4659 /* Double to half */
4660 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4661 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4663 write_fp_sreg(s
, rd
, tcg_rd
);
4664 tcg_temp_free_i32(tcg_rd
);
4665 tcg_temp_free_i64(tcg_rn
);
4670 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4671 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4673 /* Half to single */
4674 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4675 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4676 write_fp_sreg(s
, rd
, tcg_rd
);
4677 tcg_temp_free_i32(tcg_rd
);
4679 /* Half to double */
4680 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4681 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4682 write_fp_dreg(s
, rd
, tcg_rd
);
4683 tcg_temp_free_i64(tcg_rd
);
4685 tcg_temp_free_i32(tcg_rn
);
4693 /* C3.6.25 Floating point data-processing (1 source)
4694 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4695 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4696 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4697 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4699 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4701 int type
= extract32(insn
, 22, 2);
4702 int opcode
= extract32(insn
, 15, 6);
4703 int rn
= extract32(insn
, 5, 5);
4704 int rd
= extract32(insn
, 0, 5);
4707 case 0x4: case 0x5: case 0x7:
4709 /* FCVT between half, single and double precision */
4710 int dtype
= extract32(opcode
, 0, 2);
4711 if (type
== 2 || dtype
== type
) {
4712 unallocated_encoding(s
);
4715 if (!fp_access_check(s
)) {
4719 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4725 /* 32-to-32 and 64-to-64 ops */
4728 if (!fp_access_check(s
)) {
4732 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4735 if (!fp_access_check(s
)) {
4739 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4742 unallocated_encoding(s
);
4746 unallocated_encoding(s
);
4751 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4752 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4753 int rd
, int rn
, int rm
)
4760 tcg_res
= tcg_temp_new_i32();
4761 fpst
= get_fpstatus_ptr();
4762 tcg_op1
= read_fp_sreg(s
, rn
);
4763 tcg_op2
= read_fp_sreg(s
, rm
);
4766 case 0x0: /* FMUL */
4767 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4769 case 0x1: /* FDIV */
4770 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4772 case 0x2: /* FADD */
4773 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4775 case 0x3: /* FSUB */
4776 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4778 case 0x4: /* FMAX */
4779 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4781 case 0x5: /* FMIN */
4782 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4784 case 0x6: /* FMAXNM */
4785 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4787 case 0x7: /* FMINNM */
4788 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4790 case 0x8: /* FNMUL */
4791 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4792 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4796 write_fp_sreg(s
, rd
, tcg_res
);
4798 tcg_temp_free_ptr(fpst
);
4799 tcg_temp_free_i32(tcg_op1
);
4800 tcg_temp_free_i32(tcg_op2
);
4801 tcg_temp_free_i32(tcg_res
);
4804 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4805 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4806 int rd
, int rn
, int rm
)
4813 tcg_res
= tcg_temp_new_i64();
4814 fpst
= get_fpstatus_ptr();
4815 tcg_op1
= read_fp_dreg(s
, rn
);
4816 tcg_op2
= read_fp_dreg(s
, rm
);
4819 case 0x0: /* FMUL */
4820 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4822 case 0x1: /* FDIV */
4823 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4825 case 0x2: /* FADD */
4826 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4828 case 0x3: /* FSUB */
4829 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4831 case 0x4: /* FMAX */
4832 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4834 case 0x5: /* FMIN */
4835 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4837 case 0x6: /* FMAXNM */
4838 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4840 case 0x7: /* FMINNM */
4841 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4843 case 0x8: /* FNMUL */
4844 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4845 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4849 write_fp_dreg(s
, rd
, tcg_res
);
4851 tcg_temp_free_ptr(fpst
);
4852 tcg_temp_free_i64(tcg_op1
);
4853 tcg_temp_free_i64(tcg_op2
);
4854 tcg_temp_free_i64(tcg_res
);
4857 /* C3.6.26 Floating point data-processing (2 source)
4858 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4859 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4860 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4861 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4863 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4865 int type
= extract32(insn
, 22, 2);
4866 int rd
= extract32(insn
, 0, 5);
4867 int rn
= extract32(insn
, 5, 5);
4868 int rm
= extract32(insn
, 16, 5);
4869 int opcode
= extract32(insn
, 12, 4);
4872 unallocated_encoding(s
);
4878 if (!fp_access_check(s
)) {
4881 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4884 if (!fp_access_check(s
)) {
4887 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4890 unallocated_encoding(s
);
4894 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4895 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4896 int rd
, int rn
, int rm
, int ra
)
4898 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4899 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4900 TCGv_ptr fpst
= get_fpstatus_ptr();
4902 tcg_op1
= read_fp_sreg(s
, rn
);
4903 tcg_op2
= read_fp_sreg(s
, rm
);
4904 tcg_op3
= read_fp_sreg(s
, ra
);
4906 /* These are fused multiply-add, and must be done as one
4907 * floating point operation with no rounding between the
4908 * multiplication and addition steps.
4909 * NB that doing the negations here as separate steps is
4910 * correct : an input NaN should come out with its sign bit
4911 * flipped if it is a negated-input.
4914 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4918 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4921 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4923 write_fp_sreg(s
, rd
, tcg_res
);
4925 tcg_temp_free_ptr(fpst
);
4926 tcg_temp_free_i32(tcg_op1
);
4927 tcg_temp_free_i32(tcg_op2
);
4928 tcg_temp_free_i32(tcg_op3
);
4929 tcg_temp_free_i32(tcg_res
);
4932 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4933 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4934 int rd
, int rn
, int rm
, int ra
)
4936 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4937 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4938 TCGv_ptr fpst
= get_fpstatus_ptr();
4940 tcg_op1
= read_fp_dreg(s
, rn
);
4941 tcg_op2
= read_fp_dreg(s
, rm
);
4942 tcg_op3
= read_fp_dreg(s
, ra
);
4944 /* These are fused multiply-add, and must be done as one
4945 * floating point operation with no rounding between the
4946 * multiplication and addition steps.
4947 * NB that doing the negations here as separate steps is
4948 * correct : an input NaN should come out with its sign bit
4949 * flipped if it is a negated-input.
4952 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4956 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4959 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4961 write_fp_dreg(s
, rd
, tcg_res
);
4963 tcg_temp_free_ptr(fpst
);
4964 tcg_temp_free_i64(tcg_op1
);
4965 tcg_temp_free_i64(tcg_op2
);
4966 tcg_temp_free_i64(tcg_op3
);
4967 tcg_temp_free_i64(tcg_res
);
4970 /* C3.6.27 Floating point data-processing (3 source)
4971 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4972 * +---+---+---+-----------+------+----+------+----+------+------+------+
4973 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4974 * +---+---+---+-----------+------+----+------+----+------+------+------+
4976 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4978 int type
= extract32(insn
, 22, 2);
4979 int rd
= extract32(insn
, 0, 5);
4980 int rn
= extract32(insn
, 5, 5);
4981 int ra
= extract32(insn
, 10, 5);
4982 int rm
= extract32(insn
, 16, 5);
4983 bool o0
= extract32(insn
, 15, 1);
4984 bool o1
= extract32(insn
, 21, 1);
4988 if (!fp_access_check(s
)) {
4991 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4994 if (!fp_access_check(s
)) {
4997 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5000 unallocated_encoding(s
);
5004 /* C3.6.28 Floating point immediate
5005 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5006 * +---+---+---+-----------+------+---+------------+-------+------+------+
5007 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5008 * +---+---+---+-----------+------+---+------------+-------+------+------+
5010 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5012 int rd
= extract32(insn
, 0, 5);
5013 int imm8
= extract32(insn
, 13, 8);
5014 int is_double
= extract32(insn
, 22, 2);
5018 if (is_double
> 1) {
5019 unallocated_encoding(s
);
5023 if (!fp_access_check(s
)) {
5027 /* The imm8 encodes the sign bit, enough bits to represent
5028 * an exponent in the range 01....1xx to 10....0xx,
5029 * and the most significant 4 bits of the mantissa; see
5030 * VFPExpandImm() in the v8 ARM ARM.
5033 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5034 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5035 extract32(imm8
, 0, 6);
5038 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5039 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5040 (extract32(imm8
, 0, 6) << 3);
5044 tcg_res
= tcg_const_i64(imm
);
5045 write_fp_dreg(s
, rd
, tcg_res
);
5046 tcg_temp_free_i64(tcg_res
);
5049 /* Handle floating point <=> fixed point conversions. Note that we can
5050 * also deal with fp <=> integer conversions as a special case (scale == 64)
5051 * OPTME: consider handling that special case specially or at least skipping
5052 * the call to scalbn in the helpers for zero shifts.
5054 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5055 bool itof
, int rmode
, int scale
, int sf
, int type
)
5057 bool is_signed
= !(opcode
& 1);
5058 bool is_double
= type
;
5059 TCGv_ptr tcg_fpstatus
;
5062 tcg_fpstatus
= get_fpstatus_ptr();
5064 tcg_shift
= tcg_const_i32(64 - scale
);
5067 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5069 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5072 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5074 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5077 tcg_int
= tcg_extend
;
5081 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5083 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5084 tcg_shift
, tcg_fpstatus
);
5086 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5087 tcg_shift
, tcg_fpstatus
);
5089 write_fp_dreg(s
, rd
, tcg_double
);
5090 tcg_temp_free_i64(tcg_double
);
5092 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5094 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5095 tcg_shift
, tcg_fpstatus
);
5097 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5098 tcg_shift
, tcg_fpstatus
);
5100 write_fp_sreg(s
, rd
, tcg_single
);
5101 tcg_temp_free_i32(tcg_single
);
5104 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5107 if (extract32(opcode
, 2, 1)) {
5108 /* There are too many rounding modes to all fit into rmode,
5109 * so FCVTA[US] is a special case.
5111 rmode
= FPROUNDING_TIEAWAY
;
5114 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5116 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5119 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5122 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5123 tcg_shift
, tcg_fpstatus
);
5125 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5126 tcg_shift
, tcg_fpstatus
);
5130 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5131 tcg_shift
, tcg_fpstatus
);
5133 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5134 tcg_shift
, tcg_fpstatus
);
5137 tcg_temp_free_i64(tcg_double
);
5139 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5142 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5143 tcg_shift
, tcg_fpstatus
);
5145 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5146 tcg_shift
, tcg_fpstatus
);
5149 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5151 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5152 tcg_shift
, tcg_fpstatus
);
5154 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5155 tcg_shift
, tcg_fpstatus
);
5157 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5158 tcg_temp_free_i32(tcg_dest
);
5160 tcg_temp_free_i32(tcg_single
);
5163 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5164 tcg_temp_free_i32(tcg_rmode
);
5167 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5171 tcg_temp_free_ptr(tcg_fpstatus
);
5172 tcg_temp_free_i32(tcg_shift
);
5175 /* C3.6.29 Floating point <-> fixed point conversions
5176 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5177 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5178 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5179 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5181 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5183 int rd
= extract32(insn
, 0, 5);
5184 int rn
= extract32(insn
, 5, 5);
5185 int scale
= extract32(insn
, 10, 6);
5186 int opcode
= extract32(insn
, 16, 3);
5187 int rmode
= extract32(insn
, 19, 2);
5188 int type
= extract32(insn
, 22, 2);
5189 bool sbit
= extract32(insn
, 29, 1);
5190 bool sf
= extract32(insn
, 31, 1);
5193 if (sbit
|| (type
> 1)
5194 || (!sf
&& scale
< 32)) {
5195 unallocated_encoding(s
);
5199 switch ((rmode
<< 3) | opcode
) {
5200 case 0x2: /* SCVTF */
5201 case 0x3: /* UCVTF */
5204 case 0x18: /* FCVTZS */
5205 case 0x19: /* FCVTZU */
5209 unallocated_encoding(s
);
5213 if (!fp_access_check(s
)) {
5217 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5220 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5222 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5223 * without conversion.
5227 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5233 TCGv_i64 tmp
= tcg_temp_new_i64();
5234 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5235 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5236 tcg_gen_movi_i64(tmp
, 0);
5237 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5238 tcg_temp_free_i64(tmp
);
5244 TCGv_i64 tmp
= tcg_const_i64(0);
5245 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5246 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5247 tcg_temp_free_i64(tmp
);
5251 /* 64 bit to top half. */
5252 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5256 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5261 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5265 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5268 /* 64 bits from top half */
5269 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5275 /* C3.6.30 Floating point <-> integer conversions
5276 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5277 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5278 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5279 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5281 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5283 int rd
= extract32(insn
, 0, 5);
5284 int rn
= extract32(insn
, 5, 5);
5285 int opcode
= extract32(insn
, 16, 3);
5286 int rmode
= extract32(insn
, 19, 2);
5287 int type
= extract32(insn
, 22, 2);
5288 bool sbit
= extract32(insn
, 29, 1);
5289 bool sf
= extract32(insn
, 31, 1);
5292 unallocated_encoding(s
);
5298 bool itof
= opcode
& 1;
5301 unallocated_encoding(s
);
5305 switch (sf
<< 3 | type
<< 1 | rmode
) {
5306 case 0x0: /* 32 bit */
5307 case 0xa: /* 64 bit */
5308 case 0xd: /* 64 bit to top half of quad */
5311 /* all other sf/type/rmode combinations are invalid */
5312 unallocated_encoding(s
);
5316 if (!fp_access_check(s
)) {
5319 handle_fmov(s
, rd
, rn
, type
, itof
);
5321 /* actual FP conversions */
5322 bool itof
= extract32(opcode
, 1, 1);
5324 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5325 unallocated_encoding(s
);
5329 if (!fp_access_check(s
)) {
5332 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5336 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5337 * 31 30 29 28 25 24 0
5338 * +---+---+---+---------+-----------------------------+
5339 * | | 0 | | 1 1 1 1 | |
5340 * +---+---+---+---------+-----------------------------+
5342 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5344 if (extract32(insn
, 24, 1)) {
5345 /* Floating point data-processing (3 source) */
5346 disas_fp_3src(s
, insn
);
5347 } else if (extract32(insn
, 21, 1) == 0) {
5348 /* Floating point to fixed point conversions */
5349 disas_fp_fixed_conv(s
, insn
);
5351 switch (extract32(insn
, 10, 2)) {
5353 /* Floating point conditional compare */
5354 disas_fp_ccomp(s
, insn
);
5357 /* Floating point data-processing (2 source) */
5358 disas_fp_2src(s
, insn
);
5361 /* Floating point conditional select */
5362 disas_fp_csel(s
, insn
);
5365 switch (ctz32(extract32(insn
, 12, 4))) {
5366 case 0: /* [15:12] == xxx1 */
5367 /* Floating point immediate */
5368 disas_fp_imm(s
, insn
);
5370 case 1: /* [15:12] == xx10 */
5371 /* Floating point compare */
5372 disas_fp_compare(s
, insn
);
5374 case 2: /* [15:12] == x100 */
5375 /* Floating point data-processing (1 source) */
5376 disas_fp_1src(s
, insn
);
5378 case 3: /* [15:12] == 1000 */
5379 unallocated_encoding(s
);
5381 default: /* [15:12] == 0000 */
5382 /* Floating point <-> integer conversions */
5383 disas_fp_int_conv(s
, insn
);
5391 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5394 /* Extract 64 bits from the middle of two concatenated 64 bit
5395 * vector register slices left:right. The extracted bits start
5396 * at 'pos' bits into the right (least significant) side.
5397 * We return the result in tcg_right, and guarantee not to
5400 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5401 assert(pos
> 0 && pos
< 64);
5403 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5404 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5405 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5407 tcg_temp_free_i64(tcg_tmp
);
5411 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5412 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5413 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5414 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5416 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5418 int is_q
= extract32(insn
, 30, 1);
5419 int op2
= extract32(insn
, 22, 2);
5420 int imm4
= extract32(insn
, 11, 4);
5421 int rm
= extract32(insn
, 16, 5);
5422 int rn
= extract32(insn
, 5, 5);
5423 int rd
= extract32(insn
, 0, 5);
5424 int pos
= imm4
<< 3;
5425 TCGv_i64 tcg_resl
, tcg_resh
;
5427 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5428 unallocated_encoding(s
);
5432 if (!fp_access_check(s
)) {
5436 tcg_resh
= tcg_temp_new_i64();
5437 tcg_resl
= tcg_temp_new_i64();
5439 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5440 * either extracting 128 bits from a 128:128 concatenation, or
5441 * extracting 64 bits from a 64:64 concatenation.
5444 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5446 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5447 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5449 tcg_gen_movi_i64(tcg_resh
, 0);
5456 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5457 EltPosns
*elt
= eltposns
;
5464 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5466 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5469 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5470 tcg_hh
= tcg_temp_new_i64();
5471 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5472 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5473 tcg_temp_free_i64(tcg_hh
);
5477 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5478 tcg_temp_free_i64(tcg_resl
);
5479 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5480 tcg_temp_free_i64(tcg_resh
);
5484 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5485 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5486 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5487 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5489 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5491 int op2
= extract32(insn
, 22, 2);
5492 int is_q
= extract32(insn
, 30, 1);
5493 int rm
= extract32(insn
, 16, 5);
5494 int rn
= extract32(insn
, 5, 5);
5495 int rd
= extract32(insn
, 0, 5);
5496 int is_tblx
= extract32(insn
, 12, 1);
5497 int len
= extract32(insn
, 13, 2);
5498 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5499 TCGv_i32 tcg_regno
, tcg_numregs
;
5502 unallocated_encoding(s
);
5506 if (!fp_access_check(s
)) {
5510 /* This does a table lookup: for every byte element in the input
5511 * we index into a table formed from up to four vector registers,
5512 * and then the output is the result of the lookups. Our helper
5513 * function does the lookup operation for a single 64 bit part of
5516 tcg_resl
= tcg_temp_new_i64();
5517 tcg_resh
= tcg_temp_new_i64();
5520 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5522 tcg_gen_movi_i64(tcg_resl
, 0);
5524 if (is_tblx
&& is_q
) {
5525 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5527 tcg_gen_movi_i64(tcg_resh
, 0);
5530 tcg_idx
= tcg_temp_new_i64();
5531 tcg_regno
= tcg_const_i32(rn
);
5532 tcg_numregs
= tcg_const_i32(len
+ 1);
5533 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5534 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5535 tcg_regno
, tcg_numregs
);
5537 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5538 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5539 tcg_regno
, tcg_numregs
);
5541 tcg_temp_free_i64(tcg_idx
);
5542 tcg_temp_free_i32(tcg_regno
);
5543 tcg_temp_free_i32(tcg_numregs
);
5545 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5546 tcg_temp_free_i64(tcg_resl
);
5547 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5548 tcg_temp_free_i64(tcg_resh
);
5551 /* C3.6.3 ZIP/UZP/TRN
5552 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5553 * +---+---+-------------+------+---+------+---+------------------+------+
5554 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5555 * +---+---+-------------+------+---+------+---+------------------+------+
5557 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5559 int rd
= extract32(insn
, 0, 5);
5560 int rn
= extract32(insn
, 5, 5);
5561 int rm
= extract32(insn
, 16, 5);
5562 int size
= extract32(insn
, 22, 2);
5563 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5564 * bit 2 indicates 1 vs 2 variant of the insn.
5566 int opcode
= extract32(insn
, 12, 2);
5567 bool part
= extract32(insn
, 14, 1);
5568 bool is_q
= extract32(insn
, 30, 1);
5569 int esize
= 8 << size
;
5571 int datasize
= is_q
? 128 : 64;
5572 int elements
= datasize
/ esize
;
5573 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5575 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5576 unallocated_encoding(s
);
5580 if (!fp_access_check(s
)) {
5584 tcg_resl
= tcg_const_i64(0);
5585 tcg_resh
= tcg_const_i64(0);
5586 tcg_res
= tcg_temp_new_i64();
5588 for (i
= 0; i
< elements
; i
++) {
5590 case 1: /* UZP1/2 */
5592 int midpoint
= elements
/ 2;
5594 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5596 read_vec_element(s
, tcg_res
, rm
,
5597 2 * (i
- midpoint
) + part
, size
);
5601 case 2: /* TRN1/2 */
5603 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5605 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5608 case 3: /* ZIP1/2 */
5610 int base
= part
* elements
/ 2;
5612 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5614 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5619 g_assert_not_reached();
5624 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5625 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5627 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5628 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5632 tcg_temp_free_i64(tcg_res
);
5634 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5635 tcg_temp_free_i64(tcg_resl
);
5636 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5637 tcg_temp_free_i64(tcg_resh
);
5640 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5641 int opc
, bool is_min
, TCGv_ptr fpst
)
5643 /* Helper function for disas_simd_across_lanes: do a single precision
5644 * min/max operation on the specified two inputs,
5645 * and return the result in tcg_elt1.
5649 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5651 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5656 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5658 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5663 /* C3.6.4 AdvSIMD across lanes
5664 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5665 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5666 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5667 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5669 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5671 int rd
= extract32(insn
, 0, 5);
5672 int rn
= extract32(insn
, 5, 5);
5673 int size
= extract32(insn
, 22, 2);
5674 int opcode
= extract32(insn
, 12, 5);
5675 bool is_q
= extract32(insn
, 30, 1);
5676 bool is_u
= extract32(insn
, 29, 1);
5678 bool is_min
= false;
5682 TCGv_i64 tcg_res
, tcg_elt
;
5685 case 0x1b: /* ADDV */
5687 unallocated_encoding(s
);
5691 case 0x3: /* SADDLV, UADDLV */
5692 case 0xa: /* SMAXV, UMAXV */
5693 case 0x1a: /* SMINV, UMINV */
5694 if (size
== 3 || (size
== 2 && !is_q
)) {
5695 unallocated_encoding(s
);
5699 case 0xc: /* FMAXNMV, FMINNMV */
5700 case 0xf: /* FMAXV, FMINV */
5701 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5702 unallocated_encoding(s
);
5705 /* Bit 1 of size field encodes min vs max, and actual size is always
5706 * 32 bits: adjust the size variable so following code can rely on it
5708 is_min
= extract32(size
, 1, 1);
5713 unallocated_encoding(s
);
5717 if (!fp_access_check(s
)) {
5722 elements
= (is_q
? 128 : 64) / esize
;
5724 tcg_res
= tcg_temp_new_i64();
5725 tcg_elt
= tcg_temp_new_i64();
5727 /* These instructions operate across all lanes of a vector
5728 * to produce a single result. We can guarantee that a 64
5729 * bit intermediate is sufficient:
5730 * + for [US]ADDLV the maximum element size is 32 bits, and
5731 * the result type is 64 bits
5732 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5733 * same as the element size, which is 32 bits at most
5734 * For the integer operations we can choose to work at 64
5735 * or 32 bits and truncate at the end; for simplicity
5736 * we use 64 bits always. The floating point
5737 * ops do require 32 bit intermediates, though.
5740 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5742 for (i
= 1; i
< elements
; i
++) {
5743 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5746 case 0x03: /* SADDLV / UADDLV */
5747 case 0x1b: /* ADDV */
5748 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5750 case 0x0a: /* SMAXV / UMAXV */
5751 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5753 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5755 case 0x1a: /* SMINV / UMINV */
5756 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5758 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5762 g_assert_not_reached();
5767 /* Floating point ops which work on 32 bit (single) intermediates.
5768 * Note that correct NaN propagation requires that we do these
5769 * operations in exactly the order specified by the pseudocode.
5771 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5772 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5773 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5774 TCGv_ptr fpst
= get_fpstatus_ptr();
5776 assert(esize
== 32);
5777 assert(elements
== 4);
5779 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5780 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5781 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5782 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5784 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5786 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5787 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5788 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5789 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5791 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5793 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5795 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5796 tcg_temp_free_i32(tcg_elt1
);
5797 tcg_temp_free_i32(tcg_elt2
);
5798 tcg_temp_free_i32(tcg_elt3
);
5799 tcg_temp_free_ptr(fpst
);
5802 tcg_temp_free_i64(tcg_elt
);
5804 /* Now truncate the result to the width required for the final output */
5805 if (opcode
== 0x03) {
5806 /* SADDLV, UADDLV: result is 2*esize */
5812 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5815 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5818 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5823 g_assert_not_reached();
5826 write_fp_dreg(s
, rd
, tcg_res
);
5827 tcg_temp_free_i64(tcg_res
);
5830 /* C6.3.31 DUP (Element, Vector)
5832 * 31 30 29 21 20 16 15 10 9 5 4 0
5833 * +---+---+-------------------+--------+-------------+------+------+
5834 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5835 * +---+---+-------------------+--------+-------------+------+------+
5837 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5839 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5842 int size
= ctz32(imm5
);
5843 int esize
= 8 << size
;
5844 int elements
= (is_q
? 128 : 64) / esize
;
5848 if (size
> 3 || (size
== 3 && !is_q
)) {
5849 unallocated_encoding(s
);
5853 if (!fp_access_check(s
)) {
5857 index
= imm5
>> (size
+ 1);
5859 tmp
= tcg_temp_new_i64();
5860 read_vec_element(s
, tmp
, rn
, index
, size
);
5862 for (i
= 0; i
< elements
; i
++) {
5863 write_vec_element(s
, tmp
, rd
, i
, size
);
5867 clear_vec_high(s
, rd
);
5870 tcg_temp_free_i64(tmp
);
5873 /* C6.3.31 DUP (element, scalar)
5874 * 31 21 20 16 15 10 9 5 4 0
5875 * +-----------------------+--------+-------------+------+------+
5876 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5877 * +-----------------------+--------+-------------+------+------+
5879 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5882 int size
= ctz32(imm5
);
5887 unallocated_encoding(s
);
5891 if (!fp_access_check(s
)) {
5895 index
= imm5
>> (size
+ 1);
5897 /* This instruction just extracts the specified element and
5898 * zero-extends it into the bottom of the destination register.
5900 tmp
= tcg_temp_new_i64();
5901 read_vec_element(s
, tmp
, rn
, index
, size
);
5902 write_fp_dreg(s
, rd
, tmp
);
5903 tcg_temp_free_i64(tmp
);
5906 /* C6.3.32 DUP (General)
5908 * 31 30 29 21 20 16 15 10 9 5 4 0
5909 * +---+---+-------------------+--------+-------------+------+------+
5910 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5911 * +---+---+-------------------+--------+-------------+------+------+
5913 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5915 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5918 int size
= ctz32(imm5
);
5919 int esize
= 8 << size
;
5920 int elements
= (is_q
? 128 : 64)/esize
;
5923 if (size
> 3 || ((size
== 3) && !is_q
)) {
5924 unallocated_encoding(s
);
5928 if (!fp_access_check(s
)) {
5932 for (i
= 0; i
< elements
; i
++) {
5933 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5936 clear_vec_high(s
, rd
);
5940 /* C6.3.150 INS (Element)
5942 * 31 21 20 16 15 14 11 10 9 5 4 0
5943 * +-----------------------+--------+------------+---+------+------+
5944 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5945 * +-----------------------+--------+------------+---+------+------+
5947 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5948 * index: encoded in imm5<4:size+1>
5950 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5953 int size
= ctz32(imm5
);
5954 int src_index
, dst_index
;
5958 unallocated_encoding(s
);
5962 if (!fp_access_check(s
)) {
5966 dst_index
= extract32(imm5
, 1+size
, 5);
5967 src_index
= extract32(imm4
, size
, 4);
5969 tmp
= tcg_temp_new_i64();
5971 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5972 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5974 tcg_temp_free_i64(tmp
);
5978 /* C6.3.151 INS (General)
5980 * 31 21 20 16 15 10 9 5 4 0
5981 * +-----------------------+--------+-------------+------+------+
5982 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5983 * +-----------------------+--------+-------------+------+------+
5985 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5986 * index: encoded in imm5<4:size+1>
5988 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5990 int size
= ctz32(imm5
);
5994 unallocated_encoding(s
);
5998 if (!fp_access_check(s
)) {
6002 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6003 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6007 * C6.3.321 UMOV (General)
6008 * C6.3.237 SMOV (General)
6010 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6011 * +---+---+-------------------+--------+-------------+------+------+
6012 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6013 * +---+---+-------------------+--------+-------------+------+------+
6015 * U: unsigned when set
6016 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6018 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6019 int rn
, int rd
, int imm5
)
6021 int size
= ctz32(imm5
);
6025 /* Check for UnallocatedEncodings */
6027 if (size
> 2 || (size
== 2 && !is_q
)) {
6028 unallocated_encoding(s
);
6033 || (size
< 3 && is_q
)
6034 || (size
== 3 && !is_q
)) {
6035 unallocated_encoding(s
);
6040 if (!fp_access_check(s
)) {
6044 element
= extract32(imm5
, 1+size
, 4);
6046 tcg_rd
= cpu_reg(s
, rd
);
6047 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6048 if (is_signed
&& !is_q
) {
6049 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6053 /* C3.6.5 AdvSIMD copy
6054 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6055 * +---+---+----+-----------------+------+---+------+---+------+------+
6056 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6057 * +---+---+----+-----------------+------+---+------+---+------+------+
6059 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6061 int rd
= extract32(insn
, 0, 5);
6062 int rn
= extract32(insn
, 5, 5);
6063 int imm4
= extract32(insn
, 11, 4);
6064 int op
= extract32(insn
, 29, 1);
6065 int is_q
= extract32(insn
, 30, 1);
6066 int imm5
= extract32(insn
, 16, 5);
6071 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6073 unallocated_encoding(s
);
6078 /* DUP (element - vector) */
6079 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6083 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6088 handle_simd_insg(s
, rd
, rn
, imm5
);
6090 unallocated_encoding(s
);
6095 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6096 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6099 unallocated_encoding(s
);
6105 /* C3.6.6 AdvSIMD modified immediate
6106 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6107 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6108 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6109 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6111 * There are a number of operations that can be carried out here:
6112 * MOVI - move (shifted) imm into register
6113 * MVNI - move inverted (shifted) imm into register
6114 * ORR - bitwise OR of (shifted) imm with register
6115 * BIC - bitwise clear of (shifted) imm with register
6117 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6119 int rd
= extract32(insn
, 0, 5);
6120 int cmode
= extract32(insn
, 12, 4);
6121 int cmode_3_1
= extract32(cmode
, 1, 3);
6122 int cmode_0
= extract32(cmode
, 0, 1);
6123 int o2
= extract32(insn
, 11, 1);
6124 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6125 bool is_neg
= extract32(insn
, 29, 1);
6126 bool is_q
= extract32(insn
, 30, 1);
6128 TCGv_i64 tcg_rd
, tcg_imm
;
6131 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6132 unallocated_encoding(s
);
6136 if (!fp_access_check(s
)) {
6140 /* See AdvSIMDExpandImm() in ARM ARM */
6141 switch (cmode_3_1
) {
6142 case 0: /* Replicate(Zeros(24):imm8, 2) */
6143 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6144 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6145 case 3: /* Replicate(imm8:Zeros(24), 2) */
6147 int shift
= cmode_3_1
* 8;
6148 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6151 case 4: /* Replicate(Zeros(8):imm8, 4) */
6152 case 5: /* Replicate(imm8:Zeros(8), 4) */
6154 int shift
= (cmode_3_1
& 0x1) * 8;
6155 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6160 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6161 imm
= (abcdefgh
<< 16) | 0xffff;
6163 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6164 imm
= (abcdefgh
<< 8) | 0xff;
6166 imm
= bitfield_replicate(imm
, 32);
6169 if (!cmode_0
&& !is_neg
) {
6170 imm
= bitfield_replicate(abcdefgh
, 8);
6171 } else if (!cmode_0
&& is_neg
) {
6174 for (i
= 0; i
< 8; i
++) {
6175 if ((abcdefgh
) & (1 << i
)) {
6176 imm
|= 0xffULL
<< (i
* 8);
6179 } else if (cmode_0
) {
6181 imm
= (abcdefgh
& 0x3f) << 48;
6182 if (abcdefgh
& 0x80) {
6183 imm
|= 0x8000000000000000ULL
;
6185 if (abcdefgh
& 0x40) {
6186 imm
|= 0x3fc0000000000000ULL
;
6188 imm
|= 0x4000000000000000ULL
;
6191 imm
= (abcdefgh
& 0x3f) << 19;
6192 if (abcdefgh
& 0x80) {
6195 if (abcdefgh
& 0x40) {
6206 if (cmode_3_1
!= 7 && is_neg
) {
6210 tcg_imm
= tcg_const_i64(imm
);
6211 tcg_rd
= new_tmp_a64(s
);
6213 for (i
= 0; i
< 2; i
++) {
6214 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6216 if (i
== 1 && !is_q
) {
6217 /* non-quad ops clear high half of vector */
6218 tcg_gen_movi_i64(tcg_rd
, 0);
6219 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6220 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6223 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6226 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6230 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6232 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6235 tcg_temp_free_i64(tcg_imm
);
6238 /* C3.6.7 AdvSIMD scalar copy
6239 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6240 * +-----+----+-----------------+------+---+------+---+------+------+
6241 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6242 * +-----+----+-----------------+------+---+------+---+------+------+
6244 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6246 int rd
= extract32(insn
, 0, 5);
6247 int rn
= extract32(insn
, 5, 5);
6248 int imm4
= extract32(insn
, 11, 4);
6249 int imm5
= extract32(insn
, 16, 5);
6250 int op
= extract32(insn
, 29, 1);
6252 if (op
!= 0 || imm4
!= 0) {
6253 unallocated_encoding(s
);
6257 /* DUP (element, scalar) */
6258 handle_simd_dupes(s
, rd
, rn
, imm5
);
6261 /* C3.6.8 AdvSIMD scalar pairwise
6262 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6263 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6264 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6265 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6267 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6269 int u
= extract32(insn
, 29, 1);
6270 int size
= extract32(insn
, 22, 2);
6271 int opcode
= extract32(insn
, 12, 5);
6272 int rn
= extract32(insn
, 5, 5);
6273 int rd
= extract32(insn
, 0, 5);
6276 /* For some ops (the FP ones), size[1] is part of the encoding.
6277 * For ADDP strictly it is not but size[1] is always 1 for valid
6280 opcode
|= (extract32(size
, 1, 1) << 5);
6283 case 0x3b: /* ADDP */
6284 if (u
|| size
!= 3) {
6285 unallocated_encoding(s
);
6288 if (!fp_access_check(s
)) {
6292 TCGV_UNUSED_PTR(fpst
);
6294 case 0xc: /* FMAXNMP */
6295 case 0xd: /* FADDP */
6296 case 0xf: /* FMAXP */
6297 case 0x2c: /* FMINNMP */
6298 case 0x2f: /* FMINP */
6299 /* FP op, size[0] is 32 or 64 bit */
6301 unallocated_encoding(s
);
6304 if (!fp_access_check(s
)) {
6308 size
= extract32(size
, 0, 1) ? 3 : 2;
6309 fpst
= get_fpstatus_ptr();
6312 unallocated_encoding(s
);
6317 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6318 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6319 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6321 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6322 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6325 case 0x3b: /* ADDP */
6326 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6328 case 0xc: /* FMAXNMP */
6329 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6331 case 0xd: /* FADDP */
6332 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6334 case 0xf: /* FMAXP */
6335 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6337 case 0x2c: /* FMINNMP */
6338 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6340 case 0x2f: /* FMINP */
6341 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6344 g_assert_not_reached();
6347 write_fp_dreg(s
, rd
, tcg_res
);
6349 tcg_temp_free_i64(tcg_op1
);
6350 tcg_temp_free_i64(tcg_op2
);
6351 tcg_temp_free_i64(tcg_res
);
6353 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6354 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6355 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6357 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6358 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6361 case 0xc: /* FMAXNMP */
6362 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6364 case 0xd: /* FADDP */
6365 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6367 case 0xf: /* FMAXP */
6368 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6370 case 0x2c: /* FMINNMP */
6371 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6373 case 0x2f: /* FMINP */
6374 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6377 g_assert_not_reached();
6380 write_fp_sreg(s
, rd
, tcg_res
);
6382 tcg_temp_free_i32(tcg_op1
);
6383 tcg_temp_free_i32(tcg_op2
);
6384 tcg_temp_free_i32(tcg_res
);
6387 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6388 tcg_temp_free_ptr(fpst
);
6393 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6395 * This code is handles the common shifting code and is used by both
6396 * the vector and scalar code.
6398 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6399 TCGv_i64 tcg_rnd
, bool accumulate
,
6400 bool is_u
, int size
, int shift
)
6402 bool extended_result
= false;
6403 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6405 TCGv_i64 tcg_src_hi
;
6407 if (round
&& size
== 3) {
6408 extended_result
= true;
6409 ext_lshift
= 64 - shift
;
6410 tcg_src_hi
= tcg_temp_new_i64();
6411 } else if (shift
== 64) {
6412 if (!accumulate
&& is_u
) {
6413 /* result is zero */
6414 tcg_gen_movi_i64(tcg_res
, 0);
6419 /* Deal with the rounding step */
6421 if (extended_result
) {
6422 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6424 /* take care of sign extending tcg_res */
6425 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6426 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6427 tcg_src
, tcg_src_hi
,
6430 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6434 tcg_temp_free_i64(tcg_zero
);
6436 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6440 /* Now do the shift right */
6441 if (round
&& extended_result
) {
6442 /* extended case, >64 bit precision required */
6443 if (ext_lshift
== 0) {
6444 /* special case, only high bits matter */
6445 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6447 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6448 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6449 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6454 /* essentially shifting in 64 zeros */
6455 tcg_gen_movi_i64(tcg_src
, 0);
6457 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6461 /* effectively extending the sign-bit */
6462 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6464 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6470 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6472 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6475 if (extended_result
) {
6476 tcg_temp_free_i64(tcg_src_hi
);
6480 /* Common SHL/SLI - Shift left with an optional insert */
6481 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6482 bool insert
, int shift
)
6484 if (insert
) { /* SLI */
6485 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6487 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6491 /* SRI: shift right with insert */
6492 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6493 int size
, int shift
)
6495 int esize
= 8 << size
;
6497 /* shift count same as element size is valid but does nothing;
6498 * special case to avoid potential shift by 64.
6500 if (shift
!= esize
) {
6501 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6502 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6506 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6507 static void handle_scalar_simd_shri(DisasContext
*s
,
6508 bool is_u
, int immh
, int immb
,
6509 int opcode
, int rn
, int rd
)
6512 int immhb
= immh
<< 3 | immb
;
6513 int shift
= 2 * (8 << size
) - immhb
;
6514 bool accumulate
= false;
6516 bool insert
= false;
6521 if (!extract32(immh
, 3, 1)) {
6522 unallocated_encoding(s
);
6526 if (!fp_access_check(s
)) {
6531 case 0x02: /* SSRA / USRA (accumulate) */
6534 case 0x04: /* SRSHR / URSHR (rounding) */
6537 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6538 accumulate
= round
= true;
6540 case 0x08: /* SRI */
6546 uint64_t round_const
= 1ULL << (shift
- 1);
6547 tcg_round
= tcg_const_i64(round_const
);
6549 TCGV_UNUSED_I64(tcg_round
);
6552 tcg_rn
= read_fp_dreg(s
, rn
);
6553 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6556 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6558 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6559 accumulate
, is_u
, size
, shift
);
6562 write_fp_dreg(s
, rd
, tcg_rd
);
6564 tcg_temp_free_i64(tcg_rn
);
6565 tcg_temp_free_i64(tcg_rd
);
6567 tcg_temp_free_i64(tcg_round
);
6571 /* SHL/SLI - Scalar shift left */
6572 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6573 int immh
, int immb
, int opcode
,
6576 int size
= 32 - clz32(immh
) - 1;
6577 int immhb
= immh
<< 3 | immb
;
6578 int shift
= immhb
- (8 << size
);
6579 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6580 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6582 if (!extract32(immh
, 3, 1)) {
6583 unallocated_encoding(s
);
6587 if (!fp_access_check(s
)) {
6591 tcg_rn
= read_fp_dreg(s
, rn
);
6592 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6594 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6596 write_fp_dreg(s
, rd
, tcg_rd
);
6598 tcg_temp_free_i64(tcg_rn
);
6599 tcg_temp_free_i64(tcg_rd
);
6602 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6603 * (signed/unsigned) narrowing */
6604 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6605 bool is_u_shift
, bool is_u_narrow
,
6606 int immh
, int immb
, int opcode
,
6609 int immhb
= immh
<< 3 | immb
;
6610 int size
= 32 - clz32(immh
) - 1;
6611 int esize
= 8 << size
;
6612 int shift
= (2 * esize
) - immhb
;
6613 int elements
= is_scalar
? 1 : (64 / esize
);
6614 bool round
= extract32(opcode
, 0, 1);
6615 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6616 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6617 TCGv_i32 tcg_rd_narrowed
;
6620 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6621 { gen_helper_neon_narrow_sat_s8
,
6622 gen_helper_neon_unarrow_sat8
},
6623 { gen_helper_neon_narrow_sat_s16
,
6624 gen_helper_neon_unarrow_sat16
},
6625 { gen_helper_neon_narrow_sat_s32
,
6626 gen_helper_neon_unarrow_sat32
},
6629 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6630 gen_helper_neon_narrow_sat_u8
,
6631 gen_helper_neon_narrow_sat_u16
,
6632 gen_helper_neon_narrow_sat_u32
,
6635 NeonGenNarrowEnvFn
*narrowfn
;
6641 if (extract32(immh
, 3, 1)) {
6642 unallocated_encoding(s
);
6646 if (!fp_access_check(s
)) {
6651 narrowfn
= unsigned_narrow_fns
[size
];
6653 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6656 tcg_rn
= tcg_temp_new_i64();
6657 tcg_rd
= tcg_temp_new_i64();
6658 tcg_rd_narrowed
= tcg_temp_new_i32();
6659 tcg_final
= tcg_const_i64(0);
6662 uint64_t round_const
= 1ULL << (shift
- 1);
6663 tcg_round
= tcg_const_i64(round_const
);
6665 TCGV_UNUSED_I64(tcg_round
);
6668 for (i
= 0; i
< elements
; i
++) {
6669 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6670 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6671 false, is_u_shift
, size
+1, shift
);
6672 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6673 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6674 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6678 clear_vec_high(s
, rd
);
6679 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6681 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6685 tcg_temp_free_i64(tcg_round
);
6687 tcg_temp_free_i64(tcg_rn
);
6688 tcg_temp_free_i64(tcg_rd
);
6689 tcg_temp_free_i32(tcg_rd_narrowed
);
6690 tcg_temp_free_i64(tcg_final
);
6694 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6695 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6696 bool src_unsigned
, bool dst_unsigned
,
6697 int immh
, int immb
, int rn
, int rd
)
6699 int immhb
= immh
<< 3 | immb
;
6700 int size
= 32 - clz32(immh
) - 1;
6701 int shift
= immhb
- (8 << size
);
6705 assert(!(scalar
&& is_q
));
6708 if (!is_q
&& extract32(immh
, 3, 1)) {
6709 unallocated_encoding(s
);
6713 /* Since we use the variable-shift helpers we must
6714 * replicate the shift count into each element of
6715 * the tcg_shift value.
6719 shift
|= shift
<< 8;
6722 shift
|= shift
<< 16;
6728 g_assert_not_reached();
6732 if (!fp_access_check(s
)) {
6737 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6738 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6739 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6740 { NULL
, gen_helper_neon_qshl_u64
},
6742 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6743 int maxpass
= is_q
? 2 : 1;
6745 for (pass
= 0; pass
< maxpass
; pass
++) {
6746 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6748 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6749 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6750 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6752 tcg_temp_free_i64(tcg_op
);
6754 tcg_temp_free_i64(tcg_shift
);
6757 clear_vec_high(s
, rd
);
6760 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6761 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6763 { gen_helper_neon_qshl_s8
,
6764 gen_helper_neon_qshl_s16
,
6765 gen_helper_neon_qshl_s32
},
6766 { gen_helper_neon_qshlu_s8
,
6767 gen_helper_neon_qshlu_s16
,
6768 gen_helper_neon_qshlu_s32
}
6770 { NULL
, NULL
, NULL
},
6771 { gen_helper_neon_qshl_u8
,
6772 gen_helper_neon_qshl_u16
,
6773 gen_helper_neon_qshl_u32
}
6776 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6777 TCGMemOp memop
= scalar
? size
: MO_32
;
6778 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6780 for (pass
= 0; pass
< maxpass
; pass
++) {
6781 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6783 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6784 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6788 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6791 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6796 g_assert_not_reached();
6798 write_fp_sreg(s
, rd
, tcg_op
);
6800 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6803 tcg_temp_free_i32(tcg_op
);
6805 tcg_temp_free_i32(tcg_shift
);
6807 if (!is_q
&& !scalar
) {
6808 clear_vec_high(s
, rd
);
6813 /* Common vector code for handling integer to FP conversion */
6814 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6815 int elements
, int is_signed
,
6816 int fracbits
, int size
)
6818 bool is_double
= size
== 3 ? true : false;
6819 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6820 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6821 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6822 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6825 for (pass
= 0; pass
< elements
; pass
++) {
6826 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6829 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6831 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6832 tcg_shift
, tcg_fpst
);
6834 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6835 tcg_shift
, tcg_fpst
);
6837 if (elements
== 1) {
6838 write_fp_dreg(s
, rd
, tcg_double
);
6840 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6842 tcg_temp_free_i64(tcg_double
);
6844 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6846 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6847 tcg_shift
, tcg_fpst
);
6849 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6850 tcg_shift
, tcg_fpst
);
6852 if (elements
== 1) {
6853 write_fp_sreg(s
, rd
, tcg_single
);
6855 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6857 tcg_temp_free_i32(tcg_single
);
6861 if (!is_double
&& elements
== 2) {
6862 clear_vec_high(s
, rd
);
6865 tcg_temp_free_i64(tcg_int
);
6866 tcg_temp_free_ptr(tcg_fpst
);
6867 tcg_temp_free_i32(tcg_shift
);
6870 /* UCVTF/SCVTF - Integer to FP conversion */
6871 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6872 bool is_q
, bool is_u
,
6873 int immh
, int immb
, int opcode
,
6876 bool is_double
= extract32(immh
, 3, 1);
6877 int size
= is_double
? MO_64
: MO_32
;
6879 int immhb
= immh
<< 3 | immb
;
6880 int fracbits
= (is_double
? 128 : 64) - immhb
;
6882 if (!extract32(immh
, 2, 2)) {
6883 unallocated_encoding(s
);
6890 elements
= is_double
? 2 : is_q
? 4 : 2;
6891 if (is_double
&& !is_q
) {
6892 unallocated_encoding(s
);
6897 if (!fp_access_check(s
)) {
6901 /* immh == 0 would be a failure of the decode logic */
6904 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6907 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6908 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6909 bool is_q
, bool is_u
,
6910 int immh
, int immb
, int rn
, int rd
)
6912 bool is_double
= extract32(immh
, 3, 1);
6913 int immhb
= immh
<< 3 | immb
;
6914 int fracbits
= (is_double
? 128 : 64) - immhb
;
6916 TCGv_ptr tcg_fpstatus
;
6917 TCGv_i32 tcg_rmode
, tcg_shift
;
6919 if (!extract32(immh
, 2, 2)) {
6920 unallocated_encoding(s
);
6924 if (!is_scalar
&& !is_q
&& is_double
) {
6925 unallocated_encoding(s
);
6929 if (!fp_access_check(s
)) {
6933 assert(!(is_scalar
&& is_q
));
6935 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6936 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6937 tcg_fpstatus
= get_fpstatus_ptr();
6938 tcg_shift
= tcg_const_i32(fracbits
);
6941 int maxpass
= is_scalar
? 1 : 2;
6943 for (pass
= 0; pass
< maxpass
; pass
++) {
6944 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6946 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6948 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6950 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6952 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6953 tcg_temp_free_i64(tcg_op
);
6956 clear_vec_high(s
, rd
);
6959 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6960 for (pass
= 0; pass
< maxpass
; pass
++) {
6961 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6963 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6965 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6967 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6970 write_fp_sreg(s
, rd
, tcg_op
);
6972 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6974 tcg_temp_free_i32(tcg_op
);
6976 if (!is_q
&& !is_scalar
) {
6977 clear_vec_high(s
, rd
);
6981 tcg_temp_free_ptr(tcg_fpstatus
);
6982 tcg_temp_free_i32(tcg_shift
);
6983 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6984 tcg_temp_free_i32(tcg_rmode
);
6987 /* C3.6.9 AdvSIMD scalar shift by immediate
6988 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6989 * +-----+---+-------------+------+------+--------+---+------+------+
6990 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6991 * +-----+---+-------------+------+------+--------+---+------+------+
6993 * This is the scalar version so it works on a fixed sized registers
6995 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6997 int rd
= extract32(insn
, 0, 5);
6998 int rn
= extract32(insn
, 5, 5);
6999 int opcode
= extract32(insn
, 11, 5);
7000 int immb
= extract32(insn
, 16, 3);
7001 int immh
= extract32(insn
, 19, 4);
7002 bool is_u
= extract32(insn
, 29, 1);
7005 unallocated_encoding(s
);
7010 case 0x08: /* SRI */
7012 unallocated_encoding(s
);
7016 case 0x00: /* SSHR / USHR */
7017 case 0x02: /* SSRA / USRA */
7018 case 0x04: /* SRSHR / URSHR */
7019 case 0x06: /* SRSRA / URSRA */
7020 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7022 case 0x0a: /* SHL / SLI */
7023 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7025 case 0x1c: /* SCVTF, UCVTF */
7026 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7029 case 0x10: /* SQSHRUN, SQSHRUN2 */
7030 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7032 unallocated_encoding(s
);
7035 handle_vec_simd_sqshrn(s
, true, false, false, true,
7036 immh
, immb
, opcode
, rn
, rd
);
7038 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7039 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7040 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7041 immh
, immb
, opcode
, rn
, rd
);
7043 case 0xc: /* SQSHLU */
7045 unallocated_encoding(s
);
7048 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7050 case 0xe: /* SQSHL, UQSHL */
7051 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7053 case 0x1f: /* FCVTZS, FCVTZU */
7054 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7057 unallocated_encoding(s
);
7062 /* C3.6.10 AdvSIMD scalar three different
7063 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7064 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7065 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7066 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7068 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7070 bool is_u
= extract32(insn
, 29, 1);
7071 int size
= extract32(insn
, 22, 2);
7072 int opcode
= extract32(insn
, 12, 4);
7073 int rm
= extract32(insn
, 16, 5);
7074 int rn
= extract32(insn
, 5, 5);
7075 int rd
= extract32(insn
, 0, 5);
7078 unallocated_encoding(s
);
7083 case 0x9: /* SQDMLAL, SQDMLAL2 */
7084 case 0xb: /* SQDMLSL, SQDMLSL2 */
7085 case 0xd: /* SQDMULL, SQDMULL2 */
7086 if (size
== 0 || size
== 3) {
7087 unallocated_encoding(s
);
7092 unallocated_encoding(s
);
7096 if (!fp_access_check(s
)) {
7101 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7102 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7103 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7105 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7106 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7108 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7109 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7112 case 0xd: /* SQDMULL, SQDMULL2 */
7114 case 0xb: /* SQDMLSL, SQDMLSL2 */
7115 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7117 case 0x9: /* SQDMLAL, SQDMLAL2 */
7118 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7119 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7123 g_assert_not_reached();
7126 write_fp_dreg(s
, rd
, tcg_res
);
7128 tcg_temp_free_i64(tcg_op1
);
7129 tcg_temp_free_i64(tcg_op2
);
7130 tcg_temp_free_i64(tcg_res
);
7132 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7133 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7134 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7136 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7137 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7139 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7140 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7143 case 0xd: /* SQDMULL, SQDMULL2 */
7145 case 0xb: /* SQDMLSL, SQDMLSL2 */
7146 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7148 case 0x9: /* SQDMLAL, SQDMLAL2 */
7150 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7151 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7152 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7154 tcg_temp_free_i64(tcg_op3
);
7158 g_assert_not_reached();
7161 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7162 write_fp_dreg(s
, rd
, tcg_res
);
7164 tcg_temp_free_i32(tcg_op1
);
7165 tcg_temp_free_i32(tcg_op2
);
7166 tcg_temp_free_i64(tcg_res
);
7170 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7171 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7173 /* Handle 64x64->64 opcodes which are shared between the scalar
7174 * and vector 3-same groups. We cover every opcode where size == 3
7175 * is valid in either the three-reg-same (integer, not pairwise)
7176 * or scalar-three-reg-same groups. (Some opcodes are not yet
7182 case 0x1: /* SQADD */
7184 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7186 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7189 case 0x5: /* SQSUB */
7191 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7193 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7196 case 0x6: /* CMGT, CMHI */
7197 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7198 * We implement this using setcond (test) and then negating.
7200 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7202 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7203 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7205 case 0x7: /* CMGE, CMHS */
7206 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7208 case 0x11: /* CMTST, CMEQ */
7213 /* CMTST : test is "if (X & Y != 0)". */
7214 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7215 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7216 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7218 case 0x8: /* SSHL, USHL */
7220 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7222 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7225 case 0x9: /* SQSHL, UQSHL */
7227 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7229 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7232 case 0xa: /* SRSHL, URSHL */
7234 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7236 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7239 case 0xb: /* SQRSHL, UQRSHL */
7241 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7243 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7246 case 0x10: /* ADD, SUB */
7248 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7250 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7254 g_assert_not_reached();
7258 /* Handle the 3-same-operands float operations; shared by the scalar
7259 * and vector encodings. The caller must filter out any encodings
7260 * not allocated for the encoding it is dealing with.
7262 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7263 int fpopcode
, int rd
, int rn
, int rm
)
7266 TCGv_ptr fpst
= get_fpstatus_ptr();
7268 for (pass
= 0; pass
< elements
; pass
++) {
7271 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7272 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7273 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7275 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7276 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7279 case 0x39: /* FMLS */
7280 /* As usual for ARM, separate negation for fused multiply-add */
7281 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7283 case 0x19: /* FMLA */
7284 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7285 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7288 case 0x18: /* FMAXNM */
7289 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7291 case 0x1a: /* FADD */
7292 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7294 case 0x1b: /* FMULX */
7295 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7297 case 0x1c: /* FCMEQ */
7298 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7300 case 0x1e: /* FMAX */
7301 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7303 case 0x1f: /* FRECPS */
7304 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7306 case 0x38: /* FMINNM */
7307 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7309 case 0x3a: /* FSUB */
7310 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7312 case 0x3e: /* FMIN */
7313 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7315 case 0x3f: /* FRSQRTS */
7316 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7318 case 0x5b: /* FMUL */
7319 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7321 case 0x5c: /* FCMGE */
7322 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7324 case 0x5d: /* FACGE */
7325 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7327 case 0x5f: /* FDIV */
7328 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7330 case 0x7a: /* FABD */
7331 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7332 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7334 case 0x7c: /* FCMGT */
7335 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7337 case 0x7d: /* FACGT */
7338 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7341 g_assert_not_reached();
7344 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7346 tcg_temp_free_i64(tcg_res
);
7347 tcg_temp_free_i64(tcg_op1
);
7348 tcg_temp_free_i64(tcg_op2
);
7351 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7352 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7353 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7355 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7356 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7359 case 0x39: /* FMLS */
7360 /* As usual for ARM, separate negation for fused multiply-add */
7361 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7363 case 0x19: /* FMLA */
7364 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7365 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7368 case 0x1a: /* FADD */
7369 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7371 case 0x1b: /* FMULX */
7372 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7374 case 0x1c: /* FCMEQ */
7375 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7377 case 0x1e: /* FMAX */
7378 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7380 case 0x1f: /* FRECPS */
7381 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7383 case 0x18: /* FMAXNM */
7384 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7386 case 0x38: /* FMINNM */
7387 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7389 case 0x3a: /* FSUB */
7390 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7392 case 0x3e: /* FMIN */
7393 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7395 case 0x3f: /* FRSQRTS */
7396 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7398 case 0x5b: /* FMUL */
7399 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7401 case 0x5c: /* FCMGE */
7402 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7404 case 0x5d: /* FACGE */
7405 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7407 case 0x5f: /* FDIV */
7408 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7410 case 0x7a: /* FABD */
7411 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7412 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7414 case 0x7c: /* FCMGT */
7415 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7417 case 0x7d: /* FACGT */
7418 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7421 g_assert_not_reached();
7424 if (elements
== 1) {
7425 /* scalar single so clear high part */
7426 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7428 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7429 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7430 tcg_temp_free_i64(tcg_tmp
);
7432 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7435 tcg_temp_free_i32(tcg_res
);
7436 tcg_temp_free_i32(tcg_op1
);
7437 tcg_temp_free_i32(tcg_op2
);
7441 tcg_temp_free_ptr(fpst
);
7443 if ((elements
<< size
) < 4) {
7444 /* scalar, or non-quad vector op */
7445 clear_vec_high(s
, rd
);
7449 /* C3.6.11 AdvSIMD scalar three same
7450 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7451 * +-----+---+-----------+------+---+------+--------+---+------+------+
7452 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7453 * +-----+---+-----------+------+---+------+--------+---+------+------+
7455 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7457 int rd
= extract32(insn
, 0, 5);
7458 int rn
= extract32(insn
, 5, 5);
7459 int opcode
= extract32(insn
, 11, 5);
7460 int rm
= extract32(insn
, 16, 5);
7461 int size
= extract32(insn
, 22, 2);
7462 bool u
= extract32(insn
, 29, 1);
7465 if (opcode
>= 0x18) {
7466 /* Floating point: U, size[1] and opcode indicate operation */
7467 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7469 case 0x1b: /* FMULX */
7470 case 0x1f: /* FRECPS */
7471 case 0x3f: /* FRSQRTS */
7472 case 0x5d: /* FACGE */
7473 case 0x7d: /* FACGT */
7474 case 0x1c: /* FCMEQ */
7475 case 0x5c: /* FCMGE */
7476 case 0x7c: /* FCMGT */
7477 case 0x7a: /* FABD */
7480 unallocated_encoding(s
);
7484 if (!fp_access_check(s
)) {
7488 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7493 case 0x1: /* SQADD, UQADD */
7494 case 0x5: /* SQSUB, UQSUB */
7495 case 0x9: /* SQSHL, UQSHL */
7496 case 0xb: /* SQRSHL, UQRSHL */
7498 case 0x8: /* SSHL, USHL */
7499 case 0xa: /* SRSHL, URSHL */
7500 case 0x6: /* CMGT, CMHI */
7501 case 0x7: /* CMGE, CMHS */
7502 case 0x11: /* CMTST, CMEQ */
7503 case 0x10: /* ADD, SUB (vector) */
7505 unallocated_encoding(s
);
7509 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7510 if (size
!= 1 && size
!= 2) {
7511 unallocated_encoding(s
);
7516 unallocated_encoding(s
);
7520 if (!fp_access_check(s
)) {
7524 tcg_rd
= tcg_temp_new_i64();
7527 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7528 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7530 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7531 tcg_temp_free_i64(tcg_rn
);
7532 tcg_temp_free_i64(tcg_rm
);
7534 /* Do a single operation on the lowest element in the vector.
7535 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7536 * no side effects for all these operations.
7537 * OPTME: special-purpose helpers would avoid doing some
7538 * unnecessary work in the helper for the 8 and 16 bit cases.
7540 NeonGenTwoOpEnvFn
*genenvfn
;
7541 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7542 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7543 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7545 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7546 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7549 case 0x1: /* SQADD, UQADD */
7551 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7552 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7553 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7554 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7556 genenvfn
= fns
[size
][u
];
7559 case 0x5: /* SQSUB, UQSUB */
7561 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7562 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7563 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7564 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7566 genenvfn
= fns
[size
][u
];
7569 case 0x9: /* SQSHL, UQSHL */
7571 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7572 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7573 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7574 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7576 genenvfn
= fns
[size
][u
];
7579 case 0xb: /* SQRSHL, UQRSHL */
7581 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7582 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7583 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7584 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7586 genenvfn
= fns
[size
][u
];
7589 case 0x16: /* SQDMULH, SQRDMULH */
7591 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7592 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7593 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7595 assert(size
== 1 || size
== 2);
7596 genenvfn
= fns
[size
- 1][u
];
7600 g_assert_not_reached();
7603 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7604 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7605 tcg_temp_free_i32(tcg_rd32
);
7606 tcg_temp_free_i32(tcg_rn
);
7607 tcg_temp_free_i32(tcg_rm
);
7610 write_fp_dreg(s
, rd
, tcg_rd
);
7612 tcg_temp_free_i64(tcg_rd
);
7615 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7616 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7617 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7619 /* Handle 64->64 opcodes which are shared between the scalar and
7620 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7621 * is valid in either group and also the double-precision fp ops.
7622 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7628 case 0x4: /* CLS, CLZ */
7630 gen_helper_clz64(tcg_rd
, tcg_rn
);
7632 gen_helper_cls64(tcg_rd
, tcg_rn
);
7636 /* This opcode is shared with CNT and RBIT but we have earlier
7637 * enforced that size == 3 if and only if this is the NOT insn.
7639 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7641 case 0x7: /* SQABS, SQNEG */
7643 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7645 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7648 case 0xa: /* CMLT */
7649 /* 64 bit integer comparison against zero, result is
7650 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7655 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7656 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7658 case 0x8: /* CMGT, CMGE */
7659 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7661 case 0x9: /* CMEQ, CMLE */
7662 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7664 case 0xb: /* ABS, NEG */
7666 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7668 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7669 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7670 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7672 tcg_temp_free_i64(tcg_zero
);
7675 case 0x2f: /* FABS */
7676 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7678 case 0x6f: /* FNEG */
7679 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7681 case 0x7f: /* FSQRT */
7682 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7684 case 0x1a: /* FCVTNS */
7685 case 0x1b: /* FCVTMS */
7686 case 0x1c: /* FCVTAS */
7687 case 0x3a: /* FCVTPS */
7688 case 0x3b: /* FCVTZS */
7690 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7691 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7692 tcg_temp_free_i32(tcg_shift
);
7695 case 0x5a: /* FCVTNU */
7696 case 0x5b: /* FCVTMU */
7697 case 0x5c: /* FCVTAU */
7698 case 0x7a: /* FCVTPU */
7699 case 0x7b: /* FCVTZU */
7701 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7702 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7703 tcg_temp_free_i32(tcg_shift
);
7706 case 0x18: /* FRINTN */
7707 case 0x19: /* FRINTM */
7708 case 0x38: /* FRINTP */
7709 case 0x39: /* FRINTZ */
7710 case 0x58: /* FRINTA */
7711 case 0x79: /* FRINTI */
7712 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7714 case 0x59: /* FRINTX */
7715 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7718 g_assert_not_reached();
7722 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7723 bool is_scalar
, bool is_u
, bool is_q
,
7724 int size
, int rn
, int rd
)
7726 bool is_double
= (size
== 3);
7729 if (!fp_access_check(s
)) {
7733 fpst
= get_fpstatus_ptr();
7736 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7737 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7738 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7739 NeonGenTwoDoubleOPFn
*genfn
;
7744 case 0x2e: /* FCMLT (zero) */
7747 case 0x2c: /* FCMGT (zero) */
7748 genfn
= gen_helper_neon_cgt_f64
;
7750 case 0x2d: /* FCMEQ (zero) */
7751 genfn
= gen_helper_neon_ceq_f64
;
7753 case 0x6d: /* FCMLE (zero) */
7756 case 0x6c: /* FCMGE (zero) */
7757 genfn
= gen_helper_neon_cge_f64
;
7760 g_assert_not_reached();
7763 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7764 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7766 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7768 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7770 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7773 clear_vec_high(s
, rd
);
7776 tcg_temp_free_i64(tcg_res
);
7777 tcg_temp_free_i64(tcg_zero
);
7778 tcg_temp_free_i64(tcg_op
);
7780 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7781 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7782 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7783 NeonGenTwoSingleOPFn
*genfn
;
7785 int pass
, maxpasses
;
7788 case 0x2e: /* FCMLT (zero) */
7791 case 0x2c: /* FCMGT (zero) */
7792 genfn
= gen_helper_neon_cgt_f32
;
7794 case 0x2d: /* FCMEQ (zero) */
7795 genfn
= gen_helper_neon_ceq_f32
;
7797 case 0x6d: /* FCMLE (zero) */
7800 case 0x6c: /* FCMGE (zero) */
7801 genfn
= gen_helper_neon_cge_f32
;
7804 g_assert_not_reached();
7810 maxpasses
= is_q
? 4 : 2;
7813 for (pass
= 0; pass
< maxpasses
; pass
++) {
7814 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7816 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7818 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7821 write_fp_sreg(s
, rd
, tcg_res
);
7823 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7826 tcg_temp_free_i32(tcg_res
);
7827 tcg_temp_free_i32(tcg_zero
);
7828 tcg_temp_free_i32(tcg_op
);
7829 if (!is_q
&& !is_scalar
) {
7830 clear_vec_high(s
, rd
);
7834 tcg_temp_free_ptr(fpst
);
7837 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7838 bool is_scalar
, bool is_u
, bool is_q
,
7839 int size
, int rn
, int rd
)
7841 bool is_double
= (size
== 3);
7842 TCGv_ptr fpst
= get_fpstatus_ptr();
7845 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7846 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7849 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7850 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7852 case 0x3d: /* FRECPE */
7853 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7855 case 0x3f: /* FRECPX */
7856 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7858 case 0x7d: /* FRSQRTE */
7859 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7862 g_assert_not_reached();
7864 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7867 clear_vec_high(s
, rd
);
7870 tcg_temp_free_i64(tcg_res
);
7871 tcg_temp_free_i64(tcg_op
);
7873 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7874 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7875 int pass
, maxpasses
;
7880 maxpasses
= is_q
? 4 : 2;
7883 for (pass
= 0; pass
< maxpasses
; pass
++) {
7884 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7887 case 0x3c: /* URECPE */
7888 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7890 case 0x3d: /* FRECPE */
7891 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7893 case 0x3f: /* FRECPX */
7894 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7896 case 0x7d: /* FRSQRTE */
7897 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7900 g_assert_not_reached();
7904 write_fp_sreg(s
, rd
, tcg_res
);
7906 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7909 tcg_temp_free_i32(tcg_res
);
7910 tcg_temp_free_i32(tcg_op
);
7911 if (!is_q
&& !is_scalar
) {
7912 clear_vec_high(s
, rd
);
7915 tcg_temp_free_ptr(fpst
);
7918 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7919 int opcode
, bool u
, bool is_q
,
7920 int size
, int rn
, int rd
)
7922 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7923 * in the source becomes a size element in the destination).
7926 TCGv_i32 tcg_res
[2];
7927 int destelt
= is_q
? 2 : 0;
7928 int passes
= scalar
? 1 : 2;
7931 tcg_res
[1] = tcg_const_i32(0);
7934 for (pass
= 0; pass
< passes
; pass
++) {
7935 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7936 NeonGenNarrowFn
*genfn
= NULL
;
7937 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7940 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7942 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7944 tcg_res
[pass
] = tcg_temp_new_i32();
7947 case 0x12: /* XTN, SQXTUN */
7949 static NeonGenNarrowFn
* const xtnfns
[3] = {
7950 gen_helper_neon_narrow_u8
,
7951 gen_helper_neon_narrow_u16
,
7952 tcg_gen_extrl_i64_i32
,
7954 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7955 gen_helper_neon_unarrow_sat8
,
7956 gen_helper_neon_unarrow_sat16
,
7957 gen_helper_neon_unarrow_sat32
,
7960 genenvfn
= sqxtunfns
[size
];
7962 genfn
= xtnfns
[size
];
7966 case 0x14: /* SQXTN, UQXTN */
7968 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7969 { gen_helper_neon_narrow_sat_s8
,
7970 gen_helper_neon_narrow_sat_u8
},
7971 { gen_helper_neon_narrow_sat_s16
,
7972 gen_helper_neon_narrow_sat_u16
},
7973 { gen_helper_neon_narrow_sat_s32
,
7974 gen_helper_neon_narrow_sat_u32
},
7976 genenvfn
= fns
[size
][u
];
7979 case 0x16: /* FCVTN, FCVTN2 */
7980 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7982 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7984 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7985 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7986 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7987 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7988 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7989 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7990 tcg_temp_free_i32(tcg_lo
);
7991 tcg_temp_free_i32(tcg_hi
);
7994 case 0x56: /* FCVTXN, FCVTXN2 */
7995 /* 64 bit to 32 bit float conversion
7996 * with von Neumann rounding (round to odd)
7999 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
8002 g_assert_not_reached();
8006 genfn(tcg_res
[pass
], tcg_op
);
8007 } else if (genenvfn
) {
8008 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
8011 tcg_temp_free_i64(tcg_op
);
8014 for (pass
= 0; pass
< 2; pass
++) {
8015 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
8016 tcg_temp_free_i32(tcg_res
[pass
]);
8019 clear_vec_high(s
, rd
);
8023 /* Remaining saturating accumulating ops */
8024 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
8025 bool is_q
, int size
, int rn
, int rd
)
8027 bool is_double
= (size
== 3);
8030 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
8031 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8034 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8035 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
8036 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8038 if (is_u
) { /* USQADD */
8039 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8040 } else { /* SUQADD */
8041 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8043 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8046 clear_vec_high(s
, rd
);
8049 tcg_temp_free_i64(tcg_rd
);
8050 tcg_temp_free_i64(tcg_rn
);
8052 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8053 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8054 int pass
, maxpasses
;
8059 maxpasses
= is_q
? 4 : 2;
8062 for (pass
= 0; pass
< maxpasses
; pass
++) {
8064 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8065 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8067 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8068 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8071 if (is_u
) { /* USQADD */
8074 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8077 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8080 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8083 g_assert_not_reached();
8085 } else { /* SUQADD */
8088 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8091 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8094 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8097 g_assert_not_reached();
8102 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8103 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8104 tcg_temp_free_i64(tcg_zero
);
8106 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8110 clear_vec_high(s
, rd
);
8113 tcg_temp_free_i32(tcg_rd
);
8114 tcg_temp_free_i32(tcg_rn
);
8118 /* C3.6.12 AdvSIMD scalar two reg misc
8119 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8120 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8121 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8122 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8124 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8126 int rd
= extract32(insn
, 0, 5);
8127 int rn
= extract32(insn
, 5, 5);
8128 int opcode
= extract32(insn
, 12, 5);
8129 int size
= extract32(insn
, 22, 2);
8130 bool u
= extract32(insn
, 29, 1);
8131 bool is_fcvt
= false;
8134 TCGv_ptr tcg_fpstatus
;
8137 case 0x3: /* USQADD / SUQADD*/
8138 if (!fp_access_check(s
)) {
8141 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8143 case 0x7: /* SQABS / SQNEG */
8145 case 0xa: /* CMLT */
8147 unallocated_encoding(s
);
8151 case 0x8: /* CMGT, CMGE */
8152 case 0x9: /* CMEQ, CMLE */
8153 case 0xb: /* ABS, NEG */
8155 unallocated_encoding(s
);
8159 case 0x12: /* SQXTUN */
8161 unallocated_encoding(s
);
8165 case 0x14: /* SQXTN, UQXTN */
8167 unallocated_encoding(s
);
8170 if (!fp_access_check(s
)) {
8173 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8178 /* Floating point: U, size[1] and opcode indicate operation;
8179 * size[0] indicates single or double precision.
8181 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8182 size
= extract32(size
, 0, 1) ? 3 : 2;
8184 case 0x2c: /* FCMGT (zero) */
8185 case 0x2d: /* FCMEQ (zero) */
8186 case 0x2e: /* FCMLT (zero) */
8187 case 0x6c: /* FCMGE (zero) */
8188 case 0x6d: /* FCMLE (zero) */
8189 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8191 case 0x1d: /* SCVTF */
8192 case 0x5d: /* UCVTF */
8194 bool is_signed
= (opcode
== 0x1d);
8195 if (!fp_access_check(s
)) {
8198 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8201 case 0x3d: /* FRECPE */
8202 case 0x3f: /* FRECPX */
8203 case 0x7d: /* FRSQRTE */
8204 if (!fp_access_check(s
)) {
8207 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8209 case 0x1a: /* FCVTNS */
8210 case 0x1b: /* FCVTMS */
8211 case 0x3a: /* FCVTPS */
8212 case 0x3b: /* FCVTZS */
8213 case 0x5a: /* FCVTNU */
8214 case 0x5b: /* FCVTMU */
8215 case 0x7a: /* FCVTPU */
8216 case 0x7b: /* FCVTZU */
8218 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8220 case 0x1c: /* FCVTAS */
8221 case 0x5c: /* FCVTAU */
8222 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8224 rmode
= FPROUNDING_TIEAWAY
;
8226 case 0x56: /* FCVTXN, FCVTXN2 */
8228 unallocated_encoding(s
);
8231 if (!fp_access_check(s
)) {
8234 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8237 unallocated_encoding(s
);
8242 unallocated_encoding(s
);
8246 if (!fp_access_check(s
)) {
8251 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8252 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8253 tcg_fpstatus
= get_fpstatus_ptr();
8255 TCGV_UNUSED_I32(tcg_rmode
);
8256 TCGV_UNUSED_PTR(tcg_fpstatus
);
8260 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8261 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8263 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8264 write_fp_dreg(s
, rd
, tcg_rd
);
8265 tcg_temp_free_i64(tcg_rd
);
8266 tcg_temp_free_i64(tcg_rn
);
8268 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8269 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8271 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8274 case 0x7: /* SQABS, SQNEG */
8276 NeonGenOneOpEnvFn
*genfn
;
8277 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8278 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8279 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8280 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8282 genfn
= fns
[size
][u
];
8283 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8286 case 0x1a: /* FCVTNS */
8287 case 0x1b: /* FCVTMS */
8288 case 0x1c: /* FCVTAS */
8289 case 0x3a: /* FCVTPS */
8290 case 0x3b: /* FCVTZS */
8292 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8293 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8294 tcg_temp_free_i32(tcg_shift
);
8297 case 0x5a: /* FCVTNU */
8298 case 0x5b: /* FCVTMU */
8299 case 0x5c: /* FCVTAU */
8300 case 0x7a: /* FCVTPU */
8301 case 0x7b: /* FCVTZU */
8303 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8304 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8305 tcg_temp_free_i32(tcg_shift
);
8309 g_assert_not_reached();
8312 write_fp_sreg(s
, rd
, tcg_rd
);
8313 tcg_temp_free_i32(tcg_rd
);
8314 tcg_temp_free_i32(tcg_rn
);
8318 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8319 tcg_temp_free_i32(tcg_rmode
);
8320 tcg_temp_free_ptr(tcg_fpstatus
);
8324 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8325 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8326 int immh
, int immb
, int opcode
, int rn
, int rd
)
8328 int size
= 32 - clz32(immh
) - 1;
8329 int immhb
= immh
<< 3 | immb
;
8330 int shift
= 2 * (8 << size
) - immhb
;
8331 bool accumulate
= false;
8333 bool insert
= false;
8334 int dsize
= is_q
? 128 : 64;
8335 int esize
= 8 << size
;
8336 int elements
= dsize
/esize
;
8337 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8338 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8339 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8343 if (extract32(immh
, 3, 1) && !is_q
) {
8344 unallocated_encoding(s
);
8348 if (size
> 3 && !is_q
) {
8349 unallocated_encoding(s
);
8353 if (!fp_access_check(s
)) {
8358 case 0x02: /* SSRA / USRA (accumulate) */
8361 case 0x04: /* SRSHR / URSHR (rounding) */
8364 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8365 accumulate
= round
= true;
8367 case 0x08: /* SRI */
8373 uint64_t round_const
= 1ULL << (shift
- 1);
8374 tcg_round
= tcg_const_i64(round_const
);
8376 TCGV_UNUSED_I64(tcg_round
);
8379 for (i
= 0; i
< elements
; i
++) {
8380 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8381 if (accumulate
|| insert
) {
8382 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8386 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8388 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8389 accumulate
, is_u
, size
, shift
);
8392 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8396 clear_vec_high(s
, rd
);
8400 tcg_temp_free_i64(tcg_round
);
8404 /* SHL/SLI - Vector shift left */
8405 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8406 int immh
, int immb
, int opcode
, int rn
, int rd
)
8408 int size
= 32 - clz32(immh
) - 1;
8409 int immhb
= immh
<< 3 | immb
;
8410 int shift
= immhb
- (8 << size
);
8411 int dsize
= is_q
? 128 : 64;
8412 int esize
= 8 << size
;
8413 int elements
= dsize
/esize
;
8414 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8415 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8418 if (extract32(immh
, 3, 1) && !is_q
) {
8419 unallocated_encoding(s
);
8423 if (size
> 3 && !is_q
) {
8424 unallocated_encoding(s
);
8428 if (!fp_access_check(s
)) {
8432 for (i
= 0; i
< elements
; i
++) {
8433 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8435 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8438 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8440 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8444 clear_vec_high(s
, rd
);
8448 /* USHLL/SHLL - Vector shift left with widening */
8449 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8450 int immh
, int immb
, int opcode
, int rn
, int rd
)
8452 int size
= 32 - clz32(immh
) - 1;
8453 int immhb
= immh
<< 3 | immb
;
8454 int shift
= immhb
- (8 << size
);
8456 int esize
= 8 << size
;
8457 int elements
= dsize
/esize
;
8458 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8459 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8463 unallocated_encoding(s
);
8467 if (!fp_access_check(s
)) {
8471 /* For the LL variants the store is larger than the load,
8472 * so if rd == rn we would overwrite parts of our input.
8473 * So load everything right now and use shifts in the main loop.
8475 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8477 for (i
= 0; i
< elements
; i
++) {
8478 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8479 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8480 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8481 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8485 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8486 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8487 int immh
, int immb
, int opcode
, int rn
, int rd
)
8489 int immhb
= immh
<< 3 | immb
;
8490 int size
= 32 - clz32(immh
) - 1;
8492 int esize
= 8 << size
;
8493 int elements
= dsize
/esize
;
8494 int shift
= (2 * esize
) - immhb
;
8495 bool round
= extract32(opcode
, 0, 1);
8496 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8500 if (extract32(immh
, 3, 1)) {
8501 unallocated_encoding(s
);
8505 if (!fp_access_check(s
)) {
8509 tcg_rn
= tcg_temp_new_i64();
8510 tcg_rd
= tcg_temp_new_i64();
8511 tcg_final
= tcg_temp_new_i64();
8512 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8515 uint64_t round_const
= 1ULL << (shift
- 1);
8516 tcg_round
= tcg_const_i64(round_const
);
8518 TCGV_UNUSED_I64(tcg_round
);
8521 for (i
= 0; i
< elements
; i
++) {
8522 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8523 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8524 false, true, size
+1, shift
);
8526 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8530 clear_vec_high(s
, rd
);
8531 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8533 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8537 tcg_temp_free_i64(tcg_round
);
8539 tcg_temp_free_i64(tcg_rn
);
8540 tcg_temp_free_i64(tcg_rd
);
8541 tcg_temp_free_i64(tcg_final
);
8546 /* C3.6.14 AdvSIMD shift by immediate
8547 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8548 * +---+---+---+-------------+------+------+--------+---+------+------+
8549 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8550 * +---+---+---+-------------+------+------+--------+---+------+------+
8552 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8554 int rd
= extract32(insn
, 0, 5);
8555 int rn
= extract32(insn
, 5, 5);
8556 int opcode
= extract32(insn
, 11, 5);
8557 int immb
= extract32(insn
, 16, 3);
8558 int immh
= extract32(insn
, 19, 4);
8559 bool is_u
= extract32(insn
, 29, 1);
8560 bool is_q
= extract32(insn
, 30, 1);
8563 case 0x08: /* SRI */
8565 unallocated_encoding(s
);
8569 case 0x00: /* SSHR / USHR */
8570 case 0x02: /* SSRA / USRA (accumulate) */
8571 case 0x04: /* SRSHR / URSHR (rounding) */
8572 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8573 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8575 case 0x0a: /* SHL / SLI */
8576 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8578 case 0x10: /* SHRN */
8579 case 0x11: /* RSHRN / SQRSHRUN */
8581 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8584 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8587 case 0x12: /* SQSHRN / UQSHRN */
8588 case 0x13: /* SQRSHRN / UQRSHRN */
8589 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8592 case 0x14: /* SSHLL / USHLL */
8593 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8595 case 0x1c: /* SCVTF / UCVTF */
8596 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8599 case 0xc: /* SQSHLU */
8601 unallocated_encoding(s
);
8604 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8606 case 0xe: /* SQSHL, UQSHL */
8607 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8609 case 0x1f: /* FCVTZS/ FCVTZU */
8610 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8613 unallocated_encoding(s
);
8618 /* Generate code to do a "long" addition or subtraction, ie one done in
8619 * TCGv_i64 on vector lanes twice the width specified by size.
8621 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8622 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8624 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8625 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8626 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8627 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8629 NeonGenTwo64OpFn
*genfn
;
8632 genfn
= fns
[size
][is_sub
];
8633 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8636 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8637 int opcode
, int rd
, int rn
, int rm
)
8639 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8640 TCGv_i64 tcg_res
[2];
8643 tcg_res
[0] = tcg_temp_new_i64();
8644 tcg_res
[1] = tcg_temp_new_i64();
8646 /* Does this op do an adding accumulate, a subtracting accumulate,
8647 * or no accumulate at all?
8665 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8666 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8669 /* size == 2 means two 32x32->64 operations; this is worth special
8670 * casing because we can generally handle it inline.
8673 for (pass
= 0; pass
< 2; pass
++) {
8674 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8675 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8676 TCGv_i64 tcg_passres
;
8677 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8679 int elt
= pass
+ is_q
* 2;
8681 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8682 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8685 tcg_passres
= tcg_res
[pass
];
8687 tcg_passres
= tcg_temp_new_i64();
8691 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8692 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8694 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8695 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8697 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8698 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8700 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8701 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8703 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8704 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8705 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8707 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8708 tcg_temp_free_i64(tcg_tmp1
);
8709 tcg_temp_free_i64(tcg_tmp2
);
8712 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8713 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8714 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8715 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8717 case 9: /* SQDMLAL, SQDMLAL2 */
8718 case 11: /* SQDMLSL, SQDMLSL2 */
8719 case 13: /* SQDMULL, SQDMULL2 */
8720 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8721 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8722 tcg_passres
, tcg_passres
);
8725 g_assert_not_reached();
8728 if (opcode
== 9 || opcode
== 11) {
8729 /* saturating accumulate ops */
8731 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8733 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8734 tcg_res
[pass
], tcg_passres
);
8735 } else if (accop
> 0) {
8736 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8737 } else if (accop
< 0) {
8738 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8742 tcg_temp_free_i64(tcg_passres
);
8745 tcg_temp_free_i64(tcg_op1
);
8746 tcg_temp_free_i64(tcg_op2
);
8749 /* size 0 or 1, generally helper functions */
8750 for (pass
= 0; pass
< 2; pass
++) {
8751 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8752 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8753 TCGv_i64 tcg_passres
;
8754 int elt
= pass
+ is_q
* 2;
8756 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8757 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8760 tcg_passres
= tcg_res
[pass
];
8762 tcg_passres
= tcg_temp_new_i64();
8766 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8767 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8769 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8770 static NeonGenWidenFn
* const widenfns
[2][2] = {
8771 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8772 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8774 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8776 widenfn(tcg_op2_64
, tcg_op2
);
8777 widenfn(tcg_passres
, tcg_op1
);
8778 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8779 tcg_passres
, tcg_op2_64
);
8780 tcg_temp_free_i64(tcg_op2_64
);
8783 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8784 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8787 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8789 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8793 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8795 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8799 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8800 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8801 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8804 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8806 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8810 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8812 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8816 case 9: /* SQDMLAL, SQDMLAL2 */
8817 case 11: /* SQDMLSL, SQDMLSL2 */
8818 case 13: /* SQDMULL, SQDMULL2 */
8820 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8821 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8822 tcg_passres
, tcg_passres
);
8824 case 14: /* PMULL */
8826 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8829 g_assert_not_reached();
8831 tcg_temp_free_i32(tcg_op1
);
8832 tcg_temp_free_i32(tcg_op2
);
8835 if (opcode
== 9 || opcode
== 11) {
8836 /* saturating accumulate ops */
8838 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8840 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8844 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8845 tcg_res
[pass
], tcg_passres
);
8847 tcg_temp_free_i64(tcg_passres
);
8852 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8853 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8854 tcg_temp_free_i64(tcg_res
[0]);
8855 tcg_temp_free_i64(tcg_res
[1]);
8858 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8859 int opcode
, int rd
, int rn
, int rm
)
8861 TCGv_i64 tcg_res
[2];
8862 int part
= is_q
? 2 : 0;
8865 for (pass
= 0; pass
< 2; pass
++) {
8866 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8867 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8868 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8869 static NeonGenWidenFn
* const widenfns
[3][2] = {
8870 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8871 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8872 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8874 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8876 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8877 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8878 widenfn(tcg_op2_wide
, tcg_op2
);
8879 tcg_temp_free_i32(tcg_op2
);
8880 tcg_res
[pass
] = tcg_temp_new_i64();
8881 gen_neon_addl(size
, (opcode
== 3),
8882 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8883 tcg_temp_free_i64(tcg_op1
);
8884 tcg_temp_free_i64(tcg_op2_wide
);
8887 for (pass
= 0; pass
< 2; pass
++) {
8888 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8889 tcg_temp_free_i64(tcg_res
[pass
]);
8893 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8895 tcg_gen_addi_i64(in
, in
, 1U << 31);
8896 tcg_gen_extrh_i64_i32(res
, in
);
8899 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8900 int opcode
, int rd
, int rn
, int rm
)
8902 TCGv_i32 tcg_res
[2];
8903 int part
= is_q
? 2 : 0;
8906 for (pass
= 0; pass
< 2; pass
++) {
8907 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8908 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8909 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8910 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8911 { gen_helper_neon_narrow_high_u8
,
8912 gen_helper_neon_narrow_round_high_u8
},
8913 { gen_helper_neon_narrow_high_u16
,
8914 gen_helper_neon_narrow_round_high_u16
},
8915 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8917 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8919 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8920 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8922 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8924 tcg_temp_free_i64(tcg_op1
);
8925 tcg_temp_free_i64(tcg_op2
);
8927 tcg_res
[pass
] = tcg_temp_new_i32();
8928 gennarrow(tcg_res
[pass
], tcg_wideres
);
8929 tcg_temp_free_i64(tcg_wideres
);
8932 for (pass
= 0; pass
< 2; pass
++) {
8933 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8934 tcg_temp_free_i32(tcg_res
[pass
]);
8937 clear_vec_high(s
, rd
);
8941 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8943 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8944 * is the only three-reg-diff instruction which produces a
8945 * 128-bit wide result from a single operation. However since
8946 * it's possible to calculate the two halves more or less
8947 * separately we just use two helper calls.
8949 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8950 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8951 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8953 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8954 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8955 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8956 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8957 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8958 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8960 tcg_temp_free_i64(tcg_op1
);
8961 tcg_temp_free_i64(tcg_op2
);
8962 tcg_temp_free_i64(tcg_res
);
8965 /* C3.6.15 AdvSIMD three different
8966 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8967 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8968 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8969 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8971 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8973 /* Instructions in this group fall into three basic classes
8974 * (in each case with the operation working on each element in
8975 * the input vectors):
8976 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8978 * (2) wide 64 x 128 -> 128
8979 * (3) narrowing 128 x 128 -> 64
8980 * Here we do initial decode, catch unallocated cases and
8981 * dispatch to separate functions for each class.
8983 int is_q
= extract32(insn
, 30, 1);
8984 int is_u
= extract32(insn
, 29, 1);
8985 int size
= extract32(insn
, 22, 2);
8986 int opcode
= extract32(insn
, 12, 4);
8987 int rm
= extract32(insn
, 16, 5);
8988 int rn
= extract32(insn
, 5, 5);
8989 int rd
= extract32(insn
, 0, 5);
8992 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8993 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8994 /* 64 x 128 -> 128 */
8996 unallocated_encoding(s
);
8999 if (!fp_access_check(s
)) {
9002 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9004 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
9005 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
9006 /* 128 x 128 -> 64 */
9008 unallocated_encoding(s
);
9011 if (!fp_access_check(s
)) {
9014 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9016 case 14: /* PMULL, PMULL2 */
9017 if (is_u
|| size
== 1 || size
== 2) {
9018 unallocated_encoding(s
);
9022 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
9023 unallocated_encoding(s
);
9026 if (!fp_access_check(s
)) {
9029 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
9033 case 9: /* SQDMLAL, SQDMLAL2 */
9034 case 11: /* SQDMLSL, SQDMLSL2 */
9035 case 13: /* SQDMULL, SQDMULL2 */
9036 if (is_u
|| size
== 0) {
9037 unallocated_encoding(s
);
9041 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9042 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9043 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9044 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9045 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9046 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9047 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9048 /* 64 x 64 -> 128 */
9050 unallocated_encoding(s
);
9054 if (!fp_access_check(s
)) {
9058 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9061 /* opcode 15 not allocated */
9062 unallocated_encoding(s
);
9067 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9068 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9070 int rd
= extract32(insn
, 0, 5);
9071 int rn
= extract32(insn
, 5, 5);
9072 int rm
= extract32(insn
, 16, 5);
9073 int size
= extract32(insn
, 22, 2);
9074 bool is_u
= extract32(insn
, 29, 1);
9075 bool is_q
= extract32(insn
, 30, 1);
9076 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9079 if (!fp_access_check(s
)) {
9083 tcg_op1
= tcg_temp_new_i64();
9084 tcg_op2
= tcg_temp_new_i64();
9085 tcg_res
[0] = tcg_temp_new_i64();
9086 tcg_res
[1] = tcg_temp_new_i64();
9088 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9089 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9090 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9095 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9098 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9101 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9104 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9109 /* B* ops need res loaded to operate on */
9110 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9115 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9117 case 1: /* BSL bitwise select */
9118 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9119 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9120 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9122 case 2: /* BIT, bitwise insert if true */
9123 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9124 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9125 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9127 case 3: /* BIF, bitwise insert if false */
9128 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9129 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9130 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9136 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9138 tcg_gen_movi_i64(tcg_res
[1], 0);
9140 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9142 tcg_temp_free_i64(tcg_op1
);
9143 tcg_temp_free_i64(tcg_op2
);
9144 tcg_temp_free_i64(tcg_res
[0]);
9145 tcg_temp_free_i64(tcg_res
[1]);
9148 /* Helper functions for 32 bit comparisons */
9149 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9151 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9154 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9156 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9159 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9161 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9164 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9166 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9169 /* Pairwise op subgroup of C3.6.16.
9171 * This is called directly or via the handle_3same_float for float pairwise
9172 * operations where the opcode and size are calculated differently.
9174 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9175 int size
, int rn
, int rm
, int rd
)
9180 /* Floating point operations need fpst */
9181 if (opcode
>= 0x58) {
9182 fpst
= get_fpstatus_ptr();
9184 TCGV_UNUSED_PTR(fpst
);
9187 if (!fp_access_check(s
)) {
9191 /* These operations work on the concatenated rm:rn, with each pair of
9192 * adjacent elements being operated on to produce an element in the result.
9195 TCGv_i64 tcg_res
[2];
9197 for (pass
= 0; pass
< 2; pass
++) {
9198 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9199 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9200 int passreg
= (pass
== 0) ? rn
: rm
;
9202 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9203 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9204 tcg_res
[pass
] = tcg_temp_new_i64();
9207 case 0x17: /* ADDP */
9208 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9210 case 0x58: /* FMAXNMP */
9211 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9213 case 0x5a: /* FADDP */
9214 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9216 case 0x5e: /* FMAXP */
9217 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9219 case 0x78: /* FMINNMP */
9220 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9222 case 0x7e: /* FMINP */
9223 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9226 g_assert_not_reached();
9229 tcg_temp_free_i64(tcg_op1
);
9230 tcg_temp_free_i64(tcg_op2
);
9233 for (pass
= 0; pass
< 2; pass
++) {
9234 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9235 tcg_temp_free_i64(tcg_res
[pass
]);
9238 int maxpass
= is_q
? 4 : 2;
9239 TCGv_i32 tcg_res
[4];
9241 for (pass
= 0; pass
< maxpass
; pass
++) {
9242 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9243 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9244 NeonGenTwoOpFn
*genfn
= NULL
;
9245 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9246 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9248 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9249 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9250 tcg_res
[pass
] = tcg_temp_new_i32();
9253 case 0x17: /* ADDP */
9255 static NeonGenTwoOpFn
* const fns
[3] = {
9256 gen_helper_neon_padd_u8
,
9257 gen_helper_neon_padd_u16
,
9263 case 0x14: /* SMAXP, UMAXP */
9265 static NeonGenTwoOpFn
* const fns
[3][2] = {
9266 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9267 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9268 { gen_max_s32
, gen_max_u32
},
9270 genfn
= fns
[size
][u
];
9273 case 0x15: /* SMINP, UMINP */
9275 static NeonGenTwoOpFn
* const fns
[3][2] = {
9276 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9277 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9278 { gen_min_s32
, gen_min_u32
},
9280 genfn
= fns
[size
][u
];
9283 /* The FP operations are all on single floats (32 bit) */
9284 case 0x58: /* FMAXNMP */
9285 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9287 case 0x5a: /* FADDP */
9288 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9290 case 0x5e: /* FMAXP */
9291 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9293 case 0x78: /* FMINNMP */
9294 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9296 case 0x7e: /* FMINP */
9297 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9300 g_assert_not_reached();
9303 /* FP ops called directly, otherwise call now */
9305 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9308 tcg_temp_free_i32(tcg_op1
);
9309 tcg_temp_free_i32(tcg_op2
);
9312 for (pass
= 0; pass
< maxpass
; pass
++) {
9313 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9314 tcg_temp_free_i32(tcg_res
[pass
]);
9317 clear_vec_high(s
, rd
);
9321 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9322 tcg_temp_free_ptr(fpst
);
9326 /* Floating point op subgroup of C3.6.16. */
9327 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9329 /* For floating point ops, the U, size[1] and opcode bits
9330 * together indicate the operation. size[0] indicates single
9333 int fpopcode
= extract32(insn
, 11, 5)
9334 | (extract32(insn
, 23, 1) << 5)
9335 | (extract32(insn
, 29, 1) << 6);
9336 int is_q
= extract32(insn
, 30, 1);
9337 int size
= extract32(insn
, 22, 1);
9338 int rm
= extract32(insn
, 16, 5);
9339 int rn
= extract32(insn
, 5, 5);
9340 int rd
= extract32(insn
, 0, 5);
9342 int datasize
= is_q
? 128 : 64;
9343 int esize
= 32 << size
;
9344 int elements
= datasize
/ esize
;
9346 if (size
== 1 && !is_q
) {
9347 unallocated_encoding(s
);
9352 case 0x58: /* FMAXNMP */
9353 case 0x5a: /* FADDP */
9354 case 0x5e: /* FMAXP */
9355 case 0x78: /* FMINNMP */
9356 case 0x7e: /* FMINP */
9357 if (size
&& !is_q
) {
9358 unallocated_encoding(s
);
9361 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9364 case 0x1b: /* FMULX */
9365 case 0x1f: /* FRECPS */
9366 case 0x3f: /* FRSQRTS */
9367 case 0x5d: /* FACGE */
9368 case 0x7d: /* FACGT */
9369 case 0x19: /* FMLA */
9370 case 0x39: /* FMLS */
9371 case 0x18: /* FMAXNM */
9372 case 0x1a: /* FADD */
9373 case 0x1c: /* FCMEQ */
9374 case 0x1e: /* FMAX */
9375 case 0x38: /* FMINNM */
9376 case 0x3a: /* FSUB */
9377 case 0x3e: /* FMIN */
9378 case 0x5b: /* FMUL */
9379 case 0x5c: /* FCMGE */
9380 case 0x5f: /* FDIV */
9381 case 0x7a: /* FABD */
9382 case 0x7c: /* FCMGT */
9383 if (!fp_access_check(s
)) {
9387 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9390 unallocated_encoding(s
);
9395 /* Integer op subgroup of C3.6.16. */
9396 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9398 int is_q
= extract32(insn
, 30, 1);
9399 int u
= extract32(insn
, 29, 1);
9400 int size
= extract32(insn
, 22, 2);
9401 int opcode
= extract32(insn
, 11, 5);
9402 int rm
= extract32(insn
, 16, 5);
9403 int rn
= extract32(insn
, 5, 5);
9404 int rd
= extract32(insn
, 0, 5);
9408 case 0x13: /* MUL, PMUL */
9409 if (u
&& size
!= 0) {
9410 unallocated_encoding(s
);
9414 case 0x0: /* SHADD, UHADD */
9415 case 0x2: /* SRHADD, URHADD */
9416 case 0x4: /* SHSUB, UHSUB */
9417 case 0xc: /* SMAX, UMAX */
9418 case 0xd: /* SMIN, UMIN */
9419 case 0xe: /* SABD, UABD */
9420 case 0xf: /* SABA, UABA */
9421 case 0x12: /* MLA, MLS */
9423 unallocated_encoding(s
);
9427 case 0x16: /* SQDMULH, SQRDMULH */
9428 if (size
== 0 || size
== 3) {
9429 unallocated_encoding(s
);
9434 if (size
== 3 && !is_q
) {
9435 unallocated_encoding(s
);
9441 if (!fp_access_check(s
)) {
9447 for (pass
= 0; pass
< 2; pass
++) {
9448 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9449 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9450 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9452 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9453 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9455 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9457 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9459 tcg_temp_free_i64(tcg_res
);
9460 tcg_temp_free_i64(tcg_op1
);
9461 tcg_temp_free_i64(tcg_op2
);
9464 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9465 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9466 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9467 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9468 NeonGenTwoOpFn
*genfn
= NULL
;
9469 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9471 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9472 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9475 case 0x0: /* SHADD, UHADD */
9477 static NeonGenTwoOpFn
* const fns
[3][2] = {
9478 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9479 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9480 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9482 genfn
= fns
[size
][u
];
9485 case 0x1: /* SQADD, UQADD */
9487 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9488 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9489 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9490 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9492 genenvfn
= fns
[size
][u
];
9495 case 0x2: /* SRHADD, URHADD */
9497 static NeonGenTwoOpFn
* const fns
[3][2] = {
9498 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9499 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9500 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9502 genfn
= fns
[size
][u
];
9505 case 0x4: /* SHSUB, UHSUB */
9507 static NeonGenTwoOpFn
* const fns
[3][2] = {
9508 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9509 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9510 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9512 genfn
= fns
[size
][u
];
9515 case 0x5: /* SQSUB, UQSUB */
9517 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9518 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9519 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9520 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9522 genenvfn
= fns
[size
][u
];
9525 case 0x6: /* CMGT, CMHI */
9527 static NeonGenTwoOpFn
* const fns
[3][2] = {
9528 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9529 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9530 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9532 genfn
= fns
[size
][u
];
9535 case 0x7: /* CMGE, CMHS */
9537 static NeonGenTwoOpFn
* const fns
[3][2] = {
9538 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9539 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9540 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9542 genfn
= fns
[size
][u
];
9545 case 0x8: /* SSHL, USHL */
9547 static NeonGenTwoOpFn
* const fns
[3][2] = {
9548 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9549 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9550 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9552 genfn
= fns
[size
][u
];
9555 case 0x9: /* SQSHL, UQSHL */
9557 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9558 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9559 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9560 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9562 genenvfn
= fns
[size
][u
];
9565 case 0xa: /* SRSHL, URSHL */
9567 static NeonGenTwoOpFn
* const fns
[3][2] = {
9568 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9569 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9570 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9572 genfn
= fns
[size
][u
];
9575 case 0xb: /* SQRSHL, UQRSHL */
9577 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9578 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9579 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9580 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9582 genenvfn
= fns
[size
][u
];
9585 case 0xc: /* SMAX, UMAX */
9587 static NeonGenTwoOpFn
* const fns
[3][2] = {
9588 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9589 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9590 { gen_max_s32
, gen_max_u32
},
9592 genfn
= fns
[size
][u
];
9596 case 0xd: /* SMIN, UMIN */
9598 static NeonGenTwoOpFn
* const fns
[3][2] = {
9599 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9600 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9601 { gen_min_s32
, gen_min_u32
},
9603 genfn
= fns
[size
][u
];
9606 case 0xe: /* SABD, UABD */
9607 case 0xf: /* SABA, UABA */
9609 static NeonGenTwoOpFn
* const fns
[3][2] = {
9610 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9611 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9612 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9614 genfn
= fns
[size
][u
];
9617 case 0x10: /* ADD, SUB */
9619 static NeonGenTwoOpFn
* const fns
[3][2] = {
9620 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9621 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9622 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9624 genfn
= fns
[size
][u
];
9627 case 0x11: /* CMTST, CMEQ */
9629 static NeonGenTwoOpFn
* const fns
[3][2] = {
9630 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9631 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9632 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9634 genfn
= fns
[size
][u
];
9637 case 0x13: /* MUL, PMUL */
9641 genfn
= gen_helper_neon_mul_p8
;
9644 /* fall through : MUL */
9645 case 0x12: /* MLA, MLS */
9647 static NeonGenTwoOpFn
* const fns
[3] = {
9648 gen_helper_neon_mul_u8
,
9649 gen_helper_neon_mul_u16
,
9655 case 0x16: /* SQDMULH, SQRDMULH */
9657 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9658 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9659 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9661 assert(size
== 1 || size
== 2);
9662 genenvfn
= fns
[size
- 1][u
];
9666 g_assert_not_reached();
9670 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9672 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9675 if (opcode
== 0xf || opcode
== 0x12) {
9676 /* SABA, UABA, MLA, MLS: accumulating ops */
9677 static NeonGenTwoOpFn
* const fns
[3][2] = {
9678 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9679 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9680 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9682 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9684 genfn
= fns
[size
][is_sub
];
9685 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9686 genfn(tcg_res
, tcg_op1
, tcg_res
);
9689 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9691 tcg_temp_free_i32(tcg_res
);
9692 tcg_temp_free_i32(tcg_op1
);
9693 tcg_temp_free_i32(tcg_op2
);
9698 clear_vec_high(s
, rd
);
9702 /* C3.6.16 AdvSIMD three same
9703 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9704 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9705 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9706 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9708 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9710 int opcode
= extract32(insn
, 11, 5);
9713 case 0x3: /* logic ops */
9714 disas_simd_3same_logic(s
, insn
);
9716 case 0x17: /* ADDP */
9717 case 0x14: /* SMAXP, UMAXP */
9718 case 0x15: /* SMINP, UMINP */
9720 /* Pairwise operations */
9721 int is_q
= extract32(insn
, 30, 1);
9722 int u
= extract32(insn
, 29, 1);
9723 int size
= extract32(insn
, 22, 2);
9724 int rm
= extract32(insn
, 16, 5);
9725 int rn
= extract32(insn
, 5, 5);
9726 int rd
= extract32(insn
, 0, 5);
9727 if (opcode
== 0x17) {
9728 if (u
|| (size
== 3 && !is_q
)) {
9729 unallocated_encoding(s
);
9734 unallocated_encoding(s
);
9738 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9742 /* floating point ops, sz[1] and U are part of opcode */
9743 disas_simd_3same_float(s
, insn
);
9746 disas_simd_3same_int(s
, insn
);
9751 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9752 int size
, int rn
, int rd
)
9754 /* Handle 2-reg-misc ops which are widening (so each size element
9755 * in the source becomes a 2*size element in the destination.
9756 * The only instruction like this is FCVTL.
9761 /* 32 -> 64 bit fp conversion */
9762 TCGv_i64 tcg_res
[2];
9763 int srcelt
= is_q
? 2 : 0;
9765 for (pass
= 0; pass
< 2; pass
++) {
9766 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9767 tcg_res
[pass
] = tcg_temp_new_i64();
9769 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9770 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9771 tcg_temp_free_i32(tcg_op
);
9773 for (pass
= 0; pass
< 2; pass
++) {
9774 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9775 tcg_temp_free_i64(tcg_res
[pass
]);
9778 /* 16 -> 32 bit fp conversion */
9779 int srcelt
= is_q
? 4 : 0;
9780 TCGv_i32 tcg_res
[4];
9782 for (pass
= 0; pass
< 4; pass
++) {
9783 tcg_res
[pass
] = tcg_temp_new_i32();
9785 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9786 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9789 for (pass
= 0; pass
< 4; pass
++) {
9790 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9791 tcg_temp_free_i32(tcg_res
[pass
]);
9796 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9797 bool is_q
, int size
, int rn
, int rd
)
9799 int op
= (opcode
<< 1) | u
;
9800 int opsz
= op
+ size
;
9801 int grp_size
= 3 - opsz
;
9802 int dsize
= is_q
? 128 : 64;
9806 unallocated_encoding(s
);
9810 if (!fp_access_check(s
)) {
9815 /* Special case bytes, use bswap op on each group of elements */
9816 int groups
= dsize
/ (8 << grp_size
);
9818 for (i
= 0; i
< groups
; i
++) {
9819 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9821 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9824 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9827 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9830 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9833 g_assert_not_reached();
9835 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9836 tcg_temp_free_i64(tcg_tmp
);
9839 clear_vec_high(s
, rd
);
9842 int revmask
= (1 << grp_size
) - 1;
9843 int esize
= 8 << size
;
9844 int elements
= dsize
/ esize
;
9845 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9846 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9847 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9849 for (i
= 0; i
< elements
; i
++) {
9850 int e_rev
= (i
& 0xf) ^ revmask
;
9851 int off
= e_rev
* esize
;
9852 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9854 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9855 tcg_rn
, off
- 64, esize
);
9857 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9860 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9861 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9863 tcg_temp_free_i64(tcg_rd_hi
);
9864 tcg_temp_free_i64(tcg_rd
);
9865 tcg_temp_free_i64(tcg_rn
);
9869 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9870 bool is_q
, int size
, int rn
, int rd
)
9872 /* Implement the pairwise operations from 2-misc:
9873 * SADDLP, UADDLP, SADALP, UADALP.
9874 * These all add pairs of elements in the input to produce a
9875 * double-width result element in the output (possibly accumulating).
9877 bool accum
= (opcode
== 0x6);
9878 int maxpass
= is_q
? 2 : 1;
9880 TCGv_i64 tcg_res
[2];
9883 /* 32 + 32 -> 64 op */
9884 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9886 for (pass
= 0; pass
< maxpass
; pass
++) {
9887 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9888 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9890 tcg_res
[pass
] = tcg_temp_new_i64();
9892 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9893 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9894 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9896 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9897 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9900 tcg_temp_free_i64(tcg_op1
);
9901 tcg_temp_free_i64(tcg_op2
);
9904 for (pass
= 0; pass
< maxpass
; pass
++) {
9905 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9906 NeonGenOneOpFn
*genfn
;
9907 static NeonGenOneOpFn
* const fns
[2][2] = {
9908 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9909 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9912 genfn
= fns
[size
][u
];
9914 tcg_res
[pass
] = tcg_temp_new_i64();
9916 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9917 genfn(tcg_res
[pass
], tcg_op
);
9920 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9922 gen_helper_neon_addl_u16(tcg_res
[pass
],
9923 tcg_res
[pass
], tcg_op
);
9925 gen_helper_neon_addl_u32(tcg_res
[pass
],
9926 tcg_res
[pass
], tcg_op
);
9929 tcg_temp_free_i64(tcg_op
);
9933 tcg_res
[1] = tcg_const_i64(0);
9935 for (pass
= 0; pass
< 2; pass
++) {
9936 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9937 tcg_temp_free_i64(tcg_res
[pass
]);
9941 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9943 /* Implement SHLL and SHLL2 */
9945 int part
= is_q
? 2 : 0;
9946 TCGv_i64 tcg_res
[2];
9948 for (pass
= 0; pass
< 2; pass
++) {
9949 static NeonGenWidenFn
* const widenfns
[3] = {
9950 gen_helper_neon_widen_u8
,
9951 gen_helper_neon_widen_u16
,
9952 tcg_gen_extu_i32_i64
,
9954 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9955 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9957 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9958 tcg_res
[pass
] = tcg_temp_new_i64();
9959 widenfn(tcg_res
[pass
], tcg_op
);
9960 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9962 tcg_temp_free_i32(tcg_op
);
9965 for (pass
= 0; pass
< 2; pass
++) {
9966 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9967 tcg_temp_free_i64(tcg_res
[pass
]);
9971 /* C3.6.17 AdvSIMD two reg misc
9972 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9973 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9974 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9975 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9977 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9979 int size
= extract32(insn
, 22, 2);
9980 int opcode
= extract32(insn
, 12, 5);
9981 bool u
= extract32(insn
, 29, 1);
9982 bool is_q
= extract32(insn
, 30, 1);
9983 int rn
= extract32(insn
, 5, 5);
9984 int rd
= extract32(insn
, 0, 5);
9985 bool need_fpstatus
= false;
9986 bool need_rmode
= false;
9989 TCGv_ptr tcg_fpstatus
;
9992 case 0x0: /* REV64, REV32 */
9993 case 0x1: /* REV16 */
9994 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9996 case 0x5: /* CNT, NOT, RBIT */
9997 if (u
&& size
== 0) {
9998 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
10001 } else if (u
&& size
== 1) {
10004 } else if (!u
&& size
== 0) {
10008 unallocated_encoding(s
);
10010 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
10011 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
10013 unallocated_encoding(s
);
10016 if (!fp_access_check(s
)) {
10020 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
10022 case 0x4: /* CLS, CLZ */
10024 unallocated_encoding(s
);
10028 case 0x2: /* SADDLP, UADDLP */
10029 case 0x6: /* SADALP, UADALP */
10031 unallocated_encoding(s
);
10034 if (!fp_access_check(s
)) {
10037 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
10039 case 0x13: /* SHLL, SHLL2 */
10040 if (u
== 0 || size
== 3) {
10041 unallocated_encoding(s
);
10044 if (!fp_access_check(s
)) {
10047 handle_shll(s
, is_q
, size
, rn
, rd
);
10049 case 0xa: /* CMLT */
10051 unallocated_encoding(s
);
10055 case 0x8: /* CMGT, CMGE */
10056 case 0x9: /* CMEQ, CMLE */
10057 case 0xb: /* ABS, NEG */
10058 if (size
== 3 && !is_q
) {
10059 unallocated_encoding(s
);
10063 case 0x3: /* SUQADD, USQADD */
10064 if (size
== 3 && !is_q
) {
10065 unallocated_encoding(s
);
10068 if (!fp_access_check(s
)) {
10071 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10073 case 0x7: /* SQABS, SQNEG */
10074 if (size
== 3 && !is_q
) {
10075 unallocated_encoding(s
);
10080 case 0x16 ... 0x1d:
10083 /* Floating point: U, size[1] and opcode indicate operation;
10084 * size[0] indicates single or double precision.
10086 int is_double
= extract32(size
, 0, 1);
10087 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10088 size
= is_double
? 3 : 2;
10090 case 0x2f: /* FABS */
10091 case 0x6f: /* FNEG */
10092 if (size
== 3 && !is_q
) {
10093 unallocated_encoding(s
);
10097 case 0x1d: /* SCVTF */
10098 case 0x5d: /* UCVTF */
10100 bool is_signed
= (opcode
== 0x1d) ? true : false;
10101 int elements
= is_double
? 2 : is_q
? 4 : 2;
10102 if (is_double
&& !is_q
) {
10103 unallocated_encoding(s
);
10106 if (!fp_access_check(s
)) {
10109 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10112 case 0x2c: /* FCMGT (zero) */
10113 case 0x2d: /* FCMEQ (zero) */
10114 case 0x2e: /* FCMLT (zero) */
10115 case 0x6c: /* FCMGE (zero) */
10116 case 0x6d: /* FCMLE (zero) */
10117 if (size
== 3 && !is_q
) {
10118 unallocated_encoding(s
);
10121 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10123 case 0x7f: /* FSQRT */
10124 if (size
== 3 && !is_q
) {
10125 unallocated_encoding(s
);
10129 case 0x1a: /* FCVTNS */
10130 case 0x1b: /* FCVTMS */
10131 case 0x3a: /* FCVTPS */
10132 case 0x3b: /* FCVTZS */
10133 case 0x5a: /* FCVTNU */
10134 case 0x5b: /* FCVTMU */
10135 case 0x7a: /* FCVTPU */
10136 case 0x7b: /* FCVTZU */
10137 need_fpstatus
= true;
10139 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10140 if (size
== 3 && !is_q
) {
10141 unallocated_encoding(s
);
10145 case 0x5c: /* FCVTAU */
10146 case 0x1c: /* FCVTAS */
10147 need_fpstatus
= true;
10149 rmode
= FPROUNDING_TIEAWAY
;
10150 if (size
== 3 && !is_q
) {
10151 unallocated_encoding(s
);
10155 case 0x3c: /* URECPE */
10157 unallocated_encoding(s
);
10161 case 0x3d: /* FRECPE */
10162 case 0x7d: /* FRSQRTE */
10163 if (size
== 3 && !is_q
) {
10164 unallocated_encoding(s
);
10167 if (!fp_access_check(s
)) {
10170 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10172 case 0x56: /* FCVTXN, FCVTXN2 */
10174 unallocated_encoding(s
);
10178 case 0x16: /* FCVTN, FCVTN2 */
10179 /* handle_2misc_narrow does a 2*size -> size operation, but these
10180 * instructions encode the source size rather than dest size.
10182 if (!fp_access_check(s
)) {
10185 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10187 case 0x17: /* FCVTL, FCVTL2 */
10188 if (!fp_access_check(s
)) {
10191 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10193 case 0x18: /* FRINTN */
10194 case 0x19: /* FRINTM */
10195 case 0x38: /* FRINTP */
10196 case 0x39: /* FRINTZ */
10198 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10200 case 0x59: /* FRINTX */
10201 case 0x79: /* FRINTI */
10202 need_fpstatus
= true;
10203 if (size
== 3 && !is_q
) {
10204 unallocated_encoding(s
);
10208 case 0x58: /* FRINTA */
10210 rmode
= FPROUNDING_TIEAWAY
;
10211 need_fpstatus
= true;
10212 if (size
== 3 && !is_q
) {
10213 unallocated_encoding(s
);
10217 case 0x7c: /* URSQRTE */
10219 unallocated_encoding(s
);
10222 need_fpstatus
= true;
10225 unallocated_encoding(s
);
10231 unallocated_encoding(s
);
10235 if (!fp_access_check(s
)) {
10239 if (need_fpstatus
) {
10240 tcg_fpstatus
= get_fpstatus_ptr();
10242 TCGV_UNUSED_PTR(tcg_fpstatus
);
10245 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10246 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10248 TCGV_UNUSED_I32(tcg_rmode
);
10252 /* All 64-bit element operations can be shared with scalar 2misc */
10255 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10256 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10257 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10259 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10261 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10262 tcg_rmode
, tcg_fpstatus
);
10264 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10266 tcg_temp_free_i64(tcg_res
);
10267 tcg_temp_free_i64(tcg_op
);
10272 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10273 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10274 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10277 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10280 /* Special cases for 32 bit elements */
10282 case 0xa: /* CMLT */
10283 /* 32 bit integer comparison against zero, result is
10284 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10287 cond
= TCG_COND_LT
;
10289 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10290 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10292 case 0x8: /* CMGT, CMGE */
10293 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10295 case 0x9: /* CMEQ, CMLE */
10296 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10298 case 0x4: /* CLS */
10300 gen_helper_clz32(tcg_res
, tcg_op
);
10302 gen_helper_cls32(tcg_res
, tcg_op
);
10305 case 0x7: /* SQABS, SQNEG */
10307 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10309 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10312 case 0xb: /* ABS, NEG */
10314 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10316 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10317 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10318 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10319 tcg_zero
, tcg_op
, tcg_res
);
10320 tcg_temp_free_i32(tcg_zero
);
10323 case 0x2f: /* FABS */
10324 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10326 case 0x6f: /* FNEG */
10327 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10329 case 0x7f: /* FSQRT */
10330 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10332 case 0x1a: /* FCVTNS */
10333 case 0x1b: /* FCVTMS */
10334 case 0x1c: /* FCVTAS */
10335 case 0x3a: /* FCVTPS */
10336 case 0x3b: /* FCVTZS */
10338 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10339 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10340 tcg_shift
, tcg_fpstatus
);
10341 tcg_temp_free_i32(tcg_shift
);
10344 case 0x5a: /* FCVTNU */
10345 case 0x5b: /* FCVTMU */
10346 case 0x5c: /* FCVTAU */
10347 case 0x7a: /* FCVTPU */
10348 case 0x7b: /* FCVTZU */
10350 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10351 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10352 tcg_shift
, tcg_fpstatus
);
10353 tcg_temp_free_i32(tcg_shift
);
10356 case 0x18: /* FRINTN */
10357 case 0x19: /* FRINTM */
10358 case 0x38: /* FRINTP */
10359 case 0x39: /* FRINTZ */
10360 case 0x58: /* FRINTA */
10361 case 0x79: /* FRINTI */
10362 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10364 case 0x59: /* FRINTX */
10365 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10367 case 0x7c: /* URSQRTE */
10368 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10371 g_assert_not_reached();
10374 /* Use helpers for 8 and 16 bit elements */
10376 case 0x5: /* CNT, RBIT */
10377 /* For these two insns size is part of the opcode specifier
10378 * (handled earlier); they always operate on byte elements.
10381 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10383 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10386 case 0x7: /* SQABS, SQNEG */
10388 NeonGenOneOpEnvFn
*genfn
;
10389 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10390 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10391 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10393 genfn
= fns
[size
][u
];
10394 genfn(tcg_res
, cpu_env
, tcg_op
);
10397 case 0x8: /* CMGT, CMGE */
10398 case 0x9: /* CMEQ, CMLE */
10399 case 0xa: /* CMLT */
10401 static NeonGenTwoOpFn
* const fns
[3][2] = {
10402 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10403 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10404 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10406 NeonGenTwoOpFn
*genfn
;
10409 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10411 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10412 comp
= (opcode
- 0x8) * 2 + u
;
10413 /* ...but LE, LT are implemented as reverse GE, GT */
10414 reverse
= (comp
> 2);
10418 genfn
= fns
[comp
][size
];
10420 genfn(tcg_res
, tcg_zero
, tcg_op
);
10422 genfn(tcg_res
, tcg_op
, tcg_zero
);
10424 tcg_temp_free_i32(tcg_zero
);
10427 case 0xb: /* ABS, NEG */
10429 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10431 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10433 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10435 tcg_temp_free_i32(tcg_zero
);
10438 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10440 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10444 case 0x4: /* CLS, CLZ */
10447 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10449 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10453 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10455 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10460 g_assert_not_reached();
10464 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10466 tcg_temp_free_i32(tcg_res
);
10467 tcg_temp_free_i32(tcg_op
);
10471 clear_vec_high(s
, rd
);
10475 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10476 tcg_temp_free_i32(tcg_rmode
);
10478 if (need_fpstatus
) {
10479 tcg_temp_free_ptr(tcg_fpstatus
);
10483 /* C3.6.13 AdvSIMD scalar x indexed element
10484 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10485 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10486 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10487 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10488 * C3.6.18 AdvSIMD vector x indexed element
10489 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10490 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10491 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10492 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10494 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10496 /* This encoding has two kinds of instruction:
10497 * normal, where we perform elt x idxelt => elt for each
10498 * element in the vector
10499 * long, where we perform elt x idxelt and generate a result of
10500 * double the width of the input element
10501 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10503 bool is_scalar
= extract32(insn
, 28, 1);
10504 bool is_q
= extract32(insn
, 30, 1);
10505 bool u
= extract32(insn
, 29, 1);
10506 int size
= extract32(insn
, 22, 2);
10507 int l
= extract32(insn
, 21, 1);
10508 int m
= extract32(insn
, 20, 1);
10509 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10510 int rm
= extract32(insn
, 16, 4);
10511 int opcode
= extract32(insn
, 12, 4);
10512 int h
= extract32(insn
, 11, 1);
10513 int rn
= extract32(insn
, 5, 5);
10514 int rd
= extract32(insn
, 0, 5);
10515 bool is_long
= false;
10516 bool is_fp
= false;
10521 case 0x0: /* MLA */
10522 case 0x4: /* MLS */
10523 if (!u
|| is_scalar
) {
10524 unallocated_encoding(s
);
10528 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10529 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10530 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10532 unallocated_encoding(s
);
10537 case 0x3: /* SQDMLAL, SQDMLAL2 */
10538 case 0x7: /* SQDMLSL, SQDMLSL2 */
10539 case 0xb: /* SQDMULL, SQDMULL2 */
10542 case 0xc: /* SQDMULH */
10543 case 0xd: /* SQRDMULH */
10545 unallocated_encoding(s
);
10549 case 0x8: /* MUL */
10550 if (u
|| is_scalar
) {
10551 unallocated_encoding(s
);
10555 case 0x1: /* FMLA */
10556 case 0x5: /* FMLS */
10558 unallocated_encoding(s
);
10562 case 0x9: /* FMUL, FMULX */
10563 if (!extract32(size
, 1, 1)) {
10564 unallocated_encoding(s
);
10570 unallocated_encoding(s
);
10575 /* low bit of size indicates single/double */
10576 size
= extract32(size
, 0, 1) ? 3 : 2;
10578 index
= h
<< 1 | l
;
10581 unallocated_encoding(s
);
10590 index
= h
<< 2 | l
<< 1 | m
;
10593 index
= h
<< 1 | l
;
10597 unallocated_encoding(s
);
10602 if (!fp_access_check(s
)) {
10607 fpst
= get_fpstatus_ptr();
10609 TCGV_UNUSED_PTR(fpst
);
10613 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10616 assert(is_fp
&& is_q
&& !is_long
);
10618 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10620 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10621 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10622 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10624 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10627 case 0x5: /* FMLS */
10628 /* As usual for ARM, separate negation for fused multiply-add */
10629 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10631 case 0x1: /* FMLA */
10632 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10633 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10635 case 0x9: /* FMUL, FMULX */
10637 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10639 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10643 g_assert_not_reached();
10646 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10647 tcg_temp_free_i64(tcg_op
);
10648 tcg_temp_free_i64(tcg_res
);
10652 clear_vec_high(s
, rd
);
10655 tcg_temp_free_i64(tcg_idx
);
10656 } else if (!is_long
) {
10657 /* 32 bit floating point, or 16 or 32 bit integer.
10658 * For the 16 bit scalar case we use the usual Neon helpers and
10659 * rely on the fact that 0 op 0 == 0 with no side effects.
10661 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10662 int pass
, maxpasses
;
10667 maxpasses
= is_q
? 4 : 2;
10670 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10672 if (size
== 1 && !is_scalar
) {
10673 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10674 * the index into both halves of the 32 bit tcg_idx and then use
10675 * the usual Neon helpers.
10677 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10680 for (pass
= 0; pass
< maxpasses
; pass
++) {
10681 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10682 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10684 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10687 case 0x0: /* MLA */
10688 case 0x4: /* MLS */
10689 case 0x8: /* MUL */
10691 static NeonGenTwoOpFn
* const fns
[2][2] = {
10692 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10693 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10695 NeonGenTwoOpFn
*genfn
;
10696 bool is_sub
= opcode
== 0x4;
10699 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10701 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10703 if (opcode
== 0x8) {
10706 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10707 genfn
= fns
[size
- 1][is_sub
];
10708 genfn(tcg_res
, tcg_op
, tcg_res
);
10711 case 0x5: /* FMLS */
10712 /* As usual for ARM, separate negation for fused multiply-add */
10713 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10715 case 0x1: /* FMLA */
10716 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10717 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10719 case 0x9: /* FMUL, FMULX */
10721 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10723 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10726 case 0xc: /* SQDMULH */
10728 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10731 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10735 case 0xd: /* SQRDMULH */
10737 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10740 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10745 g_assert_not_reached();
10749 write_fp_sreg(s
, rd
, tcg_res
);
10751 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10754 tcg_temp_free_i32(tcg_op
);
10755 tcg_temp_free_i32(tcg_res
);
10758 tcg_temp_free_i32(tcg_idx
);
10761 clear_vec_high(s
, rd
);
10764 /* long ops: 16x16->32 or 32x32->64 */
10765 TCGv_i64 tcg_res
[2];
10767 bool satop
= extract32(opcode
, 0, 1);
10768 TCGMemOp memop
= MO_32
;
10775 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10777 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10779 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10780 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10781 TCGv_i64 tcg_passres
;
10787 passelt
= pass
+ (is_q
* 2);
10790 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10792 tcg_res
[pass
] = tcg_temp_new_i64();
10794 if (opcode
== 0xa || opcode
== 0xb) {
10795 /* Non-accumulating ops */
10796 tcg_passres
= tcg_res
[pass
];
10798 tcg_passres
= tcg_temp_new_i64();
10801 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10802 tcg_temp_free_i64(tcg_op
);
10805 /* saturating, doubling */
10806 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10807 tcg_passres
, tcg_passres
);
10810 if (opcode
== 0xa || opcode
== 0xb) {
10814 /* Accumulating op: handle accumulate step */
10815 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10818 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10819 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10821 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10822 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10824 case 0x7: /* SQDMLSL, SQDMLSL2 */
10825 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10827 case 0x3: /* SQDMLAL, SQDMLAL2 */
10828 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10833 g_assert_not_reached();
10835 tcg_temp_free_i64(tcg_passres
);
10837 tcg_temp_free_i64(tcg_idx
);
10840 clear_vec_high(s
, rd
);
10843 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10846 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10849 /* The simplest way to handle the 16x16 indexed ops is to
10850 * duplicate the index into both halves of the 32 bit tcg_idx
10851 * and then use the usual Neon helpers.
10853 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10856 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10857 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10858 TCGv_i64 tcg_passres
;
10861 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10863 read_vec_element_i32(s
, tcg_op
, rn
,
10864 pass
+ (is_q
* 2), MO_32
);
10867 tcg_res
[pass
] = tcg_temp_new_i64();
10869 if (opcode
== 0xa || opcode
== 0xb) {
10870 /* Non-accumulating ops */
10871 tcg_passres
= tcg_res
[pass
];
10873 tcg_passres
= tcg_temp_new_i64();
10876 if (memop
& MO_SIGN
) {
10877 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10879 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10882 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10883 tcg_passres
, tcg_passres
);
10885 tcg_temp_free_i32(tcg_op
);
10887 if (opcode
== 0xa || opcode
== 0xb) {
10891 /* Accumulating op: handle accumulate step */
10892 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10895 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10896 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10899 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10900 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10903 case 0x7: /* SQDMLSL, SQDMLSL2 */
10904 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10906 case 0x3: /* SQDMLAL, SQDMLAL2 */
10907 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10912 g_assert_not_reached();
10914 tcg_temp_free_i64(tcg_passres
);
10916 tcg_temp_free_i32(tcg_idx
);
10919 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10924 tcg_res
[1] = tcg_const_i64(0);
10927 for (pass
= 0; pass
< 2; pass
++) {
10928 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10929 tcg_temp_free_i64(tcg_res
[pass
]);
10933 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10934 tcg_temp_free_ptr(fpst
);
10938 /* C3.6.19 Crypto AES
10939 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10940 * +-----------------+------+-----------+--------+-----+------+------+
10941 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10942 * +-----------------+------+-----------+--------+-----+------+------+
10944 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10946 int size
= extract32(insn
, 22, 2);
10947 int opcode
= extract32(insn
, 12, 5);
10948 int rn
= extract32(insn
, 5, 5);
10949 int rd
= extract32(insn
, 0, 5);
10951 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10952 CryptoThreeOpEnvFn
*genfn
;
10954 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10956 unallocated_encoding(s
);
10961 case 0x4: /* AESE */
10963 genfn
= gen_helper_crypto_aese
;
10965 case 0x6: /* AESMC */
10967 genfn
= gen_helper_crypto_aesmc
;
10969 case 0x5: /* AESD */
10971 genfn
= gen_helper_crypto_aese
;
10973 case 0x7: /* AESIMC */
10975 genfn
= gen_helper_crypto_aesmc
;
10978 unallocated_encoding(s
);
10982 /* Note that we convert the Vx register indexes into the
10983 * index within the vfp.regs[] array, so we can share the
10984 * helper with the AArch32 instructions.
10986 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10987 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10988 tcg_decrypt
= tcg_const_i32(decrypt
);
10990 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10992 tcg_temp_free_i32(tcg_rd_regno
);
10993 tcg_temp_free_i32(tcg_rn_regno
);
10994 tcg_temp_free_i32(tcg_decrypt
);
10997 /* C3.6.20 Crypto three-reg SHA
10998 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10999 * +-----------------+------+---+------+---+--------+-----+------+------+
11000 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
11001 * +-----------------+------+---+------+---+--------+-----+------+------+
11003 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
11005 int size
= extract32(insn
, 22, 2);
11006 int opcode
= extract32(insn
, 12, 3);
11007 int rm
= extract32(insn
, 16, 5);
11008 int rn
= extract32(insn
, 5, 5);
11009 int rd
= extract32(insn
, 0, 5);
11010 CryptoThreeOpEnvFn
*genfn
;
11011 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
11012 int feature
= ARM_FEATURE_V8_SHA256
;
11015 unallocated_encoding(s
);
11020 case 0: /* SHA1C */
11021 case 1: /* SHA1P */
11022 case 2: /* SHA1M */
11023 case 3: /* SHA1SU0 */
11025 feature
= ARM_FEATURE_V8_SHA1
;
11027 case 4: /* SHA256H */
11028 genfn
= gen_helper_crypto_sha256h
;
11030 case 5: /* SHA256H2 */
11031 genfn
= gen_helper_crypto_sha256h2
;
11033 case 6: /* SHA256SU1 */
11034 genfn
= gen_helper_crypto_sha256su1
;
11037 unallocated_encoding(s
);
11041 if (!arm_dc_feature(s
, feature
)) {
11042 unallocated_encoding(s
);
11046 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11047 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11048 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11051 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11053 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11055 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11056 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11057 tcg_temp_free_i32(tcg_opcode
);
11060 tcg_temp_free_i32(tcg_rd_regno
);
11061 tcg_temp_free_i32(tcg_rn_regno
);
11062 tcg_temp_free_i32(tcg_rm_regno
);
11065 /* C3.6.21 Crypto two-reg SHA
11066 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11067 * +-----------------+------+-----------+--------+-----+------+------+
11068 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11069 * +-----------------+------+-----------+--------+-----+------+------+
11071 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11073 int size
= extract32(insn
, 22, 2);
11074 int opcode
= extract32(insn
, 12, 5);
11075 int rn
= extract32(insn
, 5, 5);
11076 int rd
= extract32(insn
, 0, 5);
11077 CryptoTwoOpEnvFn
*genfn
;
11079 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11082 unallocated_encoding(s
);
11087 case 0: /* SHA1H */
11088 feature
= ARM_FEATURE_V8_SHA1
;
11089 genfn
= gen_helper_crypto_sha1h
;
11091 case 1: /* SHA1SU1 */
11092 feature
= ARM_FEATURE_V8_SHA1
;
11093 genfn
= gen_helper_crypto_sha1su1
;
11095 case 2: /* SHA256SU0 */
11096 feature
= ARM_FEATURE_V8_SHA256
;
11097 genfn
= gen_helper_crypto_sha256su0
;
11100 unallocated_encoding(s
);
11104 if (!arm_dc_feature(s
, feature
)) {
11105 unallocated_encoding(s
);
11109 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11110 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11112 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11114 tcg_temp_free_i32(tcg_rd_regno
);
11115 tcg_temp_free_i32(tcg_rn_regno
);
11118 /* C3.6 Data processing - SIMD, inc Crypto
11120 * As the decode gets a little complex we are using a table based
11121 * approach for this part of the decode.
11123 static const AArch64DecodeTable data_proc_simd
[] = {
11124 /* pattern , mask , fn */
11125 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11126 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11127 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11128 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11129 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11130 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11131 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11132 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11133 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11134 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11135 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11136 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11137 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11138 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11139 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11140 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11141 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11142 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11143 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11144 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11145 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11146 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11147 { 0x00000000, 0x00000000, NULL
}
11150 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11152 /* Note that this is called with all non-FP cases from
11153 * table C3-6 so it must UNDEF for entries not specifically
11154 * allocated to instructions in that table.
11156 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11160 unallocated_encoding(s
);
11164 /* C3.6 Data processing - SIMD and floating point */
11165 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11167 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11168 disas_data_proc_fp(s
, insn
);
11170 /* SIMD, including crypto */
11171 disas_data_proc_simd(s
, insn
);
11175 /* C3.1 A64 instruction index by encoding */
11176 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11180 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11184 s
->fp_access_checked
= false;
11186 switch (extract32(insn
, 25, 4)) {
11187 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11188 unallocated_encoding(s
);
11190 case 0x8: case 0x9: /* Data processing - immediate */
11191 disas_data_proc_imm(s
, insn
);
11193 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11194 disas_b_exc_sys(s
, insn
);
11199 case 0xe: /* Loads and stores */
11200 disas_ldst(s
, insn
);
11203 case 0xd: /* Data processing - register */
11204 disas_data_proc_reg(s
, insn
);
11207 case 0xf: /* Data processing - SIMD and floating point */
11208 disas_data_proc_simd_fp(s
, insn
);
11211 assert(FALSE
); /* all 15 cases should be handled above */
11215 /* if we allocated any temporaries, free them here */
11219 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11221 CPUState
*cs
= CPU(cpu
);
11222 CPUARMState
*env
= &cpu
->env
;
11223 DisasContext dc1
, *dc
= &dc1
;
11224 target_ulong pc_start
;
11225 target_ulong next_page_start
;
11233 dc
->is_jmp
= DISAS_NEXT
;
11235 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11239 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11240 * there is no secure EL1, so we route exceptions to EL3.
11242 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11243 !arm_el_is_aa64(env
, 3);
11246 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11247 dc
->condexec_mask
= 0;
11248 dc
->condexec_cond
= 0;
11249 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11250 dc
->tbi0
= ARM_TBFLAG_TBI0(tb
->flags
);
11251 dc
->tbi1
= ARM_TBFLAG_TBI1(tb
->flags
);
11252 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11253 #if !defined(CONFIG_USER_ONLY)
11254 dc
->user
= (dc
->current_el
== 0);
11256 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11258 dc
->vec_stride
= 0;
11259 dc
->cp_regs
= cpu
->cp_regs
;
11260 dc
->features
= env
->features
;
11262 /* Single step state. The code-generation logic here is:
11264 * generate code with no special handling for single-stepping (except
11265 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11266 * this happens anyway because those changes are all system register or
11268 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11269 * emit code for one insn
11270 * emit code to clear PSTATE.SS
11271 * emit code to generate software step exception for completed step
11272 * end TB (as usual for having generated an exception)
11273 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11274 * emit code to generate a software step exception
11277 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11278 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11279 dc
->is_ldex
= false;
11280 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11282 init_tmp_a64_array(dc
);
11284 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11286 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11287 if (max_insns
== 0) {
11288 max_insns
= CF_COUNT_MASK
;
11290 if (max_insns
> TCG_MAX_INSNS
) {
11291 max_insns
= TCG_MAX_INSNS
;
11296 tcg_clear_temp_count();
11299 dc
->insn_start_idx
= tcg_op_buf_count();
11300 tcg_gen_insn_start(dc
->pc
, 0, 0);
11303 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11305 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11306 if (bp
->pc
== dc
->pc
) {
11307 if (bp
->flags
& BP_CPU
) {
11308 gen_a64_set_pc_im(dc
->pc
);
11309 gen_helper_check_breakpoints(cpu_env
);
11310 /* End the TB early; it likely won't be executed */
11311 dc
->is_jmp
= DISAS_UPDATE
;
11313 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11314 /* The address covered by the breakpoint must be
11315 included in [tb->pc, tb->pc + tb->size) in order
11316 to for it to be properly cleared -- thus we
11317 increment the PC here so that the logic setting
11318 tb->size below does the right thing. */
11320 goto done_generating
;
11327 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11331 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11332 /* Singlestep state is Active-pending.
11333 * If we're in this state at the start of a TB then either
11334 * a) we just took an exception to an EL which is being debugged
11335 * and this is the first insn in the exception handler
11336 * b) debug exceptions were masked and we just unmasked them
11337 * without changing EL (eg by clearing PSTATE.D)
11338 * In either case we're going to take a swstep exception in the
11339 * "did not step an insn" case, and so the syndrome ISV and EX
11340 * bits should be zero.
11342 assert(num_insns
== 1);
11343 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11344 default_exception_el(dc
));
11345 dc
->is_jmp
= DISAS_EXC
;
11349 disas_a64_insn(env
, dc
);
11351 if (tcg_check_temp_count()) {
11352 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11356 /* Translation stops when a conditional branch is encountered.
11357 * Otherwise the subsequent code could get translated several times.
11358 * Also stop translation when a page boundary is reached. This
11359 * ensures prefetch aborts occur at the right place.
11361 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11362 !cs
->singlestep_enabled
&&
11365 dc
->pc
< next_page_start
&&
11366 num_insns
< max_insns
);
11368 if (tb
->cflags
& CF_LAST_IO
) {
11372 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11373 && dc
->is_jmp
!= DISAS_EXC
) {
11374 /* Note that this means single stepping WFI doesn't halt the CPU.
11375 * For conditional branch insns this is harmless unreachable code as
11376 * gen_goto_tb() has already handled emitting the debug exception
11377 * (and thus a tb-jump is not possible when singlestepping).
11379 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11380 if (dc
->is_jmp
!= DISAS_JUMP
) {
11381 gen_a64_set_pc_im(dc
->pc
);
11383 if (cs
->singlestep_enabled
) {
11384 gen_exception_internal(EXCP_DEBUG
);
11386 gen_step_complete_exception(dc
);
11389 switch (dc
->is_jmp
) {
11391 gen_goto_tb(dc
, 1, dc
->pc
);
11395 gen_a64_set_pc_im(dc
->pc
);
11398 /* indicate that the hash table must be used to find the next TB */
11399 tcg_gen_exit_tb(0);
11401 case DISAS_TB_JUMP
:
11406 gen_a64_set_pc_im(dc
->pc
);
11407 gen_helper_wfe(cpu_env
);
11410 gen_a64_set_pc_im(dc
->pc
);
11411 gen_helper_yield(cpu_env
);
11414 /* This is a special case because we don't want to just halt the CPU
11415 * if trying to debug across a WFI.
11417 gen_a64_set_pc_im(dc
->pc
);
11418 gen_helper_wfi(cpu_env
);
11419 /* The helper doesn't necessarily throw an exception, but we
11420 * must go back to the main loop to check for interrupts anyway.
11422 tcg_gen_exit_tb(0);
11428 gen_tb_end(tb
, num_insns
);
11431 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
11432 qemu_log_in_addr_range(pc_start
)) {
11433 qemu_log("----------------\n");
11434 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11435 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11436 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11440 tb
->size
= dc
->pc
- pc_start
;
11441 tb
->icount
= num_insns
;