hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "msix.h"
  30
  31 //#define DEBUG_PCI
  32 #ifdef DEBUG_PCI
  33 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  34 #else
  35 # define PCI_DPRINTF(format, ...)       do { } while (0)
  36 #endif
  37
  38 struct PCIBus {
  39     BusState qbus;
  40     int bus_num;
  41     int devfn_min;
  42     pci_set_irq_fn set_irq;
  43     pci_map_irq_fn map_irq;
  44     pci_hotplug_fn hotplug;
  45     uint32_t config_reg; /* XXX: suppress */
  46     void *irq_opaque;
  47     PCIDevice *devices[256];
  48     PCIDevice *parent_dev;
  49     PCIBus *next;
  50     /* The bus IRQ state is the logical OR of the connected devices.
  51        Keep a count of the number of devices with raised IRQs.  */
  52     int nirq;
  53     int *irq_count;
  54 };
  55
  56 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  57
  58 static struct BusInfo pci_bus_info = {
  59     .name       = "PCI",
  60     .size       = sizeof(PCIBus),
  61     .print_dev  = pcibus_dev_print,
  62     .props      = (Property[]) {
  63         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  64         DEFINE_PROP_END_OF_LIST()
  65     }
  66 };
  67
  68 static void pci_update_mappings(PCIDevice *d);
  69 static void pci_set_irq(void *opaque, int irq_num, int level);
  70
  71 target_phys_addr_t pci_mem_base;
  72 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  73 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  74 static PCIBus *first_bus;
  75
  76 static const VMStateDescription vmstate_pcibus = {
  77     .name = "PCIBUS",
  78     .version_id = 1,
  79     .minimum_version_id = 1,
  80     .minimum_version_id_old = 1,
  81     .fields      = (VMStateField []) {
  82         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  83         VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq),
  84         VMSTATE_END_OF_LIST()
  85     }
  86 };
  87
  88 static inline int pci_bar(int reg)
  89 {
  90     return reg == PCI_ROM_SLOT ? PCI_ROM_ADDRESS : PCI_BASE_ADDRESS_0 + reg * 4;
  91 }
  92
  93 static void pci_device_reset(PCIDevice *dev)
  94 {
  95     int r;
  96
  97     memset(dev->irq_state, 0, sizeof dev->irq_state);
  98     dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  99                                   PCI_COMMAND_MASTER);
 100     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 101     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 102     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 103         if (!dev->io_regions[r].size) {
 104             continue;
 105         }
 106         pci_set_long(dev->config + pci_bar(r), dev->io_regions[r].type);
 107     }
 108     pci_update_mappings(dev);
 109 }
 110
 111 static void pci_bus_reset(void *opaque)
 112 {
 113     PCIBus *bus = opaque;
 114     int i;
 115
 116     for (i = 0; i < bus->nirq; i++) {
 117         bus->irq_count[i] = 0;
 118     }
 119     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 120         if (bus->devices[i]) {
 121             pci_device_reset(bus->devices[i]);
 122         }
 123     }
 124 }
 125
 126 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 127                          const char *name, int devfn_min)
 128 {
 129     static int nbus = 0;
 130
 131     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 132     bus->devfn_min = devfn_min;
 133     bus->next = first_bus;
 134     first_bus = bus;
 135     vmstate_register(nbus++, &vmstate_pcibus, bus);
 136     qemu_register_reset(pci_bus_reset, bus);
 137 }
 138
 139 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 140 {
 141     PCIBus *bus;
 142
 143     bus = qemu_mallocz(sizeof(*bus));
 144     bus->qbus.qdev_allocated = 1;
 145     pci_bus_new_inplace(bus, parent, name, devfn_min);
 146     return bus;
 147 }
 148
 149 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 150                   void *irq_opaque, int nirq)
 151 {
 152     bus->set_irq = set_irq;
 153     bus->map_irq = map_irq;
 154     bus->irq_opaque = irq_opaque;
 155     bus->nirq = nirq;
 156     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 157 }
 158
 159 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 160 {
 161     bus->qbus.allow_hotplug = 1;
 162     bus->hotplug = hotplug;
 163 }
 164
 165 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 166                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 167                          void *irq_opaque, int devfn_min, int nirq)
 168 {
 169     PCIBus *bus;
 170
 171     bus = pci_bus_new(parent, name, devfn_min);
 172     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 173     return bus;
 174 }
 175
 176 static void pci_register_secondary_bus(PCIBus *bus,
 177                                        PCIDevice *dev,
 178                                        pci_map_irq_fn map_irq,
 179                                        const char *name)
 180 {
 181     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 182     bus->map_irq = map_irq;
 183     bus->parent_dev = dev;
 184     bus->next = dev->bus->next;
 185     dev->bus->next = bus;
 186 }
 187
 188 int pci_bus_num(PCIBus *s)
 189 {
 190     return s->bus_num;
 191 }
 192
 193 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 194 {
 195     PCIDevice *s = container_of(pv, PCIDevice, config);
 196     uint8_t config[size];
 197     int i;
 198
 199     qemu_get_buffer(f, config, size);
 200     for (i = 0; i < size; ++i)
 201         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 202             return -EINVAL;
 203     memcpy(s->config, config, size);
 204
 205     pci_update_mappings(s);
 206
 207     return 0;
 208 }
 209
 210 /* just put buffer */
 211 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 212 {
 213     const uint8_t *v = pv;
 214     qemu_put_buffer(f, v, size);
 215 }
 216
 217 static VMStateInfo vmstate_info_pci_config = {
 218     .name = "pci config",
 219     .get  = get_pci_config_device,
 220     .put  = put_pci_config_device,
 221 };
 222
 223 const VMStateDescription vmstate_pci_device = {
 224     .name = "PCIDevice",
 225     .version_id = 2,
 226     .minimum_version_id = 1,
 227     .minimum_version_id_old = 1,
 228     .fields      = (VMStateField []) {
 229         VMSTATE_INT32_LE(version_id, PCIDevice),
 230         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 231                        typeof_field(PCIDevice,config)),
 232         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2),
 233         VMSTATE_END_OF_LIST()
 234     }
 235 };
 236
 237 void pci_device_save(PCIDevice *s, QEMUFile *f)
 238 {
 239     vmstate_save_state(f, &vmstate_pci_device, s);
 240 }
 241
 242 int pci_device_load(PCIDevice *s, QEMUFile *f)
 243 {
 244     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 245 }
 246
 247 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 248 {
 249     uint16_t *id;
 250
 251     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 252     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 253     id[1] = cpu_to_le16(pci_default_sub_device_id);
 254     return 0;
 255 }
 256
 257 /*
 258  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 259  */
 260 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 261 {
 262     const char *p;
 263     char *e;
 264     unsigned long val;
 265     unsigned long dom = 0, bus = 0;
 266     unsigned slot = 0;
 267
 268     p = addr;
 269     val = strtoul(p, &e, 16);
 270     if (e == p)
 271         return -1;
 272     if (*e == ':') {
 273         bus = val;
 274         p = e + 1;
 275         val = strtoul(p, &e, 16);
 276         if (e == p)
 277             return -1;
 278         if (*e == ':') {
 279             dom = bus;
 280             bus = val;
 281             p = e + 1;
 282             val = strtoul(p, &e, 16);
 283             if (e == p)
 284                 return -1;
 285         }
 286     }
 287
 288     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 289         return -1;
 290
 291     slot = val;
 292
 293     if (*e)
 294         return -1;
 295
 296     /* Note: QEMU doesn't implement domains other than 0 */
 297     if (dom != 0 || pci_find_bus(bus) == NULL)
 298         return -1;
 299
 300     *domp = dom;
 301     *busp = bus;
 302     *slotp = slot;
 303     return 0;
 304 }
 305
 306 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 307                      unsigned *slotp)
 308 {
 309     /* strip legacy tag */
 310     if (!strncmp(addr, "pci_addr=", 9)) {
 311         addr += 9;
 312     }
 313     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 314         monitor_printf(mon, "Invalid pci address\n");
 315         return -1;
 316     }
 317     return 0;
 318 }
 319
 320 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 321 {
 322     int dom, bus;
 323     unsigned slot;
 324
 325     if (!devaddr) {
 326         *devfnp = -1;
 327         return pci_find_bus(0);
 328     }
 329
 330     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 331         return NULL;
 332     }
 333
 334     *devfnp = slot << 3;
 335     return pci_find_bus(bus);
 336 }
 337
 338 static void pci_init_cmask(PCIDevice *dev)
 339 {
 340     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 341     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 342     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 343     dev->cmask[PCI_REVISION_ID] = 0xff;
 344     dev->cmask[PCI_CLASS_PROG] = 0xff;
 345     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 346     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 347     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 348 }
 349
 350 static void pci_init_wmask(PCIDevice *dev)
 351 {
 352     int i;
 353     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 354     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 355     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 356                               | PCI_COMMAND_MASTER;
 357     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 358         dev->wmask[i] = 0xff;
 359 }
 360
 361 /* -1 for devfn means auto assign */
 362 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 363                                          const char *name, int devfn,
 364                                          PCIConfigReadFunc *config_read,
 365                                          PCIConfigWriteFunc *config_write)
 366 {
 367     if (devfn < 0) {
 368         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 369             if (!bus->devices[devfn])
 370                 goto found;
 371         }
 372         return NULL;
 373     found: ;
 374     } else if (bus->devices[devfn]) {
 375         return NULL;
 376     }
 377     pci_dev->bus = bus;
 378     pci_dev->devfn = devfn;
 379     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 380     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 381     pci_set_default_subsystem_id(pci_dev);
 382     pci_init_cmask(pci_dev);
 383     pci_init_wmask(pci_dev);
 384
 385     if (!config_read)
 386         config_read = pci_default_read_config;
 387     if (!config_write)
 388         config_write = pci_default_write_config;
 389     pci_dev->config_read = config_read;
 390     pci_dev->config_write = config_write;
 391     bus->devices[devfn] = pci_dev;
 392     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 393     pci_dev->version_id = 2; /* Current pci device vmstate version */
 394     return pci_dev;
 395 }
 396
 397 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 398                                int instance_size, int devfn,
 399                                PCIConfigReadFunc *config_read,
 400                                PCIConfigWriteFunc *config_write)
 401 {
 402     PCIDevice *pci_dev;
 403
 404     pci_dev = qemu_mallocz(instance_size);
 405     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 406                                      config_read, config_write);
 407     return pci_dev;
 408 }
 409 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 410 {
 411     return addr + pci_mem_base;
 412 }
 413
 414 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 415 {
 416     PCIIORegion *r;
 417     int i;
 418
 419     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 420         r = &pci_dev->io_regions[i];
 421         if (!r->size || r->addr == -1)
 422             continue;
 423         if (r->type == PCI_ADDRESS_SPACE_IO) {
 424             isa_unassign_ioport(r->addr, r->size);
 425         } else {
 426             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 427                                                      r->size,
 428                                                      IO_MEM_UNASSIGNED);
 429         }
 430     }
 431 }
 432
 433 static int pci_unregister_device(DeviceState *dev)
 434 {
 435     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 436     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 437     int ret = 0;
 438
 439     if (info->exit)
 440         ret = info->exit(pci_dev);
 441     if (ret)
 442         return ret;
 443
 444     msix_uninit(pci_dev);
 445     pci_unregister_io_regions(pci_dev);
 446
 447     qemu_free_irqs(pci_dev->irq);
 448     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 449     return 0;
 450 }
 451
 452 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 453                             uint32_t size, int type,
 454                             PCIMapIORegionFunc *map_func)
 455 {
 456     PCIIORegion *r;
 457     uint32_t addr;
 458     uint32_t wmask;
 459
 460     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 461         return;
 462
 463     if (size & (size-1)) {
 464         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 465                     "type=0x%x, size=0x%x\n", type, size);
 466         exit(1);
 467     }
 468
 469     r = &pci_dev->io_regions[region_num];
 470     r->addr = -1;
 471     r->size = size;
 472     r->type = type;
 473     r->map_func = map_func;
 474
 475     wmask = ~(size - 1);
 476     addr = pci_bar(region_num);
 477     if (region_num == PCI_ROM_SLOT) {
 478         /* ROM enable bit is writeable */
 479         wmask |= PCI_ROM_ADDRESS_ENABLE;
 480     }
 481     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 482     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 483     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 484 }
 485
 486 static void pci_update_mappings(PCIDevice *d)
 487 {
 488     PCIIORegion *r;
 489     int cmd, i;
 490     uint32_t last_addr, new_addr;
 491
 492     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 493     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 494         r = &d->io_regions[i];
 495         if (r->size != 0) {
 496             if (r->type & PCI_ADDRESS_SPACE_IO) {
 497                 if (cmd & PCI_COMMAND_IO) {
 498                     new_addr = pci_get_long(d->config + pci_bar(i));
 499                     new_addr = new_addr & ~(r->size - 1);
 500                     last_addr = new_addr + r->size - 1;
 501                     /* NOTE: we have only 64K ioports on PC */
 502                     if (last_addr <= new_addr || new_addr == 0 ||
 503                         last_addr >= 0x10000) {
 504                         new_addr = -1;
 505                     }
 506                 } else {
 507                     new_addr = -1;
 508                 }
 509             } else {
 510                 if (cmd & PCI_COMMAND_MEMORY) {
 511                     new_addr = pci_get_long(d->config + pci_bar(i));
 512                     /* the ROM slot has a specific enable bit */
 513                     if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
 514                         goto no_mem_map;
 515                     new_addr = new_addr & ~(r->size - 1);
 516                     last_addr = new_addr + r->size - 1;
 517                     /* NOTE: we do not support wrapping */
 518                     /* XXX: as we cannot support really dynamic
 519                        mappings, we handle specific values as invalid
 520                        mappings. */
 521                     if (last_addr <= new_addr || new_addr == 0 ||
 522                         last_addr == -1) {
 523                         new_addr = -1;
 524                     }
 525                 } else {
 526                 no_mem_map:
 527                     new_addr = -1;
 528                 }
 529             }
 530             /* now do the real mapping */
 531             if (new_addr != r->addr) {
 532                 if (r->addr != -1) {
 533                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 534                         int class;
 535                         /* NOTE: specific hack for IDE in PC case:
 536                            only one byte must be mapped. */
 537                         class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 538                         if (class == 0x0101 && r->size == 4) {
 539                             isa_unassign_ioport(r->addr + 2, 1);
 540                         } else {
 541                             isa_unassign_ioport(r->addr, r->size);
 542                         }
 543                     } else {
 544                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 545                                                      r->size,
 546                                                      IO_MEM_UNASSIGNED);
 547                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 548                     }
 549                 }
 550                 r->addr = new_addr;
 551                 if (r->addr != -1) {
 552                     r->map_func(d, i, r->addr, r->size, r->type);
 553                 }
 554             }
 555         }
 556     }
 557 }
 558
 559 uint32_t pci_default_read_config(PCIDevice *d,
 560                                  uint32_t address, int len)
 561 {
 562     uint32_t val;
 563
 564     switch(len) {
 565     default:
 566     case 4:
 567         if (address <= 0xfc) {
 568             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 569             break;
 570         }
 571         /* fall through */
 572     case 2:
 573         if (address <= 0xfe) {
 574             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 575             break;
 576         }
 577         /* fall through */
 578     case 1:
 579         val = d->config[address];
 580         break;
 581     }
 582     return val;
 583 }
 584
 585 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 586 {
 587     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 588     int i;
 589
 590     /* not efficient, but simple */
 591     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 592     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 593         uint8_t wmask = d->wmask[addr];
 594         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 595     }
 596     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 597         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 598             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 599         pci_update_mappings(d);
 600 }
 601
 602 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 603 {
 604     PCIBus *s = opaque;
 605     PCIDevice *pci_dev;
 606     int config_addr, bus_num;
 607
 608 #if 0
 609     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 610                 addr, val, len);
 611 #endif
 612     bus_num = (addr >> 16) & 0xff;
 613     while (s && s->bus_num != bus_num)
 614         s = s->next;
 615     if (!s)
 616         return;
 617     pci_dev = s->devices[(addr >> 8) & 0xff];
 618     if (!pci_dev)
 619         return;
 620     config_addr = addr & 0xff;
 621     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 622                 pci_dev->name, config_addr, val, len);
 623     pci_dev->config_write(pci_dev, config_addr, val, len);
 624 }
 625
 626 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 627 {
 628     PCIBus *s = opaque;
 629     PCIDevice *pci_dev;
 630     int config_addr, bus_num;
 631     uint32_t val;
 632
 633     bus_num = (addr >> 16) & 0xff;
 634     while (s && s->bus_num != bus_num)
 635         s= s->next;
 636     if (!s)
 637         goto fail;
 638     pci_dev = s->devices[(addr >> 8) & 0xff];
 639     if (!pci_dev) {
 640     fail:
 641         switch(len) {
 642         case 1:
 643             val = 0xff;
 644             break;
 645         case 2:
 646             val = 0xffff;
 647             break;
 648         default:
 649         case 4:
 650             val = 0xffffffff;
 651             break;
 652         }
 653         goto the_end;
 654     }
 655     config_addr = addr & 0xff;
 656     val = pci_dev->config_read(pci_dev, config_addr, len);
 657     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 658                 pci_dev->name, config_addr, val, len);
 659  the_end:
 660 #if 0
 661     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 662                 addr, val, len);
 663 #endif
 664     return val;
 665 }
 666
 667 /***********************************************************/
 668 /* generic PCI irq support */
 669
 670 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 671 static void pci_set_irq(void *opaque, int irq_num, int level)
 672 {
 673     PCIDevice *pci_dev = opaque;
 674     PCIBus *bus;
 675     int change;
 676
 677     change = level - pci_dev->irq_state[irq_num];
 678     if (!change)
 679         return;
 680
 681     pci_dev->irq_state[irq_num] = level;
 682     for (;;) {
 683         bus = pci_dev->bus;
 684         irq_num = bus->map_irq(pci_dev, irq_num);
 685         if (bus->set_irq)
 686             break;
 687         pci_dev = bus->parent_dev;
 688     }
 689     bus->irq_count[irq_num] += change;
 690     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 691 }
 692
 693 /***********************************************************/
 694 /* monitor info on PCI */
 695
 696 typedef struct {
 697     uint16_t class;
 698     const char *desc;
 699 } pci_class_desc;
 700
 701 static const pci_class_desc pci_class_descriptions[] =
 702 {
 703     { 0x0100, "SCSI controller"},
 704     { 0x0101, "IDE controller"},
 705     { 0x0102, "Floppy controller"},
 706     { 0x0103, "IPI controller"},
 707     { 0x0104, "RAID controller"},
 708     { 0x0106, "SATA controller"},
 709     { 0x0107, "SAS controller"},
 710     { 0x0180, "Storage controller"},
 711     { 0x0200, "Ethernet controller"},
 712     { 0x0201, "Token Ring controller"},
 713     { 0x0202, "FDDI controller"},
 714     { 0x0203, "ATM controller"},
 715     { 0x0280, "Network controller"},
 716     { 0x0300, "VGA controller"},
 717     { 0x0301, "XGA controller"},
 718     { 0x0302, "3D controller"},
 719     { 0x0380, "Display controller"},
 720     { 0x0400, "Video controller"},
 721     { 0x0401, "Audio controller"},
 722     { 0x0402, "Phone"},
 723     { 0x0480, "Multimedia controller"},
 724     { 0x0500, "RAM controller"},
 725     { 0x0501, "Flash controller"},
 726     { 0x0580, "Memory controller"},
 727     { 0x0600, "Host bridge"},
 728     { 0x0601, "ISA bridge"},
 729     { 0x0602, "EISA bridge"},
 730     { 0x0603, "MC bridge"},
 731     { 0x0604, "PCI bridge"},
 732     { 0x0605, "PCMCIA bridge"},
 733     { 0x0606, "NUBUS bridge"},
 734     { 0x0607, "CARDBUS bridge"},
 735     { 0x0608, "RACEWAY bridge"},
 736     { 0x0680, "Bridge"},
 737     { 0x0c03, "USB controller"},
 738     { 0, NULL}
 739 };
 740
 741 static void pci_info_device(PCIDevice *d)
 742 {
 743     Monitor *mon = cur_mon;
 744     int i, class;
 745     PCIIORegion *r;
 746     const pci_class_desc *desc;
 747
 748     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 749                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 750     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 751     monitor_printf(mon, "    ");
 752     desc = pci_class_descriptions;
 753     while (desc->desc && class != desc->class)
 754         desc++;
 755     if (desc->desc) {
 756         monitor_printf(mon, "%s", desc->desc);
 757     } else {
 758         monitor_printf(mon, "Class %04x", class);
 759     }
 760     monitor_printf(mon, ": PCI device %04x:%04x\n",
 761            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 762            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 763
 764     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 765         monitor_printf(mon, "      IRQ %d.\n",
 766                        d->config[PCI_INTERRUPT_LINE]);
 767     }
 768     if (class == 0x0604) {
 769         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 770     }
 771     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 772         r = &d->io_regions[i];
 773         if (r->size != 0) {
 774             monitor_printf(mon, "      BAR%d: ", i);
 775             if (r->type & PCI_ADDRESS_SPACE_IO) {
 776                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 777                                r->addr, r->addr + r->size - 1);
 778             } else {
 779                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 780                                r->addr, r->addr + r->size - 1);
 781             }
 782         }
 783     }
 784     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 785     if (class == 0x0604 && d->config[0x19] != 0) {
 786         pci_for_each_device(d->config[0x19], pci_info_device);
 787     }
 788 }
 789
 790 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 791 {
 792     PCIBus *bus = first_bus;
 793     PCIDevice *d;
 794     int devfn;
 795
 796     while (bus && bus->bus_num != bus_num)
 797         bus = bus->next;
 798     if (bus) {
 799         for(devfn = 0; devfn < 256; devfn++) {
 800             d = bus->devices[devfn];
 801             if (d)
 802                 fn(d);
 803         }
 804     }
 805 }
 806
 807 void pci_info(Monitor *mon)
 808 {
 809     pci_for_each_device(0, pci_info_device);
 810 }
 811
 812 PCIDevice *pci_create(const char *name, const char *devaddr)
 813 {
 814     PCIBus *bus;
 815     int devfn;
 816     DeviceState *dev;
 817
 818     bus = pci_get_bus_devfn(&devfn, devaddr);
 819     if (!bus) {
 820         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 821                 devaddr, name);
 822         exit(1);
 823     }
 824
 825     dev = qdev_create(&bus->qbus, name);
 826     qdev_prop_set_uint32(dev, "addr", devfn);
 827     return (PCIDevice *)dev;
 828 }
 829
 830 static const char * const pci_nic_models[] = {
 831     "ne2k_pci",
 832     "i82551",
 833     "i82557b",
 834     "i82559er",
 835     "rtl8139",
 836     "e1000",
 837     "pcnet",
 838     "virtio",
 839     NULL
 840 };
 841
 842 static const char * const pci_nic_names[] = {
 843     "ne2k_pci",
 844     "i82551",
 845     "i82557b",
 846     "i82559er",
 847     "rtl8139",
 848     "e1000",
 849     "pcnet",
 850     "virtio-net-pci",
 851     NULL
 852 };
 853
 854 int pci_nic_supported(const char *model)
 855 {
 856     int i;
 857
 858     for (i = 0; pci_nic_names[i]; i++)
 859         if (strcmp(model, pci_nic_names[i]) == 0)
 860             return 1;
 861
 862     return 0;
 863 }
 864
 865 /* Initialize a PCI NIC.  */
 866 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 867                         const char *default_devaddr)
 868 {
 869     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 870     PCIBus *bus;
 871     int devfn;
 872     PCIDevice *pci_dev;
 873     DeviceState *dev;
 874     int i;
 875
 876     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
 877     if (i < 0)
 878         return NULL;
 879
 880     bus = pci_get_bus_devfn(&devfn, devaddr);
 881     if (!bus) {
 882         qemu_error("Invalid PCI device address %s for device %s\n",
 883                    devaddr, pci_nic_names[i]);
 884         return NULL;
 885     }
 886
 887     pci_dev = pci_create_noinit(bus, devfn, pci_nic_names[i]);
 888     dev = &pci_dev->qdev;
 889     if (nd->id)
 890         dev->id = qemu_strdup(nd->id);
 891     dev->nd = nd;
 892     if (qdev_init(dev) < 0)
 893         return NULL;
 894     nd->private = dev;
 895     return pci_dev;
 896 }
 897
 898 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 899                                const char *default_devaddr)
 900 {
 901     PCIDevice *res;
 902
 903     if (qemu_show_nic_models(nd->model, pci_nic_models))
 904         exit(0);
 905
 906     res = pci_nic_init(nd, default_model, default_devaddr);
 907     if (!res)
 908         exit(1);
 909     return res;
 910 }
 911
 912 typedef struct {
 913     PCIDevice dev;
 914     PCIBus bus;
 915     uint32_t vid;
 916     uint32_t did;
 917 } PCIBridge;
 918
 919 static void pci_bridge_write_config(PCIDevice *d,
 920                              uint32_t address, uint32_t val, int len)
 921 {
 922     PCIBridge *s = (PCIBridge *)d;
 923
 924     pci_default_write_config(d, address, val, len);
 925     s->bus.bus_num = d->config[PCI_SECONDARY_BUS];
 926 }
 927
 928 PCIBus *pci_find_bus(int bus_num)
 929 {
 930     PCIBus *bus = first_bus;
 931
 932     while (bus && bus->bus_num != bus_num)
 933         bus = bus->next;
 934
 935     return bus;
 936 }
 937
 938 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 939 {
 940     PCIBus *bus = pci_find_bus(bus_num);
 941
 942     if (!bus)
 943         return NULL;
 944
 945     return bus->devices[PCI_DEVFN(slot, function)];
 946 }
 947
 948 static int pci_bridge_initfn(PCIDevice *dev)
 949 {
 950     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
 951
 952     pci_config_set_vendor_id(s->dev.config, s->vid);
 953     pci_config_set_device_id(s->dev.config, s->did);
 954
 955     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 956     s->dev.config[0x05] = 0x00;
 957     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 958     s->dev.config[0x07] = 0x00; // status = fast devsel
 959     s->dev.config[0x08] = 0x00; // revision
 960     s->dev.config[0x09] = 0x00; // programming i/f
 961     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 962     s->dev.config[0x0D] = 0x10; // latency_timer
 963     s->dev.config[PCI_HEADER_TYPE] =
 964         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 965     s->dev.config[0x1E] = 0xa0; // secondary status
 966     return 0;
 967 }
 968
 969 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 970                         pci_map_irq_fn map_irq, const char *name)
 971 {
 972     PCIDevice *dev;
 973     PCIBridge *s;
 974
 975     dev = pci_create_noinit(bus, devfn, "pci-bridge");
 976     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
 977     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
 978     qdev_init(&dev->qdev);
 979
 980     s = DO_UPCAST(PCIBridge, dev, dev);
 981     pci_register_secondary_bus(&s->bus, &s->dev, map_irq, name);
 982     return &s->bus;
 983 }
 984
 985 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 986 {
 987     PCIDevice *pci_dev = (PCIDevice *)qdev;
 988     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 989     PCIBus *bus;
 990     int devfn, rc;
 991
 992     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 993     devfn = pci_dev->devfn;
 994     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 995                                      info->config_read, info->config_write);
 996     assert(pci_dev);
 997     rc = info->init(pci_dev);
 998     if (rc != 0)
 999         return rc;
1000     if (qdev->hotplugged)
1001         bus->hotplug(pci_dev, 1);
1002     return 0;
1003 }
1004
1005 static int pci_unplug_device(DeviceState *qdev)
1006 {
1007     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1008
1009     dev->bus->hotplug(dev, 0);
1010     return 0;
1011 }
1012
1013 void pci_qdev_register(PCIDeviceInfo *info)
1014 {
1015     info->qdev.init = pci_qdev_init;
1016     info->qdev.unplug = pci_unplug_device;
1017     info->qdev.exit = pci_unregister_device;
1018     info->qdev.bus_info = &pci_bus_info;
1019     qdev_register(&info->qdev);
1020 }
1021
1022 void pci_qdev_register_many(PCIDeviceInfo *info)
1023 {
1024     while (info->qdev.name) {
1025         pci_qdev_register(info);
1026         info++;
1027     }
1028 }
1029
1030 PCIDevice *pci_create_noinit(PCIBus *bus, int devfn, const char *name)
1031 {
1032     DeviceState *dev;
1033
1034     dev = qdev_create(&bus->qbus, name);
1035     qdev_prop_set_uint32(dev, "addr", devfn);
1036     return DO_UPCAST(PCIDevice, qdev, dev);
1037 }
1038
1039 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1040 {
1041     PCIDevice *dev = pci_create_noinit(bus, devfn, name);
1042     qdev_init(&dev->qdev);
1043     return dev;
1044 }
1045
1046 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1047 {
1048     int offset = PCI_CONFIG_HEADER_SIZE;
1049     int i;
1050     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
1051         if (pdev->used[i])
1052             offset = i + 1;
1053         else if (i - offset + 1 == size)
1054             return offset;
1055     return 0;
1056 }
1057
1058 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1059                                         uint8_t *prev_p)
1060 {
1061     uint8_t next, prev;
1062
1063     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1064         return 0;
1065
1066     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1067          prev = next + PCI_CAP_LIST_NEXT)
1068         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1069             break;
1070
1071     if (prev_p)
1072         *prev_p = prev;
1073     return next;
1074 }
1075
1076 /* Reserve space and add capability to the linked list in pci config space */
1077 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1078 {
1079     uint8_t offset = pci_find_space(pdev, size);
1080     uint8_t *config = pdev->config + offset;
1081     if (!offset)
1082         return -ENOSPC;
1083     config[PCI_CAP_LIST_ID] = cap_id;
1084     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1085     pdev->config[PCI_CAPABILITY_LIST] = offset;
1086     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1087     memset(pdev->used + offset, 0xFF, size);
1088     /* Make capability read-only by default */
1089     memset(pdev->wmask + offset, 0, size);
1090     /* Check capability by default */
1091     memset(pdev->cmask + offset, 0xFF, size);
1092     return offset;
1093 }
1094
1095 /* Unlink capability from the pci config space. */
1096 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1097 {
1098     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1099     if (!offset)
1100         return;
1101     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1102     /* Make capability writeable again */
1103     memset(pdev->wmask + offset, 0xff, size);
1104     /* Clear cmask as device-specific registers can't be checked */
1105     memset(pdev->cmask + offset, 0, size);
1106     memset(pdev->used + offset, 0, size);
1107
1108     if (!pdev->config[PCI_CAPABILITY_LIST])
1109         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1110 }
1111
1112 /* Reserve space for capability at a known offset (to call after load). */
1113 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1114 {
1115     memset(pdev->used + offset, 0xff, size);
1116 }
1117
1118 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1119 {
1120     return pci_find_capability_list(pdev, cap_id, NULL);
1121 }
1122
1123 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1124 {
1125     PCIDevice *d = (PCIDevice *)dev;
1126     const pci_class_desc *desc;
1127     char ctxt[64];
1128     PCIIORegion *r;
1129     int i, class;
1130
1131     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1132     desc = pci_class_descriptions;
1133     while (desc->desc && class != desc->class)
1134         desc++;
1135     if (desc->desc) {
1136         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1137     } else {
1138         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1139     }
1140
1141     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1142                    "pci id %04x:%04x (sub %04x:%04x)\n",
1143                    indent, "", ctxt,
1144                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1145                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1146                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1147                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1148                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1149     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1150         r = &d->io_regions[i];
1151         if (!r->size)
1152             continue;
1153         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1154                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1155                        r->addr, r->addr + r->size - 1);
1156     }
1157 }
1158
1159 static PCIDeviceInfo bridge_info = {
1160     .qdev.name    = "pci-bridge",
1161     .qdev.size    = sizeof(PCIBridge),
1162     .init         = pci_bridge_initfn,
1163     .config_write = pci_bridge_write_config,
1164     .qdev.props   = (Property[]) {
1165         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1166         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1167         DEFINE_PROP_END_OF_LIST(),
1168     }
1169 };
1170
1171 static void pci_register_devices(void)
1172 {
1173     pci_qdev_register(&bridge_info);
1174 }
1175
1176 device_init(pci_register_devices)