hw/sh_pci.c

   1 /*
   2  * SuperH on-chip PCIC emulation.
   3  *
   4  * Copyright (c) 2008 Takashi YOSHII
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "sysbus.h"
  25 #include "sh.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "bswap.h"
  29
  30 typedef struct SHPCIState {
  31     SysBusDevice busdev;
  32     PCIBus *bus;
  33     PCIDevice *dev;
  34     qemu_irq irq[4];
  35     int memconfig;
  36     uint32_t par;
  37     uint32_t mbr;
  38     uint32_t iobr;
  39 } SHPCIState;
  40
  41 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
  42 {
  43     SHPCIState *pcic = p;
  44     switch(addr) {
  45     case 0 ... 0xfc:
  46         cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
  47         break;
  48     case 0x1c0:
  49         pcic->par = val;
  50         break;
  51     case 0x1c4:
  52         pcic->mbr = val & 0xff000001;
  53         break;
  54     case 0x1c8:
  55         if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
  56             cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
  57                                          IO_MEM_UNASSIGNED);
  58             pcic->iobr = val & 0xfffc0001;
  59             isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
  60         }
  61         break;
  62     case 0x220:
  63         pci_data_write(pcic->bus, pcic->par, val, 4);
  64         break;
  65     }
  66 }
  67
  68 static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
  69 {
  70     SHPCIState *pcic = p;
  71     switch(addr) {
  72     case 0 ... 0xfc:
  73         return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
  74     case 0x1c0:
  75         return pcic->par;
  76     case 0x1c4:
  77         return pcic->mbr;
  78     case 0x1c8:
  79         return pcic->iobr;
  80     case 0x220:
  81         return pci_data_read(pcic->bus, pcic->par, 4);
  82     }
  83     return 0;
  84 }
  85
  86 typedef struct {
  87     CPUReadMemoryFunc * const r[3];
  88     CPUWriteMemoryFunc * const w[3];
  89 } MemOp;
  90
  91 static MemOp sh_pci_reg = {
  92     { NULL, NULL, sh_pci_reg_read },
  93     { NULL, NULL, sh_pci_reg_write },
  94 };
  95
  96 static int sh_pci_map_irq(PCIDevice *d, int irq_num)
  97 {
  98     return (d->devfn >> 3);
  99 }
 100
 101 static void sh_pci_set_irq(void *opaque, int irq_num, int level)
 102 {
 103     qemu_irq *pic = opaque;
 104
 105     qemu_set_irq(pic[irq_num], level);
 106 }
 107
 108 static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base)
 109 {
 110     SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
 111
 112     cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig);
 113     cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig);
 114
 115     s->iobr = 0xfe240000;
 116     isa_mmio_init(s->iobr, 0x40000);
 117 }
 118
 119 static int sh_pci_init_device(SysBusDevice *dev)
 120 {
 121     SHPCIState *s;
 122     int i;
 123
 124     s = FROM_SYSBUS(SHPCIState, dev);
 125     for (i = 0; i < 4; i++) {
 126         sysbus_init_irq(dev, &s->irq[i]);
 127     }
 128     s->bus = pci_register_bus(&s->busdev.qdev, "pci",
 129                               sh_pci_set_irq, sh_pci_map_irq,
 130                               s->irq, PCI_DEVFN(0, 0), 4);
 131     s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w,
 132                                           s, DEVICE_NATIVE_ENDIAN);
 133     sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);
 134     s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
 135     return 0;
 136 }
 137
 138 static int sh_pci_host_init(PCIDevice *d)
 139 {
 140     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_HITACHI);
 141     pci_config_set_device_id(d->config, PCI_DEVICE_ID_HITACHI_SH7751R);
 142     pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
 143     pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
 144                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
 145     return 0;
 146 }
 147
 148 static PCIDeviceInfo sh_pci_host_info = {
 149     .qdev.name = "sh_pci_host",
 150     .qdev.size = sizeof(PCIDevice),
 151     .init      = sh_pci_host_init,
 152 };
 153
 154 static void sh_pci_register_devices(void)
 155 {
 156     sysbus_register_dev("sh_pci", sizeof(SHPCIState),
 157                         sh_pci_init_device);
 158     pci_qdev_register(&sh_pci_host_info);
 159 }
 160
 161 device_init(sh_pci_register_devices)