target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26
  27 //#define DEBUG_KVM
  28
  29 #ifdef DEBUG_KVM
  30 #define dprintf(fmt, ...) \
  31     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  32 #else
  33 #define dprintf(fmt, ...) \
  34     do { } while (0)
  35 #endif
  36
  37 #ifdef KVM_CAP_EXT_CPUID
  38
  39 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  40 {
  41     struct kvm_cpuid2 *cpuid;
  42     int r, size;
  43
  44     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  45     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  46     cpuid->nent = max;
  47     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  48     if (r == 0 && cpuid->nent >= max) {
  49         r = -E2BIG;
  50     }
  51     if (r < 0) {
  52         if (r == -E2BIG) {
  53             qemu_free(cpuid);
  54             return NULL;
  55         } else {
  56             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  57                     strerror(-r));
  58             exit(1);
  59         }
  60     }
  61     return cpuid;
  62 }
  63
  64 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  65 {
  66     struct kvm_cpuid2 *cpuid;
  67     int i, max;
  68     uint32_t ret = 0;
  69     uint32_t cpuid_1_edx;
  70
  71     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  72         return -1U;
  73     }
  74
  75     max = 1;
  76     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  77         max *= 2;
  78     }
  79
  80     for (i = 0; i < cpuid->nent; ++i) {
  81         if (cpuid->entries[i].function == function) {
  82             switch (reg) {
  83             case R_EAX:
  84                 ret = cpuid->entries[i].eax;
  85                 break;
  86             case R_EBX:
  87                 ret = cpuid->entries[i].ebx;
  88                 break;
  89             case R_ECX:
  90                 ret = cpuid->entries[i].ecx;
  91                 break;
  92             case R_EDX:
  93                 ret = cpuid->entries[i].edx;
  94                 if (function == 0x80000001) {
  95                     /* On Intel, kvm returns cpuid according to the Intel spec,
  96                      * so add missing bits according to the AMD spec:
  97                      */
  98                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
  99                     ret |= cpuid_1_edx & 0xdfeff7ff;
 100                 }
 101                 break;
 102             }
 103         }
 104     }
 105
 106     qemu_free(cpuid);
 107
 108     return ret;
 109 }
 110
 111 #else
 112
 113 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 114 {
 115     return -1U;
 116 }
 117
 118 #endif
 119
 120 int kvm_arch_init_vcpu(CPUState *env)
 121 {
 122     struct {
 123         struct kvm_cpuid2 cpuid;
 124         struct kvm_cpuid_entry2 entries[100];
 125     } __attribute__((packed)) cpuid_data;
 126     uint32_t limit, i, j, cpuid_i;
 127     uint32_t unused;
 128
 129     env->mp_state = KVM_MP_STATE_RUNNABLE;
 130
 131     cpuid_i = 0;
 132
 133     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 134
 135     for (i = 0; i <= limit; i++) {
 136         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 137
 138         switch (i) {
 139         case 2: {
 140             /* Keep reading function 2 till all the input is received */
 141             int times;
 142
 143             c->function = i;
 144             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 145                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 146             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 147             times = c->eax & 0xff;
 148
 149             for (j = 1; j < times; ++j) {
 150                 c = &cpuid_data.entries[cpuid_i++];
 151                 c->function = i;
 152                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 153                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 154             }
 155             break;
 156         }
 157         case 4:
 158         case 0xb:
 159         case 0xd:
 160             for (j = 0; ; j++) {
 161                 c->function = i;
 162                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 163                 c->index = j;
 164                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 165
 166                 if (i == 4 && c->eax == 0)
 167                     break;
 168                 if (i == 0xb && !(c->ecx & 0xff00))
 169                     break;
 170                 if (i == 0xd && c->eax == 0)
 171                     break;
 172
 173                 c = &cpuid_data.entries[cpuid_i++];
 174             }
 175             break;
 176         default:
 177             c->function = i;
 178             c->flags = 0;
 179             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 180             break;
 181         }
 182     }
 183     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 184
 185     for (i = 0x80000000; i <= limit; i++) {
 186         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 187
 188         c->function = i;
 189         c->flags = 0;
 190         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 191     }
 192
 193     cpuid_data.cpuid.nent = cpuid_i;
 194
 195     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 196 }
 197
 198 static int kvm_has_msr_star(CPUState *env)
 199 {
 200     static int has_msr_star;
 201     int ret;
 202
 203     /* first time */
 204     if (has_msr_star == 0) {
 205         struct kvm_msr_list msr_list, *kvm_msr_list;
 206
 207         has_msr_star = -1;
 208
 209         /* Obtain MSR list from KVM.  These are the MSRs that we must
 210          * save/restore */
 211         msr_list.nmsrs = 0;
 212         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 213         if (ret < 0)
 214             return 0;
 215
 216         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 217                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 218
 219         kvm_msr_list->nmsrs = msr_list.nmsrs;
 220         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 221         if (ret >= 0) {
 222             int i;
 223
 224             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 225                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 226                     has_msr_star = 1;
 227                     break;
 228                 }
 229             }
 230         }
 231
 232         free(kvm_msr_list);
 233     }
 234
 235     if (has_msr_star == 1)
 236         return 1;
 237     return 0;
 238 }
 239
 240 int kvm_arch_init(KVMState *s, int smp_cpus)
 241 {
 242     int ret;
 243
 244     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 245      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 246      * must be part of guest physical memory, we need to allocate it.  Older
 247      * versions of KVM just assumed that it would be at the end of physical
 248      * memory but that doesn't work with more than 4GB of memory.  We simply
 249      * refuse to work with those older versions of KVM. */
 250     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 251     if (ret <= 0) {
 252         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 253         return ret;
 254     }
 255
 256     /* this address is 3 pages before the bios, and the bios should present
 257      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 258      * this?
 259      */
 260     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 261 }
 262
 263 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 264 {
 265     lhs->selector = rhs->selector;
 266     lhs->base = rhs->base;
 267     lhs->limit = rhs->limit;
 268     lhs->type = 3;
 269     lhs->present = 1;
 270     lhs->dpl = 3;
 271     lhs->db = 0;
 272     lhs->s = 1;
 273     lhs->l = 0;
 274     lhs->g = 0;
 275     lhs->avl = 0;
 276     lhs->unusable = 0;
 277 }
 278
 279 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 280 {
 281     unsigned flags = rhs->flags;
 282     lhs->selector = rhs->selector;
 283     lhs->base = rhs->base;
 284     lhs->limit = rhs->limit;
 285     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 286     lhs->present = (flags & DESC_P_MASK) != 0;
 287     lhs->dpl = rhs->selector & 3;
 288     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 289     lhs->s = (flags & DESC_S_MASK) != 0;
 290     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 291     lhs->g = (flags & DESC_G_MASK) != 0;
 292     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 293     lhs->unusable = 0;
 294 }
 295
 296 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 297 {
 298     lhs->selector = rhs->selector;
 299     lhs->base = rhs->base;
 300     lhs->limit = rhs->limit;
 301     lhs->flags =
 302         (rhs->type << DESC_TYPE_SHIFT)
 303         | (rhs->present * DESC_P_MASK)
 304         | (rhs->dpl << DESC_DPL_SHIFT)
 305         | (rhs->db << DESC_B_SHIFT)
 306         | (rhs->s * DESC_S_MASK)
 307         | (rhs->l << DESC_L_SHIFT)
 308         | (rhs->g * DESC_G_MASK)
 309         | (rhs->avl * DESC_AVL_MASK);
 310 }
 311
 312 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 313 {
 314     if (set)
 315         *kvm_reg = *qemu_reg;
 316     else
 317         *qemu_reg = *kvm_reg;
 318 }
 319
 320 static int kvm_getput_regs(CPUState *env, int set)
 321 {
 322     struct kvm_regs regs;
 323     int ret = 0;
 324
 325     if (!set) {
 326         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 327         if (ret < 0)
 328             return ret;
 329     }
 330
 331     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 332     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 333     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 334     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 335     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 336     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 337     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 338     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 339 #ifdef TARGET_X86_64
 340     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 341     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 342     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 343     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 344     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 345     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 346     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 347     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 348 #endif
 349
 350     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 351     kvm_getput_reg(&regs.rip, &env->eip, set);
 352
 353     if (set)
 354         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 355
 356     return ret;
 357 }
 358
 359 static int kvm_put_fpu(CPUState *env)
 360 {
 361     struct kvm_fpu fpu;
 362     int i;
 363
 364     memset(&fpu, 0, sizeof fpu);
 365     fpu.fsw = env->fpus & ~(7 << 11);
 366     fpu.fsw |= (env->fpstt & 7) << 11;
 367     fpu.fcw = env->fpuc;
 368     for (i = 0; i < 8; ++i)
 369         fpu.ftwx |= (!env->fptags[i]) << i;
 370     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 371     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 372     fpu.mxcsr = env->mxcsr;
 373
 374     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 375 }
 376
 377 static int kvm_put_sregs(CPUState *env)
 378 {
 379     struct kvm_sregs sregs;
 380
 381     memcpy(sregs.interrupt_bitmap,
 382            env->interrupt_bitmap,
 383            sizeof(sregs.interrupt_bitmap));
 384
 385     if ((env->eflags & VM_MASK)) {
 386             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 387             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 388             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 389             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 390             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 391             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 392     } else {
 393             set_seg(&sregs.cs, &env->segs[R_CS]);
 394             set_seg(&sregs.ds, &env->segs[R_DS]);
 395             set_seg(&sregs.es, &env->segs[R_ES]);
 396             set_seg(&sregs.fs, &env->segs[R_FS]);
 397             set_seg(&sregs.gs, &env->segs[R_GS]);
 398             set_seg(&sregs.ss, &env->segs[R_SS]);
 399
 400             if (env->cr[0] & CR0_PE_MASK) {
 401                 /* force ss cpl to cs cpl */
 402                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 403                         (sregs.cs.selector & 3);
 404                 sregs.ss.dpl = sregs.ss.selector & 3;
 405             }
 406     }
 407
 408     set_seg(&sregs.tr, &env->tr);
 409     set_seg(&sregs.ldt, &env->ldt);
 410
 411     sregs.idt.limit = env->idt.limit;
 412     sregs.idt.base = env->idt.base;
 413     sregs.gdt.limit = env->gdt.limit;
 414     sregs.gdt.base = env->gdt.base;
 415
 416     sregs.cr0 = env->cr[0];
 417     sregs.cr2 = env->cr[2];
 418     sregs.cr3 = env->cr[3];
 419     sregs.cr4 = env->cr[4];
 420
 421     sregs.cr8 = cpu_get_apic_tpr(env);
 422     sregs.apic_base = cpu_get_apic_base(env);
 423
 424     sregs.efer = env->efer;
 425
 426     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 427 }
 428
 429 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 430                               uint32_t index, uint64_t value)
 431 {
 432     entry->index = index;
 433     entry->data = value;
 434 }
 435
 436 static int kvm_put_msrs(CPUState *env)
 437 {
 438     struct {
 439         struct kvm_msrs info;
 440         struct kvm_msr_entry entries[100];
 441     } msr_data;
 442     struct kvm_msr_entry *msrs = msr_data.entries;
 443     int n = 0;
 444
 445     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 446     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 447     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 448     if (kvm_has_msr_star(env))
 449         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 450     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 451 #ifdef TARGET_X86_64
 452     /* FIXME if lm capable */
 453     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 454     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 455     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 456     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 457 #endif
 458     msr_data.info.nmsrs = n;
 459
 460     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 461
 462 }
 463
 464
 465 static int kvm_get_fpu(CPUState *env)
 466 {
 467     struct kvm_fpu fpu;
 468     int i, ret;
 469
 470     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 471     if (ret < 0)
 472         return ret;
 473
 474     env->fpstt = (fpu.fsw >> 11) & 7;
 475     env->fpus = fpu.fsw;
 476     env->fpuc = fpu.fcw;
 477     for (i = 0; i < 8; ++i)
 478         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 479     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 480     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 481     env->mxcsr = fpu.mxcsr;
 482
 483     return 0;
 484 }
 485
 486 static int kvm_get_sregs(CPUState *env)
 487 {
 488     struct kvm_sregs sregs;
 489     uint32_t hflags;
 490     int ret;
 491
 492     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 493     if (ret < 0)
 494         return ret;
 495
 496     memcpy(env->interrupt_bitmap,
 497            sregs.interrupt_bitmap,
 498            sizeof(sregs.interrupt_bitmap));
 499
 500     get_seg(&env->segs[R_CS], &sregs.cs);
 501     get_seg(&env->segs[R_DS], &sregs.ds);
 502     get_seg(&env->segs[R_ES], &sregs.es);
 503     get_seg(&env->segs[R_FS], &sregs.fs);
 504     get_seg(&env->segs[R_GS], &sregs.gs);
 505     get_seg(&env->segs[R_SS], &sregs.ss);
 506
 507     get_seg(&env->tr, &sregs.tr);
 508     get_seg(&env->ldt, &sregs.ldt);
 509
 510     env->idt.limit = sregs.idt.limit;
 511     env->idt.base = sregs.idt.base;
 512     env->gdt.limit = sregs.gdt.limit;
 513     env->gdt.base = sregs.gdt.base;
 514
 515     env->cr[0] = sregs.cr0;
 516     env->cr[2] = sregs.cr2;
 517     env->cr[3] = sregs.cr3;
 518     env->cr[4] = sregs.cr4;
 519
 520     cpu_set_apic_base(env, sregs.apic_base);
 521
 522     env->efer = sregs.efer;
 523     //cpu_set_apic_tpr(env, sregs.cr8);
 524
 525 #define HFLAG_COPY_MASK ~( \
 526                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 527                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 528                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 529                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 530
 531
 532
 533     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 534     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 535     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 536             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 537     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 538     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 539             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 540
 541     if (env->efer & MSR_EFER_LMA) {
 542         hflags |= HF_LMA_MASK;
 543     }
 544
 545     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 546         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 547     } else {
 548         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 549                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 550         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 551                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 552         if (!(env->cr[0] & CR0_PE_MASK) ||
 553                    (env->eflags & VM_MASK) ||
 554                    !(hflags & HF_CS32_MASK)) {
 555                 hflags |= HF_ADDSEG_MASK;
 556             } else {
 557                 hflags |= ((env->segs[R_DS].base |
 558                                 env->segs[R_ES].base |
 559                                 env->segs[R_SS].base) != 0) <<
 560                     HF_ADDSEG_SHIFT;
 561             }
 562     }
 563     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 564
 565     return 0;
 566 }
 567
 568 static int kvm_get_msrs(CPUState *env)
 569 {
 570     struct {
 571         struct kvm_msrs info;
 572         struct kvm_msr_entry entries[100];
 573     } msr_data;
 574     struct kvm_msr_entry *msrs = msr_data.entries;
 575     int ret, i, n;
 576
 577     n = 0;
 578     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 579     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 580     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 581     if (kvm_has_msr_star(env))
 582         msrs[n++].index = MSR_STAR;
 583     msrs[n++].index = MSR_IA32_TSC;
 584 #ifdef TARGET_X86_64
 585     /* FIXME lm_capable_kernel */
 586     msrs[n++].index = MSR_CSTAR;
 587     msrs[n++].index = MSR_KERNELGSBASE;
 588     msrs[n++].index = MSR_FMASK;
 589     msrs[n++].index = MSR_LSTAR;
 590 #endif
 591     msr_data.info.nmsrs = n;
 592     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 593     if (ret < 0)
 594         return ret;
 595
 596     for (i = 0; i < ret; i++) {
 597         switch (msrs[i].index) {
 598         case MSR_IA32_SYSENTER_CS:
 599             env->sysenter_cs = msrs[i].data;
 600             break;
 601         case MSR_IA32_SYSENTER_ESP:
 602             env->sysenter_esp = msrs[i].data;
 603             break;
 604         case MSR_IA32_SYSENTER_EIP:
 605             env->sysenter_eip = msrs[i].data;
 606             break;
 607         case MSR_STAR:
 608             env->star = msrs[i].data;
 609             break;
 610 #ifdef TARGET_X86_64
 611         case MSR_CSTAR:
 612             env->cstar = msrs[i].data;
 613             break;
 614         case MSR_KERNELGSBASE:
 615             env->kernelgsbase = msrs[i].data;
 616             break;
 617         case MSR_FMASK:
 618             env->fmask = msrs[i].data;
 619             break;
 620         case MSR_LSTAR:
 621             env->lstar = msrs[i].data;
 622             break;
 623 #endif
 624         case MSR_IA32_TSC:
 625             env->tsc = msrs[i].data;
 626             break;
 627         }
 628     }
 629
 630     return 0;
 631 }
 632
 633 int kvm_arch_put_registers(CPUState *env)
 634 {
 635     int ret;
 636
 637     ret = kvm_getput_regs(env, 1);
 638     if (ret < 0)
 639         return ret;
 640
 641     ret = kvm_put_fpu(env);
 642     if (ret < 0)
 643         return ret;
 644
 645     ret = kvm_put_sregs(env);
 646     if (ret < 0)
 647         return ret;
 648
 649     ret = kvm_put_msrs(env);
 650     if (ret < 0)
 651         return ret;
 652
 653     ret = kvm_put_mp_state(env);
 654     if (ret < 0)
 655         return ret;
 656
 657     ret = kvm_get_mp_state(env);
 658     if (ret < 0)
 659         return ret;
 660
 661     return 0;
 662 }
 663
 664 int kvm_arch_get_registers(CPUState *env)
 665 {
 666     int ret;
 667
 668     ret = kvm_getput_regs(env, 0);
 669     if (ret < 0)
 670         return ret;
 671
 672     ret = kvm_get_fpu(env);
 673     if (ret < 0)
 674         return ret;
 675
 676     ret = kvm_get_sregs(env);
 677     if (ret < 0)
 678         return ret;
 679
 680     ret = kvm_get_msrs(env);
 681     if (ret < 0)
 682         return ret;
 683
 684     return 0;
 685 }
 686
 687 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 688 {
 689     /* Try to inject an interrupt if the guest can accept it */
 690     if (run->ready_for_interrupt_injection &&
 691         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 692         (env->eflags & IF_MASK)) {
 693         int irq;
 694
 695         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 696         irq = cpu_get_pic_interrupt(env);
 697         if (irq >= 0) {
 698             struct kvm_interrupt intr;
 699             intr.irq = irq;
 700             /* FIXME: errors */
 701             dprintf("injected interrupt %d\n", irq);
 702             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 703         }
 704     }
 705
 706     /* If we have an interrupt but the guest is not ready to receive an
 707      * interrupt, request an interrupt window exit.  This will
 708      * cause a return to userspace as soon as the guest is ready to
 709      * receive interrupts. */
 710     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 711         run->request_interrupt_window = 1;
 712     else
 713         run->request_interrupt_window = 0;
 714
 715     dprintf("setting tpr\n");
 716     run->cr8 = cpu_get_apic_tpr(env);
 717
 718     return 0;
 719 }
 720
 721 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 722 {
 723     if (run->if_flag)
 724         env->eflags |= IF_MASK;
 725     else
 726         env->eflags &= ~IF_MASK;
 727
 728     cpu_set_apic_tpr(env, run->cr8);
 729     cpu_set_apic_base(env, run->apic_base);
 730
 731     return 0;
 732 }
 733
 734 static int kvm_handle_halt(CPUState *env)
 735 {
 736     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 737           (env->eflags & IF_MASK)) &&
 738         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 739         env->halted = 1;
 740         env->exception_index = EXCP_HLT;
 741         return 0;
 742     }
 743
 744     return 1;
 745 }
 746
 747 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 748 {
 749     int ret = 0;
 750
 751     switch (run->exit_reason) {
 752     case KVM_EXIT_HLT:
 753         dprintf("handle_hlt\n");
 754         ret = kvm_handle_halt(env);
 755         break;
 756     }
 757
 758     return ret;
 759 }
 760
 761 #ifdef KVM_CAP_SET_GUEST_DEBUG
 762 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 763 {
 764     const static uint8_t int3 = 0xcc;
 765
 766     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 767         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 768         return -EINVAL;
 769     return 0;
 770 }
 771
 772 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 773 {
 774     uint8_t int3;
 775
 776     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 777         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 778         return -EINVAL;
 779     return 0;
 780 }
 781
 782 static struct {
 783     target_ulong addr;
 784     int len;
 785     int type;
 786 } hw_breakpoint[4];
 787
 788 static int nb_hw_breakpoint;
 789
 790 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 791 {
 792     int n;
 793
 794     for (n = 0; n < nb_hw_breakpoint; n++)
 795         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 796             (hw_breakpoint[n].len == len || len == -1))
 797             return n;
 798     return -1;
 799 }
 800
 801 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 802                                   target_ulong len, int type)
 803 {
 804     switch (type) {
 805     case GDB_BREAKPOINT_HW:
 806         len = 1;
 807         break;
 808     case GDB_WATCHPOINT_WRITE:
 809     case GDB_WATCHPOINT_ACCESS:
 810         switch (len) {
 811         case 1:
 812             break;
 813         case 2:
 814         case 4:
 815         case 8:
 816             if (addr & (len - 1))
 817                 return -EINVAL;
 818             break;
 819         default:
 820             return -EINVAL;
 821         }
 822         break;
 823     default:
 824         return -ENOSYS;
 825     }
 826
 827     if (nb_hw_breakpoint == 4)
 828         return -ENOBUFS;
 829
 830     if (find_hw_breakpoint(addr, len, type) >= 0)
 831         return -EEXIST;
 832
 833     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 834     hw_breakpoint[nb_hw_breakpoint].len = len;
 835     hw_breakpoint[nb_hw_breakpoint].type = type;
 836     nb_hw_breakpoint++;
 837
 838     return 0;
 839 }
 840
 841 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 842                                   target_ulong len, int type)
 843 {
 844     int n;
 845
 846     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 847     if (n < 0)
 848         return -ENOENT;
 849
 850     nb_hw_breakpoint--;
 851     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 852
 853     return 0;
 854 }
 855
 856 void kvm_arch_remove_all_hw_breakpoints(void)
 857 {
 858     nb_hw_breakpoint = 0;
 859 }
 860
 861 static CPUWatchpoint hw_watchpoint;
 862
 863 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 864 {
 865     int handle = 0;
 866     int n;
 867
 868     if (arch_info->exception == 1) {
 869         if (arch_info->dr6 & (1 << 14)) {
 870             if (cpu_single_env->singlestep_enabled)
 871                 handle = 1;
 872         } else {
 873             for (n = 0; n < 4; n++)
 874                 if (arch_info->dr6 & (1 << n))
 875                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 876                     case 0x0:
 877                         handle = 1;
 878                         break;
 879                     case 0x1:
 880                         handle = 1;
 881                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 882                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 883                         hw_watchpoint.flags = BP_MEM_WRITE;
 884                         break;
 885                     case 0x3:
 886                         handle = 1;
 887                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 888                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 889                         hw_watchpoint.flags = BP_MEM_ACCESS;
 890                         break;
 891                     }
 892         }
 893     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
 894         handle = 1;
 895
 896     if (!handle)
 897         kvm_update_guest_debug(cpu_single_env,
 898                         (arch_info->exception == 1) ?
 899                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 900
 901     return handle;
 902 }
 903
 904 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 905 {
 906     const uint8_t type_code[] = {
 907         [GDB_BREAKPOINT_HW] = 0x0,
 908         [GDB_WATCHPOINT_WRITE] = 0x1,
 909         [GDB_WATCHPOINT_ACCESS] = 0x3
 910     };
 911     const uint8_t len_code[] = {
 912         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 913     };
 914     int n;
 915
 916     if (kvm_sw_breakpoints_active(env))
 917         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 918
 919     if (nb_hw_breakpoint > 0) {
 920         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 921         dbg->arch.debugreg[7] = 0x0600;
 922         for (n = 0; n < nb_hw_breakpoint; n++) {
 923             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 924             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 925                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 926                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 927         }
 928     }
 929 }
 930 #endif /* KVM_CAP_SET_GUEST_DEBUG */