2 * Arm PrimeCell PL011 UART
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
12 #include "sysemu/char.h"
15 #define TYPE_PL011 "pl011"
16 #define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
18 typedef struct PL011State
{
19 SysBusDevice parent_obj
;
30 uint32_t read_fifo
[16];
40 const unsigned char *id
;
43 #define PL011_INT_TX 0x20
44 #define PL011_INT_RX 0x10
46 #define PL011_FLAG_TXFE 0x80
47 #define PL011_FLAG_RXFF 0x40
48 #define PL011_FLAG_TXFF 0x20
49 #define PL011_FLAG_RXFE 0x10
51 static const unsigned char pl011_id_arm
[8] =
52 { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
53 static const unsigned char pl011_id_luminary
[8] =
54 { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
56 static void pl011_update(PL011State
*s
)
60 flags
= s
->int_level
& s
->int_enabled
;
61 qemu_set_irq(s
->irq
, flags
!= 0);
64 static uint64_t pl011_read(void *opaque
, hwaddr offset
,
67 PL011State
*s
= (PL011State
*)opaque
;
70 if (offset
>= 0xfe0 && offset
< 0x1000) {
71 return s
->id
[(offset
- 0xfe0) >> 2];
73 switch (offset
>> 2) {
75 s
->flags
&= ~PL011_FLAG_RXFF
;
76 c
= s
->read_fifo
[s
->read_pos
];
77 if (s
->read_count
> 0) {
79 if (++s
->read_pos
== 16)
82 if (s
->read_count
== 0) {
83 s
->flags
|= PL011_FLAG_RXFE
;
85 if (s
->read_count
== s
->read_trigger
- 1)
86 s
->int_level
&= ~ PL011_INT_RX
;
90 qemu_chr_accept_input(s
->chr
);
97 case 8: /* UARTILPR */
99 case 9: /* UARTIBRD */
101 case 10: /* UARTFBRD */
103 case 11: /* UARTLCR_H */
105 case 12: /* UARTCR */
107 case 13: /* UARTIFLS */
109 case 14: /* UARTIMSC */
110 return s
->int_enabled
;
111 case 15: /* UARTRIS */
113 case 16: /* UARTMIS */
114 return s
->int_level
& s
->int_enabled
;
115 case 18: /* UARTDMACR */
118 qemu_log_mask(LOG_GUEST_ERROR
,
119 "pl011_read: Bad offset %x\n", (int)offset
);
124 static void pl011_set_read_trigger(PL011State
*s
)
127 /* The docs say the RX interrupt is triggered when the FIFO exceeds
128 the threshold. However linux only reads the FIFO in response to an
129 interrupt. Triggering the interrupt when the FIFO is non-empty seems
130 to make things work. */
132 s
->read_trigger
= (s
->ifl
>> 1) & 0x1c;
138 static void pl011_write(void *opaque
, hwaddr offset
,
139 uint64_t value
, unsigned size
)
141 PL011State
*s
= (PL011State
*)opaque
;
144 switch (offset
>> 2) {
146 /* ??? Check if transmitter is enabled. */
149 /* XXX this blocks entire thread. Rewrite to use
150 * qemu_chr_fe_write and background I/O callbacks */
151 qemu_chr_fe_write_all(s
->chr
, &ch
, 1);
152 s
->int_level
|= PL011_INT_TX
;
155 case 1: /* UARTRSR/UARTECR */
159 /* Writes to Flag register are ignored. */
161 case 8: /* UARTUARTILPR */
164 case 9: /* UARTIBRD */
167 case 10: /* UARTFBRD */
170 case 11: /* UARTLCR_H */
171 /* Reset the FIFO state on FIFO enable or disable */
172 if ((s
->lcr
^ value
) & 0x10) {
177 pl011_set_read_trigger(s
);
179 case 12: /* UARTCR */
180 /* ??? Need to implement the enable and loopback bits. */
183 case 13: /* UARTIFS */
185 pl011_set_read_trigger(s
);
187 case 14: /* UARTIMSC */
188 s
->int_enabled
= value
;
191 case 17: /* UARTICR */
192 s
->int_level
&= ~value
;
195 case 18: /* UARTDMACR */
198 qemu_log_mask(LOG_UNIMP
, "pl011: DMA not implemented\n");
202 qemu_log_mask(LOG_GUEST_ERROR
,
203 "pl011_write: Bad offset %x\n", (int)offset
);
207 static int pl011_can_receive(void *opaque
)
209 PL011State
*s
= (PL011State
*)opaque
;
212 return s
->read_count
< 16;
214 return s
->read_count
< 1;
217 static void pl011_put_fifo(void *opaque
, uint32_t value
)
219 PL011State
*s
= (PL011State
*)opaque
;
222 slot
= s
->read_pos
+ s
->read_count
;
225 s
->read_fifo
[slot
] = value
;
227 s
->flags
&= ~PL011_FLAG_RXFE
;
228 if (!(s
->lcr
& 0x10) || s
->read_count
== 16) {
229 s
->flags
|= PL011_FLAG_RXFF
;
231 if (s
->read_count
== s
->read_trigger
) {
232 s
->int_level
|= PL011_INT_RX
;
237 static void pl011_receive(void *opaque
, const uint8_t *buf
, int size
)
239 pl011_put_fifo(opaque
, *buf
);
242 static void pl011_event(void *opaque
, int event
)
244 if (event
== CHR_EVENT_BREAK
)
245 pl011_put_fifo(opaque
, 0x400);
248 static const MemoryRegionOps pl011_ops
= {
250 .write
= pl011_write
,
251 .endianness
= DEVICE_NATIVE_ENDIAN
,
254 static const VMStateDescription vmstate_pl011
= {
257 .minimum_version_id
= 2,
258 .fields
= (VMStateField
[]) {
259 VMSTATE_UINT32(readbuff
, PL011State
),
260 VMSTATE_UINT32(flags
, PL011State
),
261 VMSTATE_UINT32(lcr
, PL011State
),
262 VMSTATE_UINT32(rsr
, PL011State
),
263 VMSTATE_UINT32(cr
, PL011State
),
264 VMSTATE_UINT32(dmacr
, PL011State
),
265 VMSTATE_UINT32(int_enabled
, PL011State
),
266 VMSTATE_UINT32(int_level
, PL011State
),
267 VMSTATE_UINT32_ARRAY(read_fifo
, PL011State
, 16),
268 VMSTATE_UINT32(ilpr
, PL011State
),
269 VMSTATE_UINT32(ibrd
, PL011State
),
270 VMSTATE_UINT32(fbrd
, PL011State
),
271 VMSTATE_UINT32(ifl
, PL011State
),
272 VMSTATE_INT32(read_pos
, PL011State
),
273 VMSTATE_INT32(read_count
, PL011State
),
274 VMSTATE_INT32(read_trigger
, PL011State
),
275 VMSTATE_END_OF_LIST()
279 static Property pl011_properties
[] = {
280 DEFINE_PROP_CHR("chardev", PL011State
, chr
),
281 DEFINE_PROP_END_OF_LIST(),
284 static void pl011_init(Object
*obj
)
286 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
287 PL011State
*s
= PL011(obj
);
289 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pl011_ops
, s
, "pl011", 0x1000);
290 sysbus_init_mmio(sbd
, &s
->iomem
);
291 sysbus_init_irq(sbd
, &s
->irq
);
298 s
->id
= pl011_id_arm
;
301 static void pl011_realize(DeviceState
*dev
, Error
**errp
)
303 PL011State
*s
= PL011(dev
);
306 qemu_chr_add_handlers(s
->chr
, pl011_can_receive
, pl011_receive
,
311 static void pl011_class_init(ObjectClass
*oc
, void *data
)
313 DeviceClass
*dc
= DEVICE_CLASS(oc
);
315 dc
->realize
= pl011_realize
;
316 dc
->vmsd
= &vmstate_pl011
;
317 dc
->props
= pl011_properties
;
320 static const TypeInfo pl011_arm_info
= {
322 .parent
= TYPE_SYS_BUS_DEVICE
,
323 .instance_size
= sizeof(PL011State
),
324 .instance_init
= pl011_init
,
325 .class_init
= pl011_class_init
,
328 static void pl011_luminary_init(Object
*obj
)
330 PL011State
*s
= PL011(obj
);
332 s
->id
= pl011_id_luminary
;
335 static const TypeInfo pl011_luminary_info
= {
336 .name
= "pl011_luminary",
337 .parent
= TYPE_PL011
,
338 .instance_init
= pl011_luminary_init
,
341 static void pl011_register_types(void)
343 type_register_static(&pl011_arm_info
);
344 type_register_static(&pl011_luminary_info
);
347 type_init(pl011_register_types
)