2 * Copyright (c) 2019 Red Hat, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2 or later, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "exec/hwaddr.h"
21 #include "qemu/notify.h"
23 #include "hw/i386/topology.h"
24 #include "hw/boards.h"
26 #include "hw/isa/isa.h"
27 #include "hw/i386/ioapic.h"
28 #include "qom/object.h"
30 struct X86MachineClass
{
36 /* TSC rate migration: */
38 /* use DMA capable linuxboot option rom */
39 bool fwcfg_dma_enabled
;
42 struct X86MachineState
{
48 /* Pointers to devices and objects: */
53 GMappedFile
*initrd_mapped_file
;
54 HotplugHandler
*acpi_dev
;
56 /* RAM information (sizes, addresses, configuration): */
57 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
59 /* CPU and apic information: */
60 bool apic_xrupt_override
;
61 unsigned pci_irq_mask
;
62 unsigned apic_id_limit
;
64 SgxEPCList
*sgx_epc_list
;
72 * Address space used by IOAPIC device. All IOAPIC interrupts
73 * will be translated to MSI messages in the address space.
75 AddressSpace
*ioapic_as
;
78 * Ratelimit enforced on detected bus locks in guest.
79 * The default value of the bus_lock_ratelimit is 0 per second,
80 * which means no limitation on the guest's bus locks.
82 uint64_t bus_lock_ratelimit
;
85 #define X86_MACHINE_SMM "smm"
86 #define X86_MACHINE_ACPI "acpi"
87 #define X86_MACHINE_OEM_ID "x-oem-id"
88 #define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id"
89 #define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit"
91 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
92 OBJECT_DECLARE_TYPE(X86MachineState
, X86MachineClass
, X86_MACHINE
)
94 void init_topo_info(X86CPUTopoInfo
*topo_info
, const X86MachineState
*x86ms
);
96 uint32_t x86_cpu_apic_id_from_index(X86MachineState
*pcms
,
97 unsigned int cpu_index
);
99 void x86_cpu_new(X86MachineState
*pcms
, int64_t apic_id
, Error
**errp
);
100 void x86_cpus_init(X86MachineState
*pcms
, int default_cpu_version
);
101 CpuInstanceProperties
x86_cpu_index_to_props(MachineState
*ms
,
103 int64_t x86_get_default_cpu_node_id(const MachineState
*ms
, int idx
);
104 const CPUArchIdList
*x86_possible_cpu_arch_ids(MachineState
*ms
);
105 CPUArchId
*x86_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
);
106 void x86_rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
);
107 void x86_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
108 DeviceState
*dev
, Error
**errp
);
109 void x86_cpu_plug(HotplugHandler
*hotplug_dev
,
110 DeviceState
*dev
, Error
**errp
);
111 void x86_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
112 DeviceState
*dev
, Error
**errp
);
113 void x86_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
114 DeviceState
*dev
, Error
**errp
);
116 void x86_bios_rom_init(MachineState
*ms
, const char *default_firmware
,
117 MemoryRegion
*rom_memory
, bool isapc_ram_fw
);
119 void x86_load_linux(X86MachineState
*x86ms
,
124 bool x86_machine_is_smm_enabled(const X86MachineState
*x86ms
);
125 bool x86_machine_is_acpi_enabled(const X86MachineState
*x86ms
);
127 /* Global System Interrupts */
129 #define GSI_NUM_PINS IOAPIC_NUM_PINS
130 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
132 typedef struct GSIState
{
133 qemu_irq i8259_irq
[ISA_NUM_IRQS
];
134 qemu_irq ioapic_irq
[IOAPIC_NUM_PINS
];
135 qemu_irq ioapic2_irq
[IOAPIC_NUM_PINS
];
138 qemu_irq
x86_allocate_cpu_irq(void);
139 void gsi_handler(void *opaque
, int n
, int level
);
140 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
);
141 DeviceState
*ioapic_init_secondary(GSIState
*gsi_state
);
144 void x86_firmware_configure(void *ptr
, int size
);