target/xtensa/xtensa-semi.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "cpu.h"
  30 #include "chardev/char-fe.h"
  31 #include "exec/helper-proto.h"
  32 #include "exec/semihost.h"
  33 #include "qapi/error.h"
  34 #include "qemu/log.h"
  35 #include "sysemu/sysemu.h"
  36
  37 static CharBackend *xtensa_sim_console;
  38
  39 enum {
  40     TARGET_SYS_exit = 1,
  41     TARGET_SYS_read = 3,
  42     TARGET_SYS_write = 4,
  43     TARGET_SYS_open = 5,
  44     TARGET_SYS_close = 6,
  45     TARGET_SYS_lseek = 19,
  46     TARGET_SYS_select_one = 29,
  47
  48     TARGET_SYS_argc = 1000,
  49     TARGET_SYS_argv_sz = 1001,
  50     TARGET_SYS_argv = 1002,
  51     TARGET_SYS_memset = 1004,
  52 };
  53
  54 enum {
  55     SELECT_ONE_READ   = 1,
  56     SELECT_ONE_WRITE  = 2,
  57     SELECT_ONE_EXCEPT = 3,
  58 };
  59
  60 enum {
  61     TARGET_EPERM        =  1,
  62     TARGET_ENOENT       =  2,
  63     TARGET_ESRCH        =  3,
  64     TARGET_EINTR        =  4,
  65     TARGET_EIO          =  5,
  66     TARGET_ENXIO        =  6,
  67     TARGET_E2BIG        =  7,
  68     TARGET_ENOEXEC      =  8,
  69     TARGET_EBADF        =  9,
  70     TARGET_ECHILD       = 10,
  71     TARGET_EAGAIN       = 11,
  72     TARGET_ENOMEM       = 12,
  73     TARGET_EACCES       = 13,
  74     TARGET_EFAULT       = 14,
  75     TARGET_ENOTBLK      = 15,
  76     TARGET_EBUSY        = 16,
  77     TARGET_EEXIST       = 17,
  78     TARGET_EXDEV        = 18,
  79     TARGET_ENODEV       = 19,
  80     TARGET_ENOTDIR      = 20,
  81     TARGET_EISDIR       = 21,
  82     TARGET_EINVAL       = 22,
  83     TARGET_ENFILE       = 23,
  84     TARGET_EMFILE       = 24,
  85     TARGET_ENOTTY       = 25,
  86     TARGET_ETXTBSY      = 26,
  87     TARGET_EFBIG        = 27,
  88     TARGET_ENOSPC       = 28,
  89     TARGET_ESPIPE       = 29,
  90     TARGET_EROFS        = 30,
  91     TARGET_EMLINK       = 31,
  92     TARGET_EPIPE        = 32,
  93     TARGET_EDOM         = 33,
  94     TARGET_ERANGE       = 34,
  95     TARGET_ENOSYS       = 88,
  96     TARGET_ELOOP        = 92,
  97 };
  98
  99 static uint32_t errno_h2g(int host_errno)
 100 {
 101     static const uint32_t guest_errno[] = {
 102         [EPERM]         = TARGET_EPERM,
 103         [ENOENT]        = TARGET_ENOENT,
 104         [ESRCH]         = TARGET_ESRCH,
 105         [EINTR]         = TARGET_EINTR,
 106         [EIO]           = TARGET_EIO,
 107         [ENXIO]         = TARGET_ENXIO,
 108         [E2BIG]         = TARGET_E2BIG,
 109         [ENOEXEC]       = TARGET_ENOEXEC,
 110         [EBADF]         = TARGET_EBADF,
 111         [ECHILD]        = TARGET_ECHILD,
 112         [EAGAIN]        = TARGET_EAGAIN,
 113         [ENOMEM]        = TARGET_ENOMEM,
 114         [EACCES]        = TARGET_EACCES,
 115         [EFAULT]        = TARGET_EFAULT,
 116 #ifdef ENOTBLK
 117         [ENOTBLK]       = TARGET_ENOTBLK,
 118 #endif
 119         [EBUSY]         = TARGET_EBUSY,
 120         [EEXIST]        = TARGET_EEXIST,
 121         [EXDEV]         = TARGET_EXDEV,
 122         [ENODEV]        = TARGET_ENODEV,
 123         [ENOTDIR]       = TARGET_ENOTDIR,
 124         [EISDIR]        = TARGET_EISDIR,
 125         [EINVAL]        = TARGET_EINVAL,
 126         [ENFILE]        = TARGET_ENFILE,
 127         [EMFILE]        = TARGET_EMFILE,
 128         [ENOTTY]        = TARGET_ENOTTY,
 129 #ifdef ETXTBSY
 130         [ETXTBSY]       = TARGET_ETXTBSY,
 131 #endif
 132         [EFBIG]         = TARGET_EFBIG,
 133         [ENOSPC]        = TARGET_ENOSPC,
 134         [ESPIPE]        = TARGET_ESPIPE,
 135         [EROFS]         = TARGET_EROFS,
 136         [EMLINK]        = TARGET_EMLINK,
 137         [EPIPE]         = TARGET_EPIPE,
 138         [EDOM]          = TARGET_EDOM,
 139         [ERANGE]        = TARGET_ERANGE,
 140         [ENOSYS]        = TARGET_ENOSYS,
 141 #ifdef ELOOP
 142         [ELOOP]         = TARGET_ELOOP,
 143 #endif
 144     };
 145
 146     if (host_errno == 0) {
 147         return 0;
 148     } else if (host_errno > 0 && host_errno < ARRAY_SIZE(guest_errno) &&
 149             guest_errno[host_errno]) {
 150         return guest_errno[host_errno];
 151     } else {
 152         return TARGET_EINVAL;
 153     }
 154 }
 155
 156 void xtensa_sim_open_console(Chardev *chr)
 157 {
 158     static CharBackend console;
 159
 160     qemu_chr_fe_init(&console, chr, &error_abort);
 161     qemu_chr_fe_set_handlers(&console, NULL, NULL, NULL, NULL, NULL, NULL, true);
 162     xtensa_sim_console = &console;
 163 }
 164
 165 void HELPER(simcall)(CPUXtensaState *env)
 166 {
 167     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 168     uint32_t *regs = env->regs;
 169
 170     switch (regs[2]) {
 171     case TARGET_SYS_exit:
 172         qemu_log("exit(%d) simcall\n", regs[3]);
 173         exit(regs[3]);
 174         break;
 175
 176     case TARGET_SYS_read:
 177     case TARGET_SYS_write:
 178         {
 179             bool is_write = regs[2] == TARGET_SYS_write;
 180             uint32_t fd = regs[3];
 181             uint32_t vaddr = regs[4];
 182             uint32_t len = regs[5];
 183             uint32_t len_done = 0;
 184
 185             while (len > 0) {
 186                 hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr);
 187                 uint32_t page_left =
 188                     TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
 189                 uint32_t io_sz = page_left < len ? page_left : len;
 190                 hwaddr sz = io_sz;
 191                 void *buf = cpu_physical_memory_map(paddr, &sz, !is_write);
 192                 uint32_t io_done;
 193                 bool error = false;
 194
 195                 if (buf) {
 196                     vaddr += io_sz;
 197                     len -= io_sz;
 198                     if (fd < 3 && xtensa_sim_console) {
 199                         if (is_write && (fd == 1 || fd == 2)) {
 200                             io_done = qemu_chr_fe_write_all(xtensa_sim_console,
 201                                                             buf, io_sz);
 202                             regs[3] = errno_h2g(errno);
 203                         } else {
 204                             qemu_log_mask(LOG_GUEST_ERROR,
 205                                           "%s fd %d is not supported with chardev console\n",
 206                                           is_write ?
 207                                           "writing to" : "reading from", fd);
 208                             io_done = -1;
 209                             regs[3] = TARGET_EBADF;
 210                         }
 211                     } else {
 212                         io_done = is_write ?
 213                             write(fd, buf, io_sz) :
 214                             read(fd, buf, io_sz);
 215                         regs[3] = errno_h2g(errno);
 216                     }
 217                     if (io_done == -1) {
 218                         error = true;
 219                         io_done = 0;
 220                     }
 221                     cpu_physical_memory_unmap(buf, sz, !is_write, io_done);
 222                 } else {
 223                     error = true;
 224                     regs[3] = TARGET_EINVAL;
 225                     break;
 226                 }
 227                 if (error) {
 228                     if (!len_done) {
 229                         len_done = -1;
 230                     }
 231                     break;
 232                 }
 233                 len_done += io_done;
 234                 if (io_done < io_sz) {
 235                     break;
 236                 }
 237             }
 238             regs[2] = len_done;
 239         }
 240         break;
 241
 242     case TARGET_SYS_open:
 243         {
 244             char name[1024];
 245             int rc;
 246             int i;
 247
 248             for (i = 0; i < ARRAY_SIZE(name); ++i) {
 249                 rc = cpu_memory_rw_debug(cs, regs[3] + i,
 250                                          (uint8_t *)name + i, 1, 0);
 251                 if (rc != 0 || name[i] == 0) {
 252                     break;
 253                 }
 254             }
 255
 256             if (rc == 0 && i < ARRAY_SIZE(name)) {
 257                 regs[2] = open(name, regs[4], regs[5]);
 258                 regs[3] = errno_h2g(errno);
 259             } else {
 260                 regs[2] = -1;
 261                 regs[3] = TARGET_EINVAL;
 262             }
 263         }
 264         break;
 265
 266     case TARGET_SYS_close:
 267         if (regs[3] < 3) {
 268             regs[2] = regs[3] = 0;
 269         } else {
 270             regs[2] = close(regs[3]);
 271             regs[3] = errno_h2g(errno);
 272         }
 273         break;
 274
 275     case TARGET_SYS_lseek:
 276         regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]);
 277         regs[3] = errno_h2g(errno);
 278         break;
 279
 280     case TARGET_SYS_select_one:
 281         {
 282             uint32_t fd = regs[3];
 283             uint32_t rq = regs[4];
 284             uint32_t target_tv = regs[5];
 285             uint32_t target_tvv[2];
 286
 287             struct timeval tv = {0};
 288
 289             if (target_tv) {
 290                 cpu_memory_rw_debug(cs, target_tv,
 291                         (uint8_t *)target_tvv, sizeof(target_tvv), 0);
 292                 tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
 293                 tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
 294             }
 295             if (fd < 3 && xtensa_sim_console) {
 296                 if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) {
 297                     regs[2] = 1;
 298                 } else {
 299                     regs[2] = 0;
 300                 }
 301                 regs[3] = 0;
 302             } else {
 303                 fd_set fdset;
 304
 305                 FD_ZERO(&fdset);
 306                 FD_SET(fd, &fdset);
 307                 regs[2] = select(fd + 1,
 308                                  rq == SELECT_ONE_READ   ? &fdset : NULL,
 309                                  rq == SELECT_ONE_WRITE  ? &fdset : NULL,
 310                                  rq == SELECT_ONE_EXCEPT ? &fdset : NULL,
 311                                  target_tv ? &tv : NULL);
 312                 regs[3] = errno_h2g(errno);
 313             }
 314         }
 315         break;
 316
 317     case TARGET_SYS_argc:
 318         regs[2] = semihosting_get_argc();
 319         regs[3] = 0;
 320         break;
 321
 322     case TARGET_SYS_argv_sz:
 323         {
 324             int argc = semihosting_get_argc();
 325             int sz = (argc + 1) * sizeof(uint32_t);
 326             int i;
 327
 328             for (i = 0; i < argc; ++i) {
 329                 sz += 1 + strlen(semihosting_get_arg(i));
 330             }
 331             regs[2] = sz;
 332             regs[3] = 0;
 333         }
 334         break;
 335
 336     case TARGET_SYS_argv:
 337         {
 338             int argc = semihosting_get_argc();
 339             int str_offset = (argc + 1) * sizeof(uint32_t);
 340             int i;
 341             uint32_t argptr;
 342
 343             for (i = 0; i < argc; ++i) {
 344                 const char *str = semihosting_get_arg(i);
 345                 int str_size = strlen(str) + 1;
 346
 347                 argptr = tswap32(regs[3] + str_offset);
 348
 349                 cpu_memory_rw_debug(cs,
 350                                     regs[3] + i * sizeof(uint32_t),
 351                                     (uint8_t *)&argptr, sizeof(argptr), 1);
 352                 cpu_memory_rw_debug(cs,
 353                                     regs[3] + str_offset,
 354                                     (uint8_t *)str, str_size, 1);
 355                 str_offset += str_size;
 356             }
 357             argptr = 0;
 358             cpu_memory_rw_debug(cs,
 359                                 regs[3] + i * sizeof(uint32_t),
 360                                 (uint8_t *)&argptr, sizeof(argptr), 1);
 361             regs[3] = 0;
 362         }
 363         break;
 364
 365     case TARGET_SYS_memset:
 366         {
 367             uint32_t base = regs[3];
 368             uint32_t sz = regs[5];
 369
 370             while (sz) {
 371                 hwaddr len = sz;
 372                 void *buf = cpu_physical_memory_map(base, &len, 1);
 373
 374                 if (buf && len) {
 375                     memset(buf, regs[4], len);
 376                     cpu_physical_memory_unmap(buf, len, 1, len);
 377                 } else {
 378                     len = 1;
 379                 }
 380                 base += len;
 381                 sz -= len;
 382             }
 383             regs[2] = regs[3];
 384             regs[3] = 0;
 385         }
 386         break;
 387
 388     default:
 389         qemu_log_mask(LOG_GUEST_ERROR, "%s(%d): not implemented\n", __func__, regs[2]);
 390         regs[2] = -1;
 391         regs[3] = TARGET_ENOSYS;
 392         break;
 393     }
 394 }