3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41 #include "exec/translator.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
46 #include "trace-tcg.h"
50 /* is_jmp field values */
51 #define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */
54 const XtensaConfig
*config
;
63 int singlestep_enabled
;
67 bool sar_m32_allocated
;
79 xtensa_insnbuf insnbuf
;
80 xtensa_insnbuf slotbuf
;
83 static TCGv_i32 cpu_pc
;
84 static TCGv_i32 cpu_R
[16];
85 static TCGv_i32 cpu_FR
[16];
86 static TCGv_i32 cpu_SR
[256];
87 static TCGv_i32 cpu_UR
[256];
89 #include "exec/gen-icount.h"
91 typedef struct XtensaReg
{
103 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
105 .opt_bits = XTENSA_OPTION_BIT(opt), \
109 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
111 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
117 #define XTENSA_REG_BITS(regname, opt) \
118 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
120 static const XtensaReg sregnames
[256] = {
121 [LBEG
] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP
),
122 [LEND
] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP
),
123 [LCOUNT
] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP
),
124 [SAR
] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL
),
125 [BR
] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN
),
126 [LITBASE
] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R
),
127 [SCOMPARE1
] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE
),
128 [ACCLO
] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16
),
129 [ACCHI
] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16
),
130 [MR
] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16
),
131 [MR
+ 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16
),
132 [MR
+ 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16
),
133 [MR
+ 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16
),
134 [WINDOW_BASE
] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER
),
135 [WINDOW_START
] = XTENSA_REG("WINDOW_START",
136 XTENSA_OPTION_WINDOWED_REGISTER
),
137 [PTEVADDR
] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU
),
138 [MMID
] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL
),
139 [RASID
] = XTENSA_REG("RASID", XTENSA_OPTION_MMU
),
140 [ITLBCFG
] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU
),
141 [DTLBCFG
] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU
),
142 [IBREAKENABLE
] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG
),
143 [MEMCTL
] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL
),
144 [CACHEATTR
] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR
),
145 [ATOMCTL
] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL
),
146 [DDR
] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG
),
147 [IBREAKA
] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG
),
148 [IBREAKA
+ 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG
),
149 [DBREAKA
] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG
),
150 [DBREAKA
+ 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG
),
151 [DBREAKC
] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG
),
152 [DBREAKC
+ 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG
),
153 [CONFIGID0
] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL
, SR_R
),
154 [EPC1
] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION
),
155 [EPC1
+ 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
156 [EPC1
+ 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
157 [EPC1
+ 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
158 [EPC1
+ 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
159 [EPC1
+ 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
160 [EPC1
+ 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
161 [DEPC
] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION
),
162 [EPS2
] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
163 [EPS2
+ 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
164 [EPS2
+ 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
165 [EPS2
+ 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
166 [EPS2
+ 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
167 [EPS2
+ 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
168 [CONFIGID1
] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL
, SR_R
),
169 [EXCSAVE1
] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION
),
170 [EXCSAVE1
+ 1] = XTENSA_REG("EXCSAVE2",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
172 [EXCSAVE1
+ 2] = XTENSA_REG("EXCSAVE3",
173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
174 [EXCSAVE1
+ 3] = XTENSA_REG("EXCSAVE4",
175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
176 [EXCSAVE1
+ 4] = XTENSA_REG("EXCSAVE5",
177 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
178 [EXCSAVE1
+ 5] = XTENSA_REG("EXCSAVE6",
179 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
180 [EXCSAVE1
+ 6] = XTENSA_REG("EXCSAVE7",
181 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
182 [CPENABLE
] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR
),
183 [INTSET
] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT
, SR_RW
),
184 [INTCLEAR
] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT
, SR_W
),
185 [INTENABLE
] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT
),
186 [PS
] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL
),
187 [VECBASE
] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR
),
188 [EXCCAUSE
] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION
),
189 [DEBUGCAUSE
] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG
, SR_R
),
190 [CCOUNT
] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT
),
191 [PRID
] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID
, SR_R
),
192 [ICOUNT
] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG
),
193 [ICOUNTLEVEL
] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG
),
194 [EXCVADDR
] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION
),
195 [CCOMPARE
] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT
),
196 [CCOMPARE
+ 1] = XTENSA_REG("CCOMPARE1",
197 XTENSA_OPTION_TIMER_INTERRUPT
),
198 [CCOMPARE
+ 2] = XTENSA_REG("CCOMPARE2",
199 XTENSA_OPTION_TIMER_INTERRUPT
),
200 [MISC
] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR
),
201 [MISC
+ 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR
),
202 [MISC
+ 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR
),
203 [MISC
+ 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR
),
206 static const XtensaReg uregnames
[256] = {
207 [EXPSTATE
] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL
),
208 [THREADPTR
] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER
),
209 [FCR
] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR
),
210 [FSR
] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR
),
213 void xtensa_translate_init(void)
215 static const char * const regnames
[] = {
216 "ar0", "ar1", "ar2", "ar3",
217 "ar4", "ar5", "ar6", "ar7",
218 "ar8", "ar9", "ar10", "ar11",
219 "ar12", "ar13", "ar14", "ar15",
221 static const char * const fregnames
[] = {
222 "f0", "f1", "f2", "f3",
223 "f4", "f5", "f6", "f7",
224 "f8", "f9", "f10", "f11",
225 "f12", "f13", "f14", "f15",
229 cpu_pc
= tcg_global_mem_new_i32(cpu_env
,
230 offsetof(CPUXtensaState
, pc
), "pc");
232 for (i
= 0; i
< 16; i
++) {
233 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
234 offsetof(CPUXtensaState
, regs
[i
]),
238 for (i
= 0; i
< 16; i
++) {
239 cpu_FR
[i
] = tcg_global_mem_new_i32(cpu_env
,
240 offsetof(CPUXtensaState
, fregs
[i
].f32
[FP_F32_LOW
]),
244 for (i
= 0; i
< 256; ++i
) {
245 if (sregnames
[i
].name
) {
246 cpu_SR
[i
] = tcg_global_mem_new_i32(cpu_env
,
247 offsetof(CPUXtensaState
, sregs
[i
]),
252 for (i
= 0; i
< 256; ++i
) {
253 if (uregnames
[i
].name
) {
254 cpu_UR
[i
] = tcg_global_mem_new_i32(cpu_env
,
255 offsetof(CPUXtensaState
, uregs
[i
]),
261 static inline bool option_enabled(DisasContext
*dc
, int opt
)
263 return xtensa_option_enabled(dc
->config
, opt
);
266 static void init_sar_tracker(DisasContext
*dc
)
268 dc
->sar_5bit
= false;
269 dc
->sar_m32_5bit
= false;
270 dc
->sar_m32_allocated
= false;
273 static void reset_sar_tracker(DisasContext
*dc
)
275 if (dc
->sar_m32_allocated
) {
276 tcg_temp_free(dc
->sar_m32
);
280 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
282 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
283 if (dc
->sar_m32_5bit
) {
284 tcg_gen_discard_i32(dc
->sar_m32
);
287 dc
->sar_m32_5bit
= false;
290 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
292 TCGv_i32 tmp
= tcg_const_i32(32);
293 if (!dc
->sar_m32_allocated
) {
294 dc
->sar_m32
= tcg_temp_local_new_i32();
295 dc
->sar_m32_allocated
= true;
297 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
298 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
299 dc
->sar_5bit
= false;
300 dc
->sar_m32_5bit
= true;
304 static void gen_exception(DisasContext
*dc
, int excp
)
306 TCGv_i32 tmp
= tcg_const_i32(excp
);
307 gen_helper_exception(cpu_env
, tmp
);
311 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
313 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
314 TCGv_i32 tcause
= tcg_const_i32(cause
);
315 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
317 tcg_temp_free(tcause
);
318 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
319 cause
== SYSCALL_CAUSE
) {
320 dc
->is_jmp
= DISAS_UPDATE
;
324 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
327 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
328 TCGv_i32 tcause
= tcg_const_i32(cause
);
329 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
331 tcg_temp_free(tcause
);
334 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
336 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
337 TCGv_i32 tcause
= tcg_const_i32(cause
);
338 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
340 tcg_temp_free(tcause
);
341 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
342 dc
->is_jmp
= DISAS_UPDATE
;
346 static bool gen_check_privilege(DisasContext
*dc
)
348 #ifndef CONFIG_USER_ONLY
353 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
354 dc
->is_jmp
= DISAS_UPDATE
;
358 static bool gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
360 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
361 !(dc
->cpenable
& (1 << cp
))) {
362 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
363 dc
->is_jmp
= DISAS_UPDATE
;
369 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
371 tcg_gen_mov_i32(cpu_pc
, dest
);
373 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
375 if (dc
->singlestep_enabled
) {
376 gen_exception(dc
, EXCP_DEBUG
);
379 tcg_gen_goto_tb(slot
);
380 tcg_gen_exit_tb((uintptr_t)dc
->tb
+ slot
);
385 dc
->is_jmp
= DISAS_UPDATE
;
388 static void gen_jump(DisasContext
*dc
, TCGv dest
)
390 gen_jump_slot(dc
, dest
, -1);
393 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
395 TCGv_i32 tmp
= tcg_const_i32(dest
);
396 #ifndef CONFIG_USER_ONLY
397 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
401 gen_jump_slot(dc
, tmp
, slot
);
405 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
408 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
410 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
411 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
412 tcg_temp_free(tcallinc
);
413 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
414 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
415 gen_jump_slot(dc
, dest
, slot
);
418 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
420 gen_callw_slot(dc
, callinc
, dest
, -1);
423 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
425 TCGv_i32 tmp
= tcg_const_i32(dest
);
426 #ifndef CONFIG_USER_ONLY
427 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
431 gen_callw_slot(dc
, callinc
, tmp
, slot
);
435 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
437 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
438 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
439 dc
->next_pc
== dc
->lend
) {
440 TCGLabel
*label
= gen_new_label();
442 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
443 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
444 gen_jumpi(dc
, dc
->lbeg
, slot
);
445 gen_set_label(label
);
446 gen_jumpi(dc
, dc
->next_pc
, -1);
452 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
454 if (!gen_check_loop_end(dc
, slot
)) {
455 gen_jumpi(dc
, dc
->next_pc
, slot
);
459 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
460 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t addr
)
462 TCGLabel
*label
= gen_new_label();
464 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
465 gen_jumpi_check_loop_end(dc
, 0);
466 gen_set_label(label
);
467 gen_jumpi(dc
, addr
, 1);
470 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
471 TCGv_i32 t0
, uint32_t t1
, uint32_t addr
)
473 TCGv_i32 tmp
= tcg_const_i32(t1
);
474 gen_brcond(dc
, cond
, t0
, tmp
, addr
);
478 static bool gen_check_sr(DisasContext
*dc
, uint32_t sr
, unsigned access
)
480 if (!xtensa_option_bits_enabled(dc
->config
, sregnames
[sr
].opt_bits
)) {
481 if (sregnames
[sr
].name
) {
482 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not configured\n", sregnames
[sr
].name
);
484 qemu_log_mask(LOG_UNIMP
, "SR %d is not implemented\n", sr
);
486 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
488 } else if (!(sregnames
[sr
].access
& access
)) {
489 static const char * const access_text
[] = {
494 assert(access
< ARRAY_SIZE(access_text
) && access_text
[access
]);
495 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not available for %s\n", sregnames
[sr
].name
,
496 access_text
[access
]);
497 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
503 #ifndef CONFIG_USER_ONLY
504 static bool gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
506 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
509 gen_helper_update_ccount(cpu_env
);
510 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
511 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
518 static bool gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
520 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
521 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
522 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
527 static bool gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
529 static bool (* const rsr_handler
[256])(DisasContext
*dc
,
530 TCGv_i32 d
, uint32_t sr
) = {
531 #ifndef CONFIG_USER_ONLY
532 [CCOUNT
] = gen_rsr_ccount
,
533 [INTSET
] = gen_rsr_ccount
,
534 [PTEVADDR
] = gen_rsr_ptevaddr
,
538 if (rsr_handler
[sr
]) {
539 return rsr_handler
[sr
](dc
, d
, sr
);
541 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
546 static bool gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
548 gen_helper_wsr_lbeg(cpu_env
, s
);
549 gen_jumpi_check_loop_end(dc
, 0);
553 static bool gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
555 gen_helper_wsr_lend(cpu_env
, s
);
556 gen_jumpi_check_loop_end(dc
, 0);
560 static bool gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
562 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
563 if (dc
->sar_m32_5bit
) {
564 tcg_gen_discard_i32(dc
->sar_m32
);
566 dc
->sar_5bit
= false;
567 dc
->sar_m32_5bit
= false;
571 static bool gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
573 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
577 static bool gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
579 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
580 /* This can change tb->flags, so exit tb */
581 gen_jumpi_check_loop_end(dc
, -1);
585 static bool gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
587 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
591 #ifndef CONFIG_USER_ONLY
592 static bool gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
594 gen_helper_wsr_windowbase(cpu_env
, v
);
595 /* This can change tb->flags, so exit tb */
596 gen_jumpi_check_loop_end(dc
, -1);
600 static bool gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
602 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
603 /* This can change tb->flags, so exit tb */
604 gen_jumpi_check_loop_end(dc
, -1);
608 static bool gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
610 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
614 static bool gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
616 gen_helper_wsr_rasid(cpu_env
, v
);
617 /* This can change tb->flags, so exit tb */
618 gen_jumpi_check_loop_end(dc
, -1);
622 static bool gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
624 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
628 static bool gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
630 gen_helper_wsr_ibreakenable(cpu_env
, v
);
631 gen_jumpi_check_loop_end(dc
, 0);
635 static bool gen_wsr_memctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
637 gen_helper_wsr_memctl(cpu_env
, v
);
641 static bool gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
643 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
647 static bool gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
649 unsigned id
= sr
- IBREAKA
;
651 if (id
< dc
->config
->nibreak
) {
652 TCGv_i32 tmp
= tcg_const_i32(id
);
653 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
655 gen_jumpi_check_loop_end(dc
, 0);
661 static bool gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
663 unsigned id
= sr
- DBREAKA
;
665 if (id
< dc
->config
->ndbreak
) {
666 TCGv_i32 tmp
= tcg_const_i32(id
);
667 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
673 static bool gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
675 unsigned id
= sr
- DBREAKC
;
677 if (id
< dc
->config
->ndbreak
) {
678 TCGv_i32 tmp
= tcg_const_i32(id
);
679 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
685 static bool gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
687 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
688 /* This can change tb->flags, so exit tb */
689 gen_jumpi_check_loop_end(dc
, -1);
693 static void gen_check_interrupts(DisasContext
*dc
)
695 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
698 gen_helper_check_interrupts(cpu_env
);
699 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
704 static bool gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
706 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
707 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
708 gen_check_interrupts(dc
);
709 gen_jumpi_check_loop_end(dc
, 0);
713 static bool gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
715 TCGv_i32 tmp
= tcg_temp_new_i32();
717 tcg_gen_andi_i32(tmp
, v
,
718 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
719 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
720 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
721 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
723 gen_check_interrupts(dc
);
724 gen_jumpi_check_loop_end(dc
, 0);
728 static bool gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
730 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
731 gen_check_interrupts(dc
);
732 gen_jumpi_check_loop_end(dc
, 0);
736 static bool gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
738 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
739 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
741 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
744 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
745 gen_check_interrupts(dc
);
746 /* This can change mmu index and tb->flags, so exit tb */
747 gen_jumpi_check_loop_end(dc
, -1);
751 static bool gen_wsr_ccount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
753 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
756 gen_helper_wsr_ccount(cpu_env
, v
);
757 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
759 gen_jumpi_check_loop_end(dc
, 0);
765 static bool gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
768 tcg_gen_mov_i32(dc
->next_icount
, v
);
770 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
775 static bool gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
777 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
778 /* This can change tb->flags, so exit tb */
779 gen_jumpi_check_loop_end(dc
, -1);
783 static bool gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
785 uint32_t id
= sr
- CCOMPARE
;
788 if (id
< dc
->config
->nccompare
) {
789 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
790 TCGv_i32 tmp
= tcg_const_i32(id
);
792 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
793 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
794 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
797 gen_helper_update_ccompare(cpu_env
, tmp
);
798 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
800 gen_jumpi_check_loop_end(dc
, 0);
808 static void gen_check_interrupts(DisasContext
*dc
)
813 static bool gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
815 static bool (* const wsr_handler
[256])(DisasContext
*dc
,
816 uint32_t sr
, TCGv_i32 v
) = {
817 [LBEG
] = gen_wsr_lbeg
,
818 [LEND
] = gen_wsr_lend
,
821 [LITBASE
] = gen_wsr_litbase
,
822 [ACCHI
] = gen_wsr_acchi
,
823 #ifndef CONFIG_USER_ONLY
824 [WINDOW_BASE
] = gen_wsr_windowbase
,
825 [WINDOW_START
] = gen_wsr_windowstart
,
826 [PTEVADDR
] = gen_wsr_ptevaddr
,
827 [RASID
] = gen_wsr_rasid
,
828 [ITLBCFG
] = gen_wsr_tlbcfg
,
829 [DTLBCFG
] = gen_wsr_tlbcfg
,
830 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
831 [MEMCTL
] = gen_wsr_memctl
,
832 [ATOMCTL
] = gen_wsr_atomctl
,
833 [IBREAKA
] = gen_wsr_ibreaka
,
834 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
835 [DBREAKA
] = gen_wsr_dbreaka
,
836 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
837 [DBREAKC
] = gen_wsr_dbreakc
,
838 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
839 [CPENABLE
] = gen_wsr_cpenable
,
840 [INTSET
] = gen_wsr_intset
,
841 [INTCLEAR
] = gen_wsr_intclear
,
842 [INTENABLE
] = gen_wsr_intenable
,
844 [CCOUNT
] = gen_wsr_ccount
,
845 [ICOUNT
] = gen_wsr_icount
,
846 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
847 [CCOMPARE
] = gen_wsr_ccompare
,
848 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
849 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
853 if (wsr_handler
[sr
]) {
854 return wsr_handler
[sr
](dc
, sr
, s
);
856 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
861 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
865 gen_helper_wur_fcr(cpu_env
, s
);
869 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
873 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
878 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
879 TCGv_i32 addr
, bool no_hw_alignment
)
881 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
882 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
883 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
885 TCGLabel
*label
= gen_new_label();
886 TCGv_i32 tmp
= tcg_temp_new_i32();
887 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
888 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
889 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
890 gen_set_label(label
);
895 #ifndef CONFIG_USER_ONLY
896 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
898 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
899 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
901 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
904 gen_helper_waiti(cpu_env
, pc
, intlevel
);
905 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
909 tcg_temp_free(intlevel
);
910 gen_jumpi_check_loop_end(dc
, 0);
914 static bool gen_window_check1(DisasContext
*dc
, unsigned r1
)
916 if (r1
/ 4 > dc
->window
) {
917 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
918 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
920 gen_helper_window_check(cpu_env
, pc
, w
);
921 dc
->is_jmp
= DISAS_UPDATE
;
927 static bool gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
929 return gen_window_check1(dc
, r1
> r2
? r1
: r2
);
932 static bool gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
935 return gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
938 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
940 TCGv_i32 m
= tcg_temp_new_i32();
943 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
945 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
950 static inline unsigned xtensa_op0_insn_len(DisasContext
*dc
, uint8_t op0
)
952 return xtensa_isa_length_from_chars(dc
->config
->isa
, &op0
);
955 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
957 xtensa_isa isa
= dc
->config
->isa
;
958 unsigned char b
[MAX_INSN_LENGTH
] = {cpu_ldub_code(env
, dc
->pc
)};
959 unsigned len
= xtensa_op0_insn_len(dc
, b
[0]);
964 if (len
== XTENSA_UNDEFINED
) {
965 qemu_log_mask(LOG_GUEST_ERROR
,
966 "unknown instruction length (pc = %08x)\n",
968 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
972 dc
->next_pc
= dc
->pc
+ len
;
973 for (i
= 1; i
< len
; ++i
) {
974 b
[i
] = cpu_ldub_code(env
, dc
->pc
+ i
);
976 xtensa_insnbuf_from_chars(isa
, dc
->insnbuf
, b
, len
);
977 fmt
= xtensa_format_decode(isa
, dc
->insnbuf
);
978 if (fmt
== XTENSA_UNDEFINED
) {
979 qemu_log_mask(LOG_GUEST_ERROR
,
980 "unrecognized instruction format (pc = %08x)\n",
982 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
985 slots
= xtensa_format_num_slots(isa
, fmt
);
986 for (slot
= 0; slot
< slots
; ++slot
) {
988 int opnd
, vopnd
, opnds
;
989 uint32_t raw_arg
[MAX_OPCODE_ARGS
];
990 uint32_t arg
[MAX_OPCODE_ARGS
];
991 XtensaOpcodeOps
*ops
;
993 dc
->raw_arg
= raw_arg
;
995 xtensa_format_get_slot(isa
, fmt
, slot
, dc
->insnbuf
, dc
->slotbuf
);
996 opc
= xtensa_opcode_decode(isa
, fmt
, slot
, dc
->slotbuf
);
997 if (opc
== XTENSA_UNDEFINED
) {
998 qemu_log_mask(LOG_GUEST_ERROR
,
999 "unrecognized opcode in slot %d (pc = %08x)\n",
1001 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1004 opnds
= xtensa_opcode_num_operands(isa
, opc
);
1006 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
1007 if (xtensa_operand_is_visible(isa
, opc
, opnd
)) {
1010 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
1012 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
1014 if (xtensa_operand_is_PCrelative(isa
, opc
, opnd
)) {
1015 xtensa_operand_undo_reloc(isa
, opc
, opnd
, &v
, dc
->pc
);
1021 ops
= dc
->config
->opcode_ops
[opc
];
1023 ops
->translate(dc
, arg
, ops
->par
);
1025 qemu_log_mask(LOG_GUEST_ERROR
,
1026 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
1027 xtensa_opcode_name(isa
, opc
), slot
, dc
->pc
);
1028 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1032 if (dc
->is_jmp
== DISAS_NEXT
) {
1033 gen_check_loop_end(dc
, 0);
1035 dc
->pc
= dc
->next_pc
;
1038 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
1040 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
1041 return xtensa_op0_insn_len(dc
, b0
);
1044 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
1048 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
1049 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
1050 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
1051 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
1057 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
1059 CPUXtensaState
*env
= cs
->env_ptr
;
1062 int max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
1063 uint32_t pc_start
= tb
->pc
;
1064 uint32_t page_start
= pc_start
& TARGET_PAGE_MASK
;
1066 if (max_insns
== 0) {
1067 max_insns
= CF_COUNT_MASK
;
1069 if (max_insns
> TCG_MAX_INSNS
) {
1070 max_insns
= TCG_MAX_INSNS
;
1073 dc
.config
= env
->config
;
1074 dc
.singlestep_enabled
= cs
->singlestep_enabled
;
1077 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
1078 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
1079 dc
.lbeg
= env
->sregs
[LBEG
];
1080 dc
.lend
= env
->sregs
[LEND
];
1081 dc
.is_jmp
= DISAS_NEXT
;
1082 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
1083 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
1084 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
1085 XTENSA_TBFLAG_CPENABLE_SHIFT
;
1086 dc
.window
= ((tb
->flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
1087 XTENSA_TBFLAG_WINDOW_SHIFT
);
1089 if (dc
.config
->isa
) {
1090 dc
.insnbuf
= xtensa_insnbuf_alloc(dc
.config
->isa
);
1091 dc
.slotbuf
= xtensa_insnbuf_alloc(dc
.config
->isa
);
1094 init_sar_tracker(&dc
);
1096 dc
.next_icount
= tcg_temp_local_new_i32();
1101 if ((tb_cflags(tb
) & CF_USE_ICOUNT
) &&
1102 (tb
->flags
& XTENSA_TBFLAG_YIELD
)) {
1103 tcg_gen_insn_start(dc
.pc
);
1105 gen_exception(&dc
, EXCP_YIELD
);
1106 dc
.is_jmp
= DISAS_UPDATE
;
1109 if (tb
->flags
& XTENSA_TBFLAG_EXCEPTION
) {
1110 tcg_gen_insn_start(dc
.pc
);
1112 gen_exception(&dc
, EXCP_DEBUG
);
1113 dc
.is_jmp
= DISAS_UPDATE
;
1118 tcg_gen_insn_start(dc
.pc
);
1121 if (unlikely(cpu_breakpoint_test(cs
, dc
.pc
, BP_ANY
))) {
1122 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1123 gen_exception(&dc
, EXCP_DEBUG
);
1124 dc
.is_jmp
= DISAS_UPDATE
;
1125 /* The address covered by the breakpoint must be included in
1126 [tb->pc, tb->pc + tb->size) in order to for it to be
1127 properly cleared -- thus we increment the PC here so that
1128 the logic setting tb->size below does the right thing. */
1133 if (insn_count
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
1138 TCGLabel
*label
= gen_new_label();
1140 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
1141 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
1142 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
1144 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
1146 gen_set_label(label
);
1150 gen_ibreak_check(env
, &dc
);
1153 disas_xtensa_insn(env
, &dc
);
1155 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
1157 if (cs
->singlestep_enabled
) {
1158 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1159 gen_exception(&dc
, EXCP_DEBUG
);
1162 } while (dc
.is_jmp
== DISAS_NEXT
&&
1163 insn_count
< max_insns
&&
1164 dc
.pc
- page_start
< TARGET_PAGE_SIZE
&&
1165 dc
.pc
- page_start
+ xtensa_insn_len(env
, &dc
) <= TARGET_PAGE_SIZE
1166 && !tcg_op_buf_full());
1168 reset_sar_tracker(&dc
);
1170 tcg_temp_free(dc
.next_icount
);
1172 if (dc
.config
->isa
) {
1173 xtensa_insnbuf_free(dc
.config
->isa
, dc
.insnbuf
);
1174 xtensa_insnbuf_free(dc
.config
->isa
, dc
.slotbuf
);
1177 if (tb_cflags(tb
) & CF_LAST_IO
) {
1181 if (dc
.is_jmp
== DISAS_NEXT
) {
1182 gen_jumpi(&dc
, dc
.pc
, 0);
1184 gen_tb_end(tb
, insn_count
);
1187 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
1188 && qemu_log_in_addr_range(pc_start
)) {
1190 qemu_log("----------------\n");
1191 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
1192 log_target_disas(cs
, pc_start
, dc
.pc
- pc_start
);
1197 tb
->size
= dc
.pc
- pc_start
;
1198 tb
->icount
= insn_count
;
1201 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
,
1202 fprintf_function cpu_fprintf
, int flags
)
1204 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
1205 CPUXtensaState
*env
= &cpu
->env
;
1208 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1210 for (i
= j
= 0; i
< 256; ++i
) {
1211 if (xtensa_option_bits_enabled(env
->config
, sregnames
[i
].opt_bits
)) {
1212 cpu_fprintf(f
, "%12s=%08x%c", sregnames
[i
].name
, env
->sregs
[i
],
1213 (j
++ % 4) == 3 ? '\n' : ' ');
1217 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1219 for (i
= j
= 0; i
< 256; ++i
) {
1220 if (xtensa_option_bits_enabled(env
->config
, uregnames
[i
].opt_bits
)) {
1221 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
].name
, env
->uregs
[i
],
1222 (j
++ % 4) == 3 ? '\n' : ' ');
1226 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1228 for (i
= 0; i
< 16; ++i
) {
1229 cpu_fprintf(f
, " A%02d=%08x%c", i
, env
->regs
[i
],
1230 (i
% 4) == 3 ? '\n' : ' ');
1233 xtensa_sync_phys_from_window(env
);
1234 cpu_fprintf(f
, "\n");
1236 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
1237 cpu_fprintf(f
, "AR%02d=%08x ", i
, env
->phys_regs
[i
]);
1239 bool ws
= (env
->sregs
[WINDOW_START
] & (1 << (i
/ 4))) != 0;
1240 bool cw
= env
->sregs
[WINDOW_BASE
] == i
/ 4;
1242 cpu_fprintf(f
, "%c%c\n", ws
? '<' : ' ', cw
? '=' : ' ');
1246 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
1247 cpu_fprintf(f
, "\n");
1249 for (i
= 0; i
< 16; ++i
) {
1250 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
1251 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
1252 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
1253 (i
% 2) == 1 ? '\n' : ' ');
1258 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
,
1264 static int compare_opcode_ops(const void *a
, const void *b
)
1266 return strcmp((const char *)a
,
1267 ((const XtensaOpcodeOps
*)b
)->name
);
1271 xtensa_find_opcode_ops(const XtensaOpcodeTranslators
*t
,
1274 XtensaOpcodeOps
*ops
;
1276 ops
= bsearch(name
, t
->opcode
, t
->num_opcodes
,
1277 sizeof(XtensaOpcodeOps
), compare_opcode_ops
);
1281 static void translate_abs(DisasContext
*dc
, const uint32_t arg
[],
1282 const uint32_t par
[])
1284 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1285 TCGv_i32 zero
= tcg_const_i32(0);
1286 TCGv_i32 neg
= tcg_temp_new_i32();
1288 tcg_gen_neg_i32(neg
, cpu_R
[arg
[1]]);
1289 tcg_gen_movcond_i32(TCG_COND_GE
, cpu_R
[arg
[0]],
1290 cpu_R
[arg
[1]], zero
, cpu_R
[arg
[1]], neg
);
1292 tcg_temp_free(zero
);
1296 static void translate_add(DisasContext
*dc
, const uint32_t arg
[],
1297 const uint32_t par
[])
1299 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1300 tcg_gen_add_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1304 static void translate_addi(DisasContext
*dc
, const uint32_t arg
[],
1305 const uint32_t par
[])
1307 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1308 tcg_gen_addi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1312 static void translate_addx(DisasContext
*dc
, const uint32_t arg
[],
1313 const uint32_t par
[])
1315 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1316 TCGv_i32 tmp
= tcg_temp_new_i32();
1317 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
1318 tcg_gen_add_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
1323 static void translate_all(DisasContext
*dc
, const uint32_t arg
[],
1324 const uint32_t par
[])
1326 uint32_t shift
= par
[1];
1327 TCGv_i32 mask
= tcg_const_i32(((1 << shift
) - 1) << arg
[1]);
1328 TCGv_i32 tmp
= tcg_temp_new_i32();
1330 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1332 tcg_gen_addi_i32(tmp
, tmp
, 1 << arg
[1]);
1334 tcg_gen_add_i32(tmp
, tmp
, mask
);
1336 tcg_gen_shri_i32(tmp
, tmp
, arg
[1] + shift
);
1337 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1339 tcg_temp_free(mask
);
1343 static void translate_and(DisasContext
*dc
, const uint32_t arg
[],
1344 const uint32_t par
[])
1346 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1347 tcg_gen_and_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1351 static void translate_ball(DisasContext
*dc
, const uint32_t arg
[],
1352 const uint32_t par
[])
1354 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1355 TCGv_i32 tmp
= tcg_temp_new_i32();
1356 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1357 gen_brcond(dc
, par
[0], tmp
, cpu_R
[arg
[1]], arg
[2]);
1362 static void translate_bany(DisasContext
*dc
, const uint32_t arg
[],
1363 const uint32_t par
[])
1365 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1366 TCGv_i32 tmp
= tcg_temp_new_i32();
1367 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1368 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1373 static void translate_b(DisasContext
*dc
, const uint32_t arg
[],
1374 const uint32_t par
[])
1376 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1377 gen_brcond(dc
, par
[0], cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1381 static void translate_bb(DisasContext
*dc
, const uint32_t arg
[],
1382 const uint32_t par
[])
1384 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1385 #ifdef TARGET_WORDS_BIGENDIAN
1386 TCGv_i32 bit
= tcg_const_i32(0x80000000u
);
1388 TCGv_i32 bit
= tcg_const_i32(0x00000001u
);
1390 TCGv_i32 tmp
= tcg_temp_new_i32();
1391 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[1]], 0x1f);
1392 #ifdef TARGET_WORDS_BIGENDIAN
1393 tcg_gen_shr_i32(bit
, bit
, tmp
);
1395 tcg_gen_shl_i32(bit
, bit
, tmp
);
1397 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], bit
);
1398 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1404 static void translate_bbi(DisasContext
*dc
, const uint32_t arg
[],
1405 const uint32_t par
[])
1407 if (gen_window_check1(dc
, arg
[0])) {
1408 TCGv_i32 tmp
= tcg_temp_new_i32();
1409 #ifdef TARGET_WORDS_BIGENDIAN
1410 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x80000000u
>> arg
[1]);
1412 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x00000001u
<< arg
[1]);
1414 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1419 static void translate_bi(DisasContext
*dc
, const uint32_t arg
[],
1420 const uint32_t par
[])
1422 if (gen_window_check1(dc
, arg
[0])) {
1423 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], arg
[1], arg
[2]);
1427 static void translate_bz(DisasContext
*dc
, const uint32_t arg
[],
1428 const uint32_t par
[])
1430 if (gen_window_check1(dc
, arg
[0])) {
1431 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], 0, arg
[1]);
1443 static void translate_boolean(DisasContext
*dc
, const uint32_t arg
[],
1444 const uint32_t par
[])
1446 static void (* const op
[])(TCGv_i32
, TCGv_i32
, TCGv_i32
) = {
1447 [BOOLEAN_AND
] = tcg_gen_and_i32
,
1448 [BOOLEAN_ANDC
] = tcg_gen_andc_i32
,
1449 [BOOLEAN_OR
] = tcg_gen_or_i32
,
1450 [BOOLEAN_ORC
] = tcg_gen_orc_i32
,
1451 [BOOLEAN_XOR
] = tcg_gen_xor_i32
,
1454 TCGv_i32 tmp1
= tcg_temp_new_i32();
1455 TCGv_i32 tmp2
= tcg_temp_new_i32();
1457 tcg_gen_shri_i32(tmp1
, cpu_SR
[BR
], arg
[1]);
1458 tcg_gen_shri_i32(tmp2
, cpu_SR
[BR
], arg
[2]);
1459 op
[par
[0]](tmp1
, tmp1
, tmp2
);
1460 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
], tmp1
, arg
[0], 1);
1461 tcg_temp_free(tmp1
);
1462 tcg_temp_free(tmp2
);
1465 static void translate_bp(DisasContext
*dc
, const uint32_t arg
[],
1466 const uint32_t par
[])
1468 TCGv_i32 tmp
= tcg_temp_new_i32();
1470 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[0]);
1471 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[1]);
1475 static void translate_break(DisasContext
*dc
, const uint32_t arg
[],
1476 const uint32_t par
[])
1479 gen_debug_exception(dc
, par
[0]);
1483 static void translate_call0(DisasContext
*dc
, const uint32_t arg
[],
1484 const uint32_t par
[])
1486 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1487 gen_jumpi(dc
, arg
[0], 0);
1490 static void translate_callw(DisasContext
*dc
, const uint32_t arg
[],
1491 const uint32_t par
[])
1493 if (gen_window_check1(dc
, par
[0] << 2)) {
1494 gen_callwi(dc
, par
[0], arg
[0], 0);
1498 static void translate_callx0(DisasContext
*dc
, const uint32_t arg
[],
1499 const uint32_t par
[])
1501 if (gen_window_check1(dc
, arg
[0])) {
1502 TCGv_i32 tmp
= tcg_temp_new_i32();
1503 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1504 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1510 static void translate_callxw(DisasContext
*dc
, const uint32_t arg
[],
1511 const uint32_t par
[])
1513 if (gen_window_check2(dc
, arg
[0], par
[0] << 2)) {
1514 TCGv_i32 tmp
= tcg_temp_new_i32();
1516 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1517 gen_callw(dc
, par
[0], tmp
);
1522 static void translate_clamps(DisasContext
*dc
, const uint32_t arg
[],
1523 const uint32_t par
[])
1525 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1526 TCGv_i32 tmp1
= tcg_const_i32(-1u << arg
[2]);
1527 TCGv_i32 tmp2
= tcg_const_i32((1 << arg
[2]) - 1);
1529 tcg_gen_smax_i32(tmp1
, tmp1
, cpu_R
[arg
[1]]);
1530 tcg_gen_smin_i32(cpu_R
[arg
[0]], tmp1
, tmp2
);
1531 tcg_temp_free(tmp1
);
1532 tcg_temp_free(tmp2
);
1536 static void translate_clrb_expstate(DisasContext
*dc
, const uint32_t arg
[],
1537 const uint32_t par
[])
1539 /* TODO: GPIO32 may be a part of coprocessor */
1540 tcg_gen_andi_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], ~(1u << arg
[0]));
1543 static void translate_const16(DisasContext
*dc
, const uint32_t arg
[],
1544 const uint32_t par
[])
1546 if (gen_window_check1(dc
, arg
[0])) {
1547 TCGv_i32 c
= tcg_const_i32(arg
[1]);
1549 tcg_gen_deposit_i32(cpu_R
[arg
[0]], c
, cpu_R
[arg
[0]], 16, 16);
1554 /* par[0]: privileged, par[1]: check memory access */
1555 static void translate_dcache(DisasContext
*dc
, const uint32_t arg
[],
1556 const uint32_t par
[])
1558 if ((!par
[0] || gen_check_privilege(dc
)) &&
1559 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1560 TCGv_i32 addr
= tcg_temp_new_i32();
1561 TCGv_i32 res
= tcg_temp_new_i32();
1563 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1564 tcg_gen_qemu_ld8u(res
, addr
, dc
->cring
);
1565 tcg_temp_free(addr
);
1570 static void translate_depbits(DisasContext
*dc
, const uint32_t arg
[],
1571 const uint32_t par
[])
1573 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1574 tcg_gen_deposit_i32(cpu_R
[arg
[1]], cpu_R
[arg
[1]], cpu_R
[arg
[0]],
1579 static void translate_entry(DisasContext
*dc
, const uint32_t arg
[],
1580 const uint32_t par
[])
1582 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1583 TCGv_i32 s
= tcg_const_i32(arg
[0]);
1584 TCGv_i32 imm
= tcg_const_i32(arg
[1]);
1585 gen_helper_entry(cpu_env
, pc
, s
, imm
);
1589 /* This can change tb->flags, so exit tb */
1590 gen_jumpi_check_loop_end(dc
, -1);
1593 static void translate_extui(DisasContext
*dc
, const uint32_t arg
[],
1594 const uint32_t par
[])
1596 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1597 int maskimm
= (1 << arg
[3]) - 1;
1599 TCGv_i32 tmp
= tcg_temp_new_i32();
1600 tcg_gen_shri_i32(tmp
, cpu_R
[arg
[1]], arg
[2]);
1601 tcg_gen_andi_i32(cpu_R
[arg
[0]], tmp
, maskimm
);
1606 /* par[0]: privileged, par[1]: check memory access */
1607 static void translate_icache(DisasContext
*dc
, const uint32_t arg
[],
1608 const uint32_t par
[])
1610 if ((!par
[0] || gen_check_privilege(dc
)) &&
1611 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1612 #ifndef CONFIG_USER_ONLY
1613 TCGv_i32 addr
= tcg_temp_new_i32();
1615 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1616 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1617 gen_helper_itlb_hit_test(cpu_env
, addr
);
1618 tcg_temp_free(addr
);
1623 static void translate_itlb(DisasContext
*dc
, const uint32_t arg
[],
1624 const uint32_t par
[])
1626 if (gen_check_privilege(dc
) &&
1627 gen_window_check1(dc
, arg
[0])) {
1628 #ifndef CONFIG_USER_ONLY
1629 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
1631 gen_helper_itlb(cpu_env
, cpu_R
[arg
[0]], dtlb
);
1632 /* This could change memory mapping, so exit tb */
1633 gen_jumpi_check_loop_end(dc
, -1);
1634 tcg_temp_free(dtlb
);
1639 static void translate_ill(DisasContext
*dc
, const uint32_t arg
[],
1640 const uint32_t par
[])
1642 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1645 static void translate_j(DisasContext
*dc
, const uint32_t arg
[],
1646 const uint32_t par
[])
1648 gen_jumpi(dc
, arg
[0], 0);
1651 static void translate_jx(DisasContext
*dc
, const uint32_t arg
[],
1652 const uint32_t par
[])
1654 if (gen_window_check1(dc
, arg
[0])) {
1655 gen_jump(dc
, cpu_R
[arg
[0]]);
1659 static void translate_l32e(DisasContext
*dc
, const uint32_t arg
[],
1660 const uint32_t par
[])
1662 if (gen_check_privilege(dc
) &&
1663 gen_window_check2(dc
, arg
[0], arg
[1])) {
1664 TCGv_i32 addr
= tcg_temp_new_i32();
1666 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1667 gen_load_store_alignment(dc
, 2, addr
, false);
1668 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
1669 tcg_temp_free(addr
);
1673 static void translate_ldst(DisasContext
*dc
, const uint32_t arg
[],
1674 const uint32_t par
[])
1676 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1677 TCGv_i32 addr
= tcg_temp_new_i32();
1679 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1680 if (par
[0] & MO_SIZE
) {
1681 gen_load_store_alignment(dc
, par
[0] & MO_SIZE
, addr
, par
[1]);
1685 tcg_gen_mb(TCG_BAR_STRL
| TCG_MO_ALL
);
1687 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1689 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1691 tcg_gen_mb(TCG_BAR_LDAQ
| TCG_MO_ALL
);
1694 tcg_temp_free(addr
);
1698 static void translate_l32r(DisasContext
*dc
, const uint32_t arg
[],
1699 const uint32_t par
[])
1701 if (gen_window_check1(dc
, arg
[0])) {
1704 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1705 tmp
= tcg_const_i32(dc
->raw_arg
[1] - 1);
1706 tcg_gen_add_i32(tmp
, cpu_SR
[LITBASE
], tmp
);
1708 tmp
= tcg_const_i32(arg
[1]);
1710 tcg_gen_qemu_ld32u(cpu_R
[arg
[0]], tmp
, dc
->cring
);
1715 static void translate_loop(DisasContext
*dc
, const uint32_t arg
[],
1716 const uint32_t par
[])
1718 if (gen_window_check1(dc
, arg
[0])) {
1719 uint32_t lend
= arg
[1];
1720 TCGv_i32 tmp
= tcg_const_i32(lend
);
1722 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[arg
[0]], 1);
1723 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
1724 gen_helper_wsr_lend(cpu_env
, tmp
);
1727 if (par
[0] != TCG_COND_NEVER
) {
1728 TCGLabel
*label
= gen_new_label();
1729 tcg_gen_brcondi_i32(par
[0], cpu_R
[arg
[0]], 0, label
);
1730 gen_jumpi(dc
, lend
, 1);
1731 gen_set_label(label
);
1734 gen_jumpi(dc
, dc
->next_pc
, 0);
1766 static void translate_mac16(DisasContext
*dc
, const uint32_t arg
[],
1767 const uint32_t par
[])
1770 bool is_m1_sr
= par
[1] & MAC16_DX
;
1771 bool is_m2_sr
= par
[1] & MAC16_XD
;
1772 unsigned half
= par
[2];
1773 uint32_t ld_offset
= par
[3];
1774 unsigned off
= ld_offset
? 2 : 0;
1775 uint32_t ar
[3] = {0};
1778 if (op
!= MAC16_NONE
) {
1780 ar
[n_ar
++] = arg
[off
];
1783 ar
[n_ar
++] = arg
[off
+ 1];
1788 ar
[n_ar
++] = arg
[1];
1791 if (gen_window_check3(dc
, ar
[0], ar
[1], ar
[2])) {
1792 TCGv_i32 vaddr
= tcg_temp_new_i32();
1793 TCGv_i32 mem32
= tcg_temp_new_i32();
1796 tcg_gen_addi_i32(vaddr
, cpu_R
[arg
[1]], ld_offset
);
1797 gen_load_store_alignment(dc
, 2, vaddr
, false);
1798 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
1800 if (op
!= MAC16_NONE
) {
1801 TCGv_i32 m1
= gen_mac16_m(is_m1_sr
?
1802 cpu_SR
[MR
+ arg
[off
]] :
1804 half
& MAC16_HX
, op
== MAC16_UMUL
);
1805 TCGv_i32 m2
= gen_mac16_m(is_m2_sr
?
1806 cpu_SR
[MR
+ arg
[off
+ 1]] :
1807 cpu_R
[arg
[off
+ 1]],
1808 half
& MAC16_XH
, op
== MAC16_UMUL
);
1810 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
1811 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
1812 if (op
== MAC16_UMUL
) {
1813 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
1815 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
1818 TCGv_i32 lo
= tcg_temp_new_i32();
1819 TCGv_i32 hi
= tcg_temp_new_i32();
1821 tcg_gen_mul_i32(lo
, m1
, m2
);
1822 tcg_gen_sari_i32(hi
, lo
, 31);
1823 if (op
== MAC16_MULA
) {
1824 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1825 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1828 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1829 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1832 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
1834 tcg_temp_free_i32(lo
);
1835 tcg_temp_free_i32(hi
);
1841 tcg_gen_mov_i32(cpu_R
[arg
[1]], vaddr
);
1842 tcg_gen_mov_i32(cpu_SR
[MR
+ arg
[0]], mem32
);
1844 tcg_temp_free(vaddr
);
1845 tcg_temp_free(mem32
);
1849 static void translate_memw(DisasContext
*dc
, const uint32_t arg
[],
1850 const uint32_t par
[])
1852 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
1855 static void translate_smin(DisasContext
*dc
, const uint32_t arg
[],
1856 const uint32_t par
[])
1858 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1859 tcg_gen_smin_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1863 static void translate_umin(DisasContext
*dc
, const uint32_t arg
[],
1864 const uint32_t par
[])
1866 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1867 tcg_gen_umin_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1871 static void translate_smax(DisasContext
*dc
, const uint32_t arg
[],
1872 const uint32_t par
[])
1874 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1875 tcg_gen_smax_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1879 static void translate_umax(DisasContext
*dc
, const uint32_t arg
[],
1880 const uint32_t par
[])
1882 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1883 tcg_gen_umax_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1887 static void translate_mov(DisasContext
*dc
, const uint32_t arg
[],
1888 const uint32_t par
[])
1890 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1891 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1895 static void translate_movcond(DisasContext
*dc
, const uint32_t arg
[],
1896 const uint32_t par
[])
1898 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1899 TCGv_i32 zero
= tcg_const_i32(0);
1901 tcg_gen_movcond_i32(par
[0], cpu_R
[arg
[0]],
1902 cpu_R
[arg
[2]], zero
, cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1903 tcg_temp_free(zero
);
1907 static void translate_movi(DisasContext
*dc
, const uint32_t arg
[],
1908 const uint32_t par
[])
1910 if (gen_window_check1(dc
, arg
[0])) {
1911 tcg_gen_movi_i32(cpu_R
[arg
[0]], arg
[1]);
1915 static void translate_movp(DisasContext
*dc
, const uint32_t arg
[],
1916 const uint32_t par
[])
1918 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1919 TCGv_i32 zero
= tcg_const_i32(0);
1920 TCGv_i32 tmp
= tcg_temp_new_i32();
1922 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
1923 tcg_gen_movcond_i32(par
[0],
1924 cpu_R
[arg
[0]], tmp
, zero
,
1925 cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1927 tcg_temp_free(zero
);
1931 static void translate_movsp(DisasContext
*dc
, const uint32_t arg
[],
1932 const uint32_t par
[])
1934 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1935 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1936 gen_helper_movsp(cpu_env
, pc
);
1937 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1942 static void translate_mul16(DisasContext
*dc
, const uint32_t arg
[],
1943 const uint32_t par
[])
1945 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1946 TCGv_i32 v1
= tcg_temp_new_i32();
1947 TCGv_i32 v2
= tcg_temp_new_i32();
1950 tcg_gen_ext16s_i32(v1
, cpu_R
[arg
[1]]);
1951 tcg_gen_ext16s_i32(v2
, cpu_R
[arg
[2]]);
1953 tcg_gen_ext16u_i32(v1
, cpu_R
[arg
[1]]);
1954 tcg_gen_ext16u_i32(v2
, cpu_R
[arg
[2]]);
1956 tcg_gen_mul_i32(cpu_R
[arg
[0]], v1
, v2
);
1962 static void translate_mull(DisasContext
*dc
, const uint32_t arg
[],
1963 const uint32_t par
[])
1965 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1966 tcg_gen_mul_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1970 static void translate_mulh(DisasContext
*dc
, const uint32_t arg
[],
1971 const uint32_t par
[])
1973 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1974 TCGv_i32 lo
= tcg_temp_new();
1977 tcg_gen_muls2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1979 tcg_gen_mulu2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1985 static void translate_neg(DisasContext
*dc
, const uint32_t arg
[],
1986 const uint32_t par
[])
1988 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1989 tcg_gen_neg_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1993 static void translate_nop(DisasContext
*dc
, const uint32_t arg
[],
1994 const uint32_t par
[])
1998 static void translate_nsa(DisasContext
*dc
, const uint32_t arg
[],
1999 const uint32_t par
[])
2001 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2002 tcg_gen_clrsb_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2006 static void translate_nsau(DisasContext
*dc
, const uint32_t arg
[],
2007 const uint32_t par
[])
2009 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2010 tcg_gen_clzi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], 32);
2014 static void translate_or(DisasContext
*dc
, const uint32_t arg
[],
2015 const uint32_t par
[])
2017 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2018 tcg_gen_or_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2022 static void translate_ptlb(DisasContext
*dc
, const uint32_t arg
[],
2023 const uint32_t par
[])
2025 if (gen_check_privilege(dc
) &&
2026 gen_window_check2(dc
, arg
[0], arg
[1])) {
2027 #ifndef CONFIG_USER_ONLY
2028 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2030 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2031 gen_helper_ptlb(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
2032 tcg_temp_free(dtlb
);
2037 static void gen_zero_check(DisasContext
*dc
, const uint32_t arg
[])
2039 TCGLabel
*label
= gen_new_label();
2041 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0, label
);
2042 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
2043 gen_set_label(label
);
2046 static void translate_quos(DisasContext
*dc
, const uint32_t arg
[],
2047 const uint32_t par
[])
2049 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2050 TCGLabel
*label1
= gen_new_label();
2051 TCGLabel
*label2
= gen_new_label();
2053 gen_zero_check(dc
, arg
);
2055 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[1]], 0x80000000,
2057 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0xffffffff,
2059 tcg_gen_movi_i32(cpu_R
[arg
[0]],
2060 par
[0] ? 0x80000000 : 0);
2062 gen_set_label(label1
);
2064 tcg_gen_div_i32(cpu_R
[arg
[0]],
2065 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2067 tcg_gen_rem_i32(cpu_R
[arg
[0]],
2068 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2070 gen_set_label(label2
);
2074 static void translate_quou(DisasContext
*dc
, const uint32_t arg
[],
2075 const uint32_t par
[])
2077 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2078 gen_zero_check(dc
, arg
);
2080 tcg_gen_divu_i32(cpu_R
[arg
[0]],
2081 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2083 tcg_gen_remu_i32(cpu_R
[arg
[0]],
2084 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2089 static void translate_read_impwire(DisasContext
*dc
, const uint32_t arg
[],
2090 const uint32_t par
[])
2092 if (gen_window_check1(dc
, arg
[0])) {
2093 /* TODO: GPIO32 may be a part of coprocessor */
2094 tcg_gen_movi_i32(cpu_R
[arg
[0]], 0);
2098 static void translate_rer(DisasContext
*dc
, const uint32_t arg
[],
2099 const uint32_t par
[])
2101 if (gen_check_privilege(dc
) &&
2102 gen_window_check2(dc
, arg
[0], arg
[1])) {
2103 gen_helper_rer(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]]);
2107 static void translate_ret(DisasContext
*dc
, const uint32_t arg
[],
2108 const uint32_t par
[])
2110 gen_jump(dc
, cpu_R
[0]);
2113 static void translate_retw(DisasContext
*dc
, const uint32_t arg
[],
2114 const uint32_t par
[])
2116 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2117 gen_helper_retw(tmp
, cpu_env
, tmp
);
2122 static void translate_rfde(DisasContext
*dc
, const uint32_t arg
[],
2123 const uint32_t par
[])
2125 if (gen_check_privilege(dc
)) {
2126 gen_jump(dc
, cpu_SR
[dc
->config
->ndepc
? DEPC
: EPC1
]);
2130 static void translate_rfe(DisasContext
*dc
, const uint32_t arg
[],
2131 const uint32_t par
[])
2133 if (gen_check_privilege(dc
)) {
2134 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2135 gen_check_interrupts(dc
);
2136 gen_jump(dc
, cpu_SR
[EPC1
]);
2140 static void translate_rfi(DisasContext
*dc
, const uint32_t arg
[],
2141 const uint32_t par
[])
2143 if (gen_check_privilege(dc
)) {
2144 tcg_gen_mov_i32(cpu_SR
[PS
], cpu_SR
[EPS2
+ arg
[0] - 2]);
2145 gen_check_interrupts(dc
);
2146 gen_jump(dc
, cpu_SR
[EPC1
+ arg
[0] - 1]);
2150 static void translate_rfw(DisasContext
*dc
, const uint32_t arg
[],
2151 const uint32_t par
[])
2153 if (gen_check_privilege(dc
)) {
2154 TCGv_i32 tmp
= tcg_const_i32(1);
2156 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2157 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
2160 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2161 cpu_SR
[WINDOW_START
], tmp
);
2163 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
2164 cpu_SR
[WINDOW_START
], tmp
);
2167 gen_helper_restore_owb(cpu_env
);
2168 gen_check_interrupts(dc
);
2169 gen_jump(dc
, cpu_SR
[EPC1
]);
2175 static void translate_rotw(DisasContext
*dc
, const uint32_t arg
[],
2176 const uint32_t par
[])
2178 if (gen_check_privilege(dc
)) {
2179 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2180 gen_helper_rotw(cpu_env
, tmp
);
2182 /* This can change tb->flags, so exit tb */
2183 gen_jumpi_check_loop_end(dc
, -1);
2187 static void translate_rsil(DisasContext
*dc
, const uint32_t arg
[],
2188 const uint32_t par
[])
2190 if (gen_check_privilege(dc
) &&
2191 gen_window_check1(dc
, arg
[0])) {
2192 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_SR
[PS
]);
2193 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
2194 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], arg
[1]);
2195 gen_check_interrupts(dc
);
2196 gen_jumpi_check_loop_end(dc
, 0);
2200 static void translate_rsr(DisasContext
*dc
, const uint32_t arg
[],
2201 const uint32_t par
[])
2203 if (gen_check_sr(dc
, par
[0], SR_R
) &&
2204 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2205 gen_window_check1(dc
, arg
[0])) {
2206 if (gen_rsr(dc
, cpu_R
[arg
[0]], par
[0])) {
2207 gen_jumpi_check_loop_end(dc
, 0);
2212 static void translate_rtlb(DisasContext
*dc
, const uint32_t arg
[],
2213 const uint32_t par
[])
2215 static void (* const helper
[])(TCGv_i32 r
, TCGv_env env
, TCGv_i32 a1
,
2217 #ifndef CONFIG_USER_ONLY
2223 if (gen_check_privilege(dc
) &&
2224 gen_window_check2(dc
, arg
[0], arg
[1])) {
2225 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2227 helper
[par
[1]](cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
2228 tcg_temp_free(dtlb
);
2232 static void translate_rur(DisasContext
*dc
, const uint32_t arg
[],
2233 const uint32_t par
[])
2235 if (gen_window_check1(dc
, arg
[0])) {
2236 if (uregnames
[par
[0]].name
) {
2237 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_UR
[par
[0]]);
2239 qemu_log_mask(LOG_UNIMP
, "RUR %d not implemented, ", par
[0]);
2244 static void translate_setb_expstate(DisasContext
*dc
, const uint32_t arg
[],
2245 const uint32_t par
[])
2247 /* TODO: GPIO32 may be a part of coprocessor */
2248 tcg_gen_ori_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], 1u << arg
[0]);
2251 #ifdef CONFIG_USER_ONLY
2252 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2256 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2258 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
2260 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2265 static void translate_s32c1i(DisasContext
*dc
, const uint32_t arg
[],
2266 const uint32_t par
[])
2268 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2269 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2270 TCGv_i32 addr
= tcg_temp_local_new_i32();
2272 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2273 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2274 gen_load_store_alignment(dc
, 2, addr
, true);
2275 gen_check_atomctl(dc
, addr
);
2276 tcg_gen_atomic_cmpxchg_i32(cpu_R
[arg
[0]], addr
, cpu_SR
[SCOMPARE1
],
2277 tmp
, dc
->cring
, MO_32
);
2278 tcg_temp_free(addr
);
2283 static void translate_s32e(DisasContext
*dc
, const uint32_t arg
[],
2284 const uint32_t par
[])
2286 if (gen_check_privilege(dc
) &&
2287 gen_window_check2(dc
, arg
[0], arg
[1])) {
2288 TCGv_i32 addr
= tcg_temp_new_i32();
2290 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2291 gen_load_store_alignment(dc
, 2, addr
, false);
2292 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
2293 tcg_temp_free(addr
);
2297 static void translate_salt(DisasContext
*dc
, const uint32_t arg
[],
2298 const uint32_t par
[])
2300 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2301 tcg_gen_setcond_i32(par
[0],
2303 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2307 static void translate_sext(DisasContext
*dc
, const uint32_t arg
[],
2308 const uint32_t par
[])
2310 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2311 int shift
= 31 - arg
[2];
2314 tcg_gen_ext8s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2315 } else if (shift
== 16) {
2316 tcg_gen_ext16s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2318 TCGv_i32 tmp
= tcg_temp_new_i32();
2319 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], shift
);
2320 tcg_gen_sari_i32(cpu_R
[arg
[0]], tmp
, shift
);
2326 static void translate_simcall(DisasContext
*dc
, const uint32_t arg
[],
2327 const uint32_t par
[])
2329 #ifndef CONFIG_USER_ONLY
2330 if (semihosting_enabled()) {
2331 if (gen_check_privilege(dc
)) {
2332 gen_helper_simcall(cpu_env
);
2337 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
2338 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2343 * Note: 64 bit ops are used here solely because SAR values
2346 #define gen_shift_reg(cmd, reg) do { \
2347 TCGv_i64 tmp = tcg_temp_new_i64(); \
2348 tcg_gen_extu_i32_i64(tmp, reg); \
2349 tcg_gen_##cmd##_i64(v, v, tmp); \
2350 tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \
2351 tcg_temp_free_i64(v); \
2352 tcg_temp_free_i64(tmp); \
2355 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2357 static void translate_sll(DisasContext
*dc
, const uint32_t arg
[],
2358 const uint32_t par
[])
2360 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2361 if (dc
->sar_m32_5bit
) {
2362 tcg_gen_shl_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], dc
->sar_m32
);
2364 TCGv_i64 v
= tcg_temp_new_i64();
2365 TCGv_i32 s
= tcg_const_i32(32);
2366 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
2367 tcg_gen_andi_i32(s
, s
, 0x3f);
2368 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2369 gen_shift_reg(shl
, s
);
2375 static void translate_slli(DisasContext
*dc
, const uint32_t arg
[],
2376 const uint32_t par
[])
2378 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2380 qemu_log_mask(LOG_GUEST_ERROR
, "slli a%d, a%d, 32 is undefined",
2383 tcg_gen_shli_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2] & 0x1f);
2387 static void translate_sra(DisasContext
*dc
, const uint32_t arg
[],
2388 const uint32_t par
[])
2390 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2391 if (dc
->sar_m32_5bit
) {
2392 tcg_gen_sar_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2394 TCGv_i64 v
= tcg_temp_new_i64();
2395 tcg_gen_ext_i32_i64(v
, cpu_R
[arg
[1]]);
2401 static void translate_srai(DisasContext
*dc
, const uint32_t arg
[],
2402 const uint32_t par
[])
2404 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2405 tcg_gen_sari_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2409 static void translate_src(DisasContext
*dc
, const uint32_t arg
[],
2410 const uint32_t par
[])
2412 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2413 TCGv_i64 v
= tcg_temp_new_i64();
2414 tcg_gen_concat_i32_i64(v
, cpu_R
[arg
[2]], cpu_R
[arg
[1]]);
2419 static void translate_srl(DisasContext
*dc
, const uint32_t arg
[],
2420 const uint32_t par
[])
2422 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2423 if (dc
->sar_m32_5bit
) {
2424 tcg_gen_shr_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2426 TCGv_i64 v
= tcg_temp_new_i64();
2427 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2434 #undef gen_shift_reg
2436 static void translate_srli(DisasContext
*dc
, const uint32_t arg
[],
2437 const uint32_t par
[])
2439 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2440 tcg_gen_shri_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2444 static void translate_ssa8b(DisasContext
*dc
, const uint32_t arg
[],
2445 const uint32_t par
[])
2447 if (gen_window_check1(dc
, arg
[0])) {
2448 TCGv_i32 tmp
= tcg_temp_new_i32();
2449 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2450 gen_left_shift_sar(dc
, tmp
);
2455 static void translate_ssa8l(DisasContext
*dc
, const uint32_t arg
[],
2456 const uint32_t par
[])
2458 if (gen_window_check1(dc
, arg
[0])) {
2459 TCGv_i32 tmp
= tcg_temp_new_i32();
2460 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2461 gen_right_shift_sar(dc
, tmp
);
2466 static void translate_ssai(DisasContext
*dc
, const uint32_t arg
[],
2467 const uint32_t par
[])
2469 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2470 gen_right_shift_sar(dc
, tmp
);
2474 static void translate_ssl(DisasContext
*dc
, const uint32_t arg
[],
2475 const uint32_t par
[])
2477 if (gen_window_check1(dc
, arg
[0])) {
2478 gen_left_shift_sar(dc
, cpu_R
[arg
[0]]);
2482 static void translate_ssr(DisasContext
*dc
, const uint32_t arg
[],
2483 const uint32_t par
[])
2485 if (gen_window_check1(dc
, arg
[0])) {
2486 gen_right_shift_sar(dc
, cpu_R
[arg
[0]]);
2490 static void translate_sub(DisasContext
*dc
, const uint32_t arg
[],
2491 const uint32_t par
[])
2493 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2494 tcg_gen_sub_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2498 static void translate_subx(DisasContext
*dc
, const uint32_t arg
[],
2499 const uint32_t par
[])
2501 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2502 TCGv_i32 tmp
= tcg_temp_new_i32();
2503 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
2504 tcg_gen_sub_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
2509 static void translate_syscall(DisasContext
*dc
, const uint32_t arg
[],
2510 const uint32_t par
[])
2512 gen_exception_cause(dc
, SYSCALL_CAUSE
);
2515 static void translate_waiti(DisasContext
*dc
, const uint32_t arg
[],
2516 const uint32_t par
[])
2518 if (gen_check_privilege(dc
)) {
2519 #ifndef CONFIG_USER_ONLY
2520 gen_waiti(dc
, arg
[0]);
2525 static void translate_wtlb(DisasContext
*dc
, const uint32_t arg
[],
2526 const uint32_t par
[])
2528 if (gen_check_privilege(dc
) &&
2529 gen_window_check2(dc
, arg
[0], arg
[1])) {
2530 #ifndef CONFIG_USER_ONLY
2531 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2533 gen_helper_wtlb(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], dtlb
);
2534 /* This could change memory mapping, so exit tb */
2535 gen_jumpi_check_loop_end(dc
, -1);
2536 tcg_temp_free(dtlb
);
2541 static void translate_wer(DisasContext
*dc
, const uint32_t arg
[],
2542 const uint32_t par
[])
2544 if (gen_check_privilege(dc
) &&
2545 gen_window_check2(dc
, arg
[0], arg
[1])) {
2546 gen_helper_wer(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2550 static void translate_wrmsk_expstate(DisasContext
*dc
, const uint32_t arg
[],
2551 const uint32_t par
[])
2553 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2554 /* TODO: GPIO32 may be a part of coprocessor */
2555 tcg_gen_and_i32(cpu_UR
[EXPSTATE
], cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2559 static void translate_wsr(DisasContext
*dc
, const uint32_t arg
[],
2560 const uint32_t par
[])
2562 if (gen_check_sr(dc
, par
[0], SR_W
) &&
2563 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2564 gen_window_check1(dc
, arg
[0])) {
2565 gen_wsr(dc
, par
[0], cpu_R
[arg
[0]]);
2569 static void translate_wur(DisasContext
*dc
, const uint32_t arg
[],
2570 const uint32_t par
[])
2572 if (gen_window_check1(dc
, arg
[0])) {
2573 if (uregnames
[par
[0]].name
) {
2574 gen_wur(par
[0], cpu_R
[arg
[0]]);
2576 qemu_log_mask(LOG_UNIMP
, "WUR %d not implemented, ", par
[0]);
2581 static void translate_xor(DisasContext
*dc
, const uint32_t arg
[],
2582 const uint32_t par
[])
2584 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2585 tcg_gen_xor_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2589 static void translate_xsr(DisasContext
*dc
, const uint32_t arg
[],
2590 const uint32_t par
[])
2592 if (gen_check_sr(dc
, par
[0], SR_X
) &&
2593 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2594 gen_window_check1(dc
, arg
[0])) {
2595 TCGv_i32 tmp
= tcg_temp_new_i32();
2596 bool rsr_end
, wsr_end
;
2598 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2599 rsr_end
= gen_rsr(dc
, cpu_R
[arg
[0]], par
[0]);
2600 wsr_end
= gen_wsr(dc
, par
[0], tmp
);
2602 if (rsr_end
&& !wsr_end
) {
2603 gen_jumpi_check_loop_end(dc
, 0);
2608 static const XtensaOpcodeOps core_ops
[] = {
2611 .translate
= translate_abs
,
2614 .translate
= translate_add
,
2617 .translate
= translate_add
,
2620 .translate
= translate_addi
,
2623 .translate
= translate_addi
,
2626 .translate
= translate_addi
,
2629 .translate
= translate_addx
,
2630 .par
= (const uint32_t[]){1},
2633 .translate
= translate_addx
,
2634 .par
= (const uint32_t[]){2},
2637 .translate
= translate_addx
,
2638 .par
= (const uint32_t[]){3},
2641 .translate
= translate_all
,
2642 .par
= (const uint32_t[]){true, 4},
2645 .translate
= translate_all
,
2646 .par
= (const uint32_t[]){true, 8},
2649 .translate
= translate_and
,
2652 .translate
= translate_boolean
,
2653 .par
= (const uint32_t[]){BOOLEAN_AND
},
2656 .translate
= translate_boolean
,
2657 .par
= (const uint32_t[]){BOOLEAN_ANDC
},
2660 .translate
= translate_all
,
2661 .par
= (const uint32_t[]){false, 4},
2664 .translate
= translate_all
,
2665 .par
= (const uint32_t[]){false, 8},
2668 .translate
= translate_ball
,
2669 .par
= (const uint32_t[]){TCG_COND_EQ
},
2672 .translate
= translate_bany
,
2673 .par
= (const uint32_t[]){TCG_COND_NE
},
2676 .translate
= translate_bb
,
2677 .par
= (const uint32_t[]){TCG_COND_EQ
},
2680 .translate
= translate_bbi
,
2681 .par
= (const uint32_t[]){TCG_COND_EQ
},
2684 .translate
= translate_bb
,
2685 .par
= (const uint32_t[]){TCG_COND_NE
},
2688 .translate
= translate_bbi
,
2689 .par
= (const uint32_t[]){TCG_COND_NE
},
2692 .translate
= translate_b
,
2693 .par
= (const uint32_t[]){TCG_COND_EQ
},
2696 .translate
= translate_bi
,
2697 .par
= (const uint32_t[]){TCG_COND_EQ
},
2700 .translate
= translate_bz
,
2701 .par
= (const uint32_t[]){TCG_COND_EQ
},
2704 .translate
= translate_bz
,
2705 .par
= (const uint32_t[]){TCG_COND_EQ
},
2708 .translate
= translate_bp
,
2709 .par
= (const uint32_t[]){TCG_COND_EQ
},
2712 .translate
= translate_b
,
2713 .par
= (const uint32_t[]){TCG_COND_GE
},
2716 .translate
= translate_bi
,
2717 .par
= (const uint32_t[]){TCG_COND_GE
},
2720 .translate
= translate_b
,
2721 .par
= (const uint32_t[]){TCG_COND_GEU
},
2724 .translate
= translate_bi
,
2725 .par
= (const uint32_t[]){TCG_COND_GEU
},
2728 .translate
= translate_bz
,
2729 .par
= (const uint32_t[]){TCG_COND_GE
},
2732 .translate
= translate_b
,
2733 .par
= (const uint32_t[]){TCG_COND_LT
},
2736 .translate
= translate_bi
,
2737 .par
= (const uint32_t[]){TCG_COND_LT
},
2740 .translate
= translate_b
,
2741 .par
= (const uint32_t[]){TCG_COND_LTU
},
2744 .translate
= translate_bi
,
2745 .par
= (const uint32_t[]){TCG_COND_LTU
},
2748 .translate
= translate_bz
,
2749 .par
= (const uint32_t[]){TCG_COND_LT
},
2752 .translate
= translate_ball
,
2753 .par
= (const uint32_t[]){TCG_COND_NE
},
2756 .translate
= translate_b
,
2757 .par
= (const uint32_t[]){TCG_COND_NE
},
2760 .translate
= translate_bi
,
2761 .par
= (const uint32_t[]){TCG_COND_NE
},
2764 .translate
= translate_bz
,
2765 .par
= (const uint32_t[]){TCG_COND_NE
},
2768 .translate
= translate_bz
,
2769 .par
= (const uint32_t[]){TCG_COND_NE
},
2772 .translate
= translate_bany
,
2773 .par
= (const uint32_t[]){TCG_COND_EQ
},
2776 .translate
= translate_break
,
2777 .par
= (const uint32_t[]){DEBUGCAUSE_BI
},
2780 .translate
= translate_break
,
2781 .par
= (const uint32_t[]){DEBUGCAUSE_BN
},
2784 .translate
= translate_bp
,
2785 .par
= (const uint32_t[]){TCG_COND_NE
},
2788 .translate
= translate_call0
,
2791 .translate
= translate_callw
,
2792 .par
= (const uint32_t[]){3},
2795 .translate
= translate_callw
,
2796 .par
= (const uint32_t[]){1},
2799 .translate
= translate_callw
,
2800 .par
= (const uint32_t[]){2},
2803 .translate
= translate_callx0
,
2806 .translate
= translate_callxw
,
2807 .par
= (const uint32_t[]){3},
2810 .translate
= translate_callxw
,
2811 .par
= (const uint32_t[]){1},
2814 .translate
= translate_callxw
,
2815 .par
= (const uint32_t[]){2},
2818 .translate
= translate_clamps
,
2820 .name
= "clrb_expstate",
2821 .translate
= translate_clrb_expstate
,
2824 .translate
= translate_const16
,
2827 .translate
= translate_depbits
,
2830 .translate
= translate_dcache
,
2831 .par
= (const uint32_t[]){true, true},
2834 .translate
= translate_dcache
,
2835 .par
= (const uint32_t[]){true, true},
2838 .translate
= translate_dcache
,
2839 .par
= (const uint32_t[]){false, true},
2842 .translate
= translate_dcache
,
2843 .par
= (const uint32_t[]){false, true},
2846 .translate
= translate_dcache
,
2847 .par
= (const uint32_t[]){true, false},
2850 .translate
= translate_dcache
,
2851 .par
= (const uint32_t[]){true, false},
2854 .translate
= translate_dcache
,
2855 .par
= (const uint32_t[]){true, false},
2858 .translate
= translate_dcache
,
2859 .par
= (const uint32_t[]){true, false},
2862 .translate
= translate_dcache
,
2863 .par
= (const uint32_t[]){true, true},
2866 .translate
= translate_dcache
,
2867 .par
= (const uint32_t[]){false, false},
2870 .translate
= translate_dcache
,
2871 .par
= (const uint32_t[]){false, false},
2874 .translate
= translate_dcache
,
2875 .par
= (const uint32_t[]){false, false},
2878 .translate
= translate_dcache
,
2879 .par
= (const uint32_t[]){false, false},
2882 .translate
= translate_nop
,
2885 .translate
= translate_entry
,
2888 .translate
= translate_nop
,
2891 .translate
= translate_nop
,
2894 .translate
= translate_extui
,
2897 .translate
= translate_memw
,
2900 .translate
= translate_ill
,
2903 .translate
= translate_ill
,
2906 .translate
= translate_itlb
,
2907 .par
= (const uint32_t[]){true},
2910 .translate
= translate_icache
,
2911 .par
= (const uint32_t[]){false, true},
2914 .translate
= translate_icache
,
2915 .par
= (const uint32_t[]){true, true},
2918 .translate
= translate_icache
,
2919 .par
= (const uint32_t[]){true, false},
2922 .translate
= translate_itlb
,
2923 .par
= (const uint32_t[]){false},
2926 .translate
= translate_icache
,
2927 .par
= (const uint32_t[]){true, false},
2930 .translate
= translate_ill
,
2933 .translate
= translate_ill
,
2936 .translate
= translate_icache
,
2937 .par
= (const uint32_t[]){false, false},
2940 .translate
= translate_icache
,
2941 .par
= (const uint32_t[]){true, true},
2944 .translate
= translate_nop
,
2947 .translate
= translate_j
,
2950 .translate
= translate_jx
,
2953 .translate
= translate_ldst
,
2954 .par
= (const uint32_t[]){MO_TESW
, false, false},
2957 .translate
= translate_ldst
,
2958 .par
= (const uint32_t[]){MO_TEUW
, false, false},
2961 .translate
= translate_ldst
,
2962 .par
= (const uint32_t[]){MO_TEUL
, true, false},
2965 .translate
= translate_l32e
,
2968 .translate
= translate_ldst
,
2969 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2972 .translate
= translate_ldst
,
2973 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2976 .translate
= translate_l32r
,
2979 .translate
= translate_ldst
,
2980 .par
= (const uint32_t[]){MO_UB
, false, false},
2983 .translate
= translate_mac16
,
2984 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, -4},
2987 .translate
= translate_mac16
,
2988 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, 4},
2991 .translate
= translate_ill
,
2994 .translate
= translate_loop
,
2995 .par
= (const uint32_t[]){TCG_COND_NEVER
},
2998 .translate
= translate_loop
,
2999 .par
= (const uint32_t[]){TCG_COND_GT
},
3002 .translate
= translate_loop
,
3003 .par
= (const uint32_t[]){TCG_COND_NE
},
3006 .translate
= translate_smax
,
3009 .translate
= translate_umax
,
3012 .translate
= translate_memw
,
3015 .translate
= translate_smin
,
3018 .translate
= translate_umin
,
3021 .translate
= translate_mov
,
3024 .translate
= translate_mov
,
3027 .translate
= translate_movcond
,
3028 .par
= (const uint32_t[]){TCG_COND_EQ
},
3031 .translate
= translate_movp
,
3032 .par
= (const uint32_t[]){TCG_COND_EQ
},
3035 .translate
= translate_movcond
,
3036 .par
= (const uint32_t[]){TCG_COND_GE
},
3039 .translate
= translate_movi
,
3042 .translate
= translate_movi
,
3045 .translate
= translate_movcond
,
3046 .par
= (const uint32_t[]){TCG_COND_LT
},
3049 .translate
= translate_movcond
,
3050 .par
= (const uint32_t[]){TCG_COND_NE
},
3053 .translate
= translate_movsp
,
3056 .translate
= translate_movp
,
3057 .par
= (const uint32_t[]){TCG_COND_NE
},
3059 .name
= "mul.aa.hh",
3060 .translate
= translate_mac16
,
3061 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HH
, 0},
3063 .name
= "mul.aa.hl",
3064 .translate
= translate_mac16
,
3065 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HL
, 0},
3067 .name
= "mul.aa.lh",
3068 .translate
= translate_mac16
,
3069 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LH
, 0},
3071 .name
= "mul.aa.ll",
3072 .translate
= translate_mac16
,
3073 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LL
, 0},
3075 .name
= "mul.ad.hh",
3076 .translate
= translate_mac16
,
3077 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HH
, 0},
3079 .name
= "mul.ad.hl",
3080 .translate
= translate_mac16
,
3081 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HL
, 0},
3083 .name
= "mul.ad.lh",
3084 .translate
= translate_mac16
,
3085 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LH
, 0},
3087 .name
= "mul.ad.ll",
3088 .translate
= translate_mac16
,
3089 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LL
, 0},
3091 .name
= "mul.da.hh",
3092 .translate
= translate_mac16
,
3093 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HH
, 0},
3095 .name
= "mul.da.hl",
3096 .translate
= translate_mac16
,
3097 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HL
, 0},
3099 .name
= "mul.da.lh",
3100 .translate
= translate_mac16
,
3101 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LH
, 0},
3103 .name
= "mul.da.ll",
3104 .translate
= translate_mac16
,
3105 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LL
, 0},
3107 .name
= "mul.dd.hh",
3108 .translate
= translate_mac16
,
3109 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HH
, 0},
3111 .name
= "mul.dd.hl",
3112 .translate
= translate_mac16
,
3113 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HL
, 0},
3115 .name
= "mul.dd.lh",
3116 .translate
= translate_mac16
,
3117 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LH
, 0},
3119 .name
= "mul.dd.ll",
3120 .translate
= translate_mac16
,
3121 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LL
, 0},
3124 .translate
= translate_mul16
,
3125 .par
= (const uint32_t[]){true},
3128 .translate
= translate_mul16
,
3129 .par
= (const uint32_t[]){false},
3131 .name
= "mula.aa.hh",
3132 .translate
= translate_mac16
,
3133 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HH
, 0},
3135 .name
= "mula.aa.hl",
3136 .translate
= translate_mac16
,
3137 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HL
, 0},
3139 .name
= "mula.aa.lh",
3140 .translate
= translate_mac16
,
3141 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LH
, 0},
3143 .name
= "mula.aa.ll",
3144 .translate
= translate_mac16
,
3145 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LL
, 0},
3147 .name
= "mula.ad.hh",
3148 .translate
= translate_mac16
,
3149 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HH
, 0},
3151 .name
= "mula.ad.hl",
3152 .translate
= translate_mac16
,
3153 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HL
, 0},
3155 .name
= "mula.ad.lh",
3156 .translate
= translate_mac16
,
3157 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LH
, 0},
3159 .name
= "mula.ad.ll",
3160 .translate
= translate_mac16
,
3161 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LL
, 0},
3163 .name
= "mula.da.hh",
3164 .translate
= translate_mac16
,
3165 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 0},
3167 .name
= "mula.da.hh.lddec",
3168 .translate
= translate_mac16
,
3169 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, -4},
3171 .name
= "mula.da.hh.ldinc",
3172 .translate
= translate_mac16
,
3173 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 4},
3175 .name
= "mula.da.hl",
3176 .translate
= translate_mac16
,
3177 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 0},
3179 .name
= "mula.da.hl.lddec",
3180 .translate
= translate_mac16
,
3181 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, -4},
3183 .name
= "mula.da.hl.ldinc",
3184 .translate
= translate_mac16
,
3185 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 4},
3187 .name
= "mula.da.lh",
3188 .translate
= translate_mac16
,
3189 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 0},
3191 .name
= "mula.da.lh.lddec",
3192 .translate
= translate_mac16
,
3193 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, -4},
3195 .name
= "mula.da.lh.ldinc",
3196 .translate
= translate_mac16
,
3197 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 4},
3199 .name
= "mula.da.ll",
3200 .translate
= translate_mac16
,
3201 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 0},
3203 .name
= "mula.da.ll.lddec",
3204 .translate
= translate_mac16
,
3205 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, -4},
3207 .name
= "mula.da.ll.ldinc",
3208 .translate
= translate_mac16
,
3209 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 4},
3211 .name
= "mula.dd.hh",
3212 .translate
= translate_mac16
,
3213 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 0},
3215 .name
= "mula.dd.hh.lddec",
3216 .translate
= translate_mac16
,
3217 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, -4},
3219 .name
= "mula.dd.hh.ldinc",
3220 .translate
= translate_mac16
,
3221 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 4},
3223 .name
= "mula.dd.hl",
3224 .translate
= translate_mac16
,
3225 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 0},
3227 .name
= "mula.dd.hl.lddec",
3228 .translate
= translate_mac16
,
3229 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, -4},
3231 .name
= "mula.dd.hl.ldinc",
3232 .translate
= translate_mac16
,
3233 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 4},
3235 .name
= "mula.dd.lh",
3236 .translate
= translate_mac16
,
3237 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 0},
3239 .name
= "mula.dd.lh.lddec",
3240 .translate
= translate_mac16
,
3241 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, -4},
3243 .name
= "mula.dd.lh.ldinc",
3244 .translate
= translate_mac16
,
3245 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 4},
3247 .name
= "mula.dd.ll",
3248 .translate
= translate_mac16
,
3249 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 0},
3251 .name
= "mula.dd.ll.lddec",
3252 .translate
= translate_mac16
,
3253 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, -4},
3255 .name
= "mula.dd.ll.ldinc",
3256 .translate
= translate_mac16
,
3257 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 4},
3260 .translate
= translate_mull
,
3262 .name
= "muls.aa.hh",
3263 .translate
= translate_mac16
,
3264 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HH
, 0},
3266 .name
= "muls.aa.hl",
3267 .translate
= translate_mac16
,
3268 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HL
, 0},
3270 .name
= "muls.aa.lh",
3271 .translate
= translate_mac16
,
3272 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LH
, 0},
3274 .name
= "muls.aa.ll",
3275 .translate
= translate_mac16
,
3276 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LL
, 0},
3278 .name
= "muls.ad.hh",
3279 .translate
= translate_mac16
,
3280 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HH
, 0},
3282 .name
= "muls.ad.hl",
3283 .translate
= translate_mac16
,
3284 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HL
, 0},
3286 .name
= "muls.ad.lh",
3287 .translate
= translate_mac16
,
3288 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LH
, 0},
3290 .name
= "muls.ad.ll",
3291 .translate
= translate_mac16
,
3292 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LL
, 0},
3294 .name
= "muls.da.hh",
3295 .translate
= translate_mac16
,
3296 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HH
, 0},
3298 .name
= "muls.da.hl",
3299 .translate
= translate_mac16
,
3300 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HL
, 0},
3302 .name
= "muls.da.lh",
3303 .translate
= translate_mac16
,
3304 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LH
, 0},
3306 .name
= "muls.da.ll",
3307 .translate
= translate_mac16
,
3308 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LL
, 0},
3310 .name
= "muls.dd.hh",
3311 .translate
= translate_mac16
,
3312 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HH
, 0},
3314 .name
= "muls.dd.hl",
3315 .translate
= translate_mac16
,
3316 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HL
, 0},
3318 .name
= "muls.dd.lh",
3319 .translate
= translate_mac16
,
3320 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LH
, 0},
3322 .name
= "muls.dd.ll",
3323 .translate
= translate_mac16
,
3324 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LL
, 0},
3327 .translate
= translate_mulh
,
3328 .par
= (const uint32_t[]){true},
3331 .translate
= translate_mulh
,
3332 .par
= (const uint32_t[]){false},
3335 .translate
= translate_neg
,
3338 .translate
= translate_nop
,
3341 .translate
= translate_nop
,
3344 .translate
= translate_nsa
,
3347 .translate
= translate_nsau
,
3350 .translate
= translate_or
,
3353 .translate
= translate_boolean
,
3354 .par
= (const uint32_t[]){BOOLEAN_OR
},
3357 .translate
= translate_boolean
,
3358 .par
= (const uint32_t[]){BOOLEAN_ORC
},
3361 .translate
= translate_ptlb
,
3362 .par
= (const uint32_t[]){true},
3365 .translate
= translate_ptlb
,
3366 .par
= (const uint32_t[]){false},
3369 .translate
= translate_quos
,
3370 .par
= (const uint32_t[]){true},
3373 .translate
= translate_quou
,
3374 .par
= (const uint32_t[]){true},
3377 .translate
= translate_rtlb
,
3378 .par
= (const uint32_t[]){true, 0},
3381 .translate
= translate_rtlb
,
3382 .par
= (const uint32_t[]){true, 1},
3384 .name
= "read_impwire",
3385 .translate
= translate_read_impwire
,
3388 .translate
= translate_quos
,
3389 .par
= (const uint32_t[]){false},
3392 .translate
= translate_quou
,
3393 .par
= (const uint32_t[]){false},
3396 .translate
= translate_rer
,
3399 .translate
= translate_ret
,
3402 .translate
= translate_ret
,
3405 .translate
= translate_retw
,
3408 .translate
= translate_retw
,
3411 .translate
= translate_ill
,
3414 .translate
= translate_rfde
,
3417 .translate
= translate_ill
,
3420 .translate
= translate_rfe
,
3423 .translate
= translate_rfi
,
3426 .translate
= translate_rfw
,
3427 .par
= (const uint32_t[]){true},
3430 .translate
= translate_rfw
,
3431 .par
= (const uint32_t[]){false},
3434 .translate
= translate_rtlb
,
3435 .par
= (const uint32_t[]){false, 0},
3438 .translate
= translate_rtlb
,
3439 .par
= (const uint32_t[]){false, 1},
3442 .translate
= translate_rotw
,
3445 .translate
= translate_rsil
,
3448 .translate
= translate_rsr
,
3449 .par
= (const uint32_t[]){176},
3452 .translate
= translate_rsr
,
3453 .par
= (const uint32_t[]){208},
3455 .name
= "rsr.acchi",
3456 .translate
= translate_rsr
,
3457 .par
= (const uint32_t[]){ACCHI
},
3459 .name
= "rsr.acclo",
3460 .translate
= translate_rsr
,
3461 .par
= (const uint32_t[]){ACCLO
},
3463 .name
= "rsr.atomctl",
3464 .translate
= translate_rsr
,
3465 .par
= (const uint32_t[]){ATOMCTL
},
3468 .translate
= translate_rsr
,
3469 .par
= (const uint32_t[]){BR
},
3471 .name
= "rsr.cacheattr",
3472 .translate
= translate_rsr
,
3473 .par
= (const uint32_t[]){CACHEATTR
},
3475 .name
= "rsr.ccompare0",
3476 .translate
= translate_rsr
,
3477 .par
= (const uint32_t[]){CCOMPARE
},
3479 .name
= "rsr.ccompare1",
3480 .translate
= translate_rsr
,
3481 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3483 .name
= "rsr.ccompare2",
3484 .translate
= translate_rsr
,
3485 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3487 .name
= "rsr.ccount",
3488 .translate
= translate_rsr
,
3489 .par
= (const uint32_t[]){CCOUNT
},
3491 .name
= "rsr.configid0",
3492 .translate
= translate_rsr
,
3493 .par
= (const uint32_t[]){CONFIGID0
},
3495 .name
= "rsr.configid1",
3496 .translate
= translate_rsr
,
3497 .par
= (const uint32_t[]){CONFIGID1
},
3499 .name
= "rsr.cpenable",
3500 .translate
= translate_rsr
,
3501 .par
= (const uint32_t[]){CPENABLE
},
3503 .name
= "rsr.dbreaka0",
3504 .translate
= translate_rsr
,
3505 .par
= (const uint32_t[]){DBREAKA
},
3507 .name
= "rsr.dbreaka1",
3508 .translate
= translate_rsr
,
3509 .par
= (const uint32_t[]){DBREAKA
+ 1},
3511 .name
= "rsr.dbreakc0",
3512 .translate
= translate_rsr
,
3513 .par
= (const uint32_t[]){DBREAKC
},
3515 .name
= "rsr.dbreakc1",
3516 .translate
= translate_rsr
,
3517 .par
= (const uint32_t[]){DBREAKC
+ 1},
3520 .translate
= translate_rsr
,
3521 .par
= (const uint32_t[]){DDR
},
3523 .name
= "rsr.debugcause",
3524 .translate
= translate_rsr
,
3525 .par
= (const uint32_t[]){DEBUGCAUSE
},
3528 .translate
= translate_rsr
,
3529 .par
= (const uint32_t[]){DEPC
},
3531 .name
= "rsr.dtlbcfg",
3532 .translate
= translate_rsr
,
3533 .par
= (const uint32_t[]){DTLBCFG
},
3536 .translate
= translate_rsr
,
3537 .par
= (const uint32_t[]){EPC1
},
3540 .translate
= translate_rsr
,
3541 .par
= (const uint32_t[]){EPC1
+ 1},
3544 .translate
= translate_rsr
,
3545 .par
= (const uint32_t[]){EPC1
+ 2},
3548 .translate
= translate_rsr
,
3549 .par
= (const uint32_t[]){EPC1
+ 3},
3552 .translate
= translate_rsr
,
3553 .par
= (const uint32_t[]){EPC1
+ 4},
3556 .translate
= translate_rsr
,
3557 .par
= (const uint32_t[]){EPC1
+ 5},
3560 .translate
= translate_rsr
,
3561 .par
= (const uint32_t[]){EPC1
+ 6},
3564 .translate
= translate_rsr
,
3565 .par
= (const uint32_t[]){EPS2
},
3568 .translate
= translate_rsr
,
3569 .par
= (const uint32_t[]){EPS2
+ 1},
3572 .translate
= translate_rsr
,
3573 .par
= (const uint32_t[]){EPS2
+ 2},
3576 .translate
= translate_rsr
,
3577 .par
= (const uint32_t[]){EPS2
+ 3},
3580 .translate
= translate_rsr
,
3581 .par
= (const uint32_t[]){EPS2
+ 4},
3584 .translate
= translate_rsr
,
3585 .par
= (const uint32_t[]){EPS2
+ 5},
3587 .name
= "rsr.exccause",
3588 .translate
= translate_rsr
,
3589 .par
= (const uint32_t[]){EXCCAUSE
},
3591 .name
= "rsr.excsave1",
3592 .translate
= translate_rsr
,
3593 .par
= (const uint32_t[]){EXCSAVE1
},
3595 .name
= "rsr.excsave2",
3596 .translate
= translate_rsr
,
3597 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
3599 .name
= "rsr.excsave3",
3600 .translate
= translate_rsr
,
3601 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
3603 .name
= "rsr.excsave4",
3604 .translate
= translate_rsr
,
3605 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
3607 .name
= "rsr.excsave5",
3608 .translate
= translate_rsr
,
3609 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
3611 .name
= "rsr.excsave6",
3612 .translate
= translate_rsr
,
3613 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
3615 .name
= "rsr.excsave7",
3616 .translate
= translate_rsr
,
3617 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
3619 .name
= "rsr.excvaddr",
3620 .translate
= translate_rsr
,
3621 .par
= (const uint32_t[]){EXCVADDR
},
3623 .name
= "rsr.ibreaka0",
3624 .translate
= translate_rsr
,
3625 .par
= (const uint32_t[]){IBREAKA
},
3627 .name
= "rsr.ibreaka1",
3628 .translate
= translate_rsr
,
3629 .par
= (const uint32_t[]){IBREAKA
+ 1},
3631 .name
= "rsr.ibreakenable",
3632 .translate
= translate_rsr
,
3633 .par
= (const uint32_t[]){IBREAKENABLE
},
3635 .name
= "rsr.icount",
3636 .translate
= translate_rsr
,
3637 .par
= (const uint32_t[]){ICOUNT
},
3639 .name
= "rsr.icountlevel",
3640 .translate
= translate_rsr
,
3641 .par
= (const uint32_t[]){ICOUNTLEVEL
},
3643 .name
= "rsr.intclear",
3644 .translate
= translate_rsr
,
3645 .par
= (const uint32_t[]){INTCLEAR
},
3647 .name
= "rsr.intenable",
3648 .translate
= translate_rsr
,
3649 .par
= (const uint32_t[]){INTENABLE
},
3651 .name
= "rsr.interrupt",
3652 .translate
= translate_rsr
,
3653 .par
= (const uint32_t[]){INTSET
},
3655 .name
= "rsr.intset",
3656 .translate
= translate_rsr
,
3657 .par
= (const uint32_t[]){INTSET
},
3659 .name
= "rsr.itlbcfg",
3660 .translate
= translate_rsr
,
3661 .par
= (const uint32_t[]){ITLBCFG
},
3664 .translate
= translate_rsr
,
3665 .par
= (const uint32_t[]){LBEG
},
3667 .name
= "rsr.lcount",
3668 .translate
= translate_rsr
,
3669 .par
= (const uint32_t[]){LCOUNT
},
3672 .translate
= translate_rsr
,
3673 .par
= (const uint32_t[]){LEND
},
3675 .name
= "rsr.litbase",
3676 .translate
= translate_rsr
,
3677 .par
= (const uint32_t[]){LITBASE
},
3680 .translate
= translate_rsr
,
3681 .par
= (const uint32_t[]){MR
},
3684 .translate
= translate_rsr
,
3685 .par
= (const uint32_t[]){MR
+ 1},
3688 .translate
= translate_rsr
,
3689 .par
= (const uint32_t[]){MR
+ 2},
3692 .translate
= translate_rsr
,
3693 .par
= (const uint32_t[]){MR
+ 3},
3695 .name
= "rsr.memctl",
3696 .translate
= translate_rsr
,
3697 .par
= (const uint32_t[]){MEMCTL
},
3699 .name
= "rsr.misc0",
3700 .translate
= translate_rsr
,
3701 .par
= (const uint32_t[]){MISC
},
3703 .name
= "rsr.misc1",
3704 .translate
= translate_rsr
,
3705 .par
= (const uint32_t[]){MISC
+ 1},
3707 .name
= "rsr.misc2",
3708 .translate
= translate_rsr
,
3709 .par
= (const uint32_t[]){MISC
+ 2},
3711 .name
= "rsr.misc3",
3712 .translate
= translate_rsr
,
3713 .par
= (const uint32_t[]){MISC
+ 3},
3716 .translate
= translate_rsr
,
3717 .par
= (const uint32_t[]){PRID
},
3720 .translate
= translate_rsr
,
3721 .par
= (const uint32_t[]){PS
},
3723 .name
= "rsr.ptevaddr",
3724 .translate
= translate_rsr
,
3725 .par
= (const uint32_t[]){PTEVADDR
},
3727 .name
= "rsr.rasid",
3728 .translate
= translate_rsr
,
3729 .par
= (const uint32_t[]){RASID
},
3732 .translate
= translate_rsr
,
3733 .par
= (const uint32_t[]){SAR
},
3735 .name
= "rsr.scompare1",
3736 .translate
= translate_rsr
,
3737 .par
= (const uint32_t[]){SCOMPARE1
},
3739 .name
= "rsr.vecbase",
3740 .translate
= translate_rsr
,
3741 .par
= (const uint32_t[]){VECBASE
},
3743 .name
= "rsr.windowbase",
3744 .translate
= translate_rsr
,
3745 .par
= (const uint32_t[]){WINDOW_BASE
},
3747 .name
= "rsr.windowstart",
3748 .translate
= translate_rsr
,
3749 .par
= (const uint32_t[]){WINDOW_START
},
3752 .translate
= translate_nop
,
3754 .name
= "rur.expstate",
3755 .translate
= translate_rur
,
3756 .par
= (const uint32_t[]){EXPSTATE
},
3759 .translate
= translate_rur
,
3760 .par
= (const uint32_t[]){FCR
},
3763 .translate
= translate_rur
,
3764 .par
= (const uint32_t[]){FSR
},
3766 .name
= "rur.threadptr",
3767 .translate
= translate_rur
,
3768 .par
= (const uint32_t[]){THREADPTR
},
3771 .translate
= translate_ldst
,
3772 .par
= (const uint32_t[]){MO_TEUW
, false, true},
3775 .translate
= translate_s32c1i
,
3778 .translate
= translate_s32e
,
3781 .translate
= translate_ldst
,
3782 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3785 .translate
= translate_ldst
,
3786 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3789 .translate
= translate_ldst
,
3790 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3793 .translate
= translate_ldst
,
3794 .par
= (const uint32_t[]){MO_TEUL
, true, true},
3797 .translate
= translate_ldst
,
3798 .par
= (const uint32_t[]){MO_UB
, false, true},
3801 .translate
= translate_salt
,
3802 .par
= (const uint32_t[]){TCG_COND_LT
},
3805 .translate
= translate_salt
,
3806 .par
= (const uint32_t[]){TCG_COND_LTU
},
3808 .name
= "setb_expstate",
3809 .translate
= translate_setb_expstate
,
3812 .translate
= translate_sext
,
3815 .translate
= translate_simcall
,
3818 .translate
= translate_sll
,
3821 .translate
= translate_slli
,
3824 .translate
= translate_sra
,
3827 .translate
= translate_srai
,
3830 .translate
= translate_src
,
3833 .translate
= translate_srl
,
3836 .translate
= translate_srli
,
3839 .translate
= translate_ssa8b
,
3842 .translate
= translate_ssa8l
,
3845 .translate
= translate_ssai
,
3848 .translate
= translate_ssl
,
3851 .translate
= translate_ssr
,
3854 .translate
= translate_sub
,
3857 .translate
= translate_subx
,
3858 .par
= (const uint32_t[]){1},
3861 .translate
= translate_subx
,
3862 .par
= (const uint32_t[]){2},
3865 .translate
= translate_subx
,
3866 .par
= (const uint32_t[]){3},
3869 .translate
= translate_syscall
,
3871 .name
= "umul.aa.hh",
3872 .translate
= translate_mac16
,
3873 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HH
, 0},
3875 .name
= "umul.aa.hl",
3876 .translate
= translate_mac16
,
3877 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HL
, 0},
3879 .name
= "umul.aa.lh",
3880 .translate
= translate_mac16
,
3881 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LH
, 0},
3883 .name
= "umul.aa.ll",
3884 .translate
= translate_mac16
,
3885 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LL
, 0},
3888 .translate
= translate_waiti
,
3891 .translate
= translate_wtlb
,
3892 .par
= (const uint32_t[]){true},
3895 .translate
= translate_wer
,
3898 .translate
= translate_wtlb
,
3899 .par
= (const uint32_t[]){false},
3901 .name
= "wrmsk_expstate",
3902 .translate
= translate_wrmsk_expstate
,
3905 .translate
= translate_wsr
,
3906 .par
= (const uint32_t[]){176},
3909 .translate
= translate_wsr
,
3910 .par
= (const uint32_t[]){208},
3912 .name
= "wsr.acchi",
3913 .translate
= translate_wsr
,
3914 .par
= (const uint32_t[]){ACCHI
},
3916 .name
= "wsr.acclo",
3917 .translate
= translate_wsr
,
3918 .par
= (const uint32_t[]){ACCLO
},
3920 .name
= "wsr.atomctl",
3921 .translate
= translate_wsr
,
3922 .par
= (const uint32_t[]){ATOMCTL
},
3925 .translate
= translate_wsr
,
3926 .par
= (const uint32_t[]){BR
},
3928 .name
= "wsr.cacheattr",
3929 .translate
= translate_wsr
,
3930 .par
= (const uint32_t[]){CACHEATTR
},
3932 .name
= "wsr.ccompare0",
3933 .translate
= translate_wsr
,
3934 .par
= (const uint32_t[]){CCOMPARE
},
3936 .name
= "wsr.ccompare1",
3937 .translate
= translate_wsr
,
3938 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3940 .name
= "wsr.ccompare2",
3941 .translate
= translate_wsr
,
3942 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3944 .name
= "wsr.ccount",
3945 .translate
= translate_wsr
,
3946 .par
= (const uint32_t[]){CCOUNT
},
3948 .name
= "wsr.configid0",
3949 .translate
= translate_wsr
,
3950 .par
= (const uint32_t[]){CONFIGID0
},
3952 .name
= "wsr.configid1",
3953 .translate
= translate_wsr
,
3954 .par
= (const uint32_t[]){CONFIGID1
},
3956 .name
= "wsr.cpenable",
3957 .translate
= translate_wsr
,
3958 .par
= (const uint32_t[]){CPENABLE
},
3960 .name
= "wsr.dbreaka0",
3961 .translate
= translate_wsr
,
3962 .par
= (const uint32_t[]){DBREAKA
},
3964 .name
= "wsr.dbreaka1",
3965 .translate
= translate_wsr
,
3966 .par
= (const uint32_t[]){DBREAKA
+ 1},
3968 .name
= "wsr.dbreakc0",
3969 .translate
= translate_wsr
,
3970 .par
= (const uint32_t[]){DBREAKC
},
3972 .name
= "wsr.dbreakc1",
3973 .translate
= translate_wsr
,
3974 .par
= (const uint32_t[]){DBREAKC
+ 1},
3977 .translate
= translate_wsr
,
3978 .par
= (const uint32_t[]){DDR
},
3980 .name
= "wsr.debugcause",
3981 .translate
= translate_wsr
,
3982 .par
= (const uint32_t[]){DEBUGCAUSE
},
3985 .translate
= translate_wsr
,
3986 .par
= (const uint32_t[]){DEPC
},
3988 .name
= "wsr.dtlbcfg",
3989 .translate
= translate_wsr
,
3990 .par
= (const uint32_t[]){DTLBCFG
},
3993 .translate
= translate_wsr
,
3994 .par
= (const uint32_t[]){EPC1
},
3997 .translate
= translate_wsr
,
3998 .par
= (const uint32_t[]){EPC1
+ 1},
4001 .translate
= translate_wsr
,
4002 .par
= (const uint32_t[]){EPC1
+ 2},
4005 .translate
= translate_wsr
,
4006 .par
= (const uint32_t[]){EPC1
+ 3},
4009 .translate
= translate_wsr
,
4010 .par
= (const uint32_t[]){EPC1
+ 4},
4013 .translate
= translate_wsr
,
4014 .par
= (const uint32_t[]){EPC1
+ 5},
4017 .translate
= translate_wsr
,
4018 .par
= (const uint32_t[]){EPC1
+ 6},
4021 .translate
= translate_wsr
,
4022 .par
= (const uint32_t[]){EPS2
},
4025 .translate
= translate_wsr
,
4026 .par
= (const uint32_t[]){EPS2
+ 1},
4029 .translate
= translate_wsr
,
4030 .par
= (const uint32_t[]){EPS2
+ 2},
4033 .translate
= translate_wsr
,
4034 .par
= (const uint32_t[]){EPS2
+ 3},
4037 .translate
= translate_wsr
,
4038 .par
= (const uint32_t[]){EPS2
+ 4},
4041 .translate
= translate_wsr
,
4042 .par
= (const uint32_t[]){EPS2
+ 5},
4044 .name
= "wsr.exccause",
4045 .translate
= translate_wsr
,
4046 .par
= (const uint32_t[]){EXCCAUSE
},
4048 .name
= "wsr.excsave1",
4049 .translate
= translate_wsr
,
4050 .par
= (const uint32_t[]){EXCSAVE1
},
4052 .name
= "wsr.excsave2",
4053 .translate
= translate_wsr
,
4054 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
4056 .name
= "wsr.excsave3",
4057 .translate
= translate_wsr
,
4058 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
4060 .name
= "wsr.excsave4",
4061 .translate
= translate_wsr
,
4062 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
4064 .name
= "wsr.excsave5",
4065 .translate
= translate_wsr
,
4066 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4068 .name
= "wsr.excsave6",
4069 .translate
= translate_wsr
,
4070 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4072 .name
= "wsr.excsave7",
4073 .translate
= translate_wsr
,
4074 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4076 .name
= "wsr.excvaddr",
4077 .translate
= translate_wsr
,
4078 .par
= (const uint32_t[]){EXCVADDR
},
4080 .name
= "wsr.ibreaka0",
4081 .translate
= translate_wsr
,
4082 .par
= (const uint32_t[]){IBREAKA
},
4084 .name
= "wsr.ibreaka1",
4085 .translate
= translate_wsr
,
4086 .par
= (const uint32_t[]){IBREAKA
+ 1},
4088 .name
= "wsr.ibreakenable",
4089 .translate
= translate_wsr
,
4090 .par
= (const uint32_t[]){IBREAKENABLE
},
4092 .name
= "wsr.icount",
4093 .translate
= translate_wsr
,
4094 .par
= (const uint32_t[]){ICOUNT
},
4096 .name
= "wsr.icountlevel",
4097 .translate
= translate_wsr
,
4098 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4100 .name
= "wsr.intclear",
4101 .translate
= translate_wsr
,
4102 .par
= (const uint32_t[]){INTCLEAR
},
4104 .name
= "wsr.intenable",
4105 .translate
= translate_wsr
,
4106 .par
= (const uint32_t[]){INTENABLE
},
4108 .name
= "wsr.interrupt",
4109 .translate
= translate_wsr
,
4110 .par
= (const uint32_t[]){INTSET
},
4112 .name
= "wsr.intset",
4113 .translate
= translate_wsr
,
4114 .par
= (const uint32_t[]){INTSET
},
4116 .name
= "wsr.itlbcfg",
4117 .translate
= translate_wsr
,
4118 .par
= (const uint32_t[]){ITLBCFG
},
4121 .translate
= translate_wsr
,
4122 .par
= (const uint32_t[]){LBEG
},
4124 .name
= "wsr.lcount",
4125 .translate
= translate_wsr
,
4126 .par
= (const uint32_t[]){LCOUNT
},
4129 .translate
= translate_wsr
,
4130 .par
= (const uint32_t[]){LEND
},
4132 .name
= "wsr.litbase",
4133 .translate
= translate_wsr
,
4134 .par
= (const uint32_t[]){LITBASE
},
4137 .translate
= translate_wsr
,
4138 .par
= (const uint32_t[]){MR
},
4141 .translate
= translate_wsr
,
4142 .par
= (const uint32_t[]){MR
+ 1},
4145 .translate
= translate_wsr
,
4146 .par
= (const uint32_t[]){MR
+ 2},
4149 .translate
= translate_wsr
,
4150 .par
= (const uint32_t[]){MR
+ 3},
4152 .name
= "wsr.memctl",
4153 .translate
= translate_wsr
,
4154 .par
= (const uint32_t[]){MEMCTL
},
4156 .name
= "wsr.misc0",
4157 .translate
= translate_wsr
,
4158 .par
= (const uint32_t[]){MISC
},
4160 .name
= "wsr.misc1",
4161 .translate
= translate_wsr
,
4162 .par
= (const uint32_t[]){MISC
+ 1},
4164 .name
= "wsr.misc2",
4165 .translate
= translate_wsr
,
4166 .par
= (const uint32_t[]){MISC
+ 2},
4168 .name
= "wsr.misc3",
4169 .translate
= translate_wsr
,
4170 .par
= (const uint32_t[]){MISC
+ 3},
4173 .translate
= translate_wsr
,
4174 .par
= (const uint32_t[]){MMID
},
4177 .translate
= translate_wsr
,
4178 .par
= (const uint32_t[]){PRID
},
4181 .translate
= translate_wsr
,
4182 .par
= (const uint32_t[]){PS
},
4184 .name
= "wsr.ptevaddr",
4185 .translate
= translate_wsr
,
4186 .par
= (const uint32_t[]){PTEVADDR
},
4188 .name
= "wsr.rasid",
4189 .translate
= translate_wsr
,
4190 .par
= (const uint32_t[]){RASID
},
4193 .translate
= translate_wsr
,
4194 .par
= (const uint32_t[]){SAR
},
4196 .name
= "wsr.scompare1",
4197 .translate
= translate_wsr
,
4198 .par
= (const uint32_t[]){SCOMPARE1
},
4200 .name
= "wsr.vecbase",
4201 .translate
= translate_wsr
,
4202 .par
= (const uint32_t[]){VECBASE
},
4204 .name
= "wsr.windowbase",
4205 .translate
= translate_wsr
,
4206 .par
= (const uint32_t[]){WINDOW_BASE
},
4208 .name
= "wsr.windowstart",
4209 .translate
= translate_wsr
,
4210 .par
= (const uint32_t[]){WINDOW_START
},
4212 .name
= "wur.expstate",
4213 .translate
= translate_wur
,
4214 .par
= (const uint32_t[]){EXPSTATE
},
4217 .translate
= translate_wur
,
4218 .par
= (const uint32_t[]){FCR
},
4221 .translate
= translate_wur
,
4222 .par
= (const uint32_t[]){FSR
},
4224 .name
= "wur.threadptr",
4225 .translate
= translate_wur
,
4226 .par
= (const uint32_t[]){THREADPTR
},
4229 .translate
= translate_xor
,
4232 .translate
= translate_boolean
,
4233 .par
= (const uint32_t[]){BOOLEAN_XOR
},
4236 .translate
= translate_xsr
,
4237 .par
= (const uint32_t[]){176},
4240 .translate
= translate_xsr
,
4241 .par
= (const uint32_t[]){208},
4243 .name
= "xsr.acchi",
4244 .translate
= translate_xsr
,
4245 .par
= (const uint32_t[]){ACCHI
},
4247 .name
= "xsr.acclo",
4248 .translate
= translate_xsr
,
4249 .par
= (const uint32_t[]){ACCLO
},
4251 .name
= "xsr.atomctl",
4252 .translate
= translate_xsr
,
4253 .par
= (const uint32_t[]){ATOMCTL
},
4256 .translate
= translate_xsr
,
4257 .par
= (const uint32_t[]){BR
},
4259 .name
= "xsr.cacheattr",
4260 .translate
= translate_xsr
,
4261 .par
= (const uint32_t[]){CACHEATTR
},
4263 .name
= "xsr.ccompare0",
4264 .translate
= translate_xsr
,
4265 .par
= (const uint32_t[]){CCOMPARE
},
4267 .name
= "xsr.ccompare1",
4268 .translate
= translate_xsr
,
4269 .par
= (const uint32_t[]){CCOMPARE
+ 1},
4271 .name
= "xsr.ccompare2",
4272 .translate
= translate_xsr
,
4273 .par
= (const uint32_t[]){CCOMPARE
+ 2},
4275 .name
= "xsr.ccount",
4276 .translate
= translate_xsr
,
4277 .par
= (const uint32_t[]){CCOUNT
},
4279 .name
= "xsr.configid0",
4280 .translate
= translate_xsr
,
4281 .par
= (const uint32_t[]){CONFIGID0
},
4283 .name
= "xsr.configid1",
4284 .translate
= translate_xsr
,
4285 .par
= (const uint32_t[]){CONFIGID1
},
4287 .name
= "xsr.cpenable",
4288 .translate
= translate_xsr
,
4289 .par
= (const uint32_t[]){CPENABLE
},
4291 .name
= "xsr.dbreaka0",
4292 .translate
= translate_xsr
,
4293 .par
= (const uint32_t[]){DBREAKA
},
4295 .name
= "xsr.dbreaka1",
4296 .translate
= translate_xsr
,
4297 .par
= (const uint32_t[]){DBREAKA
+ 1},
4299 .name
= "xsr.dbreakc0",
4300 .translate
= translate_xsr
,
4301 .par
= (const uint32_t[]){DBREAKC
},
4303 .name
= "xsr.dbreakc1",
4304 .translate
= translate_xsr
,
4305 .par
= (const uint32_t[]){DBREAKC
+ 1},
4308 .translate
= translate_xsr
,
4309 .par
= (const uint32_t[]){DDR
},
4311 .name
= "xsr.debugcause",
4312 .translate
= translate_xsr
,
4313 .par
= (const uint32_t[]){DEBUGCAUSE
},
4316 .translate
= translate_xsr
,
4317 .par
= (const uint32_t[]){DEPC
},
4319 .name
= "xsr.dtlbcfg",
4320 .translate
= translate_xsr
,
4321 .par
= (const uint32_t[]){DTLBCFG
},
4324 .translate
= translate_xsr
,
4325 .par
= (const uint32_t[]){EPC1
},
4328 .translate
= translate_xsr
,
4329 .par
= (const uint32_t[]){EPC1
+ 1},
4332 .translate
= translate_xsr
,
4333 .par
= (const uint32_t[]){EPC1
+ 2},
4336 .translate
= translate_xsr
,
4337 .par
= (const uint32_t[]){EPC1
+ 3},
4340 .translate
= translate_xsr
,
4341 .par
= (const uint32_t[]){EPC1
+ 4},
4344 .translate
= translate_xsr
,
4345 .par
= (const uint32_t[]){EPC1
+ 5},
4348 .translate
= translate_xsr
,
4349 .par
= (const uint32_t[]){EPC1
+ 6},
4352 .translate
= translate_xsr
,
4353 .par
= (const uint32_t[]){EPS2
},
4356 .translate
= translate_xsr
,
4357 .par
= (const uint32_t[]){EPS2
+ 1},
4360 .translate
= translate_xsr
,
4361 .par
= (const uint32_t[]){EPS2
+ 2},
4364 .translate
= translate_xsr
,
4365 .par
= (const uint32_t[]){EPS2
+ 3},
4368 .translate
= translate_xsr
,
4369 .par
= (const uint32_t[]){EPS2
+ 4},
4372 .translate
= translate_xsr
,
4373 .par
= (const uint32_t[]){EPS2
+ 5},
4375 .name
= "xsr.exccause",
4376 .translate
= translate_xsr
,
4377 .par
= (const uint32_t[]){EXCCAUSE
},
4379 .name
= "xsr.excsave1",
4380 .translate
= translate_xsr
,
4381 .par
= (const uint32_t[]){EXCSAVE1
},
4383 .name
= "xsr.excsave2",
4384 .translate
= translate_xsr
,
4385 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
4387 .name
= "xsr.excsave3",
4388 .translate
= translate_xsr
,
4389 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
4391 .name
= "xsr.excsave4",
4392 .translate
= translate_xsr
,
4393 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
4395 .name
= "xsr.excsave5",
4396 .translate
= translate_xsr
,
4397 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4399 .name
= "xsr.excsave6",
4400 .translate
= translate_xsr
,
4401 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4403 .name
= "xsr.excsave7",
4404 .translate
= translate_xsr
,
4405 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4407 .name
= "xsr.excvaddr",
4408 .translate
= translate_xsr
,
4409 .par
= (const uint32_t[]){EXCVADDR
},
4411 .name
= "xsr.ibreaka0",
4412 .translate
= translate_xsr
,
4413 .par
= (const uint32_t[]){IBREAKA
},
4415 .name
= "xsr.ibreaka1",
4416 .translate
= translate_xsr
,
4417 .par
= (const uint32_t[]){IBREAKA
+ 1},
4419 .name
= "xsr.ibreakenable",
4420 .translate
= translate_xsr
,
4421 .par
= (const uint32_t[]){IBREAKENABLE
},
4423 .name
= "xsr.icount",
4424 .translate
= translate_xsr
,
4425 .par
= (const uint32_t[]){ICOUNT
},
4427 .name
= "xsr.icountlevel",
4428 .translate
= translate_xsr
,
4429 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4431 .name
= "xsr.intclear",
4432 .translate
= translate_xsr
,
4433 .par
= (const uint32_t[]){INTCLEAR
},
4435 .name
= "xsr.intenable",
4436 .translate
= translate_xsr
,
4437 .par
= (const uint32_t[]){INTENABLE
},
4439 .name
= "xsr.interrupt",
4440 .translate
= translate_xsr
,
4441 .par
= (const uint32_t[]){INTSET
},
4443 .name
= "xsr.intset",
4444 .translate
= translate_xsr
,
4445 .par
= (const uint32_t[]){INTSET
},
4447 .name
= "xsr.itlbcfg",
4448 .translate
= translate_xsr
,
4449 .par
= (const uint32_t[]){ITLBCFG
},
4452 .translate
= translate_xsr
,
4453 .par
= (const uint32_t[]){LBEG
},
4455 .name
= "xsr.lcount",
4456 .translate
= translate_xsr
,
4457 .par
= (const uint32_t[]){LCOUNT
},
4460 .translate
= translate_xsr
,
4461 .par
= (const uint32_t[]){LEND
},
4463 .name
= "xsr.litbase",
4464 .translate
= translate_xsr
,
4465 .par
= (const uint32_t[]){LITBASE
},
4468 .translate
= translate_xsr
,
4469 .par
= (const uint32_t[]){MR
},
4472 .translate
= translate_xsr
,
4473 .par
= (const uint32_t[]){MR
+ 1},
4476 .translate
= translate_xsr
,
4477 .par
= (const uint32_t[]){MR
+ 2},
4480 .translate
= translate_xsr
,
4481 .par
= (const uint32_t[]){MR
+ 3},
4483 .name
= "xsr.memctl",
4484 .translate
= translate_xsr
,
4485 .par
= (const uint32_t[]){MEMCTL
},
4487 .name
= "xsr.misc0",
4488 .translate
= translate_xsr
,
4489 .par
= (const uint32_t[]){MISC
},
4491 .name
= "xsr.misc1",
4492 .translate
= translate_xsr
,
4493 .par
= (const uint32_t[]){MISC
+ 1},
4495 .name
= "xsr.misc2",
4496 .translate
= translate_xsr
,
4497 .par
= (const uint32_t[]){MISC
+ 2},
4499 .name
= "xsr.misc3",
4500 .translate
= translate_xsr
,
4501 .par
= (const uint32_t[]){MISC
+ 3},
4504 .translate
= translate_xsr
,
4505 .par
= (const uint32_t[]){PRID
},
4508 .translate
= translate_xsr
,
4509 .par
= (const uint32_t[]){PS
},
4511 .name
= "xsr.ptevaddr",
4512 .translate
= translate_xsr
,
4513 .par
= (const uint32_t[]){PTEVADDR
},
4515 .name
= "xsr.rasid",
4516 .translate
= translate_xsr
,
4517 .par
= (const uint32_t[]){RASID
},
4520 .translate
= translate_xsr
,
4521 .par
= (const uint32_t[]){SAR
},
4523 .name
= "xsr.scompare1",
4524 .translate
= translate_xsr
,
4525 .par
= (const uint32_t[]){SCOMPARE1
},
4527 .name
= "xsr.vecbase",
4528 .translate
= translate_xsr
,
4529 .par
= (const uint32_t[]){VECBASE
},
4531 .name
= "xsr.windowbase",
4532 .translate
= translate_xsr
,
4533 .par
= (const uint32_t[]){WINDOW_BASE
},
4535 .name
= "xsr.windowstart",
4536 .translate
= translate_xsr
,
4537 .par
= (const uint32_t[]){WINDOW_START
},
4541 const XtensaOpcodeTranslators xtensa_core_opcodes
= {
4542 .num_opcodes
= ARRAY_SIZE(core_ops
),
4547 static void translate_abs_s(DisasContext
*dc
, const uint32_t arg
[],
4548 const uint32_t par
[])
4550 if (gen_check_cpenable(dc
, 0)) {
4551 gen_helper_abs_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4555 static void translate_add_s(DisasContext
*dc
, const uint32_t arg
[],
4556 const uint32_t par
[])
4558 if (gen_check_cpenable(dc
, 0)) {
4559 gen_helper_add_s(cpu_FR
[arg
[0]], cpu_env
,
4560 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4574 static void translate_compare_s(DisasContext
*dc
, const uint32_t arg
[],
4575 const uint32_t par
[])
4577 static void (* const helper
[])(TCGv_env env
, TCGv_i32 bit
,
4578 TCGv_i32 s
, TCGv_i32 t
) = {
4579 [COMPARE_UN
] = gen_helper_un_s
,
4580 [COMPARE_OEQ
] = gen_helper_oeq_s
,
4581 [COMPARE_UEQ
] = gen_helper_ueq_s
,
4582 [COMPARE_OLT
] = gen_helper_olt_s
,
4583 [COMPARE_ULT
] = gen_helper_ult_s
,
4584 [COMPARE_OLE
] = gen_helper_ole_s
,
4585 [COMPARE_ULE
] = gen_helper_ule_s
,
4588 if (gen_check_cpenable(dc
, 0)) {
4589 TCGv_i32 bit
= tcg_const_i32(1 << arg
[0]);
4591 helper
[par
[0]](cpu_env
, bit
, cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4596 static void translate_float_s(DisasContext
*dc
, const uint32_t arg
[],
4597 const uint32_t par
[])
4599 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4600 TCGv_i32 scale
= tcg_const_i32(-arg
[2]);
4603 gen_helper_uitof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4605 gen_helper_itof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4607 tcg_temp_free(scale
);
4611 static void translate_ftoi_s(DisasContext
*dc
, const uint32_t arg
[],
4612 const uint32_t par
[])
4614 if (gen_window_check1(dc
, arg
[0]) && gen_check_cpenable(dc
, 0)) {
4615 TCGv_i32 rounding_mode
= tcg_const_i32(par
[0]);
4616 TCGv_i32 scale
= tcg_const_i32(arg
[2]);
4619 gen_helper_ftoui(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4620 rounding_mode
, scale
);
4622 gen_helper_ftoi(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4623 rounding_mode
, scale
);
4625 tcg_temp_free(rounding_mode
);
4626 tcg_temp_free(scale
);
4630 static void translate_ldsti(DisasContext
*dc
, const uint32_t arg
[],
4631 const uint32_t par
[])
4633 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4634 TCGv_i32 addr
= tcg_temp_new_i32();
4636 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
4637 gen_load_store_alignment(dc
, 2, addr
, false);
4639 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4641 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4644 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4646 tcg_temp_free(addr
);
4650 static void translate_ldstx(DisasContext
*dc
, const uint32_t arg
[],
4651 const uint32_t par
[])
4653 if (gen_window_check2(dc
, arg
[1], arg
[2]) && gen_check_cpenable(dc
, 0)) {
4654 TCGv_i32 addr
= tcg_temp_new_i32();
4656 tcg_gen_add_i32(addr
, cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
4657 gen_load_store_alignment(dc
, 2, addr
, false);
4659 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4661 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4664 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4666 tcg_temp_free(addr
);
4670 static void translate_madd_s(DisasContext
*dc
, const uint32_t arg
[],
4671 const uint32_t par
[])
4673 if (gen_check_cpenable(dc
, 0)) {
4674 gen_helper_madd_s(cpu_FR
[arg
[0]], cpu_env
,
4675 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4679 static void translate_mov_s(DisasContext
*dc
, const uint32_t arg
[],
4680 const uint32_t par
[])
4682 if (gen_check_cpenable(dc
, 0)) {
4683 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4687 static void translate_movcond_s(DisasContext
*dc
, const uint32_t arg
[],
4688 const uint32_t par
[])
4690 if (gen_window_check1(dc
, arg
[2]) && gen_check_cpenable(dc
, 0)) {
4691 TCGv_i32 zero
= tcg_const_i32(0);
4693 tcg_gen_movcond_i32(par
[0], cpu_FR
[arg
[0]],
4694 cpu_R
[arg
[2]], zero
,
4695 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4696 tcg_temp_free(zero
);
4700 static void translate_movp_s(DisasContext
*dc
, const uint32_t arg
[],
4701 const uint32_t par
[])
4703 if (gen_check_cpenable(dc
, 0)) {
4704 TCGv_i32 zero
= tcg_const_i32(0);
4705 TCGv_i32 tmp
= tcg_temp_new_i32();
4707 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
4708 tcg_gen_movcond_i32(par
[0],
4709 cpu_FR
[arg
[0]], tmp
, zero
,
4710 cpu_FR
[arg
[1]], cpu_FR
[arg
[0]]);
4712 tcg_temp_free(zero
);
4716 static void translate_mul_s(DisasContext
*dc
, const uint32_t arg
[],
4717 const uint32_t par
[])
4719 if (gen_check_cpenable(dc
, 0)) {
4720 gen_helper_mul_s(cpu_FR
[arg
[0]], cpu_env
,
4721 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4725 static void translate_msub_s(DisasContext
*dc
, const uint32_t arg
[],
4726 const uint32_t par
[])
4728 if (gen_check_cpenable(dc
, 0)) {
4729 gen_helper_msub_s(cpu_FR
[arg
[0]], cpu_env
,
4730 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4734 static void translate_neg_s(DisasContext
*dc
, const uint32_t arg
[],
4735 const uint32_t par
[])
4737 if (gen_check_cpenable(dc
, 0)) {
4738 gen_helper_neg_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4742 static void translate_rfr_s(DisasContext
*dc
, const uint32_t arg
[],
4743 const uint32_t par
[])
4745 if (gen_window_check1(dc
, arg
[0]) &&
4746 gen_check_cpenable(dc
, 0)) {
4747 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_FR
[arg
[1]]);
4751 static void translate_sub_s(DisasContext
*dc
, const uint32_t arg
[],
4752 const uint32_t par
[])
4754 if (gen_check_cpenable(dc
, 0)) {
4755 gen_helper_sub_s(cpu_FR
[arg
[0]], cpu_env
,
4756 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4760 static void translate_wfr_s(DisasContext
*dc
, const uint32_t arg
[],
4761 const uint32_t par
[])
4763 if (gen_window_check1(dc
, arg
[1]) &&
4764 gen_check_cpenable(dc
, 0)) {
4765 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_R
[arg
[1]]);
4769 static const XtensaOpcodeOps fpu2000_ops
[] = {
4772 .translate
= translate_abs_s
,
4775 .translate
= translate_add_s
,
4778 .translate
= translate_ftoi_s
,
4779 .par
= (const uint32_t[]){float_round_up
, false},
4782 .translate
= translate_float_s
,
4783 .par
= (const uint32_t[]){false},
4786 .translate
= translate_ftoi_s
,
4787 .par
= (const uint32_t[]){float_round_down
, false},
4790 .translate
= translate_ldsti
,
4791 .par
= (const uint32_t[]){false, false},
4794 .translate
= translate_ldsti
,
4795 .par
= (const uint32_t[]){false, true},
4798 .translate
= translate_ldstx
,
4799 .par
= (const uint32_t[]){false, false},
4802 .translate
= translate_ldstx
,
4803 .par
= (const uint32_t[]){false, true},
4806 .translate
= translate_madd_s
,
4809 .translate
= translate_mov_s
,
4812 .translate
= translate_movcond_s
,
4813 .par
= (const uint32_t[]){TCG_COND_EQ
},
4816 .translate
= translate_movp_s
,
4817 .par
= (const uint32_t[]){TCG_COND_EQ
},
4820 .translate
= translate_movcond_s
,
4821 .par
= (const uint32_t[]){TCG_COND_GE
},
4824 .translate
= translate_movcond_s
,
4825 .par
= (const uint32_t[]){TCG_COND_LT
},
4828 .translate
= translate_movcond_s
,
4829 .par
= (const uint32_t[]){TCG_COND_NE
},
4832 .translate
= translate_movp_s
,
4833 .par
= (const uint32_t[]){TCG_COND_NE
},
4836 .translate
= translate_msub_s
,
4839 .translate
= translate_mul_s
,
4842 .translate
= translate_neg_s
,
4845 .translate
= translate_compare_s
,
4846 .par
= (const uint32_t[]){COMPARE_OEQ
},
4849 .translate
= translate_compare_s
,
4850 .par
= (const uint32_t[]){COMPARE_OLE
},
4853 .translate
= translate_compare_s
,
4854 .par
= (const uint32_t[]){COMPARE_OLT
},
4857 .translate
= translate_rfr_s
,
4860 .translate
= translate_ftoi_s
,
4861 .par
= (const uint32_t[]){float_round_nearest_even
, false},
4864 .translate
= translate_ldsti
,
4865 .par
= (const uint32_t[]){true, false},
4868 .translate
= translate_ldsti
,
4869 .par
= (const uint32_t[]){true, true},
4872 .translate
= translate_ldstx
,
4873 .par
= (const uint32_t[]){true, false},
4876 .translate
= translate_ldstx
,
4877 .par
= (const uint32_t[]){true, true},
4880 .translate
= translate_sub_s
,
4883 .translate
= translate_ftoi_s
,
4884 .par
= (const uint32_t[]){float_round_to_zero
, false},
4887 .translate
= translate_compare_s
,
4888 .par
= (const uint32_t[]){COMPARE_UEQ
},
4891 .translate
= translate_float_s
,
4892 .par
= (const uint32_t[]){true},
4895 .translate
= translate_compare_s
,
4896 .par
= (const uint32_t[]){COMPARE_ULE
},
4899 .translate
= translate_compare_s
,
4900 .par
= (const uint32_t[]){COMPARE_ULT
},
4903 .translate
= translate_compare_s
,
4904 .par
= (const uint32_t[]){COMPARE_UN
},
4907 .translate
= translate_ftoi_s
,
4908 .par
= (const uint32_t[]){float_round_to_zero
, true},
4911 .translate
= translate_wfr_s
,
4915 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
= {
4916 .num_opcodes
= ARRAY_SIZE(fpu2000_ops
),
4917 .opcode
= fpu2000_ops
,