2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #define TARGET_LONG_BITS 32
34 /* Xtensa processors have a weak memory model */
35 #define TCG_GUEST_DEFAULT_MO (0)
37 #define CPUArchState struct CPUXtensaState
39 #include "qemu-common.h"
41 #include "exec/cpu-defs.h"
42 #include "xtensa-isa.h"
44 #define NB_MMU_MODES 4
46 #define TARGET_PHYS_ADDR_SPACE_BITS 32
47 #ifdef CONFIG_USER_ONLY
48 #define TARGET_VIRT_ADDR_SPACE_BITS 30
50 #define TARGET_VIRT_ADDR_SPACE_BITS 32
52 #define TARGET_PAGE_BITS 12
55 /* Additional instructions */
56 XTENSA_OPTION_CODE_DENSITY
,
58 XTENSA_OPTION_EXTENDED_L32R
,
59 XTENSA_OPTION_16_BIT_IMUL
,
60 XTENSA_OPTION_32_BIT_IMUL
,
61 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
62 XTENSA_OPTION_32_BIT_IDIV
,
64 XTENSA_OPTION_MISC_OP_NSA
,
65 XTENSA_OPTION_MISC_OP_MINMAX
,
66 XTENSA_OPTION_MISC_OP_SEXT
,
67 XTENSA_OPTION_MISC_OP_CLAMPS
,
68 XTENSA_OPTION_COPROCESSOR
,
69 XTENSA_OPTION_BOOLEAN
,
70 XTENSA_OPTION_FP_COPROCESSOR
,
71 XTENSA_OPTION_MP_SYNCHRO
,
72 XTENSA_OPTION_CONDITIONAL_STORE
,
73 XTENSA_OPTION_ATOMCTL
,
74 XTENSA_OPTION_DEPBITS
,
76 /* Interrupts and exceptions */
77 XTENSA_OPTION_EXCEPTION
,
78 XTENSA_OPTION_RELOCATABLE_VECTOR
,
79 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
80 XTENSA_OPTION_INTERRUPT
,
81 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
82 XTENSA_OPTION_TIMER_INTERRUPT
,
86 XTENSA_OPTION_ICACHE_TEST
,
87 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
89 XTENSA_OPTION_DCACHE_TEST
,
90 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
96 XTENSA_OPTION_HW_ALIGNMENT
,
97 XTENSA_OPTION_MEMORY_ECC_PARITY
,
99 /* Memory protection and translation */
100 XTENSA_OPTION_REGION_PROTECTION
,
101 XTENSA_OPTION_REGION_TRANSLATION
,
103 XTENSA_OPTION_CACHEATTR
,
106 XTENSA_OPTION_WINDOWED_REGISTER
,
107 XTENSA_OPTION_PROCESSOR_INTERFACE
,
108 XTENSA_OPTION_MISC_SR
,
109 XTENSA_OPTION_THREAD_POINTER
,
110 XTENSA_OPTION_PROCESSOR_ID
,
112 XTENSA_OPTION_TRACE_PORT
,
113 XTENSA_OPTION_EXTERN_REGS
,
172 #define PS_INTLEVEL 0xf
173 #define PS_INTLEVEL_SHIFT 0
179 #define PS_RING_SHIFT 6
182 #define PS_OWB_SHIFT 8
185 #define PS_CALLINC 0x30000
186 #define PS_CALLINC_SHIFT 16
187 #define PS_CALLINC_LEN 2
189 #define PS_WOE 0x40000
191 #define DEBUGCAUSE_IC 0x1
192 #define DEBUGCAUSE_IB 0x2
193 #define DEBUGCAUSE_DB 0x4
194 #define DEBUGCAUSE_BI 0x8
195 #define DEBUGCAUSE_BN 0x10
196 #define DEBUGCAUSE_DI 0x20
197 #define DEBUGCAUSE_DBNUM 0xf00
198 #define DEBUGCAUSE_DBNUM_SHIFT 8
200 #define DBREAKC_SB 0x80000000
201 #define DBREAKC_LB 0x40000000
202 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
203 #define DBREAKC_MASK 0x3f
205 #define MEMCTL_INIT 0x00800000
206 #define MEMCTL_IUSEWAYS_SHIFT 18
207 #define MEMCTL_IUSEWAYS_LEN 5
208 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
209 #define MEMCTL_DALLOCWAYS_SHIFT 13
210 #define MEMCTL_DALLOCWAYS_LEN 5
211 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
212 #define MEMCTL_DUSEWAYS_SHIFT 8
213 #define MEMCTL_DUSEWAYS_LEN 5
214 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
215 #define MEMCTL_ISNP 0x4
216 #define MEMCTL_DSNP 0x2
217 #define MEMCTL_IL0EN 0x1
219 #define MAX_INSN_LENGTH 64
220 #define MAX_OPCODE_ARGS 16
222 #define MAX_NINTERRUPT 32
225 #define MAX_NCCOMPARE 3
226 #define MAX_TLB_WAY_SIZE 8
227 #define MAX_NDBREAK 2
228 #define MAX_NMEMORY 4
230 #define REGION_PAGE_MASK 0xe0000000
232 #define PAGE_CACHE_MASK 0x700
233 #define PAGE_CACHE_SHIFT 8
234 #define PAGE_CACHE_INVALID 0x000
235 #define PAGE_CACHE_BYPASS 0x100
236 #define PAGE_CACHE_WT 0x200
237 #define PAGE_CACHE_WB 0x400
238 #define PAGE_CACHE_ISOLATE 0x600
246 /* Dynamic vectors */
247 EXC_WINDOW_OVERFLOW4
,
248 EXC_WINDOW_UNDERFLOW4
,
249 EXC_WINDOW_OVERFLOW8
,
250 EXC_WINDOW_UNDERFLOW8
,
251 EXC_WINDOW_OVERFLOW12
,
252 EXC_WINDOW_UNDERFLOW12
,
262 ILLEGAL_INSTRUCTION_CAUSE
= 0,
264 INSTRUCTION_FETCH_ERROR_CAUSE
,
265 LOAD_STORE_ERROR_CAUSE
,
266 LEVEL1_INTERRUPT_CAUSE
,
268 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
269 PRIVILEGED_CAUSE
= 8,
270 LOAD_STORE_ALIGNMENT_CAUSE
,
272 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
273 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
274 INSTR_PIF_ADDR_ERROR_CAUSE
,
275 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
278 INST_TLB_MULTI_HIT_CAUSE
,
279 INST_FETCH_PRIVILEGE_CAUSE
,
280 INST_FETCH_PROHIBITED_CAUSE
= 20,
281 LOAD_STORE_TLB_MISS_CAUSE
= 24,
282 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
283 LOAD_STORE_PRIVILEGE_CAUSE
,
284 LOAD_PROHIBITED_CAUSE
= 28,
285 STORE_PROHIBITED_CAUSE
,
287 COPROCESSOR0_DISABLED
= 32,
302 struct CPUXtensaState
;
304 typedef struct xtensa_tlb_entry
{
312 typedef struct xtensa_tlb
{
314 const unsigned way_size
[10];
316 unsigned nrefillentries
;
319 typedef struct XtensaGdbReg
{
327 typedef struct XtensaGdbRegmap
{
330 /* PC + a + ar + sr + ur */
331 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
334 typedef struct XtensaCcompareTimer
{
335 struct CPUXtensaState
*env
;
337 } XtensaCcompareTimer
;
339 typedef struct XtensaMemory
{
341 struct XtensaMemoryRegion
{
344 } location
[MAX_NMEMORY
];
347 typedef struct DisasContext DisasContext
;
348 typedef void (*XtensaOpcodeOp
)(DisasContext
*dc
, const uint32_t arg
[],
349 const uint32_t par
[]);
351 typedef struct XtensaOpcodeOps
{
353 XtensaOpcodeOp translate
;
357 typedef struct XtensaOpcodeTranslators
{
358 unsigned num_opcodes
;
359 const XtensaOpcodeOps
*opcode
;
360 } XtensaOpcodeTranslators
;
362 extern const XtensaOpcodeTranslators xtensa_core_opcodes
;
363 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
;
365 struct XtensaConfig
{
368 XtensaGdbRegmap gdb_regmap
;
373 uint32_t exception_vector
[EXC_MAX
];
376 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
377 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
378 uint32_t inttype_mask
[INTTYPE_MAX
];
381 interrupt_type inttype
;
382 } interrupt
[MAX_NINTERRUPT
];
384 uint32_t timerint
[MAX_NCCOMPARE
];
386 unsigned extint
[MAX_NINTERRUPT
];
388 unsigned debug_level
;
392 unsigned icache_ways
;
393 unsigned dcache_ways
;
394 uint32_t memctl_mask
;
396 XtensaMemory instrom
;
397 XtensaMemory instram
;
398 XtensaMemory datarom
;
399 XtensaMemory dataram
;
403 uint32_t configid
[2];
407 XtensaOpcodeOps
**opcode_ops
;
408 const XtensaOpcodeTranslators
**opcode_translators
;
410 uint32_t clock_freq_khz
;
416 typedef struct XtensaConfigList
{
417 const XtensaConfig
*config
;
418 struct XtensaConfigList
*next
;
421 #ifdef HOST_WORDS_BIGENDIAN
433 typedef struct CPUXtensaState
{
434 const XtensaConfig
*config
;
439 uint32_t phys_regs
[MAX_NAREG
];
444 float_status fp_status
;
446 #ifndef CONFIG_USER_ONLY
447 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
448 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
449 unsigned autorefill_idx
;
451 AddressSpace
*address_space_er
;
452 MemoryRegion
*system_er
;
453 int pending_irq_level
; /* level of last raised IRQ */
455 XtensaCcompareTimer ccompare
[MAX_NCCOMPARE
];
457 uint64_t ccount_time
;
458 uint32_t ccount_base
;
463 unsigned static_vectors
;
465 /* Watchpoints for DBREAK registers */
466 struct CPUWatchpoint
*cpu_watchpoint
[MAX_NDBREAK
];
473 * @env: #CPUXtensaState
485 static inline XtensaCPU
*xtensa_env_get_cpu(const CPUXtensaState
*env
)
487 return container_of(env
, XtensaCPU
, env
);
490 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
492 #define ENV_OFFSET offsetof(XtensaCPU, env)
495 int xtensa_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
, int size
,
497 void xtensa_cpu_do_interrupt(CPUState
*cpu
);
498 bool xtensa_cpu_exec_interrupt(CPUState
*cpu
, int interrupt_request
);
499 void xtensa_cpu_do_unassigned_access(CPUState
*cpu
, hwaddr addr
,
500 bool is_write
, bool is_exec
, int opaque
,
502 void xtensa_cpu_dump_state(CPUState
*cpu
, FILE *f
,
503 fprintf_function cpu_fprintf
, int flags
);
504 hwaddr
xtensa_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
505 int xtensa_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
506 int xtensa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
507 void xtensa_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
508 MMUAccessType access_type
,
509 int mmu_idx
, uintptr_t retaddr
);
511 #define cpu_signal_handler cpu_xtensa_signal_handler
512 #define cpu_list xtensa_cpu_list
514 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
515 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
516 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
518 #ifdef TARGET_WORDS_BIGENDIAN
519 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
520 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
522 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
523 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
525 #define XTENSA_DEFAULT_CPU_TYPE \
526 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
527 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
528 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
530 void xtensa_translate_init(void);
531 void xtensa_breakpoint_handler(CPUState
*cs
);
532 void xtensa_finalize_config(XtensaConfig
*config
);
533 void xtensa_register_core(XtensaConfigList
*node
);
534 void xtensa_sim_open_console(Chardev
*chr
);
535 void check_interrupts(CPUXtensaState
*s
);
536 void xtensa_irq_init(CPUXtensaState
*env
);
537 void *xtensa_get_extint(CPUXtensaState
*env
, unsigned extint
);
538 void xtensa_timer_irq(CPUXtensaState
*env
, uint32_t id
, uint32_t active
);
539 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
540 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
541 void xtensa_sync_window_from_phys(CPUXtensaState
*env
);
542 void xtensa_sync_phys_from_window(CPUXtensaState
*env
);
543 void xtensa_rotate_window(CPUXtensaState
*env
, uint32_t delta
);
544 void xtensa_restore_owb(CPUXtensaState
*env
);
545 void debug_exception_env(CPUXtensaState
*new_env
, uint32_t cause
);
547 static inline void xtensa_select_static_vectors(CPUXtensaState
*env
,
551 env
->static_vectors
= n
;
553 void xtensa_runstall(CPUXtensaState
*env
, bool runstall
);
554 XtensaOpcodeOps
*xtensa_find_opcode_ops(const XtensaOpcodeTranslators
*t
,
557 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
558 #define XTENSA_OPTION_ALL (~(uint64_t)0)
560 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
563 return (config
->options
& opt
) != 0;
566 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
568 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
571 static inline int xtensa_get_cintlevel(const CPUXtensaState
*env
)
573 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
574 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
575 level
= env
->config
->excm_level
;
580 static inline int xtensa_get_ring(const CPUXtensaState
*env
)
582 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
583 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
589 static inline int xtensa_get_cring(const CPUXtensaState
*env
)
591 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
592 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
593 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
599 #ifndef CONFIG_USER_ONLY
600 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState
*env
,
601 bool dtlb
, uint32_t way
);
602 void split_tlb_entry_spec_way(const CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
603 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
);
604 int xtensa_tlb_lookup(const CPUXtensaState
*env
, uint32_t addr
, bool dtlb
,
605 uint32_t *pwi
, uint32_t *pei
, uint8_t *pring
);
606 void xtensa_tlb_set_entry_mmu(const CPUXtensaState
*env
,
607 xtensa_tlb_entry
*entry
, bool dtlb
,
608 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
609 void xtensa_tlb_set_entry(CPUXtensaState
*env
, bool dtlb
,
610 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
611 int xtensa_get_physical_addr(CPUXtensaState
*env
, bool update_tlb
,
612 uint32_t vaddr
, int is_write
, int mmu_idx
,
613 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
614 void reset_mmu(CPUXtensaState
*env
);
615 void dump_mmu(FILE *f
, fprintf_function cpu_fprintf
, CPUXtensaState
*env
);
617 static inline MemoryRegion
*xtensa_get_er_region(CPUXtensaState
*env
)
619 return env
->system_er
;
622 static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUXtensaState
*env
,
623 bool dtlb
, unsigned wi
, unsigned ei
)
631 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState
*env
)
633 return env
->sregs
[WINDOW_START
] |
634 (env
->sregs
[WINDOW_START
] << env
->config
->nareg
/ 4);
637 /* MMU modes definitions */
638 #define MMU_MODE0_SUFFIX _ring0
639 #define MMU_MODE1_SUFFIX _ring1
640 #define MMU_MODE2_SUFFIX _ring2
641 #define MMU_MODE3_SUFFIX _ring3
642 #define MMU_USER_IDX 3
644 static inline int cpu_mmu_index(CPUXtensaState
*env
, bool ifetch
)
646 return xtensa_get_cring(env
);
649 #define XTENSA_TBFLAG_RING_MASK 0x3
650 #define XTENSA_TBFLAG_EXCM 0x4
651 #define XTENSA_TBFLAG_LITBASE 0x8
652 #define XTENSA_TBFLAG_DEBUG 0x10
653 #define XTENSA_TBFLAG_ICOUNT 0x20
654 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
655 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
656 #define XTENSA_TBFLAG_EXCEPTION 0x4000
657 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
658 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
659 #define XTENSA_TBFLAG_YIELD 0x20000
661 static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env
, target_ulong
*pc
,
662 target_ulong
*cs_base
, uint32_t *flags
)
664 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
669 *flags
|= xtensa_get_ring(env
);
670 if (env
->sregs
[PS
] & PS_EXCM
) {
671 *flags
|= XTENSA_TBFLAG_EXCM
;
673 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
674 (env
->sregs
[LITBASE
] & 1)) {
675 *flags
|= XTENSA_TBFLAG_LITBASE
;
677 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DEBUG
)) {
678 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
679 *flags
|= XTENSA_TBFLAG_DEBUG
;
681 if (xtensa_get_cintlevel(env
) < env
->sregs
[ICOUNTLEVEL
]) {
682 *flags
|= XTENSA_TBFLAG_ICOUNT
;
685 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_COPROCESSOR
)) {
686 *flags
|= env
->sregs
[CPENABLE
] << XTENSA_TBFLAG_CPENABLE_SHIFT
;
688 if (cs
->singlestep_enabled
&& env
->exception_taken
) {
689 *flags
|= XTENSA_TBFLAG_EXCEPTION
;
691 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
692 (env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) == PS_WOE
) {
693 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
694 (env
->sregs
[WINDOW_BASE
] + 1);
695 uint32_t w
= ctz32(windowstart
| 0x8);
697 *flags
|= w
<< XTENSA_TBFLAG_WINDOW_SHIFT
;
699 *flags
|= 3 << XTENSA_TBFLAG_WINDOW_SHIFT
;
701 if (env
->yield_needed
) {
702 *flags
|= XTENSA_TBFLAG_YIELD
;
706 #include "exec/cpu-all.h"