target/xtensa/cpu.c

   1 /*
   2  * QEMU Xtensa CPU
   3  *
   4  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in the
  14  *       documentation and/or other materials provided with the distribution.
  15  *     * Neither the name of the Open Source and Linux Lab nor the
  16  *       names of its contributors may be used to endorse or promote products
  17  *       derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qapi/error.h"
  33 #include "cpu.h"
  34 #include "qemu-common.h"
  35 #include "migration/vmstate.h"
  36 #include "exec/exec-all.h"
  37
  38
  39 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
  40 {
  41     XtensaCPU *cpu = XTENSA_CPU(cs);
  42
  43     cpu->env.pc = value;
  44 }
  45
  46 static bool xtensa_cpu_has_work(CPUState *cs)
  47 {
  48 #ifndef CONFIG_USER_ONLY
  49     XtensaCPU *cpu = XTENSA_CPU(cs);
  50
  51     return !cpu->env.runstall && cpu->env.pending_irq_level;
  52 #else
  53     return true;
  54 #endif
  55 }
  56
  57 /* CPUClass::reset() */
  58 static void xtensa_cpu_reset(CPUState *s)
  59 {
  60     XtensaCPU *cpu = XTENSA_CPU(s);
  61     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
  62     CPUXtensaState *env = &cpu->env;
  63
  64     xcc->parent_reset(s);
  65
  66     env->exception_taken = 0;
  67     env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
  68     env->sregs[LITBASE] &= ~1;
  69 #ifndef CONFIG_USER_ONLY
  70     env->sregs[PS] = xtensa_option_enabled(env->config,
  71             XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
  72     env->pending_irq_level = 0;
  73 #else
  74     env->sregs[PS] =
  75         (xtensa_option_enabled(env->config,
  76                                XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) |
  77         PS_UM | (3 << PS_RING_SHIFT);
  78 #endif
  79     env->sregs[VECBASE] = env->config->vecbase;
  80     env->sregs[IBREAKENABLE] = 0;
  81     env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
  82     env->sregs[CACHEATTR] = 0x22222222;
  83     env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
  84             XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
  85     env->sregs[CONFIGID0] = env->config->configid[0];
  86     env->sregs[CONFIGID1] = env->config->configid[1];
  87
  88 #ifndef CONFIG_USER_ONLY
  89     reset_mmu(env);
  90     s->halted = env->runstall;
  91 #endif
  92 }
  93
  94 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
  95 {
  96     ObjectClass *oc;
  97     char *typename;
  98
  99     typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
 100     oc = object_class_by_name(typename);
 101     g_free(typename);
 102     if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
 103         object_class_is_abstract(oc)) {
 104         return NULL;
 105     }
 106     return oc;
 107 }
 108
 109 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
 110 {
 111     XtensaCPU *cpu = XTENSA_CPU(cs);
 112
 113     info->private_data = cpu->env.config->isa;
 114     info->print_insn = print_insn_xtensa;
 115 }
 116
 117 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
 118 {
 119     CPUState *cs = CPU(dev);
 120     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
 121     Error *local_err = NULL;
 122
 123 #ifndef CONFIG_USER_ONLY
 124     xtensa_irq_init(&XTENSA_CPU(dev)->env);
 125 #endif
 126
 127     cpu_exec_realizefn(cs, &local_err);
 128     if (local_err != NULL) {
 129         error_propagate(errp, local_err);
 130         return;
 131     }
 132
 133     cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
 134
 135     qemu_init_vcpu(cs);
 136
 137     xcc->parent_realize(dev, errp);
 138 }
 139
 140 static void xtensa_cpu_initfn(Object *obj)
 141 {
 142     CPUState *cs = CPU(obj);
 143     XtensaCPU *cpu = XTENSA_CPU(obj);
 144     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
 145     CPUXtensaState *env = &cpu->env;
 146
 147     cs->env_ptr = env;
 148     env->config = xcc->config;
 149
 150 #ifndef CONFIG_USER_ONLY
 151     env->address_space_er = g_malloc(sizeof(*env->address_space_er));
 152     env->system_er = g_malloc(sizeof(*env->system_er));
 153     memory_region_init_io(env->system_er, NULL, NULL, env, "er",
 154                           UINT64_C(0x100000000));
 155     address_space_init(env->address_space_er, env->system_er, "ER");
 156 #endif
 157 }
 158
 159 static const VMStateDescription vmstate_xtensa_cpu = {
 160     .name = "cpu",
 161     .unmigratable = 1,
 162 };
 163
 164 static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
 165 {
 166     DeviceClass *dc = DEVICE_CLASS(oc);
 167     CPUClass *cc = CPU_CLASS(oc);
 168     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
 169
 170     device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
 171                                     &xcc->parent_realize);
 172
 173     xcc->parent_reset = cc->reset;
 174     cc->reset = xtensa_cpu_reset;
 175
 176     cc->class_by_name = xtensa_cpu_class_by_name;
 177     cc->has_work = xtensa_cpu_has_work;
 178     cc->do_interrupt = xtensa_cpu_do_interrupt;
 179     cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
 180     cc->dump_state = xtensa_cpu_dump_state;
 181     cc->set_pc = xtensa_cpu_set_pc;
 182     cc->gdb_read_register = xtensa_cpu_gdb_read_register;
 183     cc->gdb_write_register = xtensa_cpu_gdb_write_register;
 184     cc->gdb_stop_before_watchpoint = true;
 185 #ifdef CONFIG_USER_ONLY
 186     cc->handle_mmu_fault = xtensa_cpu_handle_mmu_fault;
 187 #else
 188     cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
 189     cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
 190     cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
 191 #endif
 192     cc->debug_excp_handler = xtensa_breakpoint_handler;
 193     cc->disas_set_info = xtensa_cpu_disas_set_info;
 194     cc->tcg_initialize = xtensa_translate_init;
 195     dc->vmsd = &vmstate_xtensa_cpu;
 196 }
 197
 198 static const TypeInfo xtensa_cpu_type_info = {
 199     .name = TYPE_XTENSA_CPU,
 200     .parent = TYPE_CPU,
 201     .instance_size = sizeof(XtensaCPU),
 202     .instance_init = xtensa_cpu_initfn,
 203     .abstract = true,
 204     .class_size = sizeof(XtensaCPUClass),
 205     .class_init = xtensa_cpu_class_init,
 206 };
 207
 208 static void xtensa_cpu_register_types(void)
 209 {
 210     type_register_static(&xtensa_cpu_type_info);
 211 }
 212
 213 type_init(xtensa_cpu_register_types)