target/ppc/misc_helper.c

   1 /*
   2  * Miscellaneous PowerPC emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/exec-all.h"
  22 #include "exec/helper-proto.h"
  23
  24 #include "helper_regs.h"
  25
  26 /*****************************************************************************/
  27 /* SPR accesses */
  28 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  29 {
  30     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  31              env->spr[sprn]);
  32 }
  33
  34 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  35 {
  36     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  37              env->spr[sprn]);
  38 }
  39
  40 #ifdef TARGET_PPC64
  41 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
  42                                uint32_t sprn, uint32_t cause,
  43                                uintptr_t raddr)
  44 {
  45     qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
  46
  47     env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
  48     cause &= FSCR_IC_MASK;
  49     env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
  50
  51     raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
  52 }
  53 #endif
  54
  55 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
  56                                 uint32_t sprn, uint32_t cause)
  57 {
  58 #ifdef TARGET_PPC64
  59     if (env->spr[SPR_FSCR] & (1ULL << bit)) {
  60         /* Facility is enabled, continue */
  61         return;
  62     }
  63     raise_fu_exception(env, bit, sprn, cause, GETPC());
  64 #endif
  65 }
  66
  67 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
  68                                uint32_t sprn, uint32_t cause)
  69 {
  70 #ifdef TARGET_PPC64
  71     if (env->msr & (1ULL << bit)) {
  72         /* Facility is enabled, continue */
  73         return;
  74     }
  75     raise_fu_exception(env, bit, sprn, cause, GETPC());
  76 #endif
  77 }
  78
  79 #if !defined(CONFIG_USER_ONLY)
  80
  81 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  82 {
  83     PowerPCCPU *cpu = ppc_env_get_cpu(env);
  84
  85     if (env->spr[SPR_SDR1] != val) {
  86         ppc_store_sdr1(env, val);
  87         tlb_flush(CPU(cpu));
  88     }
  89 }
  90
  91 #if defined(TARGET_PPC64)
  92 void helper_store_ptcr(CPUPPCState *env, target_ulong val)
  93 {
  94     PowerPCCPU *cpu = ppc_env_get_cpu(env);
  95
  96     if (env->spr[SPR_PTCR] != val) {
  97         ppc_store_ptcr(env, val);
  98         tlb_flush(CPU(cpu));
  99     }
 100 }
 101 #endif /* defined(TARGET_PPC64) */
 102
 103 void helper_store_pidr(CPUPPCState *env, target_ulong val)
 104 {
 105     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 106
 107     env->spr[SPR_BOOKS_PID] = val;
 108     tlb_flush(CPU(cpu));
 109 }
 110
 111 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
 112 {
 113     target_ulong hid0;
 114
 115     hid0 = env->spr[SPR_HID0];
 116     if ((val ^ hid0) & 0x00000008) {
 117         /* Change current endianness */
 118         env->hflags &= ~(1 << MSR_LE);
 119         env->hflags_nmsr &= ~(1 << MSR_LE);
 120         env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
 121         env->hflags |= env->hflags_nmsr;
 122         qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
 123                  val & 0x8 ? 'l' : 'b', env->hflags);
 124     }
 125     env->spr[SPR_HID0] = (uint32_t)val;
 126 }
 127
 128 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
 129 {
 130     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 131
 132     if (likely(env->pb[num] != value)) {
 133         env->pb[num] = value;
 134         /* Should be optimized */
 135         tlb_flush(CPU(cpu));
 136     }
 137 }
 138
 139 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
 140 {
 141     store_40x_dbcr0(env, val);
 142 }
 143
 144 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
 145 {
 146     store_40x_sler(env, val);
 147 }
 148 #endif
 149 /*****************************************************************************/
 150 /* PowerPC 601 specific instructions (POWER bridge) */
 151
 152 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
 153 {
 154     switch (arg) {
 155     case 0x0CUL:
 156         /* Instruction cache line size */
 157         return env->icache_line_size;
 158         break;
 159     case 0x0DUL:
 160         /* Data cache line size */
 161         return env->dcache_line_size;
 162         break;
 163     case 0x0EUL:
 164         /* Minimum cache line size */
 165         return (env->icache_line_size < env->dcache_line_size) ?
 166             env->icache_line_size : env->dcache_line_size;
 167         break;
 168     case 0x0FUL:
 169         /* Maximum cache line size */
 170         return (env->icache_line_size > env->dcache_line_size) ?
 171             env->icache_line_size : env->dcache_line_size;
 172         break;
 173     default:
 174         /* Undefined */
 175         return 0;
 176         break;
 177     }
 178 }
 179
 180 /*****************************************************************************/
 181 /* Special registers manipulation */
 182
 183 /* GDBstub can read and write MSR... */
 184 void ppc_store_msr(CPUPPCState *env, target_ulong value)
 185 {
 186     hreg_store_msr(env, value, 0);
 187 }
 188
 189 /* This code is lifted from MacOnLinux. It is called whenever
 190  * THRM1,2 or 3 is read an fixes up the values in such a way
 191  * that will make MacOS not hang. These registers exist on some
 192  * 75x and 74xx processors.
 193  */
 194 void helper_fixup_thrm(CPUPPCState *env)
 195 {
 196     target_ulong v, t;
 197     int i;
 198
 199 #define THRM1_TIN       (1 << 31)
 200 #define THRM1_TIV       (1 << 30)
 201 #define THRM1_THRES(x)  (((x) & 0x7f) << 23)
 202 #define THRM1_TID       (1 << 2)
 203 #define THRM1_TIE       (1 << 1)
 204 #define THRM1_V         (1 << 0)
 205 #define THRM3_E         (1 << 0)
 206
 207     if (!(env->spr[SPR_THRM3] & THRM3_E)) {
 208         return;
 209     }
 210
 211     /* Note: Thermal interrupts are unimplemented */
 212     for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
 213         v = env->spr[i];
 214         if (!(v & THRM1_V)) {
 215             continue;
 216         }
 217         v |= THRM1_TIV;
 218         v &= ~THRM1_TIN;
 219         t = v & THRM1_THRES(127);
 220         if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
 221             v |= THRM1_TIN;
 222         }
 223         if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
 224             v |= THRM1_TIN;
 225         }
 226         env->spr[i] = v;
 227     }
 228 }