microblaze/s3adsp_1800: Define macros for irq map
[qemu.git] / qom / cpu.c
blob9d624795461071bca72e6ea551fc71d298f846e4
1 /*
2 * QEMU CPU model
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu-common.h"
22 #include "qom/cpu.h"
23 #include "sysemu/kvm.h"
24 #include "qemu/notify.h"
25 #include "qemu/log.h"
26 #include "sysemu/sysemu.h"
28 bool cpu_exists(int64_t id)
30 CPUState *cpu;
32 CPU_FOREACH(cpu) {
33 CPUClass *cc = CPU_GET_CLASS(cpu);
35 if (cc->get_arch_id(cpu) == id) {
36 return true;
39 return false;
42 bool cpu_paging_enabled(const CPUState *cpu)
44 CPUClass *cc = CPU_GET_CLASS(cpu);
46 return cc->get_paging_enabled(cpu);
49 static bool cpu_common_get_paging_enabled(const CPUState *cpu)
51 return false;
54 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
55 Error **errp)
57 CPUClass *cc = CPU_GET_CLASS(cpu);
59 return cc->get_memory_mapping(cpu, list, errp);
62 static void cpu_common_get_memory_mapping(CPUState *cpu,
63 MemoryMappingList *list,
64 Error **errp)
66 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
69 /* CPU hot-plug notifiers */
70 static NotifierList cpu_added_notifiers =
71 NOTIFIER_LIST_INITIALIZER(cpu_add_notifiers);
73 void qemu_register_cpu_added_notifier(Notifier *notifier)
75 notifier_list_add(&cpu_added_notifiers, notifier);
78 void cpu_reset_interrupt(CPUState *cpu, int mask)
80 cpu->interrupt_request &= ~mask;
83 void cpu_exit(CPUState *cpu)
85 cpu->exit_request = 1;
86 cpu->tcg_exit_req = 1;
89 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
90 void *opaque)
92 CPUClass *cc = CPU_GET_CLASS(cpu);
94 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
97 static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
98 CPUState *cpu, void *opaque)
100 return -1;
103 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
104 int cpuid, void *opaque)
106 CPUClass *cc = CPU_GET_CLASS(cpu);
108 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
111 static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
112 CPUState *cpu, int cpuid,
113 void *opaque)
115 return -1;
118 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
119 void *opaque)
121 CPUClass *cc = CPU_GET_CLASS(cpu);
123 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
126 static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
127 CPUState *cpu, void *opaque)
129 return -1;
132 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
133 int cpuid, void *opaque)
135 CPUClass *cc = CPU_GET_CLASS(cpu);
137 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
140 static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
141 CPUState *cpu, int cpuid,
142 void *opaque)
144 return -1;
148 static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
150 return 0;
153 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
155 return 0;
159 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
160 int flags)
162 CPUClass *cc = CPU_GET_CLASS(cpu);
164 if (cc->dump_state) {
165 cpu_synchronize_state(cpu);
166 cc->dump_state(cpu, f, cpu_fprintf, flags);
170 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
171 int flags)
173 CPUClass *cc = CPU_GET_CLASS(cpu);
175 if (cc->dump_statistics) {
176 cc->dump_statistics(cpu, f, cpu_fprintf, flags);
180 void cpu_reset(CPUState *cpu)
182 CPUClass *klass = CPU_GET_CLASS(cpu);
184 if (klass->reset != NULL) {
185 (*klass->reset)(cpu);
189 static void cpu_common_reset(CPUState *cpu)
191 CPUClass *cc = CPU_GET_CLASS(cpu);
193 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
194 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
195 log_cpu_state(cpu, cc->reset_dump_flags);
198 cpu->exit_request = 0;
199 cpu->interrupt_request = 0;
200 cpu->current_tb = NULL;
201 cpu->halted = 0;
204 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
206 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
208 return cc->class_by_name(cpu_model);
211 static ObjectClass *cpu_common_class_by_name(const char *cpu_model)
213 return NULL;
216 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
218 CPUState *cpu = CPU(dev);
220 if (dev->hotplugged) {
221 cpu_synchronize_post_init(cpu);
222 notifier_list_notify(&cpu_added_notifiers, dev);
223 cpu_resume(cpu);
227 static void cpu_common_initfn(Object *obj)
229 CPUState *cpu = CPU(obj);
230 CPUClass *cc = CPU_GET_CLASS(obj);
232 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
235 static int64_t cpu_common_get_arch_id(CPUState *cpu)
237 return cpu->cpu_index;
240 static void cpu_class_init(ObjectClass *klass, void *data)
242 DeviceClass *dc = DEVICE_CLASS(klass);
243 CPUClass *k = CPU_CLASS(klass);
245 k->class_by_name = cpu_common_class_by_name;
246 k->reset = cpu_common_reset;
247 k->get_arch_id = cpu_common_get_arch_id;
248 k->get_paging_enabled = cpu_common_get_paging_enabled;
249 k->get_memory_mapping = cpu_common_get_memory_mapping;
250 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
251 k->write_elf32_note = cpu_common_write_elf32_note;
252 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
253 k->write_elf64_note = cpu_common_write_elf64_note;
254 k->gdb_read_register = cpu_common_gdb_read_register;
255 k->gdb_write_register = cpu_common_gdb_write_register;
256 dc->realize = cpu_common_realizefn;
258 * Reason: CPUs still need special care by board code: wiring up
259 * IRQs, adding reset handlers, halting non-first CPUs, ...
261 dc->cannot_instantiate_with_device_add_yet = true;
264 static const TypeInfo cpu_type_info = {
265 .name = TYPE_CPU,
266 .parent = TYPE_DEVICE,
267 .instance_size = sizeof(CPUState),
268 .instance_init = cpu_common_initfn,
269 .abstract = true,
270 .class_size = sizeof(CPUClass),
271 .class_init = cpu_class_init,
274 static void cpu_register_types(void)
276 type_register_static(&cpu_type_info);
279 type_init(cpu_register_types)