hw/intc/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw/hw.h"
  24 #include "hw/i386/pc.h"
  25 #include "hw/i386/ioapic.h"
  26 #include "hw/i386/ioapic_internal.h"
  27
  28 //#define DEBUG_IOAPIC
  29
  30 #ifdef DEBUG_IOAPIC
  31 #define DPRINTF(fmt, ...)                                       \
  32     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  33 #else
  34 #define DPRINTF(fmt, ...)
  35 #endif
  36
  37 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  38
  39 /* global variable from ioapic_common.c */
  40 extern int ioapic_no;
  41
  42 static void ioapic_service(IOAPICCommonState *s)
  43 {
  44     uint8_t i;
  45     uint8_t trig_mode;
  46     uint8_t vector;
  47     uint8_t delivery_mode;
  48     uint32_t mask;
  49     uint64_t entry;
  50     uint8_t dest;
  51     uint8_t dest_mode;
  52
  53     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  54         mask = 1 << i;
  55         if (s->irr & mask) {
  56             entry = s->ioredtbl[i];
  57             if (!(entry & IOAPIC_LVT_MASKED)) {
  58                 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
  59                 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
  60                 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  61                 delivery_mode =
  62                     (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
  63                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
  64                     s->irr &= ~mask;
  65                 } else {
  66                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
  67                 }
  68                 if (delivery_mode == IOAPIC_DM_EXTINT) {
  69                     vector = pic_read_irq(isa_pic);
  70                 } else {
  71                     vector = entry & IOAPIC_VECTOR_MASK;
  72                 }
  73                 apic_deliver_irq(dest, dest_mode, delivery_mode,
  74                                  vector, trig_mode);
  75             }
  76         }
  77     }
  78 }
  79
  80 static void ioapic_set_irq(void *opaque, int vector, int level)
  81 {
  82     IOAPICCommonState *s = opaque;
  83
  84     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
  85      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
  86      * the cleanest way of doing it but it should work. */
  87
  88     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
  89     if (vector == 0) {
  90         vector = 2;
  91     }
  92     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
  93         uint32_t mask = 1 << vector;
  94         uint64_t entry = s->ioredtbl[vector];
  95
  96         if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) {
  97             level = !level;
  98         }
  99         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 100             IOAPIC_TRIGGER_LEVEL) {
 101             /* level triggered */
 102             if (level) {
 103                 s->irr |= mask;
 104                 ioapic_service(s);
 105             } else {
 106                 s->irr &= ~mask;
 107             }
 108         } else {
 109             /* According to the 82093AA manual, we must ignore edge requests
 110              * if the input pin is masked. */
 111             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 112                 s->irr |= mask;
 113                 ioapic_service(s);
 114             }
 115         }
 116     }
 117 }
 118
 119 void ioapic_eoi_broadcast(int vector)
 120 {
 121     IOAPICCommonState *s;
 122     uint64_t entry;
 123     int i, n;
 124
 125     for (i = 0; i < MAX_IOAPICS; i++) {
 126         s = ioapics[i];
 127         if (!s) {
 128             continue;
 129         }
 130         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 131             entry = s->ioredtbl[n];
 132             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 133                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 134                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 135                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 136                     ioapic_service(s);
 137                 }
 138             }
 139         }
 140     }
 141 }
 142
 143 static uint64_t
 144 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 145 {
 146     IOAPICCommonState *s = opaque;
 147     int index;
 148     uint32_t val = 0;
 149
 150     switch (addr & 0xff) {
 151     case IOAPIC_IOREGSEL:
 152         val = s->ioregsel;
 153         break;
 154     case IOAPIC_IOWIN:
 155         if (size != 4) {
 156             break;
 157         }
 158         switch (s->ioregsel) {
 159         case IOAPIC_REG_ID:
 160             val = s->id << IOAPIC_ID_SHIFT;
 161             break;
 162         case IOAPIC_REG_VER:
 163             val = IOAPIC_VERSION |
 164                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 165             break;
 166         case IOAPIC_REG_ARB:
 167             val = 0;
 168             break;
 169         default:
 170             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 171             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 172                 if (s->ioregsel & 1) {
 173                     val = s->ioredtbl[index] >> 32;
 174                 } else {
 175                     val = s->ioredtbl[index] & 0xffffffff;
 176                 }
 177             }
 178         }
 179         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 180         break;
 181     }
 182     return val;
 183 }
 184
 185 static void
 186 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 187                  unsigned int size)
 188 {
 189     IOAPICCommonState *s = opaque;
 190     int index;
 191
 192     switch (addr & 0xff) {
 193     case IOAPIC_IOREGSEL:
 194         s->ioregsel = val;
 195         break;
 196     case IOAPIC_IOWIN:
 197         if (size != 4) {
 198             break;
 199         }
 200         DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
 201         switch (s->ioregsel) {
 202         case IOAPIC_REG_ID:
 203             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 204             break;
 205         case IOAPIC_REG_VER:
 206         case IOAPIC_REG_ARB:
 207             break;
 208         default:
 209             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 210             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 211                 if (s->ioregsel & 1) {
 212                     s->ioredtbl[index] &= 0xffffffff;
 213                     s->ioredtbl[index] |= (uint64_t)val << 32;
 214                 } else {
 215                     s->ioredtbl[index] &= ~0xffffffffULL;
 216                     s->ioredtbl[index] |= val;
 217                 }
 218                 ioapic_service(s);
 219             }
 220         }
 221         break;
 222     }
 223 }
 224
 225 static const MemoryRegionOps ioapic_io_ops = {
 226     .read = ioapic_mem_read,
 227     .write = ioapic_mem_write,
 228     .endianness = DEVICE_NATIVE_ENDIAN,
 229 };
 230
 231 static void ioapic_realize(DeviceState *dev, Error **errp)
 232 {
 233     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 234
 235     memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
 236                           "ioapic", 0x1000);
 237
 238     qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
 239
 240     ioapics[ioapic_no] = s;
 241 }
 242
 243 static void ioapic_class_init(ObjectClass *klass, void *data)
 244 {
 245     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 246     DeviceClass *dc = DEVICE_CLASS(klass);
 247
 248     k->realize = ioapic_realize;
 249     dc->reset = ioapic_reset_common;
 250 }
 251
 252 static const TypeInfo ioapic_info = {
 253     .name          = "ioapic",
 254     .parent        = TYPE_IOAPIC_COMMON,
 255     .instance_size = sizeof(IOAPICCommonState),
 256     .class_init    = ioapic_class_init,
 257 };
 258
 259 static void ioapic_register_types(void)
 260 {
 261     type_register_static(&ioapic_info);
 262 }
 263
 264 type_init(ioapic_register_types)