hw/timer/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/timer/m48t59.h"
  27 #include "qemu/timer.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/isa/isa.h"
  31 #include "exec/address-spaces.h"
  32
  33 //#define DEBUG_NVRAM
  34
  35 #if defined(DEBUG_NVRAM)
  36 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  37 #else
  38 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
  39 #endif
  40
  41 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
  42 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
  43     OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
  44 #define M48TXX_SYS_BUS_CLASS(klass) \
  45     OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
  46 #define M48TXX_SYS_BUS(obj) \
  47     OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
  48
  49 #define TYPE_M48TXX_ISA "isa-m48txx"
  50 #define M48TXX_ISA_GET_CLASS(obj) \
  51     OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
  52 #define M48TXX_ISA_CLASS(klass) \
  53     OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
  54 #define M48TXX_ISA(obj) \
  55     OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
  56
  57 /*
  58  * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
  59  * alarm and a watchdog timer and related control registers. In the
  60  * PPC platform there is also a nvram lock function.
  61  */
  62
  63 typedef struct M48txxInfo {
  64     const char *isa_name;
  65     const char *sysbus_name;
  66     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  67     uint32_t size;
  68 } M48txxInfo;
  69
  70 /*
  71  * Chipset docs:
  72  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  73  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  74  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  75  */
  76
  77 struct M48t59State {
  78     /* Hardware parameters */
  79     qemu_irq IRQ;
  80     MemoryRegion iomem;
  81     uint32_t size;
  82     /* RTC management */
  83     time_t   time_offset;
  84     time_t   stop_time;
  85     /* Alarm & watchdog */
  86     struct tm alarm;
  87     QEMUTimer *alrm_timer;
  88     QEMUTimer *wd_timer;
  89     /* NVRAM storage */
  90     uint8_t *buffer;
  91     /* Model parameters */
  92     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  93     /* NVRAM storage */
  94     uint16_t addr;
  95     uint8_t  lock;
  96 };
  97
  98 typedef struct M48txxISAState {
  99     ISADevice parent_obj;
 100     M48t59State state;
 101     uint32_t io_base;
 102     MemoryRegion io;
 103 } M48txxISAState;
 104
 105 typedef struct M48txxISADeviceClass {
 106     ISADeviceClass parent_class;
 107     M48txxInfo info;
 108 } M48txxISADeviceClass;
 109
 110 typedef struct M48txxSysBusState {
 111     SysBusDevice parent_obj;
 112     M48t59State state;
 113     MemoryRegion io;
 114 } M48txxSysBusState;
 115
 116 typedef struct M48txxSysBusDeviceClass {
 117     SysBusDeviceClass parent_class;
 118     M48txxInfo info;
 119 } M48txxSysBusDeviceClass;
 120
 121 static M48txxInfo m48txx_info[] = {
 122     {
 123         .sysbus_name = "sysbus-m48t02",
 124         .model = 2,
 125         .size = 0x800,
 126     },{
 127         .sysbus_name = "sysbus-m48t08",
 128         .model = 8,
 129         .size = 0x2000,
 130     },{
 131         .isa_name = "isa-m48t59",
 132         .model = 59,
 133         .size = 0x2000,
 134     }
 135 };
 136
 137
 138 /* Fake timer functions */
 139
 140 /* Alarm management */
 141 static void alarm_cb (void *opaque)
 142 {
 143     struct tm tm;
 144     uint64_t next_time;
 145     M48t59State *NVRAM = opaque;
 146
 147     qemu_set_irq(NVRAM->IRQ, 1);
 148     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
 149         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 150         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 151         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 152         /* Repeat once a month */
 153         qemu_get_timedate(&tm, NVRAM->time_offset);
 154         tm.tm_mon++;
 155         if (tm.tm_mon == 13) {
 156             tm.tm_mon = 1;
 157             tm.tm_year++;
 158         }
 159         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 160     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 161                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 162                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 163                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 164         /* Repeat once a day */
 165         next_time = 24 * 60 * 60;
 166     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 167                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 168                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 169                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 170         /* Repeat once an hour */
 171         next_time = 60 * 60;
 172     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 173                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 174                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 175                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 176         /* Repeat once a minute */
 177         next_time = 60;
 178     } else {
 179         /* Repeat once a second */
 180         next_time = 1;
 181     }
 182     timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
 183                     next_time * 1000);
 184     qemu_set_irq(NVRAM->IRQ, 0);
 185 }
 186
 187 static void set_alarm(M48t59State *NVRAM)
 188 {
 189     int diff;
 190     if (NVRAM->alrm_timer != NULL) {
 191         timer_del(NVRAM->alrm_timer);
 192         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 193         if (diff > 0)
 194             timer_mod(NVRAM->alrm_timer, diff * 1000);
 195     }
 196 }
 197
 198 /* RTC management helpers */
 199 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 200 {
 201     qemu_get_timedate(tm, NVRAM->time_offset);
 202 }
 203
 204 static void set_time(M48t59State *NVRAM, struct tm *tm)
 205 {
 206     NVRAM->time_offset = qemu_timedate_diff(tm);
 207     set_alarm(NVRAM);
 208 }
 209
 210 /* Watchdog management */
 211 static void watchdog_cb (void *opaque)
 212 {
 213     M48t59State *NVRAM = opaque;
 214
 215     NVRAM->buffer[0x1FF0] |= 0x80;
 216     if (NVRAM->buffer[0x1FF7] & 0x80) {
 217         NVRAM->buffer[0x1FF7] = 0x00;
 218         NVRAM->buffer[0x1FFC] &= ~0x40;
 219         /* May it be a hw CPU Reset instead ? */
 220         qemu_system_reset_request();
 221     } else {
 222         qemu_set_irq(NVRAM->IRQ, 1);
 223         qemu_set_irq(NVRAM->IRQ, 0);
 224     }
 225 }
 226
 227 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 228 {
 229     uint64_t interval; /* in 1/16 seconds */
 230
 231     NVRAM->buffer[0x1FF0] &= ~0x80;
 232     if (NVRAM->wd_timer != NULL) {
 233         timer_del(NVRAM->wd_timer);
 234         if (value != 0) {
 235             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 236             timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 237                            ((interval * 1000) >> 4));
 238         }
 239     }
 240 }
 241
 242 /* Direct access to NVRAM */
 243 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
 244 {
 245     M48t59State *NVRAM = opaque;
 246     struct tm tm;
 247     int tmp;
 248
 249     if (addr > 0x1FF8 && addr < 0x2000)
 250         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 251
 252     /* check for NVRAM access */
 253     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 254         (NVRAM->model == 8 && addr < 0x1ff8) ||
 255         (NVRAM->model == 59 && addr < 0x1ff0)) {
 256         goto do_write;
 257     }
 258
 259     /* TOD access */
 260     switch (addr) {
 261     case 0x1FF0:
 262         /* flags register : read-only */
 263         break;
 264     case 0x1FF1:
 265         /* unused */
 266         break;
 267     case 0x1FF2:
 268         /* alarm seconds */
 269         tmp = from_bcd(val & 0x7F);
 270         if (tmp >= 0 && tmp <= 59) {
 271             NVRAM->alarm.tm_sec = tmp;
 272             NVRAM->buffer[0x1FF2] = val;
 273             set_alarm(NVRAM);
 274         }
 275         break;
 276     case 0x1FF3:
 277         /* alarm minutes */
 278         tmp = from_bcd(val & 0x7F);
 279         if (tmp >= 0 && tmp <= 59) {
 280             NVRAM->alarm.tm_min = tmp;
 281             NVRAM->buffer[0x1FF3] = val;
 282             set_alarm(NVRAM);
 283         }
 284         break;
 285     case 0x1FF4:
 286         /* alarm hours */
 287         tmp = from_bcd(val & 0x3F);
 288         if (tmp >= 0 && tmp <= 23) {
 289             NVRAM->alarm.tm_hour = tmp;
 290             NVRAM->buffer[0x1FF4] = val;
 291             set_alarm(NVRAM);
 292         }
 293         break;
 294     case 0x1FF5:
 295         /* alarm date */
 296         tmp = from_bcd(val & 0x3F);
 297         if (tmp != 0) {
 298             NVRAM->alarm.tm_mday = tmp;
 299             NVRAM->buffer[0x1FF5] = val;
 300             set_alarm(NVRAM);
 301         }
 302         break;
 303     case 0x1FF6:
 304         /* interrupts */
 305         NVRAM->buffer[0x1FF6] = val;
 306         break;
 307     case 0x1FF7:
 308         /* watchdog */
 309         NVRAM->buffer[0x1FF7] = val;
 310         set_up_watchdog(NVRAM, val);
 311         break;
 312     case 0x1FF8:
 313     case 0x07F8:
 314         /* control */
 315        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 316         break;
 317     case 0x1FF9:
 318     case 0x07F9:
 319         /* seconds (BCD) */
 320         tmp = from_bcd(val & 0x7F);
 321         if (tmp >= 0 && tmp <= 59) {
 322             get_time(NVRAM, &tm);
 323             tm.tm_sec = tmp;
 324             set_time(NVRAM, &tm);
 325         }
 326         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 327             if (val & 0x80) {
 328                 NVRAM->stop_time = time(NULL);
 329             } else {
 330                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 331                 NVRAM->stop_time = 0;
 332             }
 333         }
 334         NVRAM->buffer[addr] = val & 0x80;
 335         break;
 336     case 0x1FFA:
 337     case 0x07FA:
 338         /* minutes (BCD) */
 339         tmp = from_bcd(val & 0x7F);
 340         if (tmp >= 0 && tmp <= 59) {
 341             get_time(NVRAM, &tm);
 342             tm.tm_min = tmp;
 343             set_time(NVRAM, &tm);
 344         }
 345         break;
 346     case 0x1FFB:
 347     case 0x07FB:
 348         /* hours (BCD) */
 349         tmp = from_bcd(val & 0x3F);
 350         if (tmp >= 0 && tmp <= 23) {
 351             get_time(NVRAM, &tm);
 352             tm.tm_hour = tmp;
 353             set_time(NVRAM, &tm);
 354         }
 355         break;
 356     case 0x1FFC:
 357     case 0x07FC:
 358         /* day of the week / century */
 359         tmp = from_bcd(val & 0x07);
 360         get_time(NVRAM, &tm);
 361         tm.tm_wday = tmp;
 362         set_time(NVRAM, &tm);
 363         NVRAM->buffer[addr] = val & 0x40;
 364         break;
 365     case 0x1FFD:
 366     case 0x07FD:
 367         /* date (BCD) */
 368        tmp = from_bcd(val & 0x3F);
 369         if (tmp != 0) {
 370             get_time(NVRAM, &tm);
 371             tm.tm_mday = tmp;
 372             set_time(NVRAM, &tm);
 373         }
 374         break;
 375     case 0x1FFE:
 376     case 0x07FE:
 377         /* month */
 378         tmp = from_bcd(val & 0x1F);
 379         if (tmp >= 1 && tmp <= 12) {
 380             get_time(NVRAM, &tm);
 381             tm.tm_mon = tmp - 1;
 382             set_time(NVRAM, &tm);
 383         }
 384         break;
 385     case 0x1FFF:
 386     case 0x07FF:
 387         /* year */
 388         tmp = from_bcd(val);
 389         if (tmp >= 0 && tmp <= 99) {
 390             get_time(NVRAM, &tm);
 391             if (NVRAM->model == 8) {
 392                 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
 393             } else {
 394                 tm.tm_year = from_bcd(val);
 395             }
 396             set_time(NVRAM, &tm);
 397         }
 398         break;
 399     default:
 400         /* Check lock registers state */
 401         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 402             break;
 403         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 404             break;
 405     do_write:
 406         if (addr < NVRAM->size) {
 407             NVRAM->buffer[addr] = val & 0xFF;
 408         }
 409         break;
 410     }
 411 }
 412
 413 uint32_t m48t59_read (void *opaque, uint32_t addr)
 414 {
 415     M48t59State *NVRAM = opaque;
 416     struct tm tm;
 417     uint32_t retval = 0xFF;
 418
 419     /* check for NVRAM access */
 420     if ((NVRAM->model == 2 && addr < 0x078f) ||
 421         (NVRAM->model == 8 && addr < 0x1ff8) ||
 422         (NVRAM->model == 59 && addr < 0x1ff0)) {
 423         goto do_read;
 424     }
 425
 426     /* TOD access */
 427     switch (addr) {
 428     case 0x1FF0:
 429         /* flags register */
 430         goto do_read;
 431     case 0x1FF1:
 432         /* unused */
 433         retval = 0;
 434         break;
 435     case 0x1FF2:
 436         /* alarm seconds */
 437         goto do_read;
 438     case 0x1FF3:
 439         /* alarm minutes */
 440         goto do_read;
 441     case 0x1FF4:
 442         /* alarm hours */
 443         goto do_read;
 444     case 0x1FF5:
 445         /* alarm date */
 446         goto do_read;
 447     case 0x1FF6:
 448         /* interrupts */
 449         goto do_read;
 450     case 0x1FF7:
 451         /* A read resets the watchdog */
 452         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 453         goto do_read;
 454     case 0x1FF8:
 455     case 0x07F8:
 456         /* control */
 457         goto do_read;
 458     case 0x1FF9:
 459     case 0x07F9:
 460         /* seconds (BCD) */
 461         get_time(NVRAM, &tm);
 462         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 463         break;
 464     case 0x1FFA:
 465     case 0x07FA:
 466         /* minutes (BCD) */
 467         get_time(NVRAM, &tm);
 468         retval = to_bcd(tm.tm_min);
 469         break;
 470     case 0x1FFB:
 471     case 0x07FB:
 472         /* hours (BCD) */
 473         get_time(NVRAM, &tm);
 474         retval = to_bcd(tm.tm_hour);
 475         break;
 476     case 0x1FFC:
 477     case 0x07FC:
 478         /* day of the week / century */
 479         get_time(NVRAM, &tm);
 480         retval = NVRAM->buffer[addr] | tm.tm_wday;
 481         break;
 482     case 0x1FFD:
 483     case 0x07FD:
 484         /* date */
 485         get_time(NVRAM, &tm);
 486         retval = to_bcd(tm.tm_mday);
 487         break;
 488     case 0x1FFE:
 489     case 0x07FE:
 490         /* month */
 491         get_time(NVRAM, &tm);
 492         retval = to_bcd(tm.tm_mon + 1);
 493         break;
 494     case 0x1FFF:
 495     case 0x07FF:
 496         /* year */
 497         get_time(NVRAM, &tm);
 498         if (NVRAM->model == 8) {
 499             retval = to_bcd(tm.tm_year - 68); // Base year is 1968
 500         } else {
 501             retval = to_bcd(tm.tm_year);
 502         }
 503         break;
 504     default:
 505         /* Check lock registers state */
 506         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 507             break;
 508         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 509             break;
 510     do_read:
 511         if (addr < NVRAM->size) {
 512             retval = NVRAM->buffer[addr];
 513         }
 514         break;
 515     }
 516     if (addr > 0x1FF9 && addr < 0x2000)
 517        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 518
 519     return retval;
 520 }
 521
 522 void m48t59_toggle_lock (void *opaque, int lock)
 523 {
 524     M48t59State *NVRAM = opaque;
 525
 526     NVRAM->lock ^= 1 << lock;
 527 }
 528
 529 /* IO access to NVRAM */
 530 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
 531                          unsigned size)
 532 {
 533     M48t59State *NVRAM = opaque;
 534
 535     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 536     switch (addr) {
 537     case 0:
 538         NVRAM->addr &= ~0x00FF;
 539         NVRAM->addr |= val;
 540         break;
 541     case 1:
 542         NVRAM->addr &= ~0xFF00;
 543         NVRAM->addr |= val << 8;
 544         break;
 545     case 3:
 546         m48t59_write(NVRAM, NVRAM->addr, val);
 547         NVRAM->addr = 0x0000;
 548         break;
 549     default:
 550         break;
 551     }
 552 }
 553
 554 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
 555 {
 556     M48t59State *NVRAM = opaque;
 557     uint32_t retval;
 558
 559     switch (addr) {
 560     case 3:
 561         retval = m48t59_read(NVRAM, NVRAM->addr);
 562         break;
 563     default:
 564         retval = -1;
 565         break;
 566     }
 567     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 568
 569     return retval;
 570 }
 571
 572 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
 573 {
 574     M48t59State *NVRAM = opaque;
 575
 576     m48t59_write(NVRAM, addr, value & 0xff);
 577 }
 578
 579 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
 580 {
 581     M48t59State *NVRAM = opaque;
 582
 583     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 584     m48t59_write(NVRAM, addr + 1, value & 0xff);
 585 }
 586
 587 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
 588 {
 589     M48t59State *NVRAM = opaque;
 590
 591     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 592     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 593     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 594     m48t59_write(NVRAM, addr + 3, value & 0xff);
 595 }
 596
 597 static uint32_t nvram_readb (void *opaque, hwaddr addr)
 598 {
 599     M48t59State *NVRAM = opaque;
 600     uint32_t retval;
 601
 602     retval = m48t59_read(NVRAM, addr);
 603     return retval;
 604 }
 605
 606 static uint32_t nvram_readw (void *opaque, hwaddr addr)
 607 {
 608     M48t59State *NVRAM = opaque;
 609     uint32_t retval;
 610
 611     retval = m48t59_read(NVRAM, addr) << 8;
 612     retval |= m48t59_read(NVRAM, addr + 1);
 613     return retval;
 614 }
 615
 616 static uint32_t nvram_readl (void *opaque, hwaddr addr)
 617 {
 618     M48t59State *NVRAM = opaque;
 619     uint32_t retval;
 620
 621     retval = m48t59_read(NVRAM, addr) << 24;
 622     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 623     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 624     retval |= m48t59_read(NVRAM, addr + 3);
 625     return retval;
 626 }
 627
 628 static const MemoryRegionOps nvram_ops = {
 629     .old_mmio = {
 630         .read = { nvram_readb, nvram_readw, nvram_readl, },
 631         .write = { nvram_writeb, nvram_writew, nvram_writel, },
 632     },
 633     .endianness = DEVICE_NATIVE_ENDIAN,
 634 };
 635
 636 static const VMStateDescription vmstate_m48t59 = {
 637     .name = "m48t59",
 638     .version_id = 1,
 639     .minimum_version_id = 1,
 640     .fields = (VMStateField[]) {
 641         VMSTATE_UINT8(lock, M48t59State),
 642         VMSTATE_UINT16(addr, M48t59State),
 643         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
 644         VMSTATE_END_OF_LIST()
 645     }
 646 };
 647
 648 static void m48t59_reset_common(M48t59State *NVRAM)
 649 {
 650     NVRAM->addr = 0;
 651     NVRAM->lock = 0;
 652     if (NVRAM->alrm_timer != NULL)
 653         timer_del(NVRAM->alrm_timer);
 654
 655     if (NVRAM->wd_timer != NULL)
 656         timer_del(NVRAM->wd_timer);
 657 }
 658
 659 static void m48t59_reset_isa(DeviceState *d)
 660 {
 661     M48txxISAState *isa = M48TXX_ISA(d);
 662     M48t59State *NVRAM = &isa->state;
 663
 664     m48t59_reset_common(NVRAM);
 665 }
 666
 667 static void m48t59_reset_sysbus(DeviceState *d)
 668 {
 669     M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
 670     M48t59State *NVRAM = &sys->state;
 671
 672     m48t59_reset_common(NVRAM);
 673 }
 674
 675 static const MemoryRegionOps m48t59_io_ops = {
 676     .read = NVRAM_readb,
 677     .write = NVRAM_writeb,
 678     .impl = {
 679         .min_access_size = 1,
 680         .max_access_size = 1,
 681     },
 682     .endianness = DEVICE_LITTLE_ENDIAN,
 683 };
 684
 685 /* Initialisation routine */
 686 M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
 687                          uint32_t io_base, uint16_t size, int model)
 688 {
 689     DeviceState *dev;
 690     SysBusDevice *s;
 691     M48txxSysBusState *d;
 692     M48t59State *state;
 693     int i;
 694
 695     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 696         if (!m48txx_info[i].sysbus_name ||
 697             m48txx_info[i].size != size ||
 698             m48txx_info[i].model != model) {
 699             continue;
 700         }
 701
 702         dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
 703         qdev_init_nofail(dev);
 704         s = SYS_BUS_DEVICE(dev);
 705         d = M48TXX_SYS_BUS(s);
 706         state = &d->state;
 707         sysbus_connect_irq(s, 0, IRQ);
 708         if (io_base != 0) {
 709             memory_region_add_subregion(get_system_io(), io_base,
 710                                         sysbus_mmio_get_region(s, 1));
 711         }
 712         if (mem_base != 0) {
 713             sysbus_mmio_map(s, 0, mem_base);
 714         }
 715
 716         return state;
 717     }
 718
 719     assert(false);
 720     return NULL;
 721 }
 722
 723 M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
 724                              int model)
 725 {
 726     DeviceState *dev;
 727     int i;
 728
 729     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 730         if (!m48txx_info[i].isa_name ||
 731             m48txx_info[i].size != size ||
 732             m48txx_info[i].model != model) {
 733             continue;
 734         }
 735
 736         dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
 737         qdev_prop_set_uint32(dev, "iobase", io_base);
 738         qdev_init_nofail(dev);
 739         return &M48TXX_ISA(dev)->state;
 740     }
 741
 742     assert(false);
 743     return NULL;
 744 }
 745
 746 static void m48t59_realize_common(M48t59State *s, Error **errp)
 747 {
 748     s->buffer = g_malloc0(s->size);
 749     if (s->model == 59) {
 750         s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
 751         s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
 752     }
 753     qemu_get_timedate(&s->alarm, 0);
 754
 755     vmstate_register(NULL, -1, &vmstate_m48t59, s);
 756 }
 757
 758 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
 759 {
 760     M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
 761     ISADevice *isadev = ISA_DEVICE(dev);
 762     M48txxISAState *d = M48TXX_ISA(dev);
 763     M48t59State *s = &d->state;
 764
 765     s->model = u->info.model;
 766     s->size = u->info.size;
 767     isa_init_irq(isadev, &s->IRQ, 8);
 768     m48t59_realize_common(s, errp);
 769     memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
 770     if (d->io_base != 0) {
 771         isa_register_ioport(isadev, &d->io, d->io_base);
 772     }
 773 }
 774
 775 static int m48t59_init1(SysBusDevice *dev)
 776 {
 777     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
 778     M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
 779     Object *o = OBJECT(dev);
 780     M48t59State *s = &d->state;
 781     Error *err = NULL;
 782
 783     s->model = u->info.model;
 784     s->size = u->info.size;
 785     sysbus_init_irq(dev, &s->IRQ);
 786
 787     memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
 788                           s->size);
 789     memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
 790     sysbus_init_mmio(dev, &s->iomem);
 791     sysbus_init_mmio(dev, &d->io);
 792     m48t59_realize_common(s, &err);
 793     if (err != NULL) {
 794         error_free(err);
 795         return -1;
 796     }
 797
 798     return 0;
 799 }
 800
 801 static Property m48t59_isa_properties[] = {
 802     DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
 803     DEFINE_PROP_END_OF_LIST(),
 804 };
 805
 806 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
 807 {
 808     DeviceClass *dc = DEVICE_CLASS(klass);
 809
 810     dc->realize = m48t59_isa_realize;
 811     dc->reset = m48t59_reset_isa;
 812     dc->props = m48t59_isa_properties;
 813 }
 814
 815 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
 816 {
 817     M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
 818     M48txxInfo *info = data;
 819
 820     u->info = *info;
 821 }
 822
 823 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
 824 {
 825     DeviceClass *dc = DEVICE_CLASS(klass);
 826     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 827
 828     k->init = m48t59_init1;
 829     dc->reset = m48t59_reset_sysbus;
 830 }
 831
 832 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
 833 {
 834     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
 835     M48txxInfo *info = data;
 836
 837     u->info = *info;
 838 }
 839
 840 static const TypeInfo m48txx_sysbus_type_info = {
 841     .name = TYPE_M48TXX_SYS_BUS,
 842     .parent = TYPE_SYS_BUS_DEVICE,
 843     .instance_size = sizeof(M48txxSysBusState),
 844     .abstract = true,
 845     .class_init = m48txx_sysbus_class_init,
 846 };
 847
 848 static const TypeInfo m48txx_isa_type_info = {
 849     .name = TYPE_M48TXX_ISA,
 850     .parent = TYPE_ISA_DEVICE,
 851     .instance_size = sizeof(M48txxISAState),
 852     .abstract = true,
 853     .class_init = m48txx_isa_class_init,
 854 };
 855
 856 static void m48t59_register_types(void)
 857 {
 858     TypeInfo sysbus_type_info = {
 859         .parent = TYPE_M48TXX_SYS_BUS,
 860         .class_size = sizeof(M48txxSysBusDeviceClass),
 861         .class_init = m48txx_sysbus_concrete_class_init,
 862     };
 863     TypeInfo isa_type_info = {
 864         .parent = TYPE_M48TXX_ISA,
 865         .class_size = sizeof(M48txxISADeviceClass),
 866         .class_init = m48txx_isa_concrete_class_init,
 867     };
 868     int i;
 869
 870     type_register_static(&m48txx_sysbus_type_info);
 871     type_register_static(&m48txx_isa_type_info);
 872
 873     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 874         if (m48txx_info[i].sysbus_name) {
 875             sysbus_type_info.name = m48txx_info[i].sysbus_name;
 876             sysbus_type_info.class_data = &m48txx_info[i];
 877             type_register(&sysbus_type_info);
 878         }
 879
 880         if (m48txx_info[i].isa_name) {
 881             isa_type_info.name = m48txx_info[i].isa_name;
 882             isa_type_info.class_data = &m48txx_info[i];
 883             type_register(&isa_type_info);
 884         }
 885     }
 886 }
 887
 888 type_init(m48t59_register_types)