2 * QEMU MC146818 RTC emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
29 #include "hpet_emul.h"
34 #define RTC_SECONDS_ALARM 1
36 #define RTC_MINUTES_ALARM 3
38 #define RTC_HOURS_ALARM 5
39 #define RTC_ALARM_DONT_CARE 0xC0
41 #define RTC_DAY_OF_WEEK 6
42 #define RTC_DAY_OF_MONTH 7
51 #define REG_A_UIP 0x80
53 #define REG_B_SET 0x80
54 #define REG_B_PIE 0x40
55 #define REG_B_AIE 0x20
56 #define REG_B_UIE 0x10
57 #define REG_B_SQWE 0x08
61 #define REG_C_IRQF 0x80
67 uint8_t cmos_data
[128];
75 QEMUTimer
*periodic_timer
;
76 int64_t next_periodic_time
;
78 int64_t next_second_time
;
79 uint32_t irq_coalesced
;
81 QEMUTimer
*coalesced_timer
;
82 QEMUTimer
*second_timer
;
83 QEMUTimer
*second_timer2
;
86 static void rtc_irq_raise(qemu_irq irq
) {
87 /* When HPET is operating in legacy mode, RTC interrupts are disabled
88 * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
89 * mode is established while interrupt is raised. We want it to
90 * be lowered in any case
92 #if defined TARGET_I386
93 if (!hpet_in_legacy_mode())
98 static void rtc_set_time(RTCState
*s
);
99 static void rtc_copy_date(RTCState
*s
);
102 static void rtc_coalesced_timer_update(RTCState
*s
)
104 if (s
->irq_coalesced
== 0) {
105 qemu_del_timer(s
->coalesced_timer
);
107 /* divide each RTC interval to 2 - 8 smaller intervals */
108 int c
= MIN(s
->irq_coalesced
, 7) + 1;
109 int64_t next_clock
= qemu_get_clock(rtc_clock
) +
110 muldiv64(s
->period
/ c
, get_ticks_per_sec(), 32768);
111 qemu_mod_timer(s
->coalesced_timer
, next_clock
);
115 static void rtc_coalesced_timer(void *opaque
)
117 RTCState
*s
= opaque
;
119 if (s
->irq_coalesced
!= 0) {
120 apic_reset_irq_delivered();
121 s
->cmos_data
[RTC_REG_C
] |= 0xc0;
122 rtc_irq_raise(s
->irq
);
123 if (apic_get_irq_delivered()) {
128 rtc_coalesced_timer_update(s
);
132 static void rtc_timer_update(RTCState
*s
, int64_t current_time
)
134 int period_code
, period
;
135 int64_t cur_clock
, next_irq_clock
;
138 period_code
= s
->cmos_data
[RTC_REG_A
] & 0x0f;
139 #if defined TARGET_I386
140 /* disable periodic timer if hpet is in legacy mode, since interrupts are
143 enable_pie
= !hpet_in_legacy_mode();
148 && (((s
->cmos_data
[RTC_REG_B
] & REG_B_PIE
) && enable_pie
)
149 || ((s
->cmos_data
[RTC_REG_B
] & REG_B_SQWE
) && s
->sqw_irq
))) {
150 if (period_code
<= 2)
152 /* period in 32 Khz cycles */
153 period
= 1 << (period_code
- 1);
155 if(period
!= s
->period
)
156 s
->irq_coalesced
= (s
->irq_coalesced
* s
->period
) / period
;
159 /* compute 32 khz clock */
160 cur_clock
= muldiv64(current_time
, 32768, get_ticks_per_sec());
161 next_irq_clock
= (cur_clock
& ~(period
- 1)) + period
;
162 s
->next_periodic_time
=
163 muldiv64(next_irq_clock
, get_ticks_per_sec(), 32768) + 1;
164 qemu_mod_timer(s
->periodic_timer
, s
->next_periodic_time
);
167 s
->irq_coalesced
= 0;
169 qemu_del_timer(s
->periodic_timer
);
173 static void rtc_periodic_timer(void *opaque
)
175 RTCState
*s
= opaque
;
177 rtc_timer_update(s
, s
->next_periodic_time
);
178 if (s
->cmos_data
[RTC_REG_B
] & REG_B_PIE
) {
179 s
->cmos_data
[RTC_REG_C
] |= 0xc0;
182 apic_reset_irq_delivered();
183 rtc_irq_raise(s
->irq
);
184 if (!apic_get_irq_delivered()) {
186 rtc_coalesced_timer_update(s
);
190 rtc_irq_raise(s
->irq
);
192 if (s
->cmos_data
[RTC_REG_B
] & REG_B_SQWE
) {
193 /* Not square wave at all but we don't want 2048Hz interrupts!
194 Must be seen as a pulse. */
195 qemu_irq_raise(s
->sqw_irq
);
199 static void cmos_ioport_write(void *opaque
, uint32_t addr
, uint32_t data
)
201 RTCState
*s
= opaque
;
203 if ((addr
& 1) == 0) {
204 s
->cmos_index
= data
& 0x7f;
207 printf("cmos: write index=0x%02x val=0x%02x\n",
208 s
->cmos_index
, data
);
210 switch(s
->cmos_index
) {
211 case RTC_SECONDS_ALARM
:
212 case RTC_MINUTES_ALARM
:
213 case RTC_HOURS_ALARM
:
214 /* XXX: not supported */
215 s
->cmos_data
[s
->cmos_index
] = data
;
220 case RTC_DAY_OF_WEEK
:
221 case RTC_DAY_OF_MONTH
:
224 s
->cmos_data
[s
->cmos_index
] = data
;
225 /* if in set mode, do not update the time */
226 if (!(s
->cmos_data
[RTC_REG_B
] & REG_B_SET
)) {
231 /* UIP bit is read only */
232 s
->cmos_data
[RTC_REG_A
] = (data
& ~REG_A_UIP
) |
233 (s
->cmos_data
[RTC_REG_A
] & REG_A_UIP
);
234 rtc_timer_update(s
, qemu_get_clock(rtc_clock
));
237 if (data
& REG_B_SET
) {
238 /* set mode: reset UIP mode */
239 s
->cmos_data
[RTC_REG_A
] &= ~REG_A_UIP
;
242 /* if disabling set mode, update the time */
243 if (s
->cmos_data
[RTC_REG_B
] & REG_B_SET
) {
247 s
->cmos_data
[RTC_REG_B
] = data
;
248 rtc_timer_update(s
, qemu_get_clock(rtc_clock
));
252 /* cannot write to them */
255 s
->cmos_data
[s
->cmos_index
] = data
;
261 static inline int to_bcd(RTCState
*s
, int a
)
263 if (s
->cmos_data
[RTC_REG_B
] & REG_B_DM
) {
266 return ((a
/ 10) << 4) | (a
% 10);
270 static inline int from_bcd(RTCState
*s
, int a
)
272 if (s
->cmos_data
[RTC_REG_B
] & REG_B_DM
) {
275 return ((a
>> 4) * 10) + (a
& 0x0f);
279 static void rtc_set_time(RTCState
*s
)
281 struct tm
*tm
= &s
->current_tm
;
283 tm
->tm_sec
= from_bcd(s
, s
->cmos_data
[RTC_SECONDS
]);
284 tm
->tm_min
= from_bcd(s
, s
->cmos_data
[RTC_MINUTES
]);
285 tm
->tm_hour
= from_bcd(s
, s
->cmos_data
[RTC_HOURS
] & 0x7f);
286 if (!(s
->cmos_data
[RTC_REG_B
] & 0x02) &&
287 (s
->cmos_data
[RTC_HOURS
] & 0x80)) {
290 tm
->tm_wday
= from_bcd(s
, s
->cmos_data
[RTC_DAY_OF_WEEK
]) - 1;
291 tm
->tm_mday
= from_bcd(s
, s
->cmos_data
[RTC_DAY_OF_MONTH
]);
292 tm
->tm_mon
= from_bcd(s
, s
->cmos_data
[RTC_MONTH
]) - 1;
293 tm
->tm_year
= from_bcd(s
, s
->cmos_data
[RTC_YEAR
]) + s
->base_year
- 1900;
296 static void rtc_copy_date(RTCState
*s
)
298 const struct tm
*tm
= &s
->current_tm
;
301 s
->cmos_data
[RTC_SECONDS
] = to_bcd(s
, tm
->tm_sec
);
302 s
->cmos_data
[RTC_MINUTES
] = to_bcd(s
, tm
->tm_min
);
303 if (s
->cmos_data
[RTC_REG_B
] & 0x02) {
305 s
->cmos_data
[RTC_HOURS
] = to_bcd(s
, tm
->tm_hour
);
308 s
->cmos_data
[RTC_HOURS
] = to_bcd(s
, tm
->tm_hour
% 12);
309 if (tm
->tm_hour
>= 12)
310 s
->cmos_data
[RTC_HOURS
] |= 0x80;
312 s
->cmos_data
[RTC_DAY_OF_WEEK
] = to_bcd(s
, tm
->tm_wday
+ 1);
313 s
->cmos_data
[RTC_DAY_OF_MONTH
] = to_bcd(s
, tm
->tm_mday
);
314 s
->cmos_data
[RTC_MONTH
] = to_bcd(s
, tm
->tm_mon
+ 1);
315 year
= (tm
->tm_year
- s
->base_year
) % 100;
318 s
->cmos_data
[RTC_YEAR
] = to_bcd(s
, year
);
321 /* month is between 0 and 11. */
322 static int get_days_in_month(int month
, int year
)
324 static const int days_tab
[12] = {
325 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
328 if ((unsigned )month
>= 12)
332 if ((year
% 4) == 0 && ((year
% 100) != 0 || (year
% 400) == 0))
338 /* update 'tm' to the next second */
339 static void rtc_next_second(struct tm
*tm
)
344 if ((unsigned)tm
->tm_sec
>= 60) {
347 if ((unsigned)tm
->tm_min
>= 60) {
350 if ((unsigned)tm
->tm_hour
>= 24) {
354 if ((unsigned)tm
->tm_wday
>= 7)
356 days_in_month
= get_days_in_month(tm
->tm_mon
,
359 if (tm
->tm_mday
< 1) {
361 } else if (tm
->tm_mday
> days_in_month
) {
364 if (tm
->tm_mon
>= 12) {
375 static void rtc_update_second(void *opaque
)
377 RTCState
*s
= opaque
;
380 /* if the oscillator is not in normal operation, we do not update */
381 if ((s
->cmos_data
[RTC_REG_A
] & 0x70) != 0x20) {
382 s
->next_second_time
+= get_ticks_per_sec();
383 qemu_mod_timer(s
->second_timer
, s
->next_second_time
);
385 rtc_next_second(&s
->current_tm
);
387 if (!(s
->cmos_data
[RTC_REG_B
] & REG_B_SET
)) {
388 /* update in progress bit */
389 s
->cmos_data
[RTC_REG_A
] |= REG_A_UIP
;
391 /* should be 244 us = 8 / 32768 seconds, but currently the
392 timers do not have the necessary resolution. */
393 delay
= (get_ticks_per_sec() * 1) / 100;
396 qemu_mod_timer(s
->second_timer2
,
397 s
->next_second_time
+ delay
);
401 static void rtc_update_second2(void *opaque
)
403 RTCState
*s
= opaque
;
405 if (!(s
->cmos_data
[RTC_REG_B
] & REG_B_SET
)) {
410 if (s
->cmos_data
[RTC_REG_B
] & REG_B_AIE
) {
411 if (((s
->cmos_data
[RTC_SECONDS_ALARM
] & 0xc0) == 0xc0 ||
412 s
->cmos_data
[RTC_SECONDS_ALARM
] == s
->current_tm
.tm_sec
) &&
413 ((s
->cmos_data
[RTC_MINUTES_ALARM
] & 0xc0) == 0xc0 ||
414 s
->cmos_data
[RTC_MINUTES_ALARM
] == s
->current_tm
.tm_mon
) &&
415 ((s
->cmos_data
[RTC_HOURS_ALARM
] & 0xc0) == 0xc0 ||
416 s
->cmos_data
[RTC_HOURS_ALARM
] == s
->current_tm
.tm_hour
)) {
418 s
->cmos_data
[RTC_REG_C
] |= 0xa0;
419 rtc_irq_raise(s
->irq
);
423 /* update ended interrupt */
424 s
->cmos_data
[RTC_REG_C
] |= REG_C_UF
;
425 if (s
->cmos_data
[RTC_REG_B
] & REG_B_UIE
) {
426 s
->cmos_data
[RTC_REG_C
] |= REG_C_IRQF
;
427 rtc_irq_raise(s
->irq
);
430 /* clear update in progress bit */
431 s
->cmos_data
[RTC_REG_A
] &= ~REG_A_UIP
;
433 s
->next_second_time
+= get_ticks_per_sec();
434 qemu_mod_timer(s
->second_timer
, s
->next_second_time
);
437 static uint32_t cmos_ioport_read(void *opaque
, uint32_t addr
)
439 RTCState
*s
= opaque
;
441 if ((addr
& 1) == 0) {
444 switch(s
->cmos_index
) {
448 case RTC_DAY_OF_WEEK
:
449 case RTC_DAY_OF_MONTH
:
452 ret
= s
->cmos_data
[s
->cmos_index
];
455 ret
= s
->cmos_data
[s
->cmos_index
];
458 ret
= s
->cmos_data
[s
->cmos_index
];
459 qemu_irq_lower(s
->irq
);
460 s
->cmos_data
[RTC_REG_C
] = 0x00;
463 ret
= s
->cmos_data
[s
->cmos_index
];
467 printf("cmos: read index=0x%02x val=0x%02x\n",
474 void rtc_set_memory(RTCState
*s
, int addr
, int val
)
476 if (addr
>= 0 && addr
<= 127)
477 s
->cmos_data
[addr
] = val
;
480 void rtc_set_date(RTCState
*s
, const struct tm
*tm
)
486 /* PC cmos mappings */
487 #define REG_IBM_CENTURY_BYTE 0x32
488 #define REG_IBM_PS2_CENTURY_BYTE 0x37
490 static void rtc_set_date_from_host(RTCState
*s
)
495 /* set the CMOS date */
496 qemu_get_timedate(&tm
, 0);
497 rtc_set_date(s
, &tm
);
499 val
= to_bcd(s
, (tm
.tm_year
/ 100) + 19);
500 rtc_set_memory(s
, REG_IBM_CENTURY_BYTE
, val
);
501 rtc_set_memory(s
, REG_IBM_PS2_CENTURY_BYTE
, val
);
504 static void rtc_save(QEMUFile
*f
, void *opaque
)
506 RTCState
*s
= opaque
;
508 qemu_put_buffer(f
, s
->cmos_data
, 128);
509 qemu_put_8s(f
, &s
->cmos_index
);
511 qemu_put_be32(f
, s
->current_tm
.tm_sec
);
512 qemu_put_be32(f
, s
->current_tm
.tm_min
);
513 qemu_put_be32(f
, s
->current_tm
.tm_hour
);
514 qemu_put_be32(f
, s
->current_tm
.tm_wday
);
515 qemu_put_be32(f
, s
->current_tm
.tm_mday
);
516 qemu_put_be32(f
, s
->current_tm
.tm_mon
);
517 qemu_put_be32(f
, s
->current_tm
.tm_year
);
519 qemu_put_timer(f
, s
->periodic_timer
);
520 qemu_put_be64(f
, s
->next_periodic_time
);
522 qemu_put_be64(f
, s
->next_second_time
);
523 qemu_put_timer(f
, s
->second_timer
);
524 qemu_put_timer(f
, s
->second_timer2
);
525 qemu_put_be32(f
, s
->irq_coalesced
);
526 qemu_put_be32(f
, s
->period
);
529 static int rtc_load(QEMUFile
*f
, void *opaque
, int version_id
)
531 RTCState
*s
= opaque
;
533 if (version_id
< 1 || version_id
> 2)
536 qemu_get_buffer(f
, s
->cmos_data
, 128);
537 qemu_get_8s(f
, &s
->cmos_index
);
539 s
->current_tm
.tm_sec
=qemu_get_be32(f
);
540 s
->current_tm
.tm_min
=qemu_get_be32(f
);
541 s
->current_tm
.tm_hour
=qemu_get_be32(f
);
542 s
->current_tm
.tm_wday
=qemu_get_be32(f
);
543 s
->current_tm
.tm_mday
=qemu_get_be32(f
);
544 s
->current_tm
.tm_mon
=qemu_get_be32(f
);
545 s
->current_tm
.tm_year
=qemu_get_be32(f
);
547 qemu_get_timer(f
, s
->periodic_timer
);
548 s
->next_periodic_time
=qemu_get_be64(f
);
550 s
->next_second_time
=qemu_get_be64(f
);
551 qemu_get_timer(f
, s
->second_timer
);
552 qemu_get_timer(f
, s
->second_timer2
);
554 if (version_id
>= 2) {
555 s
->irq_coalesced
= qemu_get_be32(f
);
556 s
->period
= qemu_get_be32(f
);
559 rtc_coalesced_timer_update(s
);
566 static void rtc_reset(void *opaque
)
568 RTCState
*s
= opaque
;
570 s
->cmos_data
[RTC_REG_B
] &= ~(REG_B_PIE
| REG_B_AIE
| REG_B_SQWE
);
571 s
->cmos_data
[RTC_REG_C
] &= ~(REG_C_UF
| REG_C_IRQF
| REG_C_PF
| REG_C_AF
);
573 qemu_irq_lower(s
->irq
);
577 s
->irq_coalesced
= 0;
581 static int rtc_initfn(ISADevice
*dev
)
583 RTCState
*s
= DO_UPCAST(RTCState
, dev
, dev
);
587 isa_init_irq(dev
, &s
->irq
, isairq
);
589 s
->cmos_data
[RTC_REG_A
] = 0x26;
590 s
->cmos_data
[RTC_REG_B
] = 0x02;
591 s
->cmos_data
[RTC_REG_C
] = 0x00;
592 s
->cmos_data
[RTC_REG_D
] = 0x80;
594 rtc_set_date_from_host(s
);
596 s
->periodic_timer
= qemu_new_timer(rtc_clock
, rtc_periodic_timer
, s
);
600 qemu_new_timer(rtc_clock
, rtc_coalesced_timer
, s
);
602 s
->second_timer
= qemu_new_timer(rtc_clock
, rtc_update_second
, s
);
603 s
->second_timer2
= qemu_new_timer(rtc_clock
, rtc_update_second2
, s
);
605 s
->next_second_time
=
606 qemu_get_clock(rtc_clock
) + (get_ticks_per_sec() * 99) / 100;
607 qemu_mod_timer(s
->second_timer2
, s
->next_second_time
);
609 register_ioport_write(base
, 2, 1, cmos_ioport_write
, s
);
610 register_ioport_read(base
, 2, 1, cmos_ioport_read
, s
);
612 register_savevm("mc146818rtc", base
, 2, rtc_save
, rtc_load
, s
);
613 qemu_register_reset(rtc_reset
, s
);
617 RTCState
*rtc_init(int base_year
)
621 dev
= isa_create("mc146818rtc");
622 qdev_prop_set_int32(&dev
->qdev
, "base_year", base_year
);
623 qdev_init_nofail(&dev
->qdev
);
624 return DO_UPCAST(RTCState
, dev
, dev
);
627 static ISADeviceInfo mc146818rtc_info
= {
628 .qdev
.name
= "mc146818rtc",
629 .qdev
.size
= sizeof(RTCState
),
632 .qdev
.props
= (Property
[]) {
633 DEFINE_PROP_INT32("base_year", RTCState
, base_year
, 1980),
634 DEFINE_PROP_END_OF_LIST(),
638 static void mc146818rtc_register(void)
640 isa_qdev_register(&mc146818rtc_info
);
642 device_init(mc146818rtc_register
)
644 /* Memory mapped interface */
645 static uint32_t cmos_mm_readb (void *opaque
, target_phys_addr_t addr
)
647 RTCState
*s
= opaque
;
649 return cmos_ioport_read(s
, addr
>> s
->it_shift
) & 0xFF;
652 static void cmos_mm_writeb (void *opaque
,
653 target_phys_addr_t addr
, uint32_t value
)
655 RTCState
*s
= opaque
;
657 cmos_ioport_write(s
, addr
>> s
->it_shift
, value
& 0xFF);
660 static uint32_t cmos_mm_readw (void *opaque
, target_phys_addr_t addr
)
662 RTCState
*s
= opaque
;
665 val
= cmos_ioport_read(s
, addr
>> s
->it_shift
) & 0xFFFF;
666 #ifdef TARGET_WORDS_BIGENDIAN
672 static void cmos_mm_writew (void *opaque
,
673 target_phys_addr_t addr
, uint32_t value
)
675 RTCState
*s
= opaque
;
676 #ifdef TARGET_WORDS_BIGENDIAN
677 value
= bswap16(value
);
679 cmos_ioport_write(s
, addr
>> s
->it_shift
, value
& 0xFFFF);
682 static uint32_t cmos_mm_readl (void *opaque
, target_phys_addr_t addr
)
684 RTCState
*s
= opaque
;
687 val
= cmos_ioport_read(s
, addr
>> s
->it_shift
);
688 #ifdef TARGET_WORDS_BIGENDIAN
694 static void cmos_mm_writel (void *opaque
,
695 target_phys_addr_t addr
, uint32_t value
)
697 RTCState
*s
= opaque
;
698 #ifdef TARGET_WORDS_BIGENDIAN
699 value
= bswap32(value
);
701 cmos_ioport_write(s
, addr
>> s
->it_shift
, value
);
704 static CPUReadMemoryFunc
* const rtc_mm_read
[] = {
710 static CPUWriteMemoryFunc
* const rtc_mm_write
[] = {
716 RTCState
*rtc_mm_init(target_phys_addr_t base
, int it_shift
, qemu_irq irq
,
722 s
= qemu_mallocz(sizeof(RTCState
));
725 s
->cmos_data
[RTC_REG_A
] = 0x26;
726 s
->cmos_data
[RTC_REG_B
] = 0x02;
727 s
->cmos_data
[RTC_REG_C
] = 0x00;
728 s
->cmos_data
[RTC_REG_D
] = 0x80;
730 s
->base_year
= base_year
;
731 rtc_set_date_from_host(s
);
733 s
->periodic_timer
= qemu_new_timer(rtc_clock
, rtc_periodic_timer
, s
);
734 s
->second_timer
= qemu_new_timer(rtc_clock
, rtc_update_second
, s
);
735 s
->second_timer2
= qemu_new_timer(rtc_clock
, rtc_update_second2
, s
);
737 s
->next_second_time
=
738 qemu_get_clock(rtc_clock
) + (get_ticks_per_sec() * 99) / 100;
739 qemu_mod_timer(s
->second_timer2
, s
->next_second_time
);
741 io_memory
= cpu_register_io_memory(rtc_mm_read
, rtc_mm_write
, s
);
742 cpu_register_physical_memory(base
, 2 << it_shift
, io_memory
);
744 register_savevm("mc146818rtc", base
, 2, rtc_save
, rtc_load
, s
);
745 qemu_register_reset(rtc_reset
, s
);