target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #include "config.h"
  23
  24 #if defined(TARGET_AARCH64)
  25   /* AArch64 definitions */
  26 #  define TARGET_LONG_BITS 64
  27 #  define ELF_MACHINE EM_AARCH64
  28 #else
  29 #  define TARGET_LONG_BITS 32
  30 #  define ELF_MACHINE EM_ARM
  31 #endif
  32
  33 #define CPUArchState struct CPUARMState
  34
  35 #include "qemu-common.h"
  36 #include "exec/cpu-defs.h"
  37
  38 #include "fpu/softfloat.h"
  39
  40 #define TARGET_HAS_ICE 1
  41
  42 #define EXCP_UDEF            1   /* undefined instruction */
  43 #define EXCP_SWI             2   /* software interrupt */
  44 #define EXCP_PREFETCH_ABORT  3
  45 #define EXCP_DATA_ABORT      4
  46 #define EXCP_IRQ             5
  47 #define EXCP_FIQ             6
  48 #define EXCP_BKPT            7
  49 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  50 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  51 #define EXCP_STREX          10
  52
  53 #define ARMV7M_EXCP_RESET   1
  54 #define ARMV7M_EXCP_NMI     2
  55 #define ARMV7M_EXCP_HARD    3
  56 #define ARMV7M_EXCP_MEM     4
  57 #define ARMV7M_EXCP_BUS     5
  58 #define ARMV7M_EXCP_USAGE   6
  59 #define ARMV7M_EXCP_SVC     11
  60 #define ARMV7M_EXCP_DEBUG   12
  61 #define ARMV7M_EXCP_PENDSV  14
  62 #define ARMV7M_EXCP_SYSTICK 15
  63
  64 /* ARM-specific interrupt pending bits.  */
  65 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  66
  67 /* Meanings of the ARMCPU object's two inbound GPIO lines */
  68 #define ARM_CPU_IRQ 0
  69 #define ARM_CPU_FIQ 1
  70
  71 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  72                             int srcreg, int operand, uint32_t value);
  73 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  74                                int dstreg, int operand);
  75
  76 struct arm_boot_info;
  77
  78 #define NB_MMU_MODES 2
  79
  80 /* We currently assume float and double are IEEE single and double
  81    precision respectively.
  82    Doing runtime conversions is tricky because VFP registers may contain
  83    integer values (eg. as the result of a FTOSI instruction).
  84    s<2n> maps to the least significant half of d<n>
  85    s<2n+1> maps to the most significant half of d<n>
  86  */
  87
  88 /* CPU state for each instance of a generic timer (in cp15 c14) */
  89 typedef struct ARMGenericTimer {
  90     uint64_t cval; /* Timer CompareValue register */
  91     uint32_t ctl; /* Timer Control register */
  92 } ARMGenericTimer;
  93
  94 #define GTIMER_PHYS 0
  95 #define GTIMER_VIRT 1
  96 #define NUM_GTIMERS 2
  97
  98 /* Scale factor for generic timers, ie number of ns per tick.
  99  * This gives a 62.5MHz timer.
 100  */
 101 #define GTIMER_SCALE 16
 102
 103 typedef struct CPUARMState {
 104     /* Regs for current mode.  */
 105     uint32_t regs[16];
 106
 107     /* 32/64 switch only happens when taking and returning from
 108      * exceptions so the overlap semantics are taken care of then
 109      * instead of having a complicated union.
 110      */
 111     /* Regs for A64 mode.  */
 112     uint64_t xregs[32];
 113     uint64_t pc;
 114     /* TODO: pstate doesn't correspond to an architectural register;
 115      * it would be better modelled as the underlying fields.
 116      */
 117     uint32_t pstate;
 118     uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
 119
 120     /* Frequently accessed CPSR bits are stored separately for efficiency.
 121        This contains all the other bits.  Use cpsr_{read,write} to access
 122        the whole CPSR.  */
 123     uint32_t uncached_cpsr;
 124     uint32_t spsr;
 125
 126     /* Banked registers.  */
 127     uint32_t banked_spsr[6];
 128     uint32_t banked_r13[6];
 129     uint32_t banked_r14[6];
 130
 131     /* These hold r8-r12.  */
 132     uint32_t usr_regs[5];
 133     uint32_t fiq_regs[5];
 134
 135     /* cpsr flag cache for faster execution */
 136     uint32_t CF; /* 0 or 1 */
 137     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 138     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 139     uint32_t ZF; /* Z set if zero.  */
 140     uint32_t QF; /* 0 or 1 */
 141     uint32_t GE; /* cpsr[19:16] */
 142     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 143     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 144
 145     /* System control coprocessor (cp15) */
 146     struct {
 147         uint32_t c0_cpuid;
 148         uint32_t c0_cssel; /* Cache size selection.  */
 149         uint32_t c1_sys; /* System control register.  */
 150         uint32_t c1_coproc; /* Coprocessor access register.  */
 151         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 152         uint32_t c1_scr; /* secure config register.  */
 153         uint32_t c2_base0; /* MMU translation table base 0.  */
 154         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 155         uint32_t c2_base1; /* MMU translation table base 0.  */
 156         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 157         uint32_t c2_control; /* MMU translation table base control.  */
 158         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 159         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 160         uint32_t c2_data; /* MPU data cachable bits.  */
 161         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 162         uint32_t c3; /* MMU domain access control register
 163                         MPU write buffer control.  */
 164         uint32_t c5_insn; /* Fault status registers.  */
 165         uint32_t c5_data;
 166         uint32_t c6_region[8]; /* MPU base/size registers.  */
 167         uint32_t c6_insn; /* Fault address registers.  */
 168         uint32_t c6_data;
 169         uint32_t c7_par;  /* Translation result. */
 170         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 171         uint32_t c9_insn; /* Cache lockdown registers.  */
 172         uint32_t c9_data;
 173         uint32_t c9_pmcr; /* performance monitor control register */
 174         uint32_t c9_pmcnten; /* perf monitor counter enables */
 175         uint32_t c9_pmovsr; /* perf monitor overflow status */
 176         uint32_t c9_pmxevtyper; /* perf monitor event type */
 177         uint32_t c9_pmuserenr; /* perf monitor user enable */
 178         uint32_t c9_pminten; /* perf monitor interrupt enables */
 179         uint32_t c12_vbar; /* vector base address register */
 180         uint32_t c13_fcse; /* FCSE PID.  */
 181         uint32_t c13_context; /* Context ID.  */
 182         uint32_t c13_tls1; /* User RW Thread register.  */
 183         uint32_t c13_tls2; /* User RO Thread register.  */
 184         uint32_t c13_tls3; /* Privileged Thread register.  */
 185         uint32_t c14_cntfrq; /* Counter Frequency register */
 186         uint32_t c14_cntkctl; /* Timer Control register */
 187         ARMGenericTimer c14_timer[NUM_GTIMERS];
 188         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 189         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 190         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 191         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 192         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 193         uint32_t c15_config_base_address; /* SCU base address.  */
 194         uint32_t c15_diagnostic; /* diagnostic register */
 195         uint32_t c15_power_diagnostic;
 196         uint32_t c15_power_control; /* power control */
 197     } cp15;
 198
 199     /* System registers (AArch64) */
 200     struct {
 201         uint64_t tpidr_el0;
 202     } sr;
 203
 204     struct {
 205         uint32_t other_sp;
 206         uint32_t vecbase;
 207         uint32_t basepri;
 208         uint32_t control;
 209         int current_sp;
 210         int exception;
 211         int pending_exception;
 212     } v7m;
 213
 214     /* Thumb-2 EE state.  */
 215     uint32_t teecr;
 216     uint32_t teehbr;
 217
 218     /* VFP coprocessor state.  */
 219     struct {
 220         /* VFP/Neon register state. Note that the mapping between S, D and Q
 221          * views of the register bank differs between AArch64 and AArch32:
 222          * In AArch32:
 223          *  Qn = regs[2n+1]:regs[2n]
 224          *  Dn = regs[n]
 225          *  Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
 226          * (and regs[32] to regs[63] are inaccessible)
 227          * In AArch64:
 228          *  Qn = regs[2n+1]:regs[2n]
 229          *  Dn = regs[2n]
 230          *  Sn = regs[2n] bits 31..0
 231          * This corresponds to the architecturally defined mapping between
 232          * the two execution states, and means we do not need to explicitly
 233          * map these registers when changing states.
 234          */
 235         float64 regs[64];
 236
 237         uint32_t xregs[16];
 238         /* We store these fpcsr fields separately for convenience.  */
 239         int vec_len;
 240         int vec_stride;
 241
 242         /* scratch space when Tn are not sufficient.  */
 243         uint32_t scratch[8];
 244
 245         /* fp_status is the "normal" fp status. standard_fp_status retains
 246          * values corresponding to the ARM "Standard FPSCR Value", ie
 247          * default-NaN, flush-to-zero, round-to-nearest and is used by
 248          * any operations (generally Neon) which the architecture defines
 249          * as controlled by the standard FPSCR value rather than the FPSCR.
 250          *
 251          * To avoid having to transfer exception bits around, we simply
 252          * say that the FPSCR cumulative exception flags are the logical
 253          * OR of the flags in the two fp statuses. This relies on the
 254          * only thing which needs to read the exception flags being
 255          * an explicit FPSCR read.
 256          */
 257         float_status fp_status;
 258         float_status standard_fp_status;
 259     } vfp;
 260     uint32_t exclusive_addr;
 261     uint32_t exclusive_val;
 262     uint32_t exclusive_high;
 263 #if defined(CONFIG_USER_ONLY)
 264     uint32_t exclusive_test;
 265     uint32_t exclusive_info;
 266 #endif
 267
 268     /* iwMMXt coprocessor state.  */
 269     struct {
 270         uint64_t regs[16];
 271         uint64_t val;
 272
 273         uint32_t cregs[16];
 274     } iwmmxt;
 275
 276     /* For mixed endian mode.  */
 277     bool bswap_code;
 278
 279 #if defined(CONFIG_USER_ONLY)
 280     /* For usermode syscall translation.  */
 281     int eabi;
 282 #endif
 283
 284     CPU_COMMON
 285
 286     /* These fields after the common ones so they are preserved on reset.  */
 287
 288     /* Internal CPU feature flags.  */
 289     uint64_t features;
 290
 291     void *nvic;
 292     const struct arm_boot_info *boot_info;
 293 } CPUARMState;
 294
 295 #include "cpu-qom.h"
 296
 297 ARMCPU *cpu_arm_init(const char *cpu_model);
 298 void arm_translate_init(void);
 299 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 300 int cpu_arm_exec(CPUARMState *s);
 301 int bank_number(int mode);
 302 void switch_mode(CPUARMState *, int);
 303 uint32_t do_arm_semihosting(CPUARMState *env);
 304
 305 static inline bool is_a64(CPUARMState *env)
 306 {
 307     return env->aarch64;
 308 }
 309
 310 #define PSTATE_N_SHIFT 3
 311 #define PSTATE_N  (1 << PSTATE_N_SHIFT)
 312 #define PSTATE_Z_SHIFT 2
 313 #define PSTATE_Z  (1 << PSTATE_Z_SHIFT)
 314 #define PSTATE_C_SHIFT 1
 315 #define PSTATE_C  (1 << PSTATE_C_SHIFT)
 316 #define PSTATE_V_SHIFT 0
 317 #define PSTATE_V  (1 << PSTATE_V_SHIFT)
 318
 319 /* you can call this signal handler from your SIGBUS and SIGSEGV
 320    signal handlers to inform the virtual CPU of exceptions. non zero
 321    is returned if the signal was handled by the virtual CPU.  */
 322 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 323                            void *puc);
 324 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 325                               int mmu_idx);
 326 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 327
 328 #define CPSR_M (0x1fU)
 329 #define CPSR_T (1U << 5)
 330 #define CPSR_F (1U << 6)
 331 #define CPSR_I (1U << 7)
 332 #define CPSR_A (1U << 8)
 333 #define CPSR_E (1U << 9)
 334 #define CPSR_IT_2_7 (0xfc00U)
 335 #define CPSR_GE (0xfU << 16)
 336 #define CPSR_RESERVED (0xfU << 20)
 337 #define CPSR_J (1U << 24)
 338 #define CPSR_IT_0_1 (3U << 25)
 339 #define CPSR_Q (1U << 27)
 340 #define CPSR_V (1U << 28)
 341 #define CPSR_C (1U << 29)
 342 #define CPSR_Z (1U << 30)
 343 #define CPSR_N (1U << 31)
 344 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 345
 346 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 347 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 348 /* Bits writable in user mode.  */
 349 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 350 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 351 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 352
 353 /* Return the current CPSR value.  */
 354 uint32_t cpsr_read(CPUARMState *env);
 355 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 356 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 357
 358 /* Return the current xPSR value.  */
 359 static inline uint32_t xpsr_read(CPUARMState *env)
 360 {
 361     int ZF;
 362     ZF = (env->ZF == 0);
 363     return (env->NF & 0x80000000) | (ZF << 30)
 364         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 365         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 366         | ((env->condexec_bits & 0xfc) << 8)
 367         | env->v7m.exception;
 368 }
 369
 370 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 371 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 372 {
 373     if (mask & CPSR_NZCV) {
 374         env->ZF = (~val) & CPSR_Z;
 375         env->NF = val;
 376         env->CF = (val >> 29) & 1;
 377         env->VF = (val << 3) & 0x80000000;
 378     }
 379     if (mask & CPSR_Q)
 380         env->QF = ((val & CPSR_Q) != 0);
 381     if (mask & (1 << 24))
 382         env->thumb = ((val & (1 << 24)) != 0);
 383     if (mask & CPSR_IT_0_1) {
 384         env->condexec_bits &= ~3;
 385         env->condexec_bits |= (val >> 25) & 3;
 386     }
 387     if (mask & CPSR_IT_2_7) {
 388         env->condexec_bits &= 3;
 389         env->condexec_bits |= (val >> 8) & 0xfc;
 390     }
 391     if (mask & 0x1ff) {
 392         env->v7m.exception = val & 0x1ff;
 393     }
 394 }
 395
 396 /* Return the current FPSCR value.  */
 397 uint32_t vfp_get_fpscr(CPUARMState *env);
 398 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 399
 400 enum arm_cpu_mode {
 401   ARM_CPU_MODE_USR = 0x10,
 402   ARM_CPU_MODE_FIQ = 0x11,
 403   ARM_CPU_MODE_IRQ = 0x12,
 404   ARM_CPU_MODE_SVC = 0x13,
 405   ARM_CPU_MODE_ABT = 0x17,
 406   ARM_CPU_MODE_UND = 0x1b,
 407   ARM_CPU_MODE_SYS = 0x1f
 408 };
 409
 410 /* VFP system registers.  */
 411 #define ARM_VFP_FPSID   0
 412 #define ARM_VFP_FPSCR   1
 413 #define ARM_VFP_MVFR1   6
 414 #define ARM_VFP_MVFR0   7
 415 #define ARM_VFP_FPEXC   8
 416 #define ARM_VFP_FPINST  9
 417 #define ARM_VFP_FPINST2 10
 418
 419 /* iwMMXt coprocessor control registers.  */
 420 #define ARM_IWMMXT_wCID         0
 421 #define ARM_IWMMXT_wCon         1
 422 #define ARM_IWMMXT_wCSSF        2
 423 #define ARM_IWMMXT_wCASF        3
 424 #define ARM_IWMMXT_wCGR0        8
 425 #define ARM_IWMMXT_wCGR1        9
 426 #define ARM_IWMMXT_wCGR2        10
 427 #define ARM_IWMMXT_wCGR3        11
 428
 429 /* If adding a feature bit which corresponds to a Linux ELF
 430  * HWCAP bit, remember to update the feature-bit-to-hwcap
 431  * mapping in linux-user/elfload.c:get_elf_hwcap().
 432  */
 433 enum arm_features {
 434     ARM_FEATURE_VFP,
 435     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 436     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 437     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 438     ARM_FEATURE_V6,
 439     ARM_FEATURE_V6K,
 440     ARM_FEATURE_V7,
 441     ARM_FEATURE_THUMB2,
 442     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 443     ARM_FEATURE_VFP3,
 444     ARM_FEATURE_VFP_FP16,
 445     ARM_FEATURE_NEON,
 446     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 447     ARM_FEATURE_M, /* Microcontroller profile.  */
 448     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 449     ARM_FEATURE_THUMB2EE,
 450     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 451     ARM_FEATURE_V4T,
 452     ARM_FEATURE_V5,
 453     ARM_FEATURE_STRONGARM,
 454     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 455     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 456     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 457     ARM_FEATURE_GENERIC_TIMER,
 458     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 459     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 460     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 461     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 462     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 463     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 464     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 465     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 466     ARM_FEATURE_V8,
 467     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
 468 };
 469
 470 static inline int arm_feature(CPUARMState *env, int feature)
 471 {
 472     return (env->features & (1ULL << feature)) != 0;
 473 }
 474
 475 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 476
 477 /* Interface between CPU and Interrupt controller.  */
 478 void armv7m_nvic_set_pending(void *opaque, int irq);
 479 int armv7m_nvic_acknowledge_irq(void *opaque);
 480 void armv7m_nvic_complete_irq(void *opaque, int irq);
 481
 482 /* Interface for defining coprocessor registers.
 483  * Registers are defined in tables of arm_cp_reginfo structs
 484  * which are passed to define_arm_cp_regs().
 485  */
 486
 487 /* When looking up a coprocessor register we look for it
 488  * via an integer which encodes all of:
 489  *  coprocessor number
 490  *  Crn, Crm, opc1, opc2 fields
 491  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 492  *    or via MRRC/MCRR?)
 493  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 494  * (In this case crn and opc2 should be zero.)
 495  */
 496 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 497     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 498      ((crm) << 7) | ((opc1) << 3) | (opc2))
 499
 500 /* Note that these must line up with the KVM/ARM register
 501  * ID field definitions (kvm.c will check this, but we
 502  * can't just use the KVM defines here as the kvm headers
 503  * are unavailable to non-KVM-specific files)
 504  */
 505 #define CP_REG_SIZE_SHIFT 52
 506 #define CP_REG_SIZE_MASK       0x00f0000000000000ULL
 507 #define CP_REG_SIZE_U32        0x0020000000000000ULL
 508 #define CP_REG_SIZE_U64        0x0030000000000000ULL
 509 #define CP_REG_ARM             0x4000000000000000ULL
 510
 511 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
 512  * version used as a key for the coprocessor register hashtable
 513  */
 514 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 515 {
 516     uint32_t cpregid = kvmid;
 517     if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 518         cpregid |= (1 << 15);
 519     }
 520     return cpregid;
 521 }
 522
 523 /* Convert a truncated 32 bit hashtable key into the full
 524  * 64 bit KVM register ID.
 525  */
 526 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 527 {
 528     uint64_t kvmid = cpregid & ~(1 << 15);
 529     if (cpregid & (1 << 15)) {
 530         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 531     } else {
 532         kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 533     }
 534     return kvmid;
 535 }
 536
 537 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 538  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 539  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 540  * TCG can assume the value to be constant (ie load at translate time)
 541  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 542  * indicates that the TB should not be ended after a write to this register
 543  * (the default is that the TB ends after cp writes). OVERRIDE permits
 544  * a register definition to override a previous definition for the
 545  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 546  * old must have the OVERRIDE bit set.
 547  * NO_MIGRATE indicates that this register should be ignored for migration;
 548  * (eg because any state is accessed via some other coprocessor register).
 549  * IO indicates that this register does I/O and therefore its accesses
 550  * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
 551  * registers which implement clocks or timers require this.
 552  */
 553 #define ARM_CP_SPECIAL 1
 554 #define ARM_CP_CONST 2
 555 #define ARM_CP_64BIT 4
 556 #define ARM_CP_SUPPRESS_TB_END 8
 557 #define ARM_CP_OVERRIDE 16
 558 #define ARM_CP_NO_MIGRATE 32
 559 #define ARM_CP_IO 64
 560 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 561 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 562 #define ARM_LAST_SPECIAL ARM_CP_WFI
 563 /* Used only as a terminator for ARMCPRegInfo lists */
 564 #define ARM_CP_SENTINEL 0xffff
 565 /* Mask of only the flag bits in a type field */
 566 #define ARM_CP_FLAG_MASK 0x7f
 567
 568 /* Return true if cptype is a valid type field. This is used to try to
 569  * catch errors where the sentinel has been accidentally left off the end
 570  * of a list of registers.
 571  */
 572 static inline bool cptype_valid(int cptype)
 573 {
 574     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 575         || ((cptype & ARM_CP_SPECIAL) &&
 576             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 577 }
 578
 579 /* Access rights:
 580  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 581  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 582  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 583  * (ie any of the privileged modes in Secure state, or Monitor mode).
 584  * If a register is accessible in one privilege level it's always accessible
 585  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 586  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 587  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 588  * terminology a little and call this PL3.
 589  *
 590  * If access permissions for a register are more complex than can be
 591  * described with these bits, then use a laxer set of restrictions, and
 592  * do the more restrictive/complex check inside a helper function.
 593  */
 594 #define PL3_R 0x80
 595 #define PL3_W 0x40
 596 #define PL2_R (0x20 | PL3_R)
 597 #define PL2_W (0x10 | PL3_W)
 598 #define PL1_R (0x08 | PL2_R)
 599 #define PL1_W (0x04 | PL2_W)
 600 #define PL0_R (0x02 | PL1_R)
 601 #define PL0_W (0x01 | PL1_W)
 602
 603 #define PL3_RW (PL3_R | PL3_W)
 604 #define PL2_RW (PL2_R | PL2_W)
 605 #define PL1_RW (PL1_R | PL1_W)
 606 #define PL0_RW (PL0_R | PL0_W)
 607
 608 static inline int arm_current_pl(CPUARMState *env)
 609 {
 610     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 611         return 0;
 612     }
 613     /* We don't currently implement the Virtualization or TrustZone
 614      * extensions, so PL2 and PL3 don't exist for us.
 615      */
 616     return 1;
 617 }
 618
 619 typedef struct ARMCPRegInfo ARMCPRegInfo;
 620
 621 /* Access functions for coprocessor registers. These should return
 622  * 0 on success, or one of the EXCP_* constants if access should cause
 623  * an exception (in which case *value is not written).
 624  */
 625 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 626                      uint64_t *value);
 627 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 628                       uint64_t value);
 629 /* Hook function for register reset */
 630 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 631
 632 #define CP_ANY 0xff
 633
 634 /* Definition of an ARM coprocessor register */
 635 struct ARMCPRegInfo {
 636     /* Name of register (useful mainly for debugging, need not be unique) */
 637     const char *name;
 638     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 639      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 640      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 641      * will be decoded to this register. The register read and write
 642      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 643      * used by the program, so it is possible to register a wildcard and
 644      * then behave differently on read/write if necessary.
 645      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 646      * must both be zero.
 647      */
 648     uint8_t cp;
 649     uint8_t crn;
 650     uint8_t crm;
 651     uint8_t opc1;
 652     uint8_t opc2;
 653     /* Register type: ARM_CP_* bits/values */
 654     int type;
 655     /* Access rights: PL*_[RW] */
 656     int access;
 657     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 658      * this register was defined: can be used to hand data through to the
 659      * register read/write functions, since they are passed the ARMCPRegInfo*.
 660      */
 661     void *opaque;
 662     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 663      * fieldoffset is non-zero, the reset value of the register.
 664      */
 665     uint64_t resetvalue;
 666     /* Offset of the field in CPUARMState for this register. This is not
 667      * needed if either:
 668      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 669      *  2. both readfn and writefn are specified
 670      */
 671     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 672     /* Function for handling reads of this register. If NULL, then reads
 673      * will be done by loading from the offset into CPUARMState specified
 674      * by fieldoffset.
 675      */
 676     CPReadFn *readfn;
 677     /* Function for handling writes of this register. If NULL, then writes
 678      * will be done by writing to the offset into CPUARMState specified
 679      * by fieldoffset.
 680      */
 681     CPWriteFn *writefn;
 682     /* Function for doing a "raw" read; used when we need to copy
 683      * coprocessor state to the kernel for KVM or out for
 684      * migration. This only needs to be provided if there is also a
 685      * readfn and it makes an access permission check.
 686      */
 687     CPReadFn *raw_readfn;
 688     /* Function for doing a "raw" write; used when we need to copy KVM
 689      * kernel coprocessor state into userspace, or for inbound
 690      * migration. This only needs to be provided if there is also a
 691      * writefn and it makes an access permission check or masks out
 692      * "unwritable" bits or has write-one-to-clear or similar behaviour.
 693      */
 694     CPWriteFn *raw_writefn;
 695     /* Function for resetting the register. If NULL, then reset will be done
 696      * by writing resetvalue to the field specified in fieldoffset. If
 697      * fieldoffset is 0 then no reset will be done.
 698      */
 699     CPResetFn *resetfn;
 700 };
 701
 702 /* Macros which are lvalues for the field in CPUARMState for the
 703  * ARMCPRegInfo *ri.
 704  */
 705 #define CPREG_FIELD32(env, ri) \
 706     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 707 #define CPREG_FIELD64(env, ri) \
 708     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 709
 710 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 711
 712 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 713                                     const ARMCPRegInfo *regs, void *opaque);
 714 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 715                                        const ARMCPRegInfo *regs, void *opaque);
 716 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 717 {
 718     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 719 }
 720 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 721 {
 722     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 723 }
 724 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 725
 726 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 727 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 728                         uint64_t value);
 729 /* CPReadFn that can be used for read-as-zero behaviour */
 730 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 731
 732 static inline bool cp_access_ok(CPUARMState *env,
 733                                 const ARMCPRegInfo *ri, int isread)
 734 {
 735     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 736 }
 737
 738 /**
 739  * write_list_to_cpustate
 740  * @cpu: ARMCPU
 741  *
 742  * For each register listed in the ARMCPU cpreg_indexes list, write
 743  * its value from the cpreg_values list into the ARMCPUState structure.
 744  * This updates TCG's working data structures from KVM data or
 745  * from incoming migration state.
 746  *
 747  * Returns: true if all register values were updated correctly,
 748  * false if some register was unknown or could not be written.
 749  * Note that we do not stop early on failure -- we will attempt
 750  * writing all registers in the list.
 751  */
 752 bool write_list_to_cpustate(ARMCPU *cpu);
 753
 754 /**
 755  * write_cpustate_to_list:
 756  * @cpu: ARMCPU
 757  *
 758  * For each register listed in the ARMCPU cpreg_indexes list, write
 759  * its value from the ARMCPUState structure into the cpreg_values list.
 760  * This is used to copy info from TCG's working data structures into
 761  * KVM or for outbound migration.
 762  *
 763  * Returns: true if all register values were read correctly,
 764  * false if some register was unknown or could not be read.
 765  * Note that we do not stop early on failure -- we will attempt
 766  * reading all registers in the list.
 767  */
 768 bool write_cpustate_to_list(ARMCPU *cpu);
 769
 770 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 771    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 772    conventional cores (ie. Application or Realtime profile).  */
 773
 774 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 775
 776 #define ARM_CPUID_TI915T      0x54029152
 777 #define ARM_CPUID_TI925T      0x54029252
 778
 779 #if defined(CONFIG_USER_ONLY)
 780 #define TARGET_PAGE_BITS 12
 781 #else
 782 /* The ARM MMU allows 1k pages.  */
 783 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 784    architecture revisions.  Maybe a configure option to disable them.  */
 785 #define TARGET_PAGE_BITS 10
 786 #endif
 787
 788 #if defined(TARGET_AARCH64)
 789 #  define TARGET_PHYS_ADDR_SPACE_BITS 48
 790 #  define TARGET_VIRT_ADDR_SPACE_BITS 64
 791 #else
 792 #  define TARGET_PHYS_ADDR_SPACE_BITS 40
 793 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 794 #endif
 795
 796 static inline CPUARMState *cpu_init(const char *cpu_model)
 797 {
 798     ARMCPU *cpu = cpu_arm_init(cpu_model);
 799     if (cpu) {
 800         return &cpu->env;
 801     }
 802     return NULL;
 803 }
 804
 805 #define cpu_exec cpu_arm_exec
 806 #define cpu_gen_code cpu_arm_gen_code
 807 #define cpu_signal_handler cpu_arm_signal_handler
 808 #define cpu_list arm_cpu_list
 809
 810 /* MMU modes definitions */
 811 #define MMU_MODE0_SUFFIX _kernel
 812 #define MMU_MODE1_SUFFIX _user
 813 #define MMU_USER_IDX 1
 814 static inline int cpu_mmu_index (CPUARMState *env)
 815 {
 816     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 817 }
 818
 819 #include "exec/cpu-all.h"
 820
 821 /* Bit usage in the TB flags field: bit 31 indicates whether we are
 822  * in 32 or 64 bit mode. The meaning of the other bits depends on that.
 823  */
 824 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
 825 #define ARM_TBFLAG_AARCH64_STATE_MASK  (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
 826
 827 /* Bit usage when in AArch32 state: */
 828 #define ARM_TBFLAG_THUMB_SHIFT      0
 829 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 830 #define ARM_TBFLAG_VECLEN_SHIFT     1
 831 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 832 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 833 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 834 #define ARM_TBFLAG_PRIV_SHIFT       6
 835 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 836 #define ARM_TBFLAG_VFPEN_SHIFT      7
 837 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 838 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 839 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 840 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 841 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 842
 843 /* Bit usage when in AArch64 state: currently no bits defined */
 844
 845 /* some convenience accessor macros */
 846 #define ARM_TBFLAG_AARCH64_STATE(F) \
 847     (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
 848 #define ARM_TBFLAG_THUMB(F) \
 849     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 850 #define ARM_TBFLAG_VECLEN(F) \
 851     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 852 #define ARM_TBFLAG_VECSTRIDE(F) \
 853     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 854 #define ARM_TBFLAG_PRIV(F) \
 855     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 856 #define ARM_TBFLAG_VFPEN(F) \
 857     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 858 #define ARM_TBFLAG_CONDEXEC(F) \
 859     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 860 #define ARM_TBFLAG_BSWAP_CODE(F) \
 861     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 862
 863 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 864                                         target_ulong *cs_base, int *flags)
 865 {
 866     if (is_a64(env)) {
 867         *pc = env->pc;
 868         *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
 869     } else {
 870         int privmode;
 871         *pc = env->regs[15];
 872         *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 873             | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 874             | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 875             | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 876             | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 877         if (arm_feature(env, ARM_FEATURE_M)) {
 878             privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 879         } else {
 880             privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 881         }
 882         if (privmode) {
 883             *flags |= ARM_TBFLAG_PRIV_MASK;
 884         }
 885         if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 886             *flags |= ARM_TBFLAG_VFPEN_MASK;
 887         }
 888     }
 889
 890     *cs_base = 0;
 891 }
 892
 893 static inline bool cpu_has_work(CPUState *cpu)
 894 {
 895     return cpu->interrupt_request &
 896         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 897 }
 898
 899 #include "exec/exec-all.h"
 900
 901 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 902 {
 903     if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
 904         env->pc = tb->pc;
 905     } else {
 906         env->regs[15] = tb->pc;
 907     }
 908 }
 909
 910 /* Load an instruction and return it in the standard little-endian order */
 911 static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
 912                                     bool do_swap)
 913 {
 914     uint32_t insn = cpu_ldl_code(env, addr);
 915     if (do_swap) {
 916         return bswap32(insn);
 917     }
 918     return insn;
 919 }
 920
 921 /* Ditto, for a halfword (Thumb) instruction */
 922 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
 923                                      bool do_swap)
 924 {
 925     uint16_t insn = cpu_lduw_code(env, addr);
 926     if (do_swap) {
 927         return bswap16(insn);
 928     }
 929     return insn;
 930 }
 931
 932 #endif