hw/pcie.c

   1 /*
   2  * pcie.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "sysemu.h"
  22 #include "pci_bridge.h"
  23 #include "pcie.h"
  24 #include "msix.h"
  25 #include "msi.h"
  26 #include "pci_internals.h"
  27 #include "pcie_regs.h"
  28
  29 //#define DEBUG_PCIE
  30 #ifdef DEBUG_PCIE
  31 # define PCIE_DPRINTF(fmt, ...)                                         \
  32     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  33 #else
  34 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  35 #endif
  36 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  37     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  38
  39
  40 /***************************************************************************
  41  * pci express capability helper functions
  42  */
  43 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
  44 {
  45     int pos;
  46     uint8_t *exp_cap;
  47
  48     assert(pci_is_express(dev));
  49
  50     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
  51                                  PCI_EXP_VER2_SIZEOF);
  52     if (pos < 0) {
  53         return pos;
  54     }
  55     dev->exp.exp_cap = pos;
  56     exp_cap = dev->config + pos;
  57
  58     /* capability register
  59        interrupt message number defaults to 0 */
  60     pci_set_word(exp_cap + PCI_EXP_FLAGS,
  61                  ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  62                  PCI_EXP_FLAGS_VER2);
  63
  64     /* device capability register
  65      * table 7-12:
  66      * roll based error reporting bit must be set by all
  67      * Functions conforming to the ECN, PCI Express Base
  68      * Specification, Revision 1.1., or subsequent PCI Express Base
  69      * Specification revisions.
  70      */
  71     pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  72
  73     pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  74                  (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  75                  PCI_EXP_LNKCAP_ASPMS_0S |
  76                  PCI_EXP_LNK_MLW_1 |
  77                  PCI_EXP_LNK_LS_25);
  78
  79     pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  80                  PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  81
  82     pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
  83                  PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
  84
  85     pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
  86     return pos;
  87 }
  88
  89 void pcie_cap_exit(PCIDevice *dev)
  90 {
  91     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
  92 }
  93
  94 uint8_t pcie_cap_get_type(const PCIDevice *dev)
  95 {
  96     uint32_t pos = dev->exp.exp_cap;
  97     assert(pos > 0);
  98     return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
  99             PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 100 }
 101
 102 /* MSI/MSI-X */
 103 /* pci express interrupt message number */
 104 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 105 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 106 {
 107     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 108     assert(vector < 32);
 109     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 110     pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 111                                vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 112 }
 113
 114 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 115 {
 116     return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 117             PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 118 }
 119
 120 void pcie_cap_deverr_init(PCIDevice *dev)
 121 {
 122     uint32_t pos = dev->exp.exp_cap;
 123     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 124                                PCI_EXP_DEVCAP_RBER);
 125     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 126                                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 127                                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 128     pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 129                                PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 130                                PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD);
 131 }
 132
 133 void pcie_cap_deverr_reset(PCIDevice *dev)
 134 {
 135     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 136     pci_long_test_and_clear_mask(devctl,
 137                                  PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 138                                  PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 139 }
 140
 141 /*
 142  * A PCI Express Hot-Plug Event has occured, so update slot status register
 143  * and notify OS of the event if necessary.
 144  *
 145  * 6.7.3 PCI Express Hot-Plug Events
 146  * 6.7.3.4 Software Notification of Hot-Plug Events
 147  */
 148 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 149 {
 150     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 151     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 152     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 153
 154     PCIE_DEV_PRINTF(dev,
 155                     "sltctl: 0x%02"PRIx16" sltsta: 0x%02"PRIx16" event: %x\n",
 156                     sltctl, sltsta, event);
 157
 158     if (pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, event)) {
 159         return;
 160     }
 161     sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 162     PCIE_DEV_PRINTF(dev, "sltsta -> %02"PRIx16"\n", sltsta);
 163
 164     if ((sltctl & PCI_EXP_SLTCTL_HPIE) &&
 165         (sltctl & event & PCI_EXP_HP_EV_SUPPORTED)) {
 166         if (pci_msi_enabled(dev)) {
 167             pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
 168         } else {
 169             qemu_set_irq(dev->irq[dev->exp.hpev_intx], 1);
 170         }
 171     }
 172 }
 173
 174 static int pcie_cap_slot_hotplug(DeviceState *qdev,
 175                                  PCIDevice *pci_dev, int state)
 176 {
 177     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
 178     uint8_t *exp_cap = d->config + d->exp.exp_cap;
 179     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 180
 181     if (!pci_dev->qdev.hotplugged) {
 182         assert(state); /* this case only happens at machine creation. */
 183         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 184                                    PCI_EXP_SLTSTA_PDS);
 185         return 0;
 186     }
 187
 188     PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state);
 189     if (sltsta & PCI_EXP_SLTSTA_EIS) {
 190         /* the slot is electromechanically locked.
 191          * This error is propagated up to qdev and then to HMP/QMP.
 192          */
 193         return -EBUSY;
 194     }
 195
 196     /* TODO: multifunction hot-plug.
 197      * Right now, only a device of function = 0 is allowed to be
 198      * hot plugged/unplugged.
 199      */
 200     assert(PCI_FUNC(pci_dev->devfn) == 0);
 201
 202     if (state) {
 203         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 204                                    PCI_EXP_SLTSTA_PDS);
 205         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 206     } else {
 207         qdev_free(&pci_dev->qdev);
 208         pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 209                                      PCI_EXP_SLTSTA_PDS);
 210         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 211     }
 212     return 0;
 213 }
 214
 215 /* pci express slot for pci express root/downstream port
 216    PCI express capability slot registers */
 217 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 218 {
 219     uint32_t pos = dev->exp.exp_cap;
 220
 221     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 222                                PCI_EXP_FLAGS_SLOT);
 223
 224     pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 225                                  ~PCI_EXP_SLTCAP_PSN);
 226     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 227                                (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 228                                PCI_EXP_SLTCAP_EIP |
 229                                PCI_EXP_SLTCAP_HPS |
 230                                PCI_EXP_SLTCAP_HPC |
 231                                PCI_EXP_SLTCAP_PIP |
 232                                PCI_EXP_SLTCAP_AIP |
 233                                PCI_EXP_SLTCAP_ABP);
 234
 235     pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 236                                  PCI_EXP_SLTCTL_PIC |
 237                                  PCI_EXP_SLTCTL_AIC);
 238     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 239                                PCI_EXP_SLTCTL_PIC_OFF |
 240                                PCI_EXP_SLTCTL_AIC_OFF);
 241     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 242                                PCI_EXP_SLTCTL_PIC |
 243                                PCI_EXP_SLTCTL_AIC |
 244                                PCI_EXP_SLTCTL_HPIE |
 245                                PCI_EXP_SLTCTL_CCIE |
 246                                PCI_EXP_SLTCTL_PDCE |
 247                                PCI_EXP_SLTCTL_ABPE);
 248     /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 249      * make the bit writable here in order to detect 1b is written.
 250      * pcie_cap_slot_write_config() test-and-clear the bit, so
 251      * this bit always returns 0 to the guest.
 252      */
 253     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 254                                PCI_EXP_SLTCTL_EIC);
 255
 256     pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 257                                PCI_EXP_HP_EV_SUPPORTED);
 258
 259     pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)),
 260                     pcie_cap_slot_hotplug, &dev->qdev);
 261 }
 262
 263 void pcie_cap_slot_reset(PCIDevice *dev)
 264 {
 265     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 266
 267     PCIE_DEV_PRINTF(dev, "reset\n");
 268
 269     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 270                                  PCI_EXP_SLTCTL_EIC |
 271                                  PCI_EXP_SLTCTL_PIC |
 272                                  PCI_EXP_SLTCTL_AIC |
 273                                  PCI_EXP_SLTCTL_HPIE |
 274                                  PCI_EXP_SLTCTL_CCIE |
 275                                  PCI_EXP_SLTCTL_PDCE |
 276                                  PCI_EXP_SLTCTL_ABPE);
 277     pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 278                                PCI_EXP_SLTCTL_PIC_OFF |
 279                                PCI_EXP_SLTCTL_AIC_OFF);
 280
 281     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 282                                  PCI_EXP_SLTSTA_EIS |/* on reset,
 283                                                         the lock is released */
 284                                  PCI_EXP_SLTSTA_CC |
 285                                  PCI_EXP_SLTSTA_PDC |
 286                                  PCI_EXP_SLTSTA_ABP);
 287 }
 288
 289 void pcie_cap_slot_write_config(PCIDevice *dev,
 290                                 uint32_t addr, uint32_t val, int len,
 291                                 uint16_t sltctl_prev)
 292 {
 293     uint32_t pos = dev->exp.exp_cap;
 294     uint8_t *exp_cap = dev->config + pos;
 295     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 296     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 297
 298     PCIE_DEV_PRINTF(dev,
 299                     "addr: 0x%"PRIx32" val: 0x%"PRIx32" len: %d\n"
 300                     "\tsltctl_prev: 0x%02"PRIx16" sltctl: 0x%02"PRIx16
 301                     " sltsta: 0x%02"PRIx16"\n",
 302                     addr, val, len, sltctl_prev, sltctl, sltsta);
 303
 304     /* SLTCTL */
 305     if (ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 306         PCIE_DEV_PRINTF(dev, "sltctl: 0x%02"PRIx16" -> 0x%02"PRIx16"\n",
 307                         sltctl_prev, sltctl);
 308         if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 309                                          PCI_EXP_SLTCTL_EIC)) {
 310             sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 311             pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 312             PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 313                             "sltsta -> 0x%02"PRIx16"\n",
 314                             sltsta);
 315         }
 316
 317         /*
 318          * The events control bits might be enabled or disabled,
 319          * Check if the software notificastion condition is satisfied
 320          * or disatisfied.
 321          *
 322          * 6.7.3.4 Software Notification of Hot-plug events
 323          */
 324         if (pci_msi_enabled(dev)) {
 325             bool msi_trigger =
 326                 (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 327                 ((sltctl_prev ^ sltctl) & sltctl & /* stlctl: 0 -> 1 */
 328                  sltsta & PCI_EXP_HP_EV_SUPPORTED);
 329             if (msi_trigger) {
 330                 pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
 331             }
 332         } else {
 333             int int_level =
 334                 (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 335                 (sltctl & sltsta & PCI_EXP_HP_EV_SUPPORTED);
 336             qemu_set_irq(dev->irq[dev->exp.hpev_intx], int_level);
 337         }
 338
 339         if (!((sltctl_prev ^ sltctl) & PCI_EXP_SLTCTL_SUPPORTED)) {
 340             PCIE_DEV_PRINTF(dev,
 341                             "sprious command completion slctl "
 342                             "0x%"PRIx16" -> 0x%"PRIx16"\n",
 343                             sltctl_prev, sltctl);
 344         }
 345
 346         /* command completion.
 347          * Real hardware might take a while to complete
 348          * requested command because physical movement would be involved
 349          * like locking the electromechanical lock.
 350          * However in our case, command is completed instantaneously above,
 351          * so send a command completion event right now.
 352          *
 353          * 6.7.3.2 Command Completed Events
 354          */
 355         /* set command completed bit */
 356         pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 357     }
 358 }
 359
 360 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 361 {
 362     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 363 }
 364
 365 /* root control/capabilities/status. PME isn't emulated for now */
 366 void pcie_cap_root_init(PCIDevice *dev)
 367 {
 368     pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 369                  PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 370                  PCI_EXP_RTCTL_SEFEE);
 371 }
 372
 373 void pcie_cap_root_reset(PCIDevice *dev)
 374 {
 375     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 376 }
 377
 378 /*
 379  * TODO: implement FLR:
 380  * Right now sets the bit which indicates FLR is supported.
 381  */
 382 /* function level reset(FLR) */
 383 void pcie_cap_flr_init(PCIDevice *dev)
 384 {
 385     pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 386                                PCI_EXP_DEVCAP_FLR);
 387
 388     /* Although reading BCR_FLR returns always 0,
 389      * the bit is made writable here in order to detect the 1b is written
 390      * pcie_cap_flr_write_config() test-and-clear the bit, so
 391      * this bit always returns 0 to the guest.
 392      */
 393     pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 394                                PCI_EXP_DEVCTL_BCR_FLR);
 395 }
 396
 397 void pcie_cap_flr_write_config(PCIDevice *dev,
 398                                uint32_t addr, uint32_t val, int len)
 399 {
 400     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 401     if (pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR)) {
 402         /* TODO: implement FLR */
 403     }
 404 }
 405
 406 /* Alternative Routing-ID Interpretation (ARI) */
 407 /* ari forwarding support for down stream port */
 408 void pcie_cap_ari_init(PCIDevice *dev)
 409 {
 410     uint32_t pos = dev->exp.exp_cap;
 411     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 412                                PCI_EXP_DEVCAP2_ARI);
 413     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 414                                PCI_EXP_DEVCTL2_ARI);
 415 }
 416
 417 void pcie_cap_ari_reset(PCIDevice *dev)
 418 {
 419     uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 420     pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 421 }
 422
 423 bool pcie_cap_is_ari_enabled(const PCIDevice *dev)
 424 {
 425     if (!pci_is_express(dev)) {
 426         return false;
 427     }
 428     if (!dev->exp.exp_cap) {
 429         return false;
 430     }
 431
 432     return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 433         PCI_EXP_DEVCTL2_ARI;
 434 }
 435
 436 /**************************************************************************
 437  * pci express extended capability allocation functions
 438  * uint16_t ext_cap_id (16 bit)
 439  * uint8_t cap_ver (4 bit)
 440  * uint16_t cap_offset (12 bit)
 441  * uint16_t ext_cap_size
 442  */
 443
 444 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
 445                                           uint16_t *prev_p)
 446 {
 447     uint16_t prev = 0;
 448     uint16_t next;
 449     uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 450
 451     if (!header) {
 452         /* no extended capability */
 453         next = 0;
 454         goto out;
 455     }
 456     for (next = PCI_CONFIG_SPACE_SIZE; next;
 457          prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 458
 459         assert(next >= PCI_CONFIG_SPACE_SIZE);
 460         assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 461
 462         header = pci_get_long(dev->config + next);
 463         if (PCI_EXT_CAP_ID(header) == cap_id) {
 464             break;
 465         }
 466     }
 467
 468 out:
 469     if (prev_p) {
 470         *prev_p = prev;
 471     }
 472     return next;
 473 }
 474
 475 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 476 {
 477     return pcie_find_capability_list(dev, cap_id, NULL);
 478 }
 479
 480 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 481 {
 482     uint16_t header = pci_get_long(dev->config + pos);
 483     assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 484     header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 485         ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 486     pci_set_long(dev->config + pos, header);
 487 }
 488
 489 /*
 490  * caller must supply valid (offset, size) * such that the range shouldn't
 491  * overlap with other capability or other registers.
 492  * This function doesn't check it.
 493  */
 494 void pcie_add_capability(PCIDevice *dev,
 495                          uint16_t cap_id, uint8_t cap_ver,
 496                          uint16_t offset, uint16_t size)
 497 {
 498     uint32_t header;
 499     uint16_t next;
 500
 501     assert(offset >= PCI_CONFIG_SPACE_SIZE);
 502     assert(offset < offset + size);
 503     assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
 504     assert(size >= 8);
 505     assert(pci_is_express(dev));
 506
 507     if (offset == PCI_CONFIG_SPACE_SIZE) {
 508         header = pci_get_long(dev->config + offset);
 509         next = PCI_EXT_CAP_NEXT(header);
 510     } else {
 511         uint16_t prev;
 512
 513         /* 0 is reserved cap id. use internally to find the last capability
 514            in the linked list */
 515         next = pcie_find_capability_list(dev, 0, &prev);
 516
 517         assert(prev >= PCI_CONFIG_SPACE_SIZE);
 518         assert(next == 0);
 519         pcie_ext_cap_set_next(dev, prev, offset);
 520     }
 521     pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
 522
 523     /* Make capability read-only by default */
 524     memset(dev->wmask + offset, 0, size);
 525     memset(dev->w1cmask + offset, 0, size);
 526     /* Check capability by default */
 527     memset(dev->cmask + offset, 0xFF, size);
 528 }
 529
 530 /**************************************************************************
 531  * pci express extended capability helper functions
 532  */
 533
 534 /* ARI */
 535 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 536 {
 537     pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 538                         offset, PCI_ARI_SIZEOF);
 539     pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn));
 540 }