4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "translate.h"
29 #include "qemu/host-utils.h"
31 #include "exec/gen-icount.h"
37 static TCGv_i64 cpu_X
[32];
38 static TCGv_i64 cpu_pc
;
39 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_addr
;
43 static TCGv_i64 cpu_exclusive_val
;
44 static TCGv_i64 cpu_exclusive_high
;
45 #ifdef CONFIG_USER_ONLY
46 static TCGv_i64 cpu_exclusive_test
;
47 static TCGv_i32 cpu_exclusive_info
;
50 static const char *regnames
[] = {
51 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
52 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
53 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
54 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
58 A64_SHIFT_TYPE_LSL
= 0,
59 A64_SHIFT_TYPE_LSR
= 1,
60 A64_SHIFT_TYPE_ASR
= 2,
61 A64_SHIFT_TYPE_ROR
= 3
64 /* Table based decoder typedefs - used when the relevant bits for decode
65 * are too awkwardly scattered across the instruction (eg SIMD).
67 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
69 typedef struct AArch64DecodeTable
{
72 AArch64DecodeFn
*disas_fn
;
75 /* Function prototype for gen_ functions for calling Neon helpers */
76 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
78 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
101 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
102 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
103 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
105 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
106 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
107 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
108 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
109 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
110 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
111 #ifdef CONFIG_USER_ONLY
112 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
113 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
114 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
115 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
119 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
120 fprintf_function cpu_fprintf
, int flags
)
122 ARMCPU
*cpu
= ARM_CPU(cs
);
123 CPUARMState
*env
= &cpu
->env
;
124 uint32_t psr
= pstate_read(env
);
127 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
128 env
->pc
, env
->xregs
[31]);
129 for (i
= 0; i
< 31; i
++) {
130 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
132 cpu_fprintf(f
, "\n");
137 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
139 psr
& PSTATE_N
? 'N' : '-',
140 psr
& PSTATE_Z
? 'Z' : '-',
141 psr
& PSTATE_C
? 'C' : '-',
142 psr
& PSTATE_V
? 'V' : '-');
143 cpu_fprintf(f
, "\n");
145 if (flags
& CPU_DUMP_FPU
) {
147 for (i
= 0; i
< numvfpregs
; i
+= 2) {
148 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
149 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
150 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
152 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
153 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
154 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
157 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
158 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
162 static int get_mem_index(DisasContext
*s
)
164 #ifdef CONFIG_USER_ONLY
171 void gen_a64_set_pc_im(uint64_t val
)
173 tcg_gen_movi_i64(cpu_pc
, val
);
176 static void gen_exception(int excp
)
178 TCGv_i32 tmp
= tcg_temp_new_i32();
179 tcg_gen_movi_i32(tmp
, excp
);
180 gen_helper_exception(cpu_env
, tmp
);
181 tcg_temp_free_i32(tmp
);
184 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
186 gen_a64_set_pc_im(s
->pc
- offset
);
188 s
->is_jmp
= DISAS_EXC
;
191 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
193 /* No direct tb linking with singlestep or deterministic io */
194 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
198 /* Only link tbs from inside the same guest page */
199 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
206 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
208 TranslationBlock
*tb
;
211 if (use_goto_tb(s
, n
, dest
)) {
213 gen_a64_set_pc_im(dest
);
214 tcg_gen_exit_tb((intptr_t)tb
+ n
);
215 s
->is_jmp
= DISAS_TB_JUMP
;
217 gen_a64_set_pc_im(dest
);
218 if (s
->singlestep_enabled
) {
219 gen_exception(EXCP_DEBUG
);
222 s
->is_jmp
= DISAS_JUMP
;
226 static void unallocated_encoding(DisasContext
*s
)
228 gen_exception_insn(s
, 4, EXCP_UDEF
);
231 #define unsupported_encoding(s, insn) \
233 qemu_log_mask(LOG_UNIMP, \
234 "%s:%d: unsupported instruction encoding 0x%08x " \
235 "at pc=%016" PRIx64 "\n", \
236 __FILE__, __LINE__, insn, s->pc - 4); \
237 unallocated_encoding(s); \
240 static void init_tmp_a64_array(DisasContext
*s
)
242 #ifdef CONFIG_DEBUG_TCG
244 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
245 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
248 s
->tmp_a64_count
= 0;
251 static void free_tmp_a64(DisasContext
*s
)
254 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
255 tcg_temp_free_i64(s
->tmp_a64
[i
]);
257 init_tmp_a64_array(s
);
260 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
262 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
263 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
266 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
268 TCGv_i64 t
= new_tmp_a64(s
);
269 tcg_gen_movi_i64(t
, 0);
274 * Register access functions
276 * These functions are used for directly accessing a register in where
277 * changes to the final register value are likely to be made. If you
278 * need to use a register for temporary calculation (e.g. index type
279 * operations) use the read_* form.
281 * B1.2.1 Register mappings
283 * In instruction register encoding 31 can refer to ZR (zero register) or
284 * the SP (stack pointer) depending on context. In QEMU's case we map SP
285 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
286 * This is the point of the _sp forms.
288 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
291 return new_tmp_a64_zero(s
);
297 /* register access for when 31 == SP */
298 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
303 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
304 * representing the register contents. This TCGv is an auto-freed
305 * temporary so it need not be explicitly freed, and may be modified.
307 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
309 TCGv_i64 v
= new_tmp_a64(s
);
312 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
314 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
317 tcg_gen_movi_i64(v
, 0);
322 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
324 TCGv_i64 v
= new_tmp_a64(s
);
326 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
328 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
333 /* Return the offset into CPUARMState of an element of specified
334 * size, 'element' places in from the least significant end of
335 * the FP/vector register Qn.
337 static inline int vec_reg_offset(int regno
, int element
, TCGMemOp size
)
339 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
340 #ifdef HOST_WORDS_BIGENDIAN
341 /* This is complicated slightly because vfp.regs[2n] is
342 * still the low half and vfp.regs[2n+1] the high half
343 * of the 128 bit vector, even on big endian systems.
344 * Calculate the offset assuming a fully bigendian 128 bits,
345 * then XOR to account for the order of the two 64 bit halves.
347 offs
+= (16 - ((element
+ 1) * (1 << size
)));
350 offs
+= element
* (1 << size
);
355 /* Return the offset into CPUARMState of a slice (from
356 * the least significant end) of FP register Qn (ie
358 * (Note that this is not the same mapping as for A32; see cpu.h)
360 static inline int fp_reg_offset(int regno
, TCGMemOp size
)
362 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
363 #ifdef HOST_WORDS_BIGENDIAN
364 offs
+= (8 - (1 << size
));
369 /* Offset of the high half of the 128 bit vector Qn */
370 static inline int fp_reg_hi_offset(int regno
)
372 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
375 /* Convenience accessors for reading and writing single and double
376 * FP registers. Writing clears the upper parts of the associated
377 * 128 bit vector register, as required by the architecture.
378 * Note that unlike the GP register accessors, the values returned
379 * by the read functions must be manually freed.
381 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
383 TCGv_i64 v
= tcg_temp_new_i64();
385 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
389 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
391 TCGv_i32 v
= tcg_temp_new_i32();
393 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(reg
, MO_32
));
397 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
399 TCGv_i64 tcg_zero
= tcg_const_i64(0);
401 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
402 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(reg
));
403 tcg_temp_free_i64(tcg_zero
);
406 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
408 TCGv_i64 tmp
= tcg_temp_new_i64();
410 tcg_gen_extu_i32_i64(tmp
, v
);
411 write_fp_dreg(s
, reg
, tmp
);
412 tcg_temp_free_i64(tmp
);
415 static TCGv_ptr
get_fpstatus_ptr(void)
417 TCGv_ptr statusptr
= tcg_temp_new_ptr();
420 /* In A64 all instructions (both FP and Neon) use the FPCR;
421 * there is no equivalent of the A32 Neon "standard FPSCR value"
422 * and all operations use vfp.fp_status.
424 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
425 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
429 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
430 * than the 32 bit equivalent.
432 static inline void gen_set_NZ64(TCGv_i64 result
)
434 TCGv_i64 flag
= tcg_temp_new_i64();
436 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
437 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
438 tcg_gen_shri_i64(flag
, result
, 32);
439 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
440 tcg_temp_free_i64(flag
);
443 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
444 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
447 gen_set_NZ64(result
);
449 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
450 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
452 tcg_gen_movi_i32(cpu_CF
, 0);
453 tcg_gen_movi_i32(cpu_VF
, 0);
456 /* dest = T0 + T1; compute C, N, V and Z flags */
457 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
460 TCGv_i64 result
, flag
, tmp
;
461 result
= tcg_temp_new_i64();
462 flag
= tcg_temp_new_i64();
463 tmp
= tcg_temp_new_i64();
465 tcg_gen_movi_i64(tmp
, 0);
466 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
468 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
470 gen_set_NZ64(result
);
472 tcg_gen_xor_i64(flag
, result
, t0
);
473 tcg_gen_xor_i64(tmp
, t0
, t1
);
474 tcg_gen_andc_i64(flag
, flag
, tmp
);
475 tcg_temp_free_i64(tmp
);
476 tcg_gen_shri_i64(flag
, flag
, 32);
477 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
479 tcg_gen_mov_i64(dest
, result
);
480 tcg_temp_free_i64(result
);
481 tcg_temp_free_i64(flag
);
483 /* 32 bit arithmetic */
484 TCGv_i32 t0_32
= tcg_temp_new_i32();
485 TCGv_i32 t1_32
= tcg_temp_new_i32();
486 TCGv_i32 tmp
= tcg_temp_new_i32();
488 tcg_gen_movi_i32(tmp
, 0);
489 tcg_gen_trunc_i64_i32(t0_32
, t0
);
490 tcg_gen_trunc_i64_i32(t1_32
, t1
);
491 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
492 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
493 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
494 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
495 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
496 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
498 tcg_temp_free_i32(tmp
);
499 tcg_temp_free_i32(t0_32
);
500 tcg_temp_free_i32(t1_32
);
504 /* dest = T0 - T1; compute C, N, V and Z flags */
505 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
508 /* 64 bit arithmetic */
509 TCGv_i64 result
, flag
, tmp
;
511 result
= tcg_temp_new_i64();
512 flag
= tcg_temp_new_i64();
513 tcg_gen_sub_i64(result
, t0
, t1
);
515 gen_set_NZ64(result
);
517 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
518 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
520 tcg_gen_xor_i64(flag
, result
, t0
);
521 tmp
= tcg_temp_new_i64();
522 tcg_gen_xor_i64(tmp
, t0
, t1
);
523 tcg_gen_and_i64(flag
, flag
, tmp
);
524 tcg_temp_free_i64(tmp
);
525 tcg_gen_shri_i64(flag
, flag
, 32);
526 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
527 tcg_gen_mov_i64(dest
, result
);
528 tcg_temp_free_i64(flag
);
529 tcg_temp_free_i64(result
);
531 /* 32 bit arithmetic */
532 TCGv_i32 t0_32
= tcg_temp_new_i32();
533 TCGv_i32 t1_32
= tcg_temp_new_i32();
536 tcg_gen_trunc_i64_i32(t0_32
, t0
);
537 tcg_gen_trunc_i64_i32(t1_32
, t1
);
538 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
539 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
540 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
541 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
542 tmp
= tcg_temp_new_i32();
543 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
544 tcg_temp_free_i32(t0_32
);
545 tcg_temp_free_i32(t1_32
);
546 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
547 tcg_temp_free_i32(tmp
);
548 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
552 /* dest = T0 + T1 + CF; do not compute flags. */
553 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
555 TCGv_i64 flag
= tcg_temp_new_i64();
556 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
557 tcg_gen_add_i64(dest
, t0
, t1
);
558 tcg_gen_add_i64(dest
, dest
, flag
);
559 tcg_temp_free_i64(flag
);
562 tcg_gen_ext32u_i64(dest
, dest
);
566 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
567 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
570 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
571 result
= tcg_temp_new_i64();
572 cf_64
= tcg_temp_new_i64();
573 vf_64
= tcg_temp_new_i64();
574 tmp
= tcg_const_i64(0);
576 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
577 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
578 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
579 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
580 gen_set_NZ64(result
);
582 tcg_gen_xor_i64(vf_64
, result
, t0
);
583 tcg_gen_xor_i64(tmp
, t0
, t1
);
584 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
585 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
586 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
588 tcg_gen_mov_i64(dest
, result
);
590 tcg_temp_free_i64(tmp
);
591 tcg_temp_free_i64(vf_64
);
592 tcg_temp_free_i64(cf_64
);
593 tcg_temp_free_i64(result
);
595 TCGv_i32 t0_32
, t1_32
, tmp
;
596 t0_32
= tcg_temp_new_i32();
597 t1_32
= tcg_temp_new_i32();
598 tmp
= tcg_const_i32(0);
600 tcg_gen_trunc_i64_i32(t0_32
, t0
);
601 tcg_gen_trunc_i64_i32(t1_32
, t1
);
602 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
603 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
605 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
606 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
607 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
608 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
609 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
611 tcg_temp_free_i32(tmp
);
612 tcg_temp_free_i32(t1_32
);
613 tcg_temp_free_i32(t0_32
);
618 * Load/Store generators
622 * Store from GPR register to memory.
624 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
625 TCGv_i64 tcg_addr
, int size
, int memidx
)
628 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
631 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
632 TCGv_i64 tcg_addr
, int size
)
634 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
638 * Load from memory to GPR register
640 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
641 int size
, bool is_signed
, bool extend
, int memidx
)
643 TCGMemOp memop
= MO_TE
+ size
;
651 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
653 if (extend
&& is_signed
) {
655 tcg_gen_ext32u_i64(dest
, dest
);
659 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
660 int size
, bool is_signed
, bool extend
)
662 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
667 * Store from FP register to memory
669 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
671 /* This writes the bottom N bits of a 128 bit wide vector to memory */
672 TCGv_i64 tmp
= tcg_temp_new_i64();
673 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(srcidx
, MO_64
));
675 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
677 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
678 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
679 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
680 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(srcidx
));
681 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
682 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
683 tcg_temp_free_i64(tcg_hiaddr
);
686 tcg_temp_free_i64(tmp
);
690 * Load from memory to FP register
692 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
694 /* This always zero-extends and writes to a full 128 bit wide vector */
695 TCGv_i64 tmplo
= tcg_temp_new_i64();
699 TCGMemOp memop
= MO_TE
+ size
;
700 tmphi
= tcg_const_i64(0);
701 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
704 tmphi
= tcg_temp_new_i64();
705 tcg_hiaddr
= tcg_temp_new_i64();
707 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
708 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
709 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
710 tcg_temp_free_i64(tcg_hiaddr
);
713 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(destidx
, MO_64
));
714 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(destidx
));
716 tcg_temp_free_i64(tmplo
);
717 tcg_temp_free_i64(tmphi
);
721 * Vector load/store helpers.
723 * The principal difference between this and a FP load is that we don't
724 * zero extend as we are filling a partial chunk of the vector register.
725 * These functions don't support 128 bit loads/stores, which would be
726 * normal load/store operations.
728 * The _i32 versions are useful when operating on 32 bit quantities
729 * (eg for floating point single or using Neon helper functions).
732 /* Get value of an element within a vector register */
733 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
734 int element
, TCGMemOp memop
)
736 int vect_off
= vec_reg_offset(srcidx
, element
, memop
& MO_SIZE
);
739 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
742 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
745 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
748 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
751 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
754 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
758 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
761 g_assert_not_reached();
765 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
766 int element
, TCGMemOp memop
)
768 int vect_off
= vec_reg_offset(srcidx
, element
, memop
& MO_SIZE
);
771 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
774 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
777 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
780 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
784 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
787 g_assert_not_reached();
791 /* Set value of an element within a vector register */
792 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
793 int element
, TCGMemOp memop
)
795 int vect_off
= vec_reg_offset(destidx
, element
, memop
& MO_SIZE
);
798 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
801 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
804 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
807 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
810 g_assert_not_reached();
814 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
815 int destidx
, int element
, TCGMemOp memop
)
817 int vect_off
= vec_reg_offset(destidx
, element
, memop
& MO_SIZE
);
820 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
823 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
826 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
829 g_assert_not_reached();
833 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
834 * vector ops all need to do this).
836 static void clear_vec_high(DisasContext
*s
, int rd
)
838 TCGv_i64 tcg_zero
= tcg_const_i64(0);
840 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
841 tcg_temp_free_i64(tcg_zero
);
844 /* Store from vector register to memory */
845 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
846 TCGv_i64 tcg_addr
, int size
)
848 TCGMemOp memop
= MO_TE
+ size
;
849 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
851 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
852 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
854 tcg_temp_free_i64(tcg_tmp
);
857 /* Load from memory to vector register */
858 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
859 TCGv_i64 tcg_addr
, int size
)
861 TCGMemOp memop
= MO_TE
+ size
;
862 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
864 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
865 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
867 tcg_temp_free_i64(tcg_tmp
);
871 * This utility function is for doing register extension with an
872 * optional shift. You will likely want to pass a temporary for the
873 * destination register. See DecodeRegExtend() in the ARM ARM.
875 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
876 int option
, unsigned int shift
)
878 int extsize
= extract32(option
, 0, 2);
879 bool is_signed
= extract32(option
, 2, 1);
884 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
887 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
890 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
893 tcg_gen_mov_i64(tcg_out
, tcg_in
);
899 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
902 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
905 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
908 tcg_gen_mov_i64(tcg_out
, tcg_in
);
914 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
918 static inline void gen_check_sp_alignment(DisasContext
*s
)
920 /* The AArch64 architecture mandates that (if enabled via PSTATE
921 * or SCTLR bits) there is a check that SP is 16-aligned on every
922 * SP-relative load or store (with an exception generated if it is not).
923 * In line with general QEMU practice regarding misaligned accesses,
924 * we omit these checks for the sake of guest program performance.
925 * This function is provided as a hook so we can more easily add these
926 * checks in future (possibly as a "favour catching guest program bugs
927 * over speed" user selectable option).
932 * This provides a simple table based table lookup decoder. It is
933 * intended to be used when the relevant bits for decode are too
934 * awkwardly placed and switch/if based logic would be confusing and
935 * deeply nested. Since it's a linear search through the table, tables
936 * should be kept small.
938 * It returns the first handler where insn & mask == pattern, or
939 * NULL if there is no match.
940 * The table is terminated by an empty mask (i.e. 0)
942 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
945 const AArch64DecodeTable
*tptr
= table
;
948 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
949 return tptr
->disas_fn
;
957 * the instruction disassembly implemented here matches
958 * the instruction encoding classifications in chapter 3 (C3)
959 * of the ARM Architecture Reference Manual (DDI0487A_a)
962 /* C3.2.7 Unconditional branch (immediate)
964 * +----+-----------+-------------------------------------+
965 * | op | 0 0 1 0 1 | imm26 |
966 * +----+-----------+-------------------------------------+
968 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
970 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
972 if (insn
& (1 << 31)) {
973 /* C5.6.26 BL Branch with link */
974 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
977 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
978 gen_goto_tb(s
, 0, addr
);
981 /* C3.2.1 Compare & branch (immediate)
982 * 31 30 25 24 23 5 4 0
983 * +----+-------------+----+---------------------+--------+
984 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
985 * +----+-------------+----+---------------------+--------+
987 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
989 unsigned int sf
, op
, rt
;
994 sf
= extract32(insn
, 31, 1);
995 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
996 rt
= extract32(insn
, 0, 5);
997 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
999 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1000 label_match
= gen_new_label();
1002 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1003 tcg_cmp
, 0, label_match
);
1005 gen_goto_tb(s
, 0, s
->pc
);
1006 gen_set_label(label_match
);
1007 gen_goto_tb(s
, 1, addr
);
1010 /* C3.2.5 Test & branch (immediate)
1011 * 31 30 25 24 23 19 18 5 4 0
1012 * +----+-------------+----+-------+-------------+------+
1013 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1014 * +----+-------------+----+-------+-------------+------+
1016 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1018 unsigned int bit_pos
, op
, rt
;
1023 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1024 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1025 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1026 rt
= extract32(insn
, 0, 5);
1028 tcg_cmp
= tcg_temp_new_i64();
1029 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1030 label_match
= gen_new_label();
1031 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1032 tcg_cmp
, 0, label_match
);
1033 tcg_temp_free_i64(tcg_cmp
);
1034 gen_goto_tb(s
, 0, s
->pc
);
1035 gen_set_label(label_match
);
1036 gen_goto_tb(s
, 1, addr
);
1039 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1040 * 31 25 24 23 5 4 3 0
1041 * +---------------+----+---------------------+----+------+
1042 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1043 * +---------------+----+---------------------+----+------+
1045 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1050 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1051 unallocated_encoding(s
);
1054 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1055 cond
= extract32(insn
, 0, 4);
1058 /* genuinely conditional branches */
1059 int label_match
= gen_new_label();
1060 arm_gen_test_cc(cond
, label_match
);
1061 gen_goto_tb(s
, 0, s
->pc
);
1062 gen_set_label(label_match
);
1063 gen_goto_tb(s
, 1, addr
);
1065 /* 0xe and 0xf are both "always" conditions */
1066 gen_goto_tb(s
, 0, addr
);
1071 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1072 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1074 unsigned int selector
= crm
<< 3 | op2
;
1077 unallocated_encoding(s
);
1085 s
->is_jmp
= DISAS_WFI
;
1091 /* we treat all as NOP at least for now */
1094 /* default specified as NOP equivalent */
1099 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1101 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1104 /* CLREX, DSB, DMB, ISB */
1105 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1106 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1109 unallocated_encoding(s
);
1120 /* We don't emulate caches so barriers are no-ops */
1123 unallocated_encoding(s
);
1128 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1129 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1130 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1132 int op
= op1
<< 3 | op2
;
1134 case 0x05: /* SPSel */
1135 if (s
->current_pl
== 0) {
1136 unallocated_encoding(s
);
1140 case 0x1e: /* DAIFSet */
1141 case 0x1f: /* DAIFClear */
1143 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1144 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1145 gen_a64_set_pc_im(s
->pc
- 4);
1146 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1147 tcg_temp_free_i32(tcg_imm
);
1148 tcg_temp_free_i32(tcg_op
);
1149 s
->is_jmp
= DISAS_UPDATE
;
1153 unallocated_encoding(s
);
1158 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1160 TCGv_i32 tmp
= tcg_temp_new_i32();
1161 TCGv_i32 nzcv
= tcg_temp_new_i32();
1163 /* build bit 31, N */
1164 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1165 /* build bit 30, Z */
1166 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1167 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1168 /* build bit 29, C */
1169 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1170 /* build bit 28, V */
1171 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1172 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1173 /* generate result */
1174 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1176 tcg_temp_free_i32(nzcv
);
1177 tcg_temp_free_i32(tmp
);
1180 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1183 TCGv_i32 nzcv
= tcg_temp_new_i32();
1185 /* take NZCV from R[t] */
1186 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1189 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1191 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1192 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1194 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1195 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1197 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1198 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1199 tcg_temp_free_i32(nzcv
);
1202 /* C5.6.129 MRS - move from system register
1203 * C5.6.131 MSR (register) - move to system register
1206 * These are all essentially the same insn in 'read' and 'write'
1207 * versions, with varying op0 fields.
1209 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1210 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1211 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1213 const ARMCPRegInfo
*ri
;
1216 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1217 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1218 crn
, crm
, op0
, op1
, op2
));
1221 /* Unknown register; this might be a guest error or a QEMU
1222 * unimplemented feature.
1224 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1225 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1226 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1227 unallocated_encoding(s
);
1231 /* Check access permissions */
1232 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
1233 unallocated_encoding(s
);
1238 /* Emit code to perform further access permissions checks at
1239 * runtime; this may result in an exception.
1242 gen_a64_set_pc_im(s
->pc
- 4);
1243 tmpptr
= tcg_const_ptr(ri
);
1244 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
);
1245 tcg_temp_free_ptr(tmpptr
);
1248 /* Handle special cases first */
1249 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1253 tcg_rt
= cpu_reg(s
, rt
);
1255 gen_get_nzcv(tcg_rt
);
1257 gen_set_nzcv(tcg_rt
);
1260 case ARM_CP_CURRENTEL
:
1261 /* Reads as current EL value from pstate, which is
1262 * guaranteed to be constant by the tb flags.
1264 tcg_rt
= cpu_reg(s
, rt
);
1265 tcg_gen_movi_i64(tcg_rt
, s
->current_pl
<< 2);
1271 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1275 tcg_rt
= cpu_reg(s
, rt
);
1278 if (ri
->type
& ARM_CP_CONST
) {
1279 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1280 } else if (ri
->readfn
) {
1282 tmpptr
= tcg_const_ptr(ri
);
1283 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1284 tcg_temp_free_ptr(tmpptr
);
1286 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1289 if (ri
->type
& ARM_CP_CONST
) {
1290 /* If not forbidden by access permissions, treat as WI */
1292 } else if (ri
->writefn
) {
1294 tmpptr
= tcg_const_ptr(ri
);
1295 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1296 tcg_temp_free_ptr(tmpptr
);
1298 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1302 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1303 /* I/O operations must end the TB here (whether read or write) */
1305 s
->is_jmp
= DISAS_UPDATE
;
1306 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1307 /* We default to ending the TB on a coprocessor register write,
1308 * but allow this to be suppressed by the register definition
1309 * (usually only necessary to work around guest bugs).
1311 s
->is_jmp
= DISAS_UPDATE
;
1316 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1317 * +---------------------+---+-----+-----+-------+-------+-----+------+
1318 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1319 * +---------------------+---+-----+-----+-------+-------+-----+------+
1321 static void disas_system(DisasContext
*s
, uint32_t insn
)
1323 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1324 l
= extract32(insn
, 21, 1);
1325 op0
= extract32(insn
, 19, 2);
1326 op1
= extract32(insn
, 16, 3);
1327 crn
= extract32(insn
, 12, 4);
1328 crm
= extract32(insn
, 8, 4);
1329 op2
= extract32(insn
, 5, 3);
1330 rt
= extract32(insn
, 0, 5);
1333 if (l
|| rt
!= 31) {
1334 unallocated_encoding(s
);
1338 case 2: /* C5.6.68 HINT */
1339 handle_hint(s
, insn
, op1
, op2
, crm
);
1341 case 3: /* CLREX, DSB, DMB, ISB */
1342 handle_sync(s
, insn
, op1
, op2
, crm
);
1344 case 4: /* C5.6.130 MSR (immediate) */
1345 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1348 unallocated_encoding(s
);
1353 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1356 /* C3.2.3 Exception generation
1358 * 31 24 23 21 20 5 4 2 1 0
1359 * +-----------------+-----+------------------------+-----+----+
1360 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1361 * +-----------------------+------------------------+----------+
1363 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1365 int opc
= extract32(insn
, 21, 3);
1366 int op2_ll
= extract32(insn
, 0, 5);
1370 /* SVC, HVC, SMC; since we don't support the Virtualization
1371 * or TrustZone extensions these all UNDEF except SVC.
1374 unallocated_encoding(s
);
1377 gen_exception_insn(s
, 0, EXCP_SWI
);
1381 unallocated_encoding(s
);
1385 gen_exception_insn(s
, 0, EXCP_BKPT
);
1389 unallocated_encoding(s
);
1393 unsupported_encoding(s
, insn
);
1396 if (op2_ll
< 1 || op2_ll
> 3) {
1397 unallocated_encoding(s
);
1400 /* DCPS1, DCPS2, DCPS3 */
1401 unsupported_encoding(s
, insn
);
1404 unallocated_encoding(s
);
1409 /* C3.2.7 Unconditional branch (register)
1410 * 31 25 24 21 20 16 15 10 9 5 4 0
1411 * +---------------+-------+-------+-------+------+-------+
1412 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1413 * +---------------+-------+-------+-------+------+-------+
1415 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1417 unsigned int opc
, op2
, op3
, rn
, op4
;
1419 opc
= extract32(insn
, 21, 4);
1420 op2
= extract32(insn
, 16, 5);
1421 op3
= extract32(insn
, 10, 6);
1422 rn
= extract32(insn
, 5, 5);
1423 op4
= extract32(insn
, 0, 5);
1425 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1426 unallocated_encoding(s
);
1435 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1440 unallocated_encoding(s
);
1442 unsupported_encoding(s
, insn
);
1446 unallocated_encoding(s
);
1450 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1451 s
->is_jmp
= DISAS_JUMP
;
1454 /* C3.2 Branches, exception generating and system instructions */
1455 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1457 switch (extract32(insn
, 25, 7)) {
1458 case 0x0a: case 0x0b:
1459 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1460 disas_uncond_b_imm(s
, insn
);
1462 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1463 disas_comp_b_imm(s
, insn
);
1465 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1466 disas_test_b_imm(s
, insn
);
1468 case 0x2a: /* Conditional branch (immediate) */
1469 disas_cond_b_imm(s
, insn
);
1471 case 0x6a: /* Exception generation / System */
1472 if (insn
& (1 << 24)) {
1473 disas_system(s
, insn
);
1478 case 0x6b: /* Unconditional branch (register) */
1479 disas_uncond_b_reg(s
, insn
);
1482 unallocated_encoding(s
);
1488 * Load/Store exclusive instructions are implemented by remembering
1489 * the value/address loaded, and seeing if these are the same
1490 * when the store is performed. This is not actually the architecturally
1491 * mandated semantics, but it works for typical guest code sequences
1492 * and avoids having to monitor regular stores.
1494 * In system emulation mode only one CPU will be running at once, so
1495 * this sequence is effectively atomic. In user emulation mode we
1496 * throw an exception and handle the atomic operation elsewhere.
1498 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1499 TCGv_i64 addr
, int size
, bool is_pair
)
1501 TCGv_i64 tmp
= tcg_temp_new_i64();
1502 TCGMemOp memop
= MO_TE
+ size
;
1504 g_assert(size
<= 3);
1505 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1508 TCGv_i64 addr2
= tcg_temp_new_i64();
1509 TCGv_i64 hitmp
= tcg_temp_new_i64();
1511 g_assert(size
>= 2);
1512 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1513 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1514 tcg_temp_free_i64(addr2
);
1515 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1516 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1517 tcg_temp_free_i64(hitmp
);
1520 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1521 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1523 tcg_temp_free_i64(tmp
);
1524 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1527 #ifdef CONFIG_USER_ONLY
1528 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1529 TCGv_i64 addr
, int size
, int is_pair
)
1531 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1532 tcg_gen_movi_i32(cpu_exclusive_info
,
1533 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1534 gen_exception_insn(s
, 4, EXCP_STREX
);
1537 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1538 TCGv_i64 inaddr
, int size
, int is_pair
)
1540 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1541 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1544 * [addr + datasize] = {Rt2};
1550 * env->exclusive_addr = -1;
1552 int fail_label
= gen_new_label();
1553 int done_label
= gen_new_label();
1554 TCGv_i64 addr
= tcg_temp_local_new_i64();
1557 /* Copy input into a local temp so it is not trashed when the
1558 * basic block ends at the branch insn.
1560 tcg_gen_mov_i64(addr
, inaddr
);
1561 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1563 tmp
= tcg_temp_new_i64();
1564 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1565 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1566 tcg_temp_free_i64(tmp
);
1569 TCGv_i64 addrhi
= tcg_temp_new_i64();
1570 TCGv_i64 tmphi
= tcg_temp_new_i64();
1572 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1573 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1574 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1576 tcg_temp_free_i64(tmphi
);
1577 tcg_temp_free_i64(addrhi
);
1580 /* We seem to still have the exclusive monitor, so do the store */
1581 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1583 TCGv_i64 addrhi
= tcg_temp_new_i64();
1585 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1586 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1587 get_mem_index(s
), MO_TE
+ size
);
1588 tcg_temp_free_i64(addrhi
);
1591 tcg_temp_free_i64(addr
);
1593 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1594 tcg_gen_br(done_label
);
1595 gen_set_label(fail_label
);
1596 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1597 gen_set_label(done_label
);
1598 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1603 /* C3.3.6 Load/store exclusive
1605 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1606 * +-----+-------------+----+---+----+------+----+-------+------+------+
1607 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1608 * +-----+-------------+----+---+----+------+----+-------+------+------+
1610 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1611 * L: 0 -> store, 1 -> load
1612 * o2: 0 -> exclusive, 1 -> not
1613 * o1: 0 -> single register, 1 -> register pair
1614 * o0: 1 -> load-acquire/store-release, 0 -> not
1616 * o0 == 0 AND o2 == 1 is un-allocated
1617 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1619 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1621 int rt
= extract32(insn
, 0, 5);
1622 int rn
= extract32(insn
, 5, 5);
1623 int rt2
= extract32(insn
, 10, 5);
1624 int is_lasr
= extract32(insn
, 15, 1);
1625 int rs
= extract32(insn
, 16, 5);
1626 int is_pair
= extract32(insn
, 21, 1);
1627 int is_store
= !extract32(insn
, 22, 1);
1628 int is_excl
= !extract32(insn
, 23, 1);
1629 int size
= extract32(insn
, 30, 2);
1632 if ((!is_excl
&& !is_lasr
) ||
1633 (is_pair
&& size
< 2)) {
1634 unallocated_encoding(s
);
1639 gen_check_sp_alignment(s
);
1641 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1643 /* Note that since TCG is single threaded load-acquire/store-release
1644 * semantics require no extra if (is_lasr) { ... } handling.
1649 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1651 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1654 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1656 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1658 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1661 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1662 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1664 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1666 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1673 * C3.3.5 Load register (literal)
1675 * 31 30 29 27 26 25 24 23 5 4 0
1676 * +-----+-------+---+-----+-------------------+-------+
1677 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1678 * +-----+-------+---+-----+-------------------+-------+
1680 * V: 1 -> vector (simd/fp)
1681 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1682 * 10-> 32 bit signed, 11 -> prefetch
1683 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1685 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1687 int rt
= extract32(insn
, 0, 5);
1688 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1689 bool is_vector
= extract32(insn
, 26, 1);
1690 int opc
= extract32(insn
, 30, 2);
1691 bool is_signed
= false;
1693 TCGv_i64 tcg_rt
, tcg_addr
;
1697 unallocated_encoding(s
);
1703 /* PRFM (literal) : prefetch */
1706 size
= 2 + extract32(opc
, 0, 1);
1707 is_signed
= extract32(opc
, 1, 1);
1710 tcg_rt
= cpu_reg(s
, rt
);
1712 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1714 do_fp_ld(s
, rt
, tcg_addr
, size
);
1716 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1718 tcg_temp_free_i64(tcg_addr
);
1722 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1723 * C5.6.81 LDP (Load Pair - non vector)
1724 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1725 * C5.6.176 STNP (Store Pair - non-temporal hint)
1726 * C5.6.177 STP (Store Pair - non vector)
1727 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1728 * C6.3.165 LDP (Load Pair of SIMD&FP)
1729 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1730 * C6.3.284 STP (Store Pair of SIMD&FP)
1732 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1733 * +-----+-------+---+---+-------+---+-----------------------------+
1734 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1735 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1737 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1739 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1740 * V: 0 -> GPR, 1 -> Vector
1741 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1742 * 10 -> signed offset, 11 -> pre-index
1743 * L: 0 -> Store 1 -> Load
1745 * Rt, Rt2 = GPR or SIMD registers to be stored
1746 * Rn = general purpose register containing address
1747 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1749 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1751 int rt
= extract32(insn
, 0, 5);
1752 int rn
= extract32(insn
, 5, 5);
1753 int rt2
= extract32(insn
, 10, 5);
1754 int64_t offset
= sextract32(insn
, 15, 7);
1755 int index
= extract32(insn
, 23, 2);
1756 bool is_vector
= extract32(insn
, 26, 1);
1757 bool is_load
= extract32(insn
, 22, 1);
1758 int opc
= extract32(insn
, 30, 2);
1760 bool is_signed
= false;
1761 bool postindex
= false;
1764 TCGv_i64 tcg_addr
; /* calculated address */
1768 unallocated_encoding(s
);
1775 size
= 2 + extract32(opc
, 1, 1);
1776 is_signed
= extract32(opc
, 0, 1);
1777 if (!is_load
&& is_signed
) {
1778 unallocated_encoding(s
);
1784 case 1: /* post-index */
1789 /* signed offset with "non-temporal" hint. Since we don't emulate
1790 * caches we don't care about hints to the cache system about
1791 * data access patterns, and handle this identically to plain
1795 /* There is no non-temporal-hint version of LDPSW */
1796 unallocated_encoding(s
);
1801 case 2: /* signed offset, rn not updated */
1804 case 3: /* pre-index */
1813 gen_check_sp_alignment(s
);
1816 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1819 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1824 do_fp_ld(s
, rt
, tcg_addr
, size
);
1826 do_fp_st(s
, rt
, tcg_addr
, size
);
1829 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1831 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1833 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1836 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1839 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1841 do_fp_st(s
, rt2
, tcg_addr
, size
);
1844 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1846 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1848 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1854 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1856 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1858 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1863 * C3.3.8 Load/store (immediate post-indexed)
1864 * C3.3.9 Load/store (immediate pre-indexed)
1865 * C3.3.12 Load/store (unscaled immediate)
1867 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1868 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1869 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1870 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1872 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1874 * V = 0 -> non-vector
1875 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1876 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1878 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1880 int rt
= extract32(insn
, 0, 5);
1881 int rn
= extract32(insn
, 5, 5);
1882 int imm9
= sextract32(insn
, 12, 9);
1883 int opc
= extract32(insn
, 22, 2);
1884 int size
= extract32(insn
, 30, 2);
1885 int idx
= extract32(insn
, 10, 2);
1886 bool is_signed
= false;
1887 bool is_store
= false;
1888 bool is_extended
= false;
1889 bool is_unpriv
= (idx
== 2);
1890 bool is_vector
= extract32(insn
, 26, 1);
1897 size
|= (opc
& 2) << 1;
1898 if (size
> 4 || is_unpriv
) {
1899 unallocated_encoding(s
);
1902 is_store
= ((opc
& 1) == 0);
1904 if (size
== 3 && opc
== 2) {
1905 /* PRFM - prefetch */
1907 unallocated_encoding(s
);
1912 if (opc
== 3 && size
> 1) {
1913 unallocated_encoding(s
);
1916 is_store
= (opc
== 0);
1917 is_signed
= opc
& (1<<1);
1918 is_extended
= (size
< 3) && (opc
& 1);
1938 gen_check_sp_alignment(s
);
1940 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1943 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1948 do_fp_st(s
, rt
, tcg_addr
, size
);
1950 do_fp_ld(s
, rt
, tcg_addr
, size
);
1953 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1954 int memidx
= is_unpriv
? 1 : get_mem_index(s
);
1957 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
1959 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
1960 is_signed
, is_extended
, memidx
);
1965 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
1967 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1969 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
1974 * C3.3.10 Load/store (register offset)
1976 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1977 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1978 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1979 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1982 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1983 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1985 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1986 * opc<0>: 0 -> store, 1 -> load
1987 * V: 1 -> vector/simd
1988 * opt: extend encoding (see DecodeRegExtend)
1989 * S: if S=1 then scale (essentially index by sizeof(size))
1990 * Rt: register to transfer into/out of
1991 * Rn: address register or SP for base
1992 * Rm: offset register or ZR for offset
1994 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
1996 int rt
= extract32(insn
, 0, 5);
1997 int rn
= extract32(insn
, 5, 5);
1998 int shift
= extract32(insn
, 12, 1);
1999 int rm
= extract32(insn
, 16, 5);
2000 int opc
= extract32(insn
, 22, 2);
2001 int opt
= extract32(insn
, 13, 3);
2002 int size
= extract32(insn
, 30, 2);
2003 bool is_signed
= false;
2004 bool is_store
= false;
2005 bool is_extended
= false;
2006 bool is_vector
= extract32(insn
, 26, 1);
2011 if (extract32(opt
, 1, 1) == 0) {
2012 unallocated_encoding(s
);
2017 size
|= (opc
& 2) << 1;
2019 unallocated_encoding(s
);
2022 is_store
= !extract32(opc
, 0, 1);
2024 if (size
== 3 && opc
== 2) {
2025 /* PRFM - prefetch */
2028 if (opc
== 3 && size
> 1) {
2029 unallocated_encoding(s
);
2032 is_store
= (opc
== 0);
2033 is_signed
= extract32(opc
, 1, 1);
2034 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2038 gen_check_sp_alignment(s
);
2040 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2042 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2043 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2045 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2049 do_fp_st(s
, rt
, tcg_addr
, size
);
2051 do_fp_ld(s
, rt
, tcg_addr
, size
);
2054 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2056 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2058 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2064 * C3.3.13 Load/store (unsigned immediate)
2066 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2067 * +----+-------+---+-----+-----+------------+-------+------+
2068 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2069 * +----+-------+---+-----+-----+------------+-------+------+
2072 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2073 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2075 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2076 * opc<0>: 0 -> store, 1 -> load
2077 * Rn: base address register (inc SP)
2078 * Rt: target register
2080 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2082 int rt
= extract32(insn
, 0, 5);
2083 int rn
= extract32(insn
, 5, 5);
2084 unsigned int imm12
= extract32(insn
, 10, 12);
2085 bool is_vector
= extract32(insn
, 26, 1);
2086 int size
= extract32(insn
, 30, 2);
2087 int opc
= extract32(insn
, 22, 2);
2088 unsigned int offset
;
2093 bool is_signed
= false;
2094 bool is_extended
= false;
2097 size
|= (opc
& 2) << 1;
2099 unallocated_encoding(s
);
2102 is_store
= !extract32(opc
, 0, 1);
2104 if (size
== 3 && opc
== 2) {
2105 /* PRFM - prefetch */
2108 if (opc
== 3 && size
> 1) {
2109 unallocated_encoding(s
);
2112 is_store
= (opc
== 0);
2113 is_signed
= extract32(opc
, 1, 1);
2114 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2118 gen_check_sp_alignment(s
);
2120 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2121 offset
= imm12
<< size
;
2122 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2126 do_fp_st(s
, rt
, tcg_addr
, size
);
2128 do_fp_ld(s
, rt
, tcg_addr
, size
);
2131 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2133 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2135 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2140 /* Load/store register (all forms) */
2141 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2143 switch (extract32(insn
, 24, 2)) {
2145 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2146 disas_ldst_reg_roffset(s
, insn
);
2148 /* Load/store register (unscaled immediate)
2149 * Load/store immediate pre/post-indexed
2150 * Load/store register unprivileged
2152 disas_ldst_reg_imm9(s
, insn
);
2156 disas_ldst_reg_unsigned_imm(s
, insn
);
2159 unallocated_encoding(s
);
2164 /* C3.3.1 AdvSIMD load/store multiple structures
2166 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2167 * +---+---+---------------+---+-------------+--------+------+------+------+
2168 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2169 * +---+---+---------------+---+-------------+--------+------+------+------+
2171 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2173 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2174 * +---+---+---------------+---+---+---------+--------+------+------+------+
2175 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2176 * +---+---+---------------+---+---+---------+--------+------+------+------+
2178 * Rt: first (or only) SIMD&FP register to be transferred
2179 * Rn: base address or SP
2180 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2182 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2184 int rt
= extract32(insn
, 0, 5);
2185 int rn
= extract32(insn
, 5, 5);
2186 int size
= extract32(insn
, 10, 2);
2187 int opcode
= extract32(insn
, 12, 4);
2188 bool is_store
= !extract32(insn
, 22, 1);
2189 bool is_postidx
= extract32(insn
, 23, 1);
2190 bool is_q
= extract32(insn
, 30, 1);
2191 TCGv_i64 tcg_addr
, tcg_rn
;
2193 int ebytes
= 1 << size
;
2194 int elements
= (is_q
? 128 : 64) / (8 << size
);
2195 int rpt
; /* num iterations */
2196 int selem
; /* structure elements */
2199 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2200 unallocated_encoding(s
);
2204 /* From the shared decode logic */
2235 unallocated_encoding(s
);
2239 if (size
== 3 && !is_q
&& selem
!= 1) {
2241 unallocated_encoding(s
);
2246 gen_check_sp_alignment(s
);
2249 tcg_rn
= cpu_reg_sp(s
, rn
);
2250 tcg_addr
= tcg_temp_new_i64();
2251 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2253 for (r
= 0; r
< rpt
; r
++) {
2255 for (e
= 0; e
< elements
; e
++) {
2256 int tt
= (rt
+ r
) % 32;
2258 for (xs
= 0; xs
< selem
; xs
++) {
2260 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2262 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2264 /* For non-quad operations, setting a slice of the low
2265 * 64 bits of the register clears the high 64 bits (in
2266 * the ARM ARM pseudocode this is implicit in the fact
2267 * that 'rval' is a 64 bit wide variable). We optimize
2268 * by noticing that we only need to do this the first
2269 * time we touch a register.
2271 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2272 clear_vec_high(s
, tt
);
2275 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2282 int rm
= extract32(insn
, 16, 5);
2284 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2286 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2289 tcg_temp_free_i64(tcg_addr
);
2292 /* C3.3.3 AdvSIMD load/store single structure
2294 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2295 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2296 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2297 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2299 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2301 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2302 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2303 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2304 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2306 * Rt: first (or only) SIMD&FP register to be transferred
2307 * Rn: base address or SP
2308 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2309 * index = encoded in Q:S:size dependent on size
2311 * lane_size = encoded in R, opc
2312 * transfer width = encoded in opc, S, size
2314 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2316 int rt
= extract32(insn
, 0, 5);
2317 int rn
= extract32(insn
, 5, 5);
2318 int size
= extract32(insn
, 10, 2);
2319 int S
= extract32(insn
, 12, 1);
2320 int opc
= extract32(insn
, 13, 3);
2321 int R
= extract32(insn
, 21, 1);
2322 int is_load
= extract32(insn
, 22, 1);
2323 int is_postidx
= extract32(insn
, 23, 1);
2324 int is_q
= extract32(insn
, 30, 1);
2326 int scale
= extract32(opc
, 1, 2);
2327 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2328 bool replicate
= false;
2329 int index
= is_q
<< 3 | S
<< 2 | size
;
2331 TCGv_i64 tcg_addr
, tcg_rn
;
2335 if (!is_load
|| S
) {
2336 unallocated_encoding(s
);
2345 if (extract32(size
, 0, 1)) {
2346 unallocated_encoding(s
);
2352 if (extract32(size
, 1, 1)) {
2353 unallocated_encoding(s
);
2356 if (!extract32(size
, 0, 1)) {
2360 unallocated_encoding(s
);
2368 g_assert_not_reached();
2371 ebytes
= 1 << scale
;
2374 gen_check_sp_alignment(s
);
2377 tcg_rn
= cpu_reg_sp(s
, rn
);
2378 tcg_addr
= tcg_temp_new_i64();
2379 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2381 for (xs
= 0; xs
< selem
; xs
++) {
2383 /* Load and replicate to all elements */
2385 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2387 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2388 get_mem_index(s
), MO_TE
+ scale
);
2391 mulconst
= 0x0101010101010101ULL
;
2394 mulconst
= 0x0001000100010001ULL
;
2397 mulconst
= 0x0000000100000001ULL
;
2403 g_assert_not_reached();
2406 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2408 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2410 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2412 clear_vec_high(s
, rt
);
2414 tcg_temp_free_i64(tcg_tmp
);
2416 /* Load/store one element per register */
2418 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2420 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2423 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2428 int rm
= extract32(insn
, 16, 5);
2430 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2432 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2435 tcg_temp_free_i64(tcg_addr
);
2438 /* C3.3 Loads and stores */
2439 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2441 switch (extract32(insn
, 24, 6)) {
2442 case 0x08: /* Load/store exclusive */
2443 disas_ldst_excl(s
, insn
);
2445 case 0x18: case 0x1c: /* Load register (literal) */
2446 disas_ld_lit(s
, insn
);
2448 case 0x28: case 0x29:
2449 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2450 disas_ldst_pair(s
, insn
);
2452 case 0x38: case 0x39:
2453 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2454 disas_ldst_reg(s
, insn
);
2456 case 0x0c: /* AdvSIMD load/store multiple structures */
2457 disas_ldst_multiple_struct(s
, insn
);
2459 case 0x0d: /* AdvSIMD load/store single structure */
2460 disas_ldst_single_struct(s
, insn
);
2463 unallocated_encoding(s
);
2468 /* C3.4.6 PC-rel. addressing
2469 * 31 30 29 28 24 23 5 4 0
2470 * +----+-------+-----------+-------------------+------+
2471 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2472 * +----+-------+-----------+-------------------+------+
2474 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2476 unsigned int page
, rd
;
2480 page
= extract32(insn
, 31, 1);
2481 /* SignExtend(immhi:immlo) -> offset */
2482 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2483 rd
= extract32(insn
, 0, 5);
2487 /* ADRP (page based) */
2492 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2496 * C3.4.1 Add/subtract (immediate)
2498 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2499 * +--+--+--+-----------+-----+-------------+-----+-----+
2500 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2501 * +--+--+--+-----------+-----+-------------+-----+-----+
2503 * sf: 0 -> 32bit, 1 -> 64bit
2504 * op: 0 -> add , 1 -> sub
2506 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2508 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2510 int rd
= extract32(insn
, 0, 5);
2511 int rn
= extract32(insn
, 5, 5);
2512 uint64_t imm
= extract32(insn
, 10, 12);
2513 int shift
= extract32(insn
, 22, 2);
2514 bool setflags
= extract32(insn
, 29, 1);
2515 bool sub_op
= extract32(insn
, 30, 1);
2516 bool is_64bit
= extract32(insn
, 31, 1);
2518 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2519 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2520 TCGv_i64 tcg_result
;
2529 unallocated_encoding(s
);
2533 tcg_result
= tcg_temp_new_i64();
2536 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2538 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2541 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2543 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2545 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2547 tcg_temp_free_i64(tcg_imm
);
2551 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2553 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2556 tcg_temp_free_i64(tcg_result
);
2559 /* The input should be a value in the bottom e bits (with higher
2560 * bits zero); returns that value replicated into every element
2561 * of size e in a 64 bit integer.
2563 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2573 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2574 static inline uint64_t bitmask64(unsigned int length
)
2576 assert(length
> 0 && length
<= 64);
2577 return ~0ULL >> (64 - length
);
2580 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2581 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2582 * value (ie should cause a guest UNDEF exception), and true if they are
2583 * valid, in which case the decoded bit pattern is written to result.
2585 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2586 unsigned int imms
, unsigned int immr
)
2589 unsigned e
, levels
, s
, r
;
2592 assert(immn
< 2 && imms
< 64 && immr
< 64);
2594 /* The bit patterns we create here are 64 bit patterns which
2595 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2596 * 64 bits each. Each element contains the same value: a run
2597 * of between 1 and e-1 non-zero bits, rotated within the
2598 * element by between 0 and e-1 bits.
2600 * The element size and run length are encoded into immn (1 bit)
2601 * and imms (6 bits) as follows:
2602 * 64 bit elements: immn = 1, imms = <length of run - 1>
2603 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2604 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2605 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2606 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2607 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2608 * Notice that immn = 0, imms = 11111x is the only combination
2609 * not covered by one of the above options; this is reserved.
2610 * Further, <length of run - 1> all-ones is a reserved pattern.
2612 * In all cases the rotation is by immr % e (and immr is 6 bits).
2615 /* First determine the element size */
2616 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2618 /* This is the immn == 0, imms == 0x11111x case */
2628 /* <length of run - 1> mustn't be all-ones. */
2632 /* Create the value of one element: s+1 set bits rotated
2633 * by r within the element (which is e bits wide)...
2635 mask
= bitmask64(s
+ 1);
2636 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2637 /* ...then replicate the element over the whole 64 bit value */
2638 mask
= bitfield_replicate(mask
, e
);
2643 /* C3.4.4 Logical (immediate)
2644 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2645 * +----+-----+-------------+---+------+------+------+------+
2646 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2647 * +----+-----+-------------+---+------+------+------+------+
2649 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2651 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2652 TCGv_i64 tcg_rd
, tcg_rn
;
2654 bool is_and
= false;
2656 sf
= extract32(insn
, 31, 1);
2657 opc
= extract32(insn
, 29, 2);
2658 is_n
= extract32(insn
, 22, 1);
2659 immr
= extract32(insn
, 16, 6);
2660 imms
= extract32(insn
, 10, 6);
2661 rn
= extract32(insn
, 5, 5);
2662 rd
= extract32(insn
, 0, 5);
2665 unallocated_encoding(s
);
2669 if (opc
== 0x3) { /* ANDS */
2670 tcg_rd
= cpu_reg(s
, rd
);
2672 tcg_rd
= cpu_reg_sp(s
, rd
);
2674 tcg_rn
= cpu_reg(s
, rn
);
2676 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2677 /* some immediate field values are reserved */
2678 unallocated_encoding(s
);
2683 wmask
&= 0xffffffff;
2687 case 0x3: /* ANDS */
2689 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2693 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2696 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2699 assert(FALSE
); /* must handle all above */
2703 if (!sf
&& !is_and
) {
2704 /* zero extend final result; we know we can skip this for AND
2705 * since the immediate had the high 32 bits clear.
2707 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2710 if (opc
== 3) { /* ANDS */
2711 gen_logic_CC(sf
, tcg_rd
);
2716 * C3.4.5 Move wide (immediate)
2718 * 31 30 29 28 23 22 21 20 5 4 0
2719 * +--+-----+-------------+-----+----------------+------+
2720 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2721 * +--+-----+-------------+-----+----------------+------+
2723 * sf: 0 -> 32 bit, 1 -> 64 bit
2724 * opc: 00 -> N, 10 -> Z, 11 -> K
2725 * hw: shift/16 (0,16, and sf only 32, 48)
2727 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2729 int rd
= extract32(insn
, 0, 5);
2730 uint64_t imm
= extract32(insn
, 5, 16);
2731 int sf
= extract32(insn
, 31, 1);
2732 int opc
= extract32(insn
, 29, 2);
2733 int pos
= extract32(insn
, 21, 2) << 4;
2734 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2737 if (!sf
&& (pos
>= 32)) {
2738 unallocated_encoding(s
);
2752 tcg_gen_movi_i64(tcg_rd
, imm
);
2755 tcg_imm
= tcg_const_i64(imm
);
2756 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2757 tcg_temp_free_i64(tcg_imm
);
2759 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2763 unallocated_encoding(s
);
2769 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2770 * +----+-----+-------------+---+------+------+------+------+
2771 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2772 * +----+-----+-------------+---+------+------+------+------+
2774 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2776 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2777 TCGv_i64 tcg_rd
, tcg_tmp
;
2779 sf
= extract32(insn
, 31, 1);
2780 opc
= extract32(insn
, 29, 2);
2781 n
= extract32(insn
, 22, 1);
2782 ri
= extract32(insn
, 16, 6);
2783 si
= extract32(insn
, 10, 6);
2784 rn
= extract32(insn
, 5, 5);
2785 rd
= extract32(insn
, 0, 5);
2786 bitsize
= sf
? 64 : 32;
2788 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2789 unallocated_encoding(s
);
2793 tcg_rd
= cpu_reg(s
, rd
);
2794 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2796 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2798 if (opc
!= 1) { /* SBFM or UBFM */
2799 tcg_gen_movi_i64(tcg_rd
, 0);
2802 /* do the bit move operation */
2804 /* Wd<s-r:0> = Wn<s:r> */
2805 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2807 len
= (si
- ri
) + 1;
2809 /* Wd<32+s-r,32-r> = Wn<s:0> */
2814 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2816 if (opc
== 0) { /* SBFM - sign extend the destination field */
2817 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2818 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2821 if (!sf
) { /* zero extend final result */
2822 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2827 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2828 * +----+------+-------------+---+----+------+--------+------+------+
2829 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2830 * +----+------+-------------+---+----+------+--------+------+------+
2832 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2834 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2836 sf
= extract32(insn
, 31, 1);
2837 n
= extract32(insn
, 22, 1);
2838 rm
= extract32(insn
, 16, 5);
2839 imm
= extract32(insn
, 10, 6);
2840 rn
= extract32(insn
, 5, 5);
2841 rd
= extract32(insn
, 0, 5);
2842 op21
= extract32(insn
, 29, 2);
2843 op0
= extract32(insn
, 21, 1);
2844 bitsize
= sf
? 64 : 32;
2846 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2847 unallocated_encoding(s
);
2849 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2851 tcg_rd
= cpu_reg(s
, rd
);
2854 /* OPTME: we can special case rm==rn as a rotate */
2855 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2856 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2857 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2858 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2859 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2861 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2864 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2865 * so an extract from bit 0 is a special case.
2868 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2870 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2877 /* C3.4 Data processing - immediate */
2878 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2880 switch (extract32(insn
, 23, 6)) {
2881 case 0x20: case 0x21: /* PC-rel. addressing */
2882 disas_pc_rel_adr(s
, insn
);
2884 case 0x22: case 0x23: /* Add/subtract (immediate) */
2885 disas_add_sub_imm(s
, insn
);
2887 case 0x24: /* Logical (immediate) */
2888 disas_logic_imm(s
, insn
);
2890 case 0x25: /* Move wide (immediate) */
2891 disas_movw_imm(s
, insn
);
2893 case 0x26: /* Bitfield */
2894 disas_bitfield(s
, insn
);
2896 case 0x27: /* Extract */
2897 disas_extract(s
, insn
);
2900 unallocated_encoding(s
);
2905 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2906 * Note that it is the caller's responsibility to ensure that the
2907 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2908 * mandated semantics for out of range shifts.
2910 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2911 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
2913 switch (shift_type
) {
2914 case A64_SHIFT_TYPE_LSL
:
2915 tcg_gen_shl_i64(dst
, src
, shift_amount
);
2917 case A64_SHIFT_TYPE_LSR
:
2918 tcg_gen_shr_i64(dst
, src
, shift_amount
);
2920 case A64_SHIFT_TYPE_ASR
:
2922 tcg_gen_ext32s_i64(dst
, src
);
2924 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
2926 case A64_SHIFT_TYPE_ROR
:
2928 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
2931 t0
= tcg_temp_new_i32();
2932 t1
= tcg_temp_new_i32();
2933 tcg_gen_trunc_i64_i32(t0
, src
);
2934 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
2935 tcg_gen_rotr_i32(t0
, t0
, t1
);
2936 tcg_gen_extu_i32_i64(dst
, t0
);
2937 tcg_temp_free_i32(t0
);
2938 tcg_temp_free_i32(t1
);
2942 assert(FALSE
); /* all shift types should be handled */
2946 if (!sf
) { /* zero extend final result */
2947 tcg_gen_ext32u_i64(dst
, dst
);
2951 /* Shift a TCGv src by immediate, put result in dst.
2952 * The shift amount must be in range (this should always be true as the
2953 * relevant instructions will UNDEF on bad shift immediates).
2955 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2956 enum a64_shift_type shift_type
, unsigned int shift_i
)
2958 assert(shift_i
< (sf
? 64 : 32));
2961 tcg_gen_mov_i64(dst
, src
);
2963 TCGv_i64 shift_const
;
2965 shift_const
= tcg_const_i64(shift_i
);
2966 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
2967 tcg_temp_free_i64(shift_const
);
2971 /* C3.5.10 Logical (shifted register)
2972 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2973 * +----+-----+-----------+-------+---+------+--------+------+------+
2974 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2975 * +----+-----+-----------+-------+---+------+--------+------+------+
2977 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
2979 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
2980 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
2982 sf
= extract32(insn
, 31, 1);
2983 opc
= extract32(insn
, 29, 2);
2984 shift_type
= extract32(insn
, 22, 2);
2985 invert
= extract32(insn
, 21, 1);
2986 rm
= extract32(insn
, 16, 5);
2987 shift_amount
= extract32(insn
, 10, 6);
2988 rn
= extract32(insn
, 5, 5);
2989 rd
= extract32(insn
, 0, 5);
2991 if (!sf
&& (shift_amount
& (1 << 5))) {
2992 unallocated_encoding(s
);
2996 tcg_rd
= cpu_reg(s
, rd
);
2998 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
2999 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3000 * register-register MOV and MVN, so it is worth special casing.
3002 tcg_rm
= cpu_reg(s
, rm
);
3004 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3006 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3010 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3012 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3018 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3021 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3024 tcg_rn
= cpu_reg(s
, rn
);
3026 switch (opc
| (invert
<< 2)) {
3029 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3032 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3035 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3039 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3042 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3045 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3053 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3057 gen_logic_CC(sf
, tcg_rd
);
3062 * C3.5.1 Add/subtract (extended register)
3064 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3065 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3066 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3067 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3069 * sf: 0 -> 32bit, 1 -> 64bit
3070 * op: 0 -> add , 1 -> sub
3073 * option: extension type (see DecodeRegExtend)
3074 * imm3: optional shift to Rm
3076 * Rd = Rn + LSL(extend(Rm), amount)
3078 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3080 int rd
= extract32(insn
, 0, 5);
3081 int rn
= extract32(insn
, 5, 5);
3082 int imm3
= extract32(insn
, 10, 3);
3083 int option
= extract32(insn
, 13, 3);
3084 int rm
= extract32(insn
, 16, 5);
3085 bool setflags
= extract32(insn
, 29, 1);
3086 bool sub_op
= extract32(insn
, 30, 1);
3087 bool sf
= extract32(insn
, 31, 1);
3089 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3091 TCGv_i64 tcg_result
;
3094 unallocated_encoding(s
);
3098 /* non-flag setting ops may use SP */
3100 tcg_rd
= cpu_reg_sp(s
, rd
);
3102 tcg_rd
= cpu_reg(s
, rd
);
3104 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3106 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3107 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3109 tcg_result
= tcg_temp_new_i64();
3113 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3115 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3119 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3121 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3126 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3128 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3131 tcg_temp_free_i64(tcg_result
);
3135 * C3.5.2 Add/subtract (shifted register)
3137 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3138 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3139 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3140 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3142 * sf: 0 -> 32bit, 1 -> 64bit
3143 * op: 0 -> add , 1 -> sub
3145 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3146 * imm6: Shift amount to apply to Rm before the add/sub
3148 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3150 int rd
= extract32(insn
, 0, 5);
3151 int rn
= extract32(insn
, 5, 5);
3152 int imm6
= extract32(insn
, 10, 6);
3153 int rm
= extract32(insn
, 16, 5);
3154 int shift_type
= extract32(insn
, 22, 2);
3155 bool setflags
= extract32(insn
, 29, 1);
3156 bool sub_op
= extract32(insn
, 30, 1);
3157 bool sf
= extract32(insn
, 31, 1);
3159 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3160 TCGv_i64 tcg_rn
, tcg_rm
;
3161 TCGv_i64 tcg_result
;
3163 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3164 unallocated_encoding(s
);
3168 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3169 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3171 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3173 tcg_result
= tcg_temp_new_i64();
3177 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3179 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3183 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3185 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3190 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3192 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3195 tcg_temp_free_i64(tcg_result
);
3198 /* C3.5.9 Data-processing (3 source)
3200 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3201 +--+------+-----------+------+------+----+------+------+------+
3202 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3203 +--+------+-----------+------+------+----+------+------+------+
3206 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3208 int rd
= extract32(insn
, 0, 5);
3209 int rn
= extract32(insn
, 5, 5);
3210 int ra
= extract32(insn
, 10, 5);
3211 int rm
= extract32(insn
, 16, 5);
3212 int op_id
= (extract32(insn
, 29, 3) << 4) |
3213 (extract32(insn
, 21, 3) << 1) |
3214 extract32(insn
, 15, 1);
3215 bool sf
= extract32(insn
, 31, 1);
3216 bool is_sub
= extract32(op_id
, 0, 1);
3217 bool is_high
= extract32(op_id
, 2, 1);
3218 bool is_signed
= false;
3223 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3225 case 0x42: /* SMADDL */
3226 case 0x43: /* SMSUBL */
3227 case 0x44: /* SMULH */
3230 case 0x0: /* MADD (32bit) */
3231 case 0x1: /* MSUB (32bit) */
3232 case 0x40: /* MADD (64bit) */
3233 case 0x41: /* MSUB (64bit) */
3234 case 0x4a: /* UMADDL */
3235 case 0x4b: /* UMSUBL */
3236 case 0x4c: /* UMULH */
3239 unallocated_encoding(s
);
3244 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3245 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3246 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3247 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3250 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3252 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3255 tcg_temp_free_i64(low_bits
);
3259 tcg_op1
= tcg_temp_new_i64();
3260 tcg_op2
= tcg_temp_new_i64();
3261 tcg_tmp
= tcg_temp_new_i64();
3264 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3265 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3268 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3269 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3271 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3272 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3276 if (ra
== 31 && !is_sub
) {
3277 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3278 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3280 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3282 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3284 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3289 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3292 tcg_temp_free_i64(tcg_op1
);
3293 tcg_temp_free_i64(tcg_op2
);
3294 tcg_temp_free_i64(tcg_tmp
);
3297 /* C3.5.3 - Add/subtract (with carry)
3298 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3299 * +--+--+--+------------------------+------+---------+------+-----+
3300 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3301 * +--+--+--+------------------------+------+---------+------+-----+
3305 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3307 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3308 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3310 if (extract32(insn
, 10, 6) != 0) {
3311 unallocated_encoding(s
);
3315 sf
= extract32(insn
, 31, 1);
3316 op
= extract32(insn
, 30, 1);
3317 setflags
= extract32(insn
, 29, 1);
3318 rm
= extract32(insn
, 16, 5);
3319 rn
= extract32(insn
, 5, 5);
3320 rd
= extract32(insn
, 0, 5);
3322 tcg_rd
= cpu_reg(s
, rd
);
3323 tcg_rn
= cpu_reg(s
, rn
);
3326 tcg_y
= new_tmp_a64(s
);
3327 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3329 tcg_y
= cpu_reg(s
, rm
);
3333 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3335 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3339 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3340 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3341 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3342 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3343 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3346 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3348 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3349 int label_continue
= -1;
3350 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3352 if (!extract32(insn
, 29, 1)) {
3353 unallocated_encoding(s
);
3356 if (insn
& (1 << 10 | 1 << 4)) {
3357 unallocated_encoding(s
);
3360 sf
= extract32(insn
, 31, 1);
3361 op
= extract32(insn
, 30, 1);
3362 is_imm
= extract32(insn
, 11, 1);
3363 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3364 cond
= extract32(insn
, 12, 4);
3365 rn
= extract32(insn
, 5, 5);
3366 nzcv
= extract32(insn
, 0, 4);
3368 if (cond
< 0x0e) { /* not always */
3369 int label_match
= gen_new_label();
3370 label_continue
= gen_new_label();
3371 arm_gen_test_cc(cond
, label_match
);
3373 tcg_tmp
= tcg_temp_new_i64();
3374 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3375 gen_set_nzcv(tcg_tmp
);
3376 tcg_temp_free_i64(tcg_tmp
);
3377 tcg_gen_br(label_continue
);
3378 gen_set_label(label_match
);
3380 /* match, or condition is always */
3382 tcg_y
= new_tmp_a64(s
);
3383 tcg_gen_movi_i64(tcg_y
, y
);
3385 tcg_y
= cpu_reg(s
, y
);
3387 tcg_rn
= cpu_reg(s
, rn
);
3389 tcg_tmp
= tcg_temp_new_i64();
3391 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3393 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3395 tcg_temp_free_i64(tcg_tmp
);
3397 if (cond
< 0x0e) { /* continue */
3398 gen_set_label(label_continue
);
3402 /* C3.5.6 Conditional select
3403 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3404 * +----+----+---+-----------------+------+------+-----+------+------+
3405 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3406 * +----+----+---+-----------------+------+------+-----+------+------+
3408 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3410 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3411 TCGv_i64 tcg_rd
, tcg_src
;
3413 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3414 /* S == 1 or op2<1> == 1 */
3415 unallocated_encoding(s
);
3418 sf
= extract32(insn
, 31, 1);
3419 else_inv
= extract32(insn
, 30, 1);
3420 rm
= extract32(insn
, 16, 5);
3421 cond
= extract32(insn
, 12, 4);
3422 else_inc
= extract32(insn
, 10, 1);
3423 rn
= extract32(insn
, 5, 5);
3424 rd
= extract32(insn
, 0, 5);
3427 /* silly no-op write; until we use movcond we must special-case
3428 * this to avoid a dead temporary across basic blocks.
3433 tcg_rd
= cpu_reg(s
, rd
);
3435 if (cond
>= 0x0e) { /* condition "always" */
3436 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3437 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3439 /* OPTME: we could use movcond here, at the cost of duplicating
3440 * a lot of the arm_gen_test_cc() logic.
3442 int label_match
= gen_new_label();
3443 int label_continue
= gen_new_label();
3445 arm_gen_test_cc(cond
, label_match
);
3447 tcg_src
= cpu_reg(s
, rm
);
3449 if (else_inv
&& else_inc
) {
3450 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3451 } else if (else_inv
) {
3452 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3453 } else if (else_inc
) {
3454 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3456 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3459 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3461 tcg_gen_br(label_continue
);
3463 gen_set_label(label_match
);
3464 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3465 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3467 gen_set_label(label_continue
);
3471 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3472 unsigned int rn
, unsigned int rd
)
3474 TCGv_i64 tcg_rd
, tcg_rn
;
3475 tcg_rd
= cpu_reg(s
, rd
);
3476 tcg_rn
= cpu_reg(s
, rn
);
3479 gen_helper_clz64(tcg_rd
, tcg_rn
);
3481 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3482 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3483 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3484 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3485 tcg_temp_free_i32(tcg_tmp32
);
3489 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3490 unsigned int rn
, unsigned int rd
)
3492 TCGv_i64 tcg_rd
, tcg_rn
;
3493 tcg_rd
= cpu_reg(s
, rd
);
3494 tcg_rn
= cpu_reg(s
, rn
);
3497 gen_helper_cls64(tcg_rd
, tcg_rn
);
3499 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3500 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3501 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3502 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3503 tcg_temp_free_i32(tcg_tmp32
);
3507 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3508 unsigned int rn
, unsigned int rd
)
3510 TCGv_i64 tcg_rd
, tcg_rn
;
3511 tcg_rd
= cpu_reg(s
, rd
);
3512 tcg_rn
= cpu_reg(s
, rn
);
3515 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3517 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3518 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3519 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3520 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3521 tcg_temp_free_i32(tcg_tmp32
);
3525 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3526 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3527 unsigned int rn
, unsigned int rd
)
3530 unallocated_encoding(s
);
3533 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3536 /* C5.6.149 REV with sf==0, opcode==2
3537 * C5.6.151 REV32 (sf==1, opcode==2)
3539 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3540 unsigned int rn
, unsigned int rd
)
3542 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3545 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3546 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3548 /* bswap32_i64 requires zero high word */
3549 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3550 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3551 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3552 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3553 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3555 tcg_temp_free_i64(tcg_tmp
);
3557 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3558 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3562 /* C5.6.150 REV16 (opcode==1) */
3563 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3564 unsigned int rn
, unsigned int rd
)
3566 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3567 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3568 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3570 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3571 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3573 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3574 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3575 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3576 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3579 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3580 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3581 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3582 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3584 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3585 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3586 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3589 tcg_temp_free_i64(tcg_tmp
);
3592 /* C3.5.7 Data-processing (1 source)
3593 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3594 * +----+---+---+-----------------+---------+--------+------+------+
3595 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3596 * +----+---+---+-----------------+---------+--------+------+------+
3598 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3600 unsigned int sf
, opcode
, rn
, rd
;
3602 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3603 unallocated_encoding(s
);
3607 sf
= extract32(insn
, 31, 1);
3608 opcode
= extract32(insn
, 10, 6);
3609 rn
= extract32(insn
, 5, 5);
3610 rd
= extract32(insn
, 0, 5);
3614 handle_rbit(s
, sf
, rn
, rd
);
3617 handle_rev16(s
, sf
, rn
, rd
);
3620 handle_rev32(s
, sf
, rn
, rd
);
3623 handle_rev64(s
, sf
, rn
, rd
);
3626 handle_clz(s
, sf
, rn
, rd
);
3629 handle_cls(s
, sf
, rn
, rd
);
3634 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3635 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3637 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3638 tcg_rd
= cpu_reg(s
, rd
);
3640 if (!sf
&& is_signed
) {
3641 tcg_n
= new_tmp_a64(s
);
3642 tcg_m
= new_tmp_a64(s
);
3643 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3644 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3646 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3647 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3651 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3653 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3656 if (!sf
) { /* zero extend final result */
3657 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3661 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3662 static void handle_shift_reg(DisasContext
*s
,
3663 enum a64_shift_type shift_type
, unsigned int sf
,
3664 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3666 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3667 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3668 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3670 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3671 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3672 tcg_temp_free_i64(tcg_shift
);
3675 /* C3.5.8 Data-processing (2 source)
3676 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3677 * +----+---+---+-----------------+------+--------+------+------+
3678 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3679 * +----+---+---+-----------------+------+--------+------+------+
3681 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3683 unsigned int sf
, rm
, opcode
, rn
, rd
;
3684 sf
= extract32(insn
, 31, 1);
3685 rm
= extract32(insn
, 16, 5);
3686 opcode
= extract32(insn
, 10, 6);
3687 rn
= extract32(insn
, 5, 5);
3688 rd
= extract32(insn
, 0, 5);
3690 if (extract32(insn
, 29, 1)) {
3691 unallocated_encoding(s
);
3697 handle_div(s
, false, sf
, rm
, rn
, rd
);
3700 handle_div(s
, true, sf
, rm
, rn
, rd
);
3703 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3706 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3709 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3712 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3721 case 23: /* CRC32 */
3722 unsupported_encoding(s
, insn
);
3725 unallocated_encoding(s
);
3730 /* C3.5 Data processing - register */
3731 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3733 switch (extract32(insn
, 24, 5)) {
3734 case 0x0a: /* Logical (shifted register) */
3735 disas_logic_reg(s
, insn
);
3737 case 0x0b: /* Add/subtract */
3738 if (insn
& (1 << 21)) { /* (extended register) */
3739 disas_add_sub_ext_reg(s
, insn
);
3741 disas_add_sub_reg(s
, insn
);
3744 case 0x1b: /* Data-processing (3 source) */
3745 disas_data_proc_3src(s
, insn
);
3748 switch (extract32(insn
, 21, 3)) {
3749 case 0x0: /* Add/subtract (with carry) */
3750 disas_adc_sbc(s
, insn
);
3752 case 0x2: /* Conditional compare */
3753 disas_cc(s
, insn
); /* both imm and reg forms */
3755 case 0x4: /* Conditional select */
3756 disas_cond_select(s
, insn
);
3758 case 0x6: /* Data-processing */
3759 if (insn
& (1 << 30)) { /* (1 source) */
3760 disas_data_proc_1src(s
, insn
);
3761 } else { /* (2 source) */
3762 disas_data_proc_2src(s
, insn
);
3766 unallocated_encoding(s
);
3771 unallocated_encoding(s
);
3776 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3777 unsigned int rn
, unsigned int rm
,
3778 bool cmp_with_zero
, bool signal_all_nans
)
3780 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3781 TCGv_ptr fpst
= get_fpstatus_ptr();
3784 TCGv_i64 tcg_vn
, tcg_vm
;
3786 tcg_vn
= read_fp_dreg(s
, rn
);
3787 if (cmp_with_zero
) {
3788 tcg_vm
= tcg_const_i64(0);
3790 tcg_vm
= read_fp_dreg(s
, rm
);
3792 if (signal_all_nans
) {
3793 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3795 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3797 tcg_temp_free_i64(tcg_vn
);
3798 tcg_temp_free_i64(tcg_vm
);
3800 TCGv_i32 tcg_vn
, tcg_vm
;
3802 tcg_vn
= read_fp_sreg(s
, rn
);
3803 if (cmp_with_zero
) {
3804 tcg_vm
= tcg_const_i32(0);
3806 tcg_vm
= read_fp_sreg(s
, rm
);
3808 if (signal_all_nans
) {
3809 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3811 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3813 tcg_temp_free_i32(tcg_vn
);
3814 tcg_temp_free_i32(tcg_vm
);
3817 tcg_temp_free_ptr(fpst
);
3819 gen_set_nzcv(tcg_flags
);
3821 tcg_temp_free_i64(tcg_flags
);
3824 /* C3.6.22 Floating point compare
3825 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
3826 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3827 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
3828 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3830 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
3832 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
3834 mos
= extract32(insn
, 29, 3);
3835 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3836 rm
= extract32(insn
, 16, 5);
3837 op
= extract32(insn
, 14, 2);
3838 rn
= extract32(insn
, 5, 5);
3839 opc
= extract32(insn
, 3, 2);
3840 op2r
= extract32(insn
, 0, 3);
3842 if (mos
|| op
|| op2r
|| type
> 1) {
3843 unallocated_encoding(s
);
3847 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
3850 /* C3.6.23 Floating point conditional compare
3851 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3852 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3853 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
3854 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3856 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
3858 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
3860 int label_continue
= -1;
3862 mos
= extract32(insn
, 29, 3);
3863 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3864 rm
= extract32(insn
, 16, 5);
3865 cond
= extract32(insn
, 12, 4);
3866 rn
= extract32(insn
, 5, 5);
3867 op
= extract32(insn
, 4, 1);
3868 nzcv
= extract32(insn
, 0, 4);
3870 if (mos
|| type
> 1) {
3871 unallocated_encoding(s
);
3875 if (cond
< 0x0e) { /* not always */
3876 int label_match
= gen_new_label();
3877 label_continue
= gen_new_label();
3878 arm_gen_test_cc(cond
, label_match
);
3880 tcg_flags
= tcg_const_i64(nzcv
<< 28);
3881 gen_set_nzcv(tcg_flags
);
3882 tcg_temp_free_i64(tcg_flags
);
3883 tcg_gen_br(label_continue
);
3884 gen_set_label(label_match
);
3887 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
3890 gen_set_label(label_continue
);
3894 /* copy src FP register to dst FP register; type specifies single or double */
3895 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
3898 TCGv_i64 v
= read_fp_dreg(s
, src
);
3899 write_fp_dreg(s
, dst
, v
);
3900 tcg_temp_free_i64(v
);
3902 TCGv_i32 v
= read_fp_sreg(s
, src
);
3903 write_fp_sreg(s
, dst
, v
);
3904 tcg_temp_free_i32(v
);
3908 /* C3.6.24 Floating point conditional select
3909 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
3910 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3911 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
3912 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3914 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
3916 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
3917 int label_continue
= -1;
3919 mos
= extract32(insn
, 29, 3);
3920 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3921 rm
= extract32(insn
, 16, 5);
3922 cond
= extract32(insn
, 12, 4);
3923 rn
= extract32(insn
, 5, 5);
3924 rd
= extract32(insn
, 0, 5);
3926 if (mos
|| type
> 1) {
3927 unallocated_encoding(s
);
3931 if (cond
< 0x0e) { /* not always */
3932 int label_match
= gen_new_label();
3933 label_continue
= gen_new_label();
3934 arm_gen_test_cc(cond
, label_match
);
3936 gen_mov_fp2fp(s
, type
, rd
, rm
);
3937 tcg_gen_br(label_continue
);
3938 gen_set_label(label_match
);
3941 gen_mov_fp2fp(s
, type
, rd
, rn
);
3943 if (cond
< 0x0e) { /* continue */
3944 gen_set_label(label_continue
);
3948 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
3949 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
3955 fpst
= get_fpstatus_ptr();
3956 tcg_op
= read_fp_sreg(s
, rn
);
3957 tcg_res
= tcg_temp_new_i32();
3960 case 0x0: /* FMOV */
3961 tcg_gen_mov_i32(tcg_res
, tcg_op
);
3963 case 0x1: /* FABS */
3964 gen_helper_vfp_abss(tcg_res
, tcg_op
);
3966 case 0x2: /* FNEG */
3967 gen_helper_vfp_negs(tcg_res
, tcg_op
);
3969 case 0x3: /* FSQRT */
3970 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
3972 case 0x8: /* FRINTN */
3973 case 0x9: /* FRINTP */
3974 case 0xa: /* FRINTM */
3975 case 0xb: /* FRINTZ */
3976 case 0xc: /* FRINTA */
3978 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
3980 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3981 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3983 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3984 tcg_temp_free_i32(tcg_rmode
);
3987 case 0xe: /* FRINTX */
3988 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
3990 case 0xf: /* FRINTI */
3991 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3997 write_fp_sreg(s
, rd
, tcg_res
);
3999 tcg_temp_free_ptr(fpst
);
4000 tcg_temp_free_i32(tcg_op
);
4001 tcg_temp_free_i32(tcg_res
);
4004 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4005 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4011 fpst
= get_fpstatus_ptr();
4012 tcg_op
= read_fp_dreg(s
, rn
);
4013 tcg_res
= tcg_temp_new_i64();
4016 case 0x0: /* FMOV */
4017 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4019 case 0x1: /* FABS */
4020 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4022 case 0x2: /* FNEG */
4023 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4025 case 0x3: /* FSQRT */
4026 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4028 case 0x8: /* FRINTN */
4029 case 0x9: /* FRINTP */
4030 case 0xa: /* FRINTM */
4031 case 0xb: /* FRINTZ */
4032 case 0xc: /* FRINTA */
4034 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4036 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4037 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4039 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4040 tcg_temp_free_i32(tcg_rmode
);
4043 case 0xe: /* FRINTX */
4044 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4046 case 0xf: /* FRINTI */
4047 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4053 write_fp_dreg(s
, rd
, tcg_res
);
4055 tcg_temp_free_ptr(fpst
);
4056 tcg_temp_free_i64(tcg_op
);
4057 tcg_temp_free_i64(tcg_res
);
4060 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4061 int rd
, int rn
, int dtype
, int ntype
)
4066 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4068 /* Single to double */
4069 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4070 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4071 write_fp_dreg(s
, rd
, tcg_rd
);
4072 tcg_temp_free_i64(tcg_rd
);
4074 /* Single to half */
4075 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4076 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4077 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4078 write_fp_sreg(s
, rd
, tcg_rd
);
4079 tcg_temp_free_i32(tcg_rd
);
4081 tcg_temp_free_i32(tcg_rn
);
4086 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4087 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4089 /* Double to single */
4090 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4092 /* Double to half */
4093 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4094 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4096 write_fp_sreg(s
, rd
, tcg_rd
);
4097 tcg_temp_free_i32(tcg_rd
);
4098 tcg_temp_free_i64(tcg_rn
);
4103 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4104 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4106 /* Half to single */
4107 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4108 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4109 write_fp_sreg(s
, rd
, tcg_rd
);
4110 tcg_temp_free_i32(tcg_rd
);
4112 /* Half to double */
4113 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4114 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4115 write_fp_dreg(s
, rd
, tcg_rd
);
4116 tcg_temp_free_i64(tcg_rd
);
4118 tcg_temp_free_i32(tcg_rn
);
4126 /* C3.6.25 Floating point data-processing (1 source)
4127 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4128 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4129 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4130 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4132 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4134 int type
= extract32(insn
, 22, 2);
4135 int opcode
= extract32(insn
, 15, 6);
4136 int rn
= extract32(insn
, 5, 5);
4137 int rd
= extract32(insn
, 0, 5);
4140 case 0x4: case 0x5: case 0x7:
4142 /* FCVT between half, single and double precision */
4143 int dtype
= extract32(opcode
, 0, 2);
4144 if (type
== 2 || dtype
== type
) {
4145 unallocated_encoding(s
);
4148 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4154 /* 32-to-32 and 64-to-64 ops */
4157 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4160 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4163 unallocated_encoding(s
);
4167 unallocated_encoding(s
);
4172 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4173 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4174 int rd
, int rn
, int rm
)
4181 tcg_res
= tcg_temp_new_i32();
4182 fpst
= get_fpstatus_ptr();
4183 tcg_op1
= read_fp_sreg(s
, rn
);
4184 tcg_op2
= read_fp_sreg(s
, rm
);
4187 case 0x0: /* FMUL */
4188 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4190 case 0x1: /* FDIV */
4191 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4193 case 0x2: /* FADD */
4194 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4196 case 0x3: /* FSUB */
4197 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4199 case 0x4: /* FMAX */
4200 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4202 case 0x5: /* FMIN */
4203 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4205 case 0x6: /* FMAXNM */
4206 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4208 case 0x7: /* FMINNM */
4209 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4211 case 0x8: /* FNMUL */
4212 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4213 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4217 write_fp_sreg(s
, rd
, tcg_res
);
4219 tcg_temp_free_ptr(fpst
);
4220 tcg_temp_free_i32(tcg_op1
);
4221 tcg_temp_free_i32(tcg_op2
);
4222 tcg_temp_free_i32(tcg_res
);
4225 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4226 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4227 int rd
, int rn
, int rm
)
4234 tcg_res
= tcg_temp_new_i64();
4235 fpst
= get_fpstatus_ptr();
4236 tcg_op1
= read_fp_dreg(s
, rn
);
4237 tcg_op2
= read_fp_dreg(s
, rm
);
4240 case 0x0: /* FMUL */
4241 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4243 case 0x1: /* FDIV */
4244 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4246 case 0x2: /* FADD */
4247 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4249 case 0x3: /* FSUB */
4250 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4252 case 0x4: /* FMAX */
4253 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4255 case 0x5: /* FMIN */
4256 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4258 case 0x6: /* FMAXNM */
4259 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4261 case 0x7: /* FMINNM */
4262 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4264 case 0x8: /* FNMUL */
4265 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4266 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4270 write_fp_dreg(s
, rd
, tcg_res
);
4272 tcg_temp_free_ptr(fpst
);
4273 tcg_temp_free_i64(tcg_op1
);
4274 tcg_temp_free_i64(tcg_op2
);
4275 tcg_temp_free_i64(tcg_res
);
4278 /* C3.6.26 Floating point data-processing (2 source)
4279 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4280 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4281 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4282 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4284 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4286 int type
= extract32(insn
, 22, 2);
4287 int rd
= extract32(insn
, 0, 5);
4288 int rn
= extract32(insn
, 5, 5);
4289 int rm
= extract32(insn
, 16, 5);
4290 int opcode
= extract32(insn
, 12, 4);
4293 unallocated_encoding(s
);
4299 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4302 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4305 unallocated_encoding(s
);
4309 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4310 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4311 int rd
, int rn
, int rm
, int ra
)
4313 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4314 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4315 TCGv_ptr fpst
= get_fpstatus_ptr();
4317 tcg_op1
= read_fp_sreg(s
, rn
);
4318 tcg_op2
= read_fp_sreg(s
, rm
);
4319 tcg_op3
= read_fp_sreg(s
, ra
);
4321 /* These are fused multiply-add, and must be done as one
4322 * floating point operation with no rounding between the
4323 * multiplication and addition steps.
4324 * NB that doing the negations here as separate steps is
4325 * correct : an input NaN should come out with its sign bit
4326 * flipped if it is a negated-input.
4329 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4333 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4336 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4338 write_fp_sreg(s
, rd
, tcg_res
);
4340 tcg_temp_free_ptr(fpst
);
4341 tcg_temp_free_i32(tcg_op1
);
4342 tcg_temp_free_i32(tcg_op2
);
4343 tcg_temp_free_i32(tcg_op3
);
4344 tcg_temp_free_i32(tcg_res
);
4347 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4348 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4349 int rd
, int rn
, int rm
, int ra
)
4351 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4352 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4353 TCGv_ptr fpst
= get_fpstatus_ptr();
4355 tcg_op1
= read_fp_dreg(s
, rn
);
4356 tcg_op2
= read_fp_dreg(s
, rm
);
4357 tcg_op3
= read_fp_dreg(s
, ra
);
4359 /* These are fused multiply-add, and must be done as one
4360 * floating point operation with no rounding between the
4361 * multiplication and addition steps.
4362 * NB that doing the negations here as separate steps is
4363 * correct : an input NaN should come out with its sign bit
4364 * flipped if it is a negated-input.
4367 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4371 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4374 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4376 write_fp_dreg(s
, rd
, tcg_res
);
4378 tcg_temp_free_ptr(fpst
);
4379 tcg_temp_free_i64(tcg_op1
);
4380 tcg_temp_free_i64(tcg_op2
);
4381 tcg_temp_free_i64(tcg_op3
);
4382 tcg_temp_free_i64(tcg_res
);
4385 /* C3.6.27 Floating point data-processing (3 source)
4386 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4387 * +---+---+---+-----------+------+----+------+----+------+------+------+
4388 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4389 * +---+---+---+-----------+------+----+------+----+------+------+------+
4391 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4393 int type
= extract32(insn
, 22, 2);
4394 int rd
= extract32(insn
, 0, 5);
4395 int rn
= extract32(insn
, 5, 5);
4396 int ra
= extract32(insn
, 10, 5);
4397 int rm
= extract32(insn
, 16, 5);
4398 bool o0
= extract32(insn
, 15, 1);
4399 bool o1
= extract32(insn
, 21, 1);
4403 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4406 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4409 unallocated_encoding(s
);
4413 /* C3.6.28 Floating point immediate
4414 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4415 * +---+---+---+-----------+------+---+------------+-------+------+------+
4416 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4417 * +---+---+---+-----------+------+---+------------+-------+------+------+
4419 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4421 int rd
= extract32(insn
, 0, 5);
4422 int imm8
= extract32(insn
, 13, 8);
4423 int is_double
= extract32(insn
, 22, 2);
4427 if (is_double
> 1) {
4428 unallocated_encoding(s
);
4432 /* The imm8 encodes the sign bit, enough bits to represent
4433 * an exponent in the range 01....1xx to 10....0xx,
4434 * and the most significant 4 bits of the mantissa; see
4435 * VFPExpandImm() in the v8 ARM ARM.
4438 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4439 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4440 extract32(imm8
, 0, 6);
4443 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4444 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4445 (extract32(imm8
, 0, 6) << 3);
4449 tcg_res
= tcg_const_i64(imm
);
4450 write_fp_dreg(s
, rd
, tcg_res
);
4451 tcg_temp_free_i64(tcg_res
);
4454 /* Handle floating point <=> fixed point conversions. Note that we can
4455 * also deal with fp <=> integer conversions as a special case (scale == 64)
4456 * OPTME: consider handling that special case specially or at least skipping
4457 * the call to scalbn in the helpers for zero shifts.
4459 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4460 bool itof
, int rmode
, int scale
, int sf
, int type
)
4462 bool is_signed
= !(opcode
& 1);
4463 bool is_double
= type
;
4464 TCGv_ptr tcg_fpstatus
;
4467 tcg_fpstatus
= get_fpstatus_ptr();
4469 tcg_shift
= tcg_const_i32(64 - scale
);
4472 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4474 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4477 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4479 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4482 tcg_int
= tcg_extend
;
4486 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4488 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4489 tcg_shift
, tcg_fpstatus
);
4491 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4492 tcg_shift
, tcg_fpstatus
);
4494 write_fp_dreg(s
, rd
, tcg_double
);
4495 tcg_temp_free_i64(tcg_double
);
4497 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4499 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4500 tcg_shift
, tcg_fpstatus
);
4502 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4503 tcg_shift
, tcg_fpstatus
);
4505 write_fp_sreg(s
, rd
, tcg_single
);
4506 tcg_temp_free_i32(tcg_single
);
4509 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4512 if (extract32(opcode
, 2, 1)) {
4513 /* There are too many rounding modes to all fit into rmode,
4514 * so FCVTA[US] is a special case.
4516 rmode
= FPROUNDING_TIEAWAY
;
4519 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4521 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4524 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4527 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4528 tcg_shift
, tcg_fpstatus
);
4530 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4531 tcg_shift
, tcg_fpstatus
);
4535 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4536 tcg_shift
, tcg_fpstatus
);
4538 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4539 tcg_shift
, tcg_fpstatus
);
4542 tcg_temp_free_i64(tcg_double
);
4544 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4547 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4548 tcg_shift
, tcg_fpstatus
);
4550 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4551 tcg_shift
, tcg_fpstatus
);
4554 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4556 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4557 tcg_shift
, tcg_fpstatus
);
4559 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4560 tcg_shift
, tcg_fpstatus
);
4562 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4563 tcg_temp_free_i32(tcg_dest
);
4565 tcg_temp_free_i32(tcg_single
);
4568 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4569 tcg_temp_free_i32(tcg_rmode
);
4572 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4576 tcg_temp_free_ptr(tcg_fpstatus
);
4577 tcg_temp_free_i32(tcg_shift
);
4580 /* C3.6.29 Floating point <-> fixed point conversions
4581 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4582 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4583 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4584 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4586 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4588 int rd
= extract32(insn
, 0, 5);
4589 int rn
= extract32(insn
, 5, 5);
4590 int scale
= extract32(insn
, 10, 6);
4591 int opcode
= extract32(insn
, 16, 3);
4592 int rmode
= extract32(insn
, 19, 2);
4593 int type
= extract32(insn
, 22, 2);
4594 bool sbit
= extract32(insn
, 29, 1);
4595 bool sf
= extract32(insn
, 31, 1);
4598 if (sbit
|| (type
> 1)
4599 || (!sf
&& scale
< 32)) {
4600 unallocated_encoding(s
);
4604 switch ((rmode
<< 3) | opcode
) {
4605 case 0x2: /* SCVTF */
4606 case 0x3: /* UCVTF */
4609 case 0x18: /* FCVTZS */
4610 case 0x19: /* FCVTZU */
4614 unallocated_encoding(s
);
4618 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4621 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4623 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4624 * without conversion.
4628 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4634 TCGv_i64 tmp
= tcg_temp_new_i64();
4635 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4636 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(rd
, MO_64
));
4637 tcg_gen_movi_i64(tmp
, 0);
4638 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
4639 tcg_temp_free_i64(tmp
);
4645 TCGv_i64 tmp
= tcg_const_i64(0);
4646 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(rd
, MO_64
));
4647 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
4648 tcg_temp_free_i64(tmp
);
4652 /* 64 bit to top half. */
4653 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(rd
));
4657 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4662 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_32
));
4666 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_64
));
4669 /* 64 bits from top half */
4670 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(rn
));
4676 /* C3.6.30 Floating point <-> integer conversions
4677 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4678 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4679 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4680 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4682 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4684 int rd
= extract32(insn
, 0, 5);
4685 int rn
= extract32(insn
, 5, 5);
4686 int opcode
= extract32(insn
, 16, 3);
4687 int rmode
= extract32(insn
, 19, 2);
4688 int type
= extract32(insn
, 22, 2);
4689 bool sbit
= extract32(insn
, 29, 1);
4690 bool sf
= extract32(insn
, 31, 1);
4693 unallocated_encoding(s
);
4699 bool itof
= opcode
& 1;
4702 unallocated_encoding(s
);
4706 switch (sf
<< 3 | type
<< 1 | rmode
) {
4707 case 0x0: /* 32 bit */
4708 case 0xa: /* 64 bit */
4709 case 0xd: /* 64 bit to top half of quad */
4712 /* all other sf/type/rmode combinations are invalid */
4713 unallocated_encoding(s
);
4717 handle_fmov(s
, rd
, rn
, type
, itof
);
4719 /* actual FP conversions */
4720 bool itof
= extract32(opcode
, 1, 1);
4722 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
4723 unallocated_encoding(s
);
4727 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
4731 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
4732 * 31 30 29 28 25 24 0
4733 * +---+---+---+---------+-----------------------------+
4734 * | | 0 | | 1 1 1 1 | |
4735 * +---+---+---+---------+-----------------------------+
4737 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
4739 if (extract32(insn
, 24, 1)) {
4740 /* Floating point data-processing (3 source) */
4741 disas_fp_3src(s
, insn
);
4742 } else if (extract32(insn
, 21, 1) == 0) {
4743 /* Floating point to fixed point conversions */
4744 disas_fp_fixed_conv(s
, insn
);
4746 switch (extract32(insn
, 10, 2)) {
4748 /* Floating point conditional compare */
4749 disas_fp_ccomp(s
, insn
);
4752 /* Floating point data-processing (2 source) */
4753 disas_fp_2src(s
, insn
);
4756 /* Floating point conditional select */
4757 disas_fp_csel(s
, insn
);
4760 switch (ctz32(extract32(insn
, 12, 4))) {
4761 case 0: /* [15:12] == xxx1 */
4762 /* Floating point immediate */
4763 disas_fp_imm(s
, insn
);
4765 case 1: /* [15:12] == xx10 */
4766 /* Floating point compare */
4767 disas_fp_compare(s
, insn
);
4769 case 2: /* [15:12] == x100 */
4770 /* Floating point data-processing (1 source) */
4771 disas_fp_1src(s
, insn
);
4773 case 3: /* [15:12] == 1000 */
4774 unallocated_encoding(s
);
4776 default: /* [15:12] == 0000 */
4777 /* Floating point <-> integer conversions */
4778 disas_fp_int_conv(s
, insn
);
4786 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
4789 /* Extract 64 bits from the middle of two concatenated 64 bit
4790 * vector register slices left:right. The extracted bits start
4791 * at 'pos' bits into the right (least significant) side.
4792 * We return the result in tcg_right, and guarantee not to
4795 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4796 assert(pos
> 0 && pos
< 64);
4798 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
4799 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
4800 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
4802 tcg_temp_free_i64(tcg_tmp
);
4806 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
4807 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4808 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
4809 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4811 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
4813 int is_q
= extract32(insn
, 30, 1);
4814 int op2
= extract32(insn
, 22, 2);
4815 int imm4
= extract32(insn
, 11, 4);
4816 int rm
= extract32(insn
, 16, 5);
4817 int rn
= extract32(insn
, 5, 5);
4818 int rd
= extract32(insn
, 0, 5);
4819 int pos
= imm4
<< 3;
4820 TCGv_i64 tcg_resl
, tcg_resh
;
4822 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
4823 unallocated_encoding(s
);
4827 tcg_resh
= tcg_temp_new_i64();
4828 tcg_resl
= tcg_temp_new_i64();
4830 /* Vd gets bits starting at pos bits into Vm:Vn. This is
4831 * either extracting 128 bits from a 128:128 concatenation, or
4832 * extracting 64 bits from a 64:64 concatenation.
4835 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
4837 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
4838 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4840 tcg_gen_movi_i64(tcg_resh
, 0);
4847 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
4848 EltPosns
*elt
= eltposns
;
4855 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
4857 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
4860 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4861 tcg_hh
= tcg_temp_new_i64();
4862 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
4863 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
4864 tcg_temp_free_i64(tcg_hh
);
4868 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4869 tcg_temp_free_i64(tcg_resl
);
4870 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4871 tcg_temp_free_i64(tcg_resh
);
4875 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
4876 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
4877 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
4878 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
4880 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
4882 int op2
= extract32(insn
, 22, 2);
4883 int is_q
= extract32(insn
, 30, 1);
4884 int rm
= extract32(insn
, 16, 5);
4885 int rn
= extract32(insn
, 5, 5);
4886 int rd
= extract32(insn
, 0, 5);
4887 int is_tblx
= extract32(insn
, 12, 1);
4888 int len
= extract32(insn
, 13, 2);
4889 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
4890 TCGv_i32 tcg_regno
, tcg_numregs
;
4893 unallocated_encoding(s
);
4897 /* This does a table lookup: for every byte element in the input
4898 * we index into a table formed from up to four vector registers,
4899 * and then the output is the result of the lookups. Our helper
4900 * function does the lookup operation for a single 64 bit part of
4903 tcg_resl
= tcg_temp_new_i64();
4904 tcg_resh
= tcg_temp_new_i64();
4907 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4909 tcg_gen_movi_i64(tcg_resl
, 0);
4911 if (is_tblx
&& is_q
) {
4912 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4914 tcg_gen_movi_i64(tcg_resh
, 0);
4917 tcg_idx
= tcg_temp_new_i64();
4918 tcg_regno
= tcg_const_i32(rn
);
4919 tcg_numregs
= tcg_const_i32(len
+ 1);
4920 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
4921 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
4922 tcg_regno
, tcg_numregs
);
4924 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
4925 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
4926 tcg_regno
, tcg_numregs
);
4928 tcg_temp_free_i64(tcg_idx
);
4929 tcg_temp_free_i32(tcg_regno
);
4930 tcg_temp_free_i32(tcg_numregs
);
4932 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4933 tcg_temp_free_i64(tcg_resl
);
4934 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4935 tcg_temp_free_i64(tcg_resh
);
4938 /* C3.6.3 ZIP/UZP/TRN
4939 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
4940 * +---+---+-------------+------+---+------+---+------------------+------+
4941 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
4942 * +---+---+-------------+------+---+------+---+------------------+------+
4944 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
4946 int rd
= extract32(insn
, 0, 5);
4947 int rn
= extract32(insn
, 5, 5);
4948 int rm
= extract32(insn
, 16, 5);
4949 int size
= extract32(insn
, 22, 2);
4950 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
4951 * bit 2 indicates 1 vs 2 variant of the insn.
4953 int opcode
= extract32(insn
, 12, 2);
4954 bool part
= extract32(insn
, 14, 1);
4955 bool is_q
= extract32(insn
, 30, 1);
4956 int esize
= 8 << size
;
4958 int datasize
= is_q
? 128 : 64;
4959 int elements
= datasize
/ esize
;
4960 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
4962 if (opcode
== 0 || (size
== 3 && !is_q
)) {
4963 unallocated_encoding(s
);
4967 tcg_resl
= tcg_const_i64(0);
4968 tcg_resh
= tcg_const_i64(0);
4969 tcg_res
= tcg_temp_new_i64();
4971 for (i
= 0; i
< elements
; i
++) {
4973 case 1: /* UZP1/2 */
4975 int midpoint
= elements
/ 2;
4977 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
4979 read_vec_element(s
, tcg_res
, rm
,
4980 2 * (i
- midpoint
) + part
, size
);
4984 case 2: /* TRN1/2 */
4986 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
4988 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
4991 case 3: /* ZIP1/2 */
4993 int base
= part
* elements
/ 2;
4995 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
4997 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5002 g_assert_not_reached();
5007 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5008 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5010 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5011 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5015 tcg_temp_free_i64(tcg_res
);
5017 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5018 tcg_temp_free_i64(tcg_resl
);
5019 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5020 tcg_temp_free_i64(tcg_resh
);
5023 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5024 int opc
, bool is_min
, TCGv_ptr fpst
)
5026 /* Helper function for disas_simd_across_lanes: do a single precision
5027 * min/max operation on the specified two inputs,
5028 * and return the result in tcg_elt1.
5032 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5034 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5039 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5041 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5046 /* C3.6.4 AdvSIMD across lanes
5047 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5048 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5049 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5050 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5052 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5054 int rd
= extract32(insn
, 0, 5);
5055 int rn
= extract32(insn
, 5, 5);
5056 int size
= extract32(insn
, 22, 2);
5057 int opcode
= extract32(insn
, 12, 5);
5058 bool is_q
= extract32(insn
, 30, 1);
5059 bool is_u
= extract32(insn
, 29, 1);
5061 bool is_min
= false;
5065 TCGv_i64 tcg_res
, tcg_elt
;
5068 case 0x1b: /* ADDV */
5070 unallocated_encoding(s
);
5074 case 0x3: /* SADDLV, UADDLV */
5075 case 0xa: /* SMAXV, UMAXV */
5076 case 0x1a: /* SMINV, UMINV */
5077 if (size
== 3 || (size
== 2 && !is_q
)) {
5078 unallocated_encoding(s
);
5082 case 0xc: /* FMAXNMV, FMINNMV */
5083 case 0xf: /* FMAXV, FMINV */
5084 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5085 unallocated_encoding(s
);
5088 /* Bit 1 of size field encodes min vs max, and actual size is always
5089 * 32 bits: adjust the size variable so following code can rely on it
5091 is_min
= extract32(size
, 1, 1);
5096 unallocated_encoding(s
);
5101 elements
= (is_q
? 128 : 64) / esize
;
5103 tcg_res
= tcg_temp_new_i64();
5104 tcg_elt
= tcg_temp_new_i64();
5106 /* These instructions operate across all lanes of a vector
5107 * to produce a single result. We can guarantee that a 64
5108 * bit intermediate is sufficient:
5109 * + for [US]ADDLV the maximum element size is 32 bits, and
5110 * the result type is 64 bits
5111 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5112 * same as the element size, which is 32 bits at most
5113 * For the integer operations we can choose to work at 64
5114 * or 32 bits and truncate at the end; for simplicity
5115 * we use 64 bits always. The floating point
5116 * ops do require 32 bit intermediates, though.
5119 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5121 for (i
= 1; i
< elements
; i
++) {
5122 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5125 case 0x03: /* SADDLV / UADDLV */
5126 case 0x1b: /* ADDV */
5127 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5129 case 0x0a: /* SMAXV / UMAXV */
5130 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5132 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5134 case 0x1a: /* SMINV / UMINV */
5135 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5137 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5141 g_assert_not_reached();
5146 /* Floating point ops which work on 32 bit (single) intermediates.
5147 * Note that correct NaN propagation requires that we do these
5148 * operations in exactly the order specified by the pseudocode.
5150 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5151 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5152 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5153 TCGv_ptr fpst
= get_fpstatus_ptr();
5155 assert(esize
== 32);
5156 assert(elements
== 4);
5158 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5159 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5160 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5161 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5163 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5165 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5166 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5167 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5168 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5170 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5172 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5174 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5175 tcg_temp_free_i32(tcg_elt1
);
5176 tcg_temp_free_i32(tcg_elt2
);
5177 tcg_temp_free_i32(tcg_elt3
);
5178 tcg_temp_free_ptr(fpst
);
5181 tcg_temp_free_i64(tcg_elt
);
5183 /* Now truncate the result to the width required for the final output */
5184 if (opcode
== 0x03) {
5185 /* SADDLV, UADDLV: result is 2*esize */
5191 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5194 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5197 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5202 g_assert_not_reached();
5205 write_fp_dreg(s
, rd
, tcg_res
);
5206 tcg_temp_free_i64(tcg_res
);
5209 /* C6.3.31 DUP (Element, Vector)
5211 * 31 30 29 21 20 16 15 10 9 5 4 0
5212 * +---+---+-------------------+--------+-------------+------+------+
5213 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5214 * +---+---+-------------------+--------+-------------+------+------+
5216 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5218 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5221 int size
= ctz32(imm5
);
5222 int esize
= 8 << size
;
5223 int elements
= (is_q
? 128 : 64) / esize
;
5227 if (size
> 3 || (size
== 3 && !is_q
)) {
5228 unallocated_encoding(s
);
5232 index
= imm5
>> (size
+ 1);
5234 tmp
= tcg_temp_new_i64();
5235 read_vec_element(s
, tmp
, rn
, index
, size
);
5237 for (i
= 0; i
< elements
; i
++) {
5238 write_vec_element(s
, tmp
, rd
, i
, size
);
5242 clear_vec_high(s
, rd
);
5245 tcg_temp_free_i64(tmp
);
5248 /* C6.3.31 DUP (element, scalar)
5249 * 31 21 20 16 15 10 9 5 4 0
5250 * +-----------------------+--------+-------------+------+------+
5251 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5252 * +-----------------------+--------+-------------+------+------+
5254 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5257 int size
= ctz32(imm5
);
5262 unallocated_encoding(s
);
5266 index
= imm5
>> (size
+ 1);
5268 /* This instruction just extracts the specified element and
5269 * zero-extends it into the bottom of the destination register.
5271 tmp
= tcg_temp_new_i64();
5272 read_vec_element(s
, tmp
, rn
, index
, size
);
5273 write_fp_dreg(s
, rd
, tmp
);
5274 tcg_temp_free_i64(tmp
);
5277 /* C6.3.32 DUP (General)
5279 * 31 30 29 21 20 16 15 10 9 5 4 0
5280 * +---+---+-------------------+--------+-------------+------+------+
5281 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5282 * +---+---+-------------------+--------+-------------+------+------+
5284 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5286 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5289 int size
= ctz32(imm5
);
5290 int esize
= 8 << size
;
5291 int elements
= (is_q
? 128 : 64)/esize
;
5294 if (size
> 3 || ((size
== 3) && !is_q
)) {
5295 unallocated_encoding(s
);
5298 for (i
= 0; i
< elements
; i
++) {
5299 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5302 clear_vec_high(s
, rd
);
5306 /* C6.3.150 INS (Element)
5308 * 31 21 20 16 15 14 11 10 9 5 4 0
5309 * +-----------------------+--------+------------+---+------+------+
5310 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5311 * +-----------------------+--------+------------+---+------+------+
5313 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5314 * index: encoded in imm5<4:size+1>
5316 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5319 int size
= ctz32(imm5
);
5320 int src_index
, dst_index
;
5324 unallocated_encoding(s
);
5327 dst_index
= extract32(imm5
, 1+size
, 5);
5328 src_index
= extract32(imm4
, size
, 4);
5330 tmp
= tcg_temp_new_i64();
5332 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5333 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5335 tcg_temp_free_i64(tmp
);
5339 /* C6.3.151 INS (General)
5341 * 31 21 20 16 15 10 9 5 4 0
5342 * +-----------------------+--------+-------------+------+------+
5343 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5344 * +-----------------------+--------+-------------+------+------+
5346 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5347 * index: encoded in imm5<4:size+1>
5349 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5351 int size
= ctz32(imm5
);
5355 unallocated_encoding(s
);
5359 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5360 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5364 * C6.3.321 UMOV (General)
5365 * C6.3.237 SMOV (General)
5367 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5368 * +---+---+-------------------+--------+-------------+------+------+
5369 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5370 * +---+---+-------------------+--------+-------------+------+------+
5372 * U: unsigned when set
5373 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5375 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5376 int rn
, int rd
, int imm5
)
5378 int size
= ctz32(imm5
);
5382 /* Check for UnallocatedEncodings */
5384 if (size
> 2 || (size
== 2 && !is_q
)) {
5385 unallocated_encoding(s
);
5390 || (size
< 3 && is_q
)
5391 || (size
== 3 && !is_q
)) {
5392 unallocated_encoding(s
);
5396 element
= extract32(imm5
, 1+size
, 4);
5398 tcg_rd
= cpu_reg(s
, rd
);
5399 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5400 if (is_signed
&& !is_q
) {
5401 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5405 /* C3.6.5 AdvSIMD copy
5406 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5407 * +---+---+----+-----------------+------+---+------+---+------+------+
5408 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5409 * +---+---+----+-----------------+------+---+------+---+------+------+
5411 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5413 int rd
= extract32(insn
, 0, 5);
5414 int rn
= extract32(insn
, 5, 5);
5415 int imm4
= extract32(insn
, 11, 4);
5416 int op
= extract32(insn
, 29, 1);
5417 int is_q
= extract32(insn
, 30, 1);
5418 int imm5
= extract32(insn
, 16, 5);
5423 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5425 unallocated_encoding(s
);
5430 /* DUP (element - vector) */
5431 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5435 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5440 handle_simd_insg(s
, rd
, rn
, imm5
);
5442 unallocated_encoding(s
);
5447 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5448 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5451 unallocated_encoding(s
);
5457 /* C3.6.6 AdvSIMD modified immediate
5458 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5459 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5460 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5461 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5463 * There are a number of operations that can be carried out here:
5464 * MOVI - move (shifted) imm into register
5465 * MVNI - move inverted (shifted) imm into register
5466 * ORR - bitwise OR of (shifted) imm with register
5467 * BIC - bitwise clear of (shifted) imm with register
5469 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5471 int rd
= extract32(insn
, 0, 5);
5472 int cmode
= extract32(insn
, 12, 4);
5473 int cmode_3_1
= extract32(cmode
, 1, 3);
5474 int cmode_0
= extract32(cmode
, 0, 1);
5475 int o2
= extract32(insn
, 11, 1);
5476 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5477 bool is_neg
= extract32(insn
, 29, 1);
5478 bool is_q
= extract32(insn
, 30, 1);
5480 TCGv_i64 tcg_rd
, tcg_imm
;
5483 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5484 unallocated_encoding(s
);
5488 /* See AdvSIMDExpandImm() in ARM ARM */
5489 switch (cmode_3_1
) {
5490 case 0: /* Replicate(Zeros(24):imm8, 2) */
5491 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5492 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5493 case 3: /* Replicate(imm8:Zeros(24), 2) */
5495 int shift
= cmode_3_1
* 8;
5496 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5499 case 4: /* Replicate(Zeros(8):imm8, 4) */
5500 case 5: /* Replicate(imm8:Zeros(8), 4) */
5502 int shift
= (cmode_3_1
& 0x1) * 8;
5503 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5508 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5509 imm
= (abcdefgh
<< 16) | 0xffff;
5511 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5512 imm
= (abcdefgh
<< 8) | 0xff;
5514 imm
= bitfield_replicate(imm
, 32);
5517 if (!cmode_0
&& !is_neg
) {
5518 imm
= bitfield_replicate(abcdefgh
, 8);
5519 } else if (!cmode_0
&& is_neg
) {
5522 for (i
= 0; i
< 8; i
++) {
5523 if ((abcdefgh
) & (1 << i
)) {
5524 imm
|= 0xffULL
<< (i
* 8);
5527 } else if (cmode_0
) {
5529 imm
= (abcdefgh
& 0x3f) << 48;
5530 if (abcdefgh
& 0x80) {
5531 imm
|= 0x8000000000000000ULL
;
5533 if (abcdefgh
& 0x40) {
5534 imm
|= 0x3fc0000000000000ULL
;
5536 imm
|= 0x4000000000000000ULL
;
5539 imm
= (abcdefgh
& 0x3f) << 19;
5540 if (abcdefgh
& 0x80) {
5543 if (abcdefgh
& 0x40) {
5554 if (cmode_3_1
!= 7 && is_neg
) {
5558 tcg_imm
= tcg_const_i64(imm
);
5559 tcg_rd
= new_tmp_a64(s
);
5561 for (i
= 0; i
< 2; i
++) {
5562 int foffs
= i
? fp_reg_hi_offset(rd
) : fp_reg_offset(rd
, MO_64
);
5564 if (i
== 1 && !is_q
) {
5565 /* non-quad ops clear high half of vector */
5566 tcg_gen_movi_i64(tcg_rd
, 0);
5567 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5568 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5571 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5574 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5578 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5580 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5583 tcg_temp_free_i64(tcg_imm
);
5586 /* C3.6.7 AdvSIMD scalar copy
5587 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5588 * +-----+----+-----------------+------+---+------+---+------+------+
5589 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5590 * +-----+----+-----------------+------+---+------+---+------+------+
5592 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5594 int rd
= extract32(insn
, 0, 5);
5595 int rn
= extract32(insn
, 5, 5);
5596 int imm4
= extract32(insn
, 11, 4);
5597 int imm5
= extract32(insn
, 16, 5);
5598 int op
= extract32(insn
, 29, 1);
5600 if (op
!= 0 || imm4
!= 0) {
5601 unallocated_encoding(s
);
5605 /* DUP (element, scalar) */
5606 handle_simd_dupes(s
, rd
, rn
, imm5
);
5609 /* C3.6.8 AdvSIMD scalar pairwise
5610 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5611 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5612 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5613 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5615 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5617 int u
= extract32(insn
, 29, 1);
5618 int size
= extract32(insn
, 22, 2);
5619 int opcode
= extract32(insn
, 12, 5);
5620 int rn
= extract32(insn
, 5, 5);
5621 int rd
= extract32(insn
, 0, 5);
5624 /* For some ops (the FP ones), size[1] is part of the encoding.
5625 * For ADDP strictly it is not but size[1] is always 1 for valid
5628 opcode
|= (extract32(size
, 1, 1) << 5);
5631 case 0x3b: /* ADDP */
5632 if (u
|| size
!= 3) {
5633 unallocated_encoding(s
);
5636 TCGV_UNUSED_PTR(fpst
);
5638 case 0xc: /* FMAXNMP */
5639 case 0xd: /* FADDP */
5640 case 0xf: /* FMAXP */
5641 case 0x2c: /* FMINNMP */
5642 case 0x2f: /* FMINP */
5643 /* FP op, size[0] is 32 or 64 bit */
5645 unallocated_encoding(s
);
5648 size
= extract32(size
, 0, 1) ? 3 : 2;
5649 fpst
= get_fpstatus_ptr();
5652 unallocated_encoding(s
);
5657 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5658 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5659 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5661 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5662 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
5665 case 0x3b: /* ADDP */
5666 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
5668 case 0xc: /* FMAXNMP */
5669 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5671 case 0xd: /* FADDP */
5672 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5674 case 0xf: /* FMAXP */
5675 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5677 case 0x2c: /* FMINNMP */
5678 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5680 case 0x2f: /* FMINP */
5681 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5684 g_assert_not_reached();
5687 write_fp_dreg(s
, rd
, tcg_res
);
5689 tcg_temp_free_i64(tcg_op1
);
5690 tcg_temp_free_i64(tcg_op2
);
5691 tcg_temp_free_i64(tcg_res
);
5693 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
5694 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
5695 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5697 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
5698 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
5701 case 0xc: /* FMAXNMP */
5702 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5704 case 0xd: /* FADDP */
5705 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5707 case 0xf: /* FMAXP */
5708 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5710 case 0x2c: /* FMINNMP */
5711 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5713 case 0x2f: /* FMINP */
5714 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5717 g_assert_not_reached();
5720 write_fp_sreg(s
, rd
, tcg_res
);
5722 tcg_temp_free_i32(tcg_op1
);
5723 tcg_temp_free_i32(tcg_op2
);
5724 tcg_temp_free_i32(tcg_res
);
5727 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
5728 tcg_temp_free_ptr(fpst
);
5733 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
5735 * This code is handles the common shifting code and is used by both
5736 * the vector and scalar code.
5738 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5739 TCGv_i64 tcg_rnd
, bool accumulate
,
5740 bool is_u
, int size
, int shift
)
5742 bool extended_result
= false;
5743 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
5745 TCGv_i64 tcg_src_hi
;
5747 if (round
&& size
== 3) {
5748 extended_result
= true;
5749 ext_lshift
= 64 - shift
;
5750 tcg_src_hi
= tcg_temp_new_i64();
5751 } else if (shift
== 64) {
5752 if (!accumulate
&& is_u
) {
5753 /* result is zero */
5754 tcg_gen_movi_i64(tcg_res
, 0);
5759 /* Deal with the rounding step */
5761 if (extended_result
) {
5762 TCGv_i64 tcg_zero
= tcg_const_i64(0);
5764 /* take care of sign extending tcg_res */
5765 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
5766 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5767 tcg_src
, tcg_src_hi
,
5770 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5774 tcg_temp_free_i64(tcg_zero
);
5776 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
5780 /* Now do the shift right */
5781 if (round
&& extended_result
) {
5782 /* extended case, >64 bit precision required */
5783 if (ext_lshift
== 0) {
5784 /* special case, only high bits matter */
5785 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
5787 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5788 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
5789 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
5794 /* essentially shifting in 64 zeros */
5795 tcg_gen_movi_i64(tcg_src
, 0);
5797 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5801 /* effectively extending the sign-bit */
5802 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
5804 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
5810 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
5812 tcg_gen_mov_i64(tcg_res
, tcg_src
);
5815 if (extended_result
) {
5816 tcg_temp_free_i64(tcg_src_hi
);
5820 /* Common SHL/SLI - Shift left with an optional insert */
5821 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5822 bool insert
, int shift
)
5824 if (insert
) { /* SLI */
5825 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
5827 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
5831 /* SRI: shift right with insert */
5832 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5833 int size
, int shift
)
5835 int esize
= 8 << size
;
5837 /* shift count same as element size is valid but does nothing;
5838 * special case to avoid potential shift by 64.
5840 if (shift
!= esize
) {
5841 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5842 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
5846 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
5847 static void handle_scalar_simd_shri(DisasContext
*s
,
5848 bool is_u
, int immh
, int immb
,
5849 int opcode
, int rn
, int rd
)
5852 int immhb
= immh
<< 3 | immb
;
5853 int shift
= 2 * (8 << size
) - immhb
;
5854 bool accumulate
= false;
5856 bool insert
= false;
5861 if (!extract32(immh
, 3, 1)) {
5862 unallocated_encoding(s
);
5867 case 0x02: /* SSRA / USRA (accumulate) */
5870 case 0x04: /* SRSHR / URSHR (rounding) */
5873 case 0x06: /* SRSRA / URSRA (accum + rounding) */
5874 accumulate
= round
= true;
5876 case 0x08: /* SRI */
5882 uint64_t round_const
= 1ULL << (shift
- 1);
5883 tcg_round
= tcg_const_i64(round_const
);
5885 TCGV_UNUSED_I64(tcg_round
);
5888 tcg_rn
= read_fp_dreg(s
, rn
);
5889 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
5892 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
5894 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
5895 accumulate
, is_u
, size
, shift
);
5898 write_fp_dreg(s
, rd
, tcg_rd
);
5900 tcg_temp_free_i64(tcg_rn
);
5901 tcg_temp_free_i64(tcg_rd
);
5903 tcg_temp_free_i64(tcg_round
);
5907 /* SHL/SLI - Scalar shift left */
5908 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
5909 int immh
, int immb
, int opcode
,
5912 int size
= 32 - clz32(immh
) - 1;
5913 int immhb
= immh
<< 3 | immb
;
5914 int shift
= immhb
- (8 << size
);
5915 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
5916 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
5918 if (!extract32(immh
, 3, 1)) {
5919 unallocated_encoding(s
);
5923 tcg_rn
= read_fp_dreg(s
, rn
);
5924 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
5926 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
5928 write_fp_dreg(s
, rd
, tcg_rd
);
5930 tcg_temp_free_i64(tcg_rn
);
5931 tcg_temp_free_i64(tcg_rd
);
5934 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
5935 * (signed/unsigned) narrowing */
5936 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
5937 bool is_u_shift
, bool is_u_narrow
,
5938 int immh
, int immb
, int opcode
,
5941 int immhb
= immh
<< 3 | immb
;
5942 int size
= 32 - clz32(immh
) - 1;
5943 int esize
= 8 << size
;
5944 int shift
= (2 * esize
) - immhb
;
5945 int elements
= is_scalar
? 1 : (64 / esize
);
5946 bool round
= extract32(opcode
, 0, 1);
5947 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
5948 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
5949 TCGv_i32 tcg_rd_narrowed
;
5952 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
5953 { gen_helper_neon_narrow_sat_s8
,
5954 gen_helper_neon_unarrow_sat8
},
5955 { gen_helper_neon_narrow_sat_s16
,
5956 gen_helper_neon_unarrow_sat16
},
5957 { gen_helper_neon_narrow_sat_s32
,
5958 gen_helper_neon_unarrow_sat32
},
5961 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
5962 gen_helper_neon_narrow_sat_u8
,
5963 gen_helper_neon_narrow_sat_u16
,
5964 gen_helper_neon_narrow_sat_u32
,
5967 NeonGenNarrowEnvFn
*narrowfn
;
5973 if (extract32(immh
, 3, 1)) {
5974 unallocated_encoding(s
);
5979 narrowfn
= unsigned_narrow_fns
[size
];
5981 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
5984 tcg_rn
= tcg_temp_new_i64();
5985 tcg_rd
= tcg_temp_new_i64();
5986 tcg_rd_narrowed
= tcg_temp_new_i32();
5987 tcg_final
= tcg_const_i64(0);
5990 uint64_t round_const
= 1ULL << (shift
- 1);
5991 tcg_round
= tcg_const_i64(round_const
);
5993 TCGV_UNUSED_I64(tcg_round
);
5996 for (i
= 0; i
< elements
; i
++) {
5997 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
5998 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
5999 false, is_u_shift
, size
+1, shift
);
6000 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6001 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6002 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6006 clear_vec_high(s
, rd
);
6007 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6009 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6013 tcg_temp_free_i64(tcg_round
);
6015 tcg_temp_free_i64(tcg_rn
);
6016 tcg_temp_free_i64(tcg_rd
);
6017 tcg_temp_free_i32(tcg_rd_narrowed
);
6018 tcg_temp_free_i64(tcg_final
);
6022 /* Common vector code for handling integer to FP conversion */
6023 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6024 int elements
, int is_signed
,
6025 int fracbits
, int size
)
6027 bool is_double
= size
== 3 ? true : false;
6028 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6029 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6030 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6031 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6034 for (pass
= 0; pass
< elements
; pass
++) {
6035 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6038 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6040 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6041 tcg_shift
, tcg_fpst
);
6043 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6044 tcg_shift
, tcg_fpst
);
6046 if (elements
== 1) {
6047 write_fp_dreg(s
, rd
, tcg_double
);
6049 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6051 tcg_temp_free_i64(tcg_double
);
6053 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6055 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6056 tcg_shift
, tcg_fpst
);
6058 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6059 tcg_shift
, tcg_fpst
);
6061 if (elements
== 1) {
6062 write_fp_sreg(s
, rd
, tcg_single
);
6064 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6066 tcg_temp_free_i32(tcg_single
);
6070 if (!is_double
&& elements
== 2) {
6071 clear_vec_high(s
, rd
);
6074 tcg_temp_free_i64(tcg_int
);
6075 tcg_temp_free_ptr(tcg_fpst
);
6076 tcg_temp_free_i32(tcg_shift
);
6079 /* UCVTF/SCVTF - Integer to FP conversion */
6080 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6081 bool is_q
, bool is_u
,
6082 int immh
, int immb
, int opcode
,
6085 bool is_double
= extract32(immh
, 3, 1);
6086 int size
= is_double
? MO_64
: MO_32
;
6088 int immhb
= immh
<< 3 | immb
;
6089 int fracbits
= (is_double
? 128 : 64) - immhb
;
6091 if (!extract32(immh
, 2, 2)) {
6092 unallocated_encoding(s
);
6099 elements
= is_double
? 2 : is_q
? 4 : 2;
6100 if (is_double
&& !is_q
) {
6101 unallocated_encoding(s
);
6105 /* immh == 0 would be a failure of the decode logic */
6108 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6111 /* C3.6.9 AdvSIMD scalar shift by immediate
6112 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6113 * +-----+---+-------------+------+------+--------+---+------+------+
6114 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6115 * +-----+---+-------------+------+------+--------+---+------+------+
6117 * This is the scalar version so it works on a fixed sized registers
6119 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6121 int rd
= extract32(insn
, 0, 5);
6122 int rn
= extract32(insn
, 5, 5);
6123 int opcode
= extract32(insn
, 11, 5);
6124 int immb
= extract32(insn
, 16, 3);
6125 int immh
= extract32(insn
, 19, 4);
6126 bool is_u
= extract32(insn
, 29, 1);
6129 unallocated_encoding(s
);
6134 case 0x08: /* SRI */
6136 unallocated_encoding(s
);
6140 case 0x00: /* SSHR / USHR */
6141 case 0x02: /* SSRA / USRA */
6142 case 0x04: /* SRSHR / URSHR */
6143 case 0x06: /* SRSRA / URSRA */
6144 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6146 case 0x0a: /* SHL / SLI */
6147 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6149 case 0x1c: /* SCVTF, UCVTF */
6150 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6153 case 0x10: /* SQSHRUN, SQSHRUN2 */
6154 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6156 unallocated_encoding(s
);
6159 handle_vec_simd_sqshrn(s
, true, false, false, true,
6160 immh
, immb
, opcode
, rn
, rd
);
6162 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6163 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6164 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6165 immh
, immb
, opcode
, rn
, rd
);
6167 case 0xc: /* SQSHLU */
6168 case 0xe: /* SQSHL, UQSHL */
6169 case 0x1f: /* FCVTZS, FCVTZU */
6170 unsupported_encoding(s
, insn
);
6173 unallocated_encoding(s
);
6178 /* C3.6.10 AdvSIMD scalar three different
6179 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6180 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6181 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6182 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6184 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6186 bool is_u
= extract32(insn
, 29, 1);
6187 int size
= extract32(insn
, 22, 2);
6188 int opcode
= extract32(insn
, 12, 4);
6189 int rm
= extract32(insn
, 16, 5);
6190 int rn
= extract32(insn
, 5, 5);
6191 int rd
= extract32(insn
, 0, 5);
6194 unallocated_encoding(s
);
6199 case 0x9: /* SQDMLAL, SQDMLAL2 */
6200 case 0xb: /* SQDMLSL, SQDMLSL2 */
6201 case 0xd: /* SQDMULL, SQDMULL2 */
6202 if (size
== 0 || size
== 3) {
6203 unallocated_encoding(s
);
6208 unallocated_encoding(s
);
6213 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6214 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6215 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6217 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6218 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6220 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6221 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6224 case 0xd: /* SQDMULL, SQDMULL2 */
6226 case 0xb: /* SQDMLSL, SQDMLSL2 */
6227 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6229 case 0x9: /* SQDMLAL, SQDMLAL2 */
6230 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6231 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6235 g_assert_not_reached();
6238 write_fp_dreg(s
, rd
, tcg_res
);
6240 tcg_temp_free_i64(tcg_op1
);
6241 tcg_temp_free_i64(tcg_op2
);
6242 tcg_temp_free_i64(tcg_res
);
6244 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6245 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6246 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6248 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6249 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6251 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6252 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6255 case 0xd: /* SQDMULL, SQDMULL2 */
6257 case 0xb: /* SQDMLSL, SQDMLSL2 */
6258 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6260 case 0x9: /* SQDMLAL, SQDMLAL2 */
6262 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6263 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6264 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6266 tcg_temp_free_i64(tcg_op3
);
6270 g_assert_not_reached();
6273 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6274 write_fp_dreg(s
, rd
, tcg_res
);
6276 tcg_temp_free_i32(tcg_op1
);
6277 tcg_temp_free_i32(tcg_op2
);
6278 tcg_temp_free_i64(tcg_res
);
6282 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6283 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6285 /* Handle 64x64->64 opcodes which are shared between the scalar
6286 * and vector 3-same groups. We cover every opcode where size == 3
6287 * is valid in either the three-reg-same (integer, not pairwise)
6288 * or scalar-three-reg-same groups. (Some opcodes are not yet
6294 case 0x1: /* SQADD */
6296 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6298 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6301 case 0x5: /* SQSUB */
6303 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6305 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6308 case 0x6: /* CMGT, CMHI */
6309 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6310 * We implement this using setcond (test) and then negating.
6312 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6314 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6315 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6317 case 0x7: /* CMGE, CMHS */
6318 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6320 case 0x11: /* CMTST, CMEQ */
6325 /* CMTST : test is "if (X & Y != 0)". */
6326 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6327 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6328 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6330 case 0x8: /* SSHL, USHL */
6332 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6334 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6337 case 0x9: /* SQSHL, UQSHL */
6339 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6341 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6344 case 0xa: /* SRSHL, URSHL */
6346 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6348 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6351 case 0xb: /* SQRSHL, UQRSHL */
6353 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6355 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6358 case 0x10: /* ADD, SUB */
6360 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6362 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6366 g_assert_not_reached();
6370 /* Handle the 3-same-operands float operations; shared by the scalar
6371 * and vector encodings. The caller must filter out any encodings
6372 * not allocated for the encoding it is dealing with.
6374 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6375 int fpopcode
, int rd
, int rn
, int rm
)
6378 TCGv_ptr fpst
= get_fpstatus_ptr();
6380 for (pass
= 0; pass
< elements
; pass
++) {
6383 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6384 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6385 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6387 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6388 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6391 case 0x39: /* FMLS */
6392 /* As usual for ARM, separate negation for fused multiply-add */
6393 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6395 case 0x19: /* FMLA */
6396 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6397 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6400 case 0x18: /* FMAXNM */
6401 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6403 case 0x1a: /* FADD */
6404 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6406 case 0x1b: /* FMULX */
6407 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6409 case 0x1c: /* FCMEQ */
6410 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6412 case 0x1e: /* FMAX */
6413 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6415 case 0x1f: /* FRECPS */
6416 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6418 case 0x38: /* FMINNM */
6419 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6421 case 0x3a: /* FSUB */
6422 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6424 case 0x3e: /* FMIN */
6425 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6427 case 0x3f: /* FRSQRTS */
6428 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6430 case 0x5b: /* FMUL */
6431 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6433 case 0x5c: /* FCMGE */
6434 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6436 case 0x5d: /* FACGE */
6437 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6439 case 0x5f: /* FDIV */
6440 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6442 case 0x7a: /* FABD */
6443 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6444 gen_helper_vfp_absd(tcg_res
, tcg_res
);
6446 case 0x7c: /* FCMGT */
6447 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6449 case 0x7d: /* FACGT */
6450 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6453 g_assert_not_reached();
6456 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6458 tcg_temp_free_i64(tcg_res
);
6459 tcg_temp_free_i64(tcg_op1
);
6460 tcg_temp_free_i64(tcg_op2
);
6463 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6464 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6465 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6467 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
6468 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
6471 case 0x39: /* FMLS */
6472 /* As usual for ARM, separate negation for fused multiply-add */
6473 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6475 case 0x19: /* FMLA */
6476 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6477 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
6480 case 0x1a: /* FADD */
6481 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6483 case 0x1b: /* FMULX */
6484 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6486 case 0x1c: /* FCMEQ */
6487 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6489 case 0x1e: /* FMAX */
6490 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6492 case 0x1f: /* FRECPS */
6493 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6495 case 0x18: /* FMAXNM */
6496 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6498 case 0x38: /* FMINNM */
6499 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6501 case 0x3a: /* FSUB */
6502 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6504 case 0x3e: /* FMIN */
6505 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6507 case 0x3f: /* FRSQRTS */
6508 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6510 case 0x5b: /* FMUL */
6511 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6513 case 0x5c: /* FCMGE */
6514 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6516 case 0x5d: /* FACGE */
6517 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6519 case 0x5f: /* FDIV */
6520 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6522 case 0x7a: /* FABD */
6523 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6524 gen_helper_vfp_abss(tcg_res
, tcg_res
);
6526 case 0x7c: /* FCMGT */
6527 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6529 case 0x7d: /* FACGT */
6530 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6533 g_assert_not_reached();
6536 if (elements
== 1) {
6537 /* scalar single so clear high part */
6538 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6540 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
6541 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
6542 tcg_temp_free_i64(tcg_tmp
);
6544 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6547 tcg_temp_free_i32(tcg_res
);
6548 tcg_temp_free_i32(tcg_op1
);
6549 tcg_temp_free_i32(tcg_op2
);
6553 tcg_temp_free_ptr(fpst
);
6555 if ((elements
<< size
) < 4) {
6556 /* scalar, or non-quad vector op */
6557 clear_vec_high(s
, rd
);
6561 /* C3.6.11 AdvSIMD scalar three same
6562 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
6563 * +-----+---+-----------+------+---+------+--------+---+------+------+
6564 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
6565 * +-----+---+-----------+------+---+------+--------+---+------+------+
6567 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
6569 int rd
= extract32(insn
, 0, 5);
6570 int rn
= extract32(insn
, 5, 5);
6571 int opcode
= extract32(insn
, 11, 5);
6572 int rm
= extract32(insn
, 16, 5);
6573 int size
= extract32(insn
, 22, 2);
6574 bool u
= extract32(insn
, 29, 1);
6577 if (opcode
>= 0x18) {
6578 /* Floating point: U, size[1] and opcode indicate operation */
6579 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
6581 case 0x1b: /* FMULX */
6582 case 0x1f: /* FRECPS */
6583 case 0x3f: /* FRSQRTS */
6584 case 0x5d: /* FACGE */
6585 case 0x7d: /* FACGT */
6586 case 0x1c: /* FCMEQ */
6587 case 0x5c: /* FCMGE */
6588 case 0x7c: /* FCMGT */
6589 case 0x7a: /* FABD */
6592 unallocated_encoding(s
);
6596 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
6601 case 0x1: /* SQADD, UQADD */
6602 case 0x5: /* SQSUB, UQSUB */
6603 case 0x9: /* SQSHL, UQSHL */
6604 case 0xb: /* SQRSHL, UQRSHL */
6606 case 0x8: /* SSHL, USHL */
6607 case 0xa: /* SRSHL, URSHL */
6608 case 0x6: /* CMGT, CMHI */
6609 case 0x7: /* CMGE, CMHS */
6610 case 0x11: /* CMTST, CMEQ */
6611 case 0x10: /* ADD, SUB (vector) */
6613 unallocated_encoding(s
);
6617 case 0x16: /* SQDMULH, SQRDMULH (vector) */
6618 if (size
!= 1 && size
!= 2) {
6619 unallocated_encoding(s
);
6624 unallocated_encoding(s
);
6628 tcg_rd
= tcg_temp_new_i64();
6631 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6632 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
6634 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
6635 tcg_temp_free_i64(tcg_rn
);
6636 tcg_temp_free_i64(tcg_rm
);
6638 /* Do a single operation on the lowest element in the vector.
6639 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
6640 * no side effects for all these operations.
6641 * OPTME: special-purpose helpers would avoid doing some
6642 * unnecessary work in the helper for the 8 and 16 bit cases.
6644 NeonGenTwoOpEnvFn
*genenvfn
;
6645 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
6646 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
6647 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
6649 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
6650 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
6653 case 0x1: /* SQADD, UQADD */
6655 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6656 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
6657 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
6658 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
6660 genenvfn
= fns
[size
][u
];
6663 case 0x5: /* SQSUB, UQSUB */
6665 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6666 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
6667 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
6668 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
6670 genenvfn
= fns
[size
][u
];
6673 case 0x9: /* SQSHL, UQSHL */
6675 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6676 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
6677 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
6678 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
6680 genenvfn
= fns
[size
][u
];
6683 case 0xb: /* SQRSHL, UQRSHL */
6685 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6686 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
6687 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
6688 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
6690 genenvfn
= fns
[size
][u
];
6693 case 0x16: /* SQDMULH, SQRDMULH */
6695 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
6696 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
6697 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
6699 assert(size
== 1 || size
== 2);
6700 genenvfn
= fns
[size
- 1][u
];
6704 g_assert_not_reached();
6707 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
6708 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
6709 tcg_temp_free_i32(tcg_rd32
);
6710 tcg_temp_free_i32(tcg_rn
);
6711 tcg_temp_free_i32(tcg_rm
);
6714 write_fp_dreg(s
, rd
, tcg_rd
);
6716 tcg_temp_free_i64(tcg_rd
);
6719 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
6720 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
6721 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
6723 /* Handle 64->64 opcodes which are shared between the scalar and
6724 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
6725 * is valid in either group and also the double-precision fp ops.
6726 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
6732 case 0x4: /* CLS, CLZ */
6734 gen_helper_clz64(tcg_rd
, tcg_rn
);
6736 gen_helper_cls64(tcg_rd
, tcg_rn
);
6740 /* This opcode is shared with CNT and RBIT but we have earlier
6741 * enforced that size == 3 if and only if this is the NOT insn.
6743 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
6745 case 0xa: /* CMLT */
6746 /* 64 bit integer comparison against zero, result is
6747 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
6752 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
6753 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6755 case 0x8: /* CMGT, CMGE */
6756 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
6758 case 0x9: /* CMEQ, CMLE */
6759 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
6761 case 0xb: /* ABS, NEG */
6763 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
6765 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6766 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
6767 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
6769 tcg_temp_free_i64(tcg_zero
);
6772 case 0x2f: /* FABS */
6773 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
6775 case 0x6f: /* FNEG */
6776 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
6778 case 0x7f: /* FSQRT */
6779 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
6781 case 0x1a: /* FCVTNS */
6782 case 0x1b: /* FCVTMS */
6783 case 0x1c: /* FCVTAS */
6784 case 0x3a: /* FCVTPS */
6785 case 0x3b: /* FCVTZS */
6787 TCGv_i32 tcg_shift
= tcg_const_i32(0);
6788 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
6789 tcg_temp_free_i32(tcg_shift
);
6792 case 0x5a: /* FCVTNU */
6793 case 0x5b: /* FCVTMU */
6794 case 0x5c: /* FCVTAU */
6795 case 0x7a: /* FCVTPU */
6796 case 0x7b: /* FCVTZU */
6798 TCGv_i32 tcg_shift
= tcg_const_i32(0);
6799 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
6800 tcg_temp_free_i32(tcg_shift
);
6803 case 0x18: /* FRINTN */
6804 case 0x19: /* FRINTM */
6805 case 0x38: /* FRINTP */
6806 case 0x39: /* FRINTZ */
6807 case 0x58: /* FRINTA */
6808 case 0x79: /* FRINTI */
6809 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
6811 case 0x59: /* FRINTX */
6812 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
6815 g_assert_not_reached();
6819 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
6820 bool is_scalar
, bool is_u
, bool is_q
,
6821 int size
, int rn
, int rd
)
6823 bool is_double
= (size
== 3);
6824 TCGv_ptr fpst
= get_fpstatus_ptr();
6827 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6828 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6829 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6830 NeonGenTwoDoubleOPFn
*genfn
;
6835 case 0x2e: /* FCMLT (zero) */
6838 case 0x2c: /* FCMGT (zero) */
6839 genfn
= gen_helper_neon_cgt_f64
;
6841 case 0x2d: /* FCMEQ (zero) */
6842 genfn
= gen_helper_neon_ceq_f64
;
6844 case 0x6d: /* FCMLE (zero) */
6847 case 0x6c: /* FCMGE (zero) */
6848 genfn
= gen_helper_neon_cge_f64
;
6851 g_assert_not_reached();
6854 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
6855 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6857 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
6859 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
6861 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6864 clear_vec_high(s
, rd
);
6867 tcg_temp_free_i64(tcg_res
);
6868 tcg_temp_free_i64(tcg_zero
);
6869 tcg_temp_free_i64(tcg_op
);
6871 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6872 TCGv_i32 tcg_zero
= tcg_const_i32(0);
6873 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6874 NeonGenTwoSingleOPFn
*genfn
;
6876 int pass
, maxpasses
;
6879 case 0x2e: /* FCMLT (zero) */
6882 case 0x2c: /* FCMGT (zero) */
6883 genfn
= gen_helper_neon_cgt_f32
;
6885 case 0x2d: /* FCMEQ (zero) */
6886 genfn
= gen_helper_neon_ceq_f32
;
6888 case 0x6d: /* FCMLE (zero) */
6891 case 0x6c: /* FCMGE (zero) */
6892 genfn
= gen_helper_neon_cge_f32
;
6895 g_assert_not_reached();
6901 maxpasses
= is_q
? 4 : 2;
6904 for (pass
= 0; pass
< maxpasses
; pass
++) {
6905 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6907 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
6909 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
6912 write_fp_sreg(s
, rd
, tcg_res
);
6914 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6917 tcg_temp_free_i32(tcg_res
);
6918 tcg_temp_free_i32(tcg_zero
);
6919 tcg_temp_free_i32(tcg_op
);
6920 if (!is_q
&& !is_scalar
) {
6921 clear_vec_high(s
, rd
);
6925 tcg_temp_free_ptr(fpst
);
6928 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
6929 bool is_scalar
, bool is_u
, bool is_q
,
6930 int size
, int rn
, int rd
)
6932 bool is_double
= (size
== 3);
6933 TCGv_ptr fpst
= get_fpstatus_ptr();
6936 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6937 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6940 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
6941 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6943 case 0x3f: /* FRECPX */
6944 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
6947 g_assert_not_reached();
6949 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6952 clear_vec_high(s
, rd
);
6955 tcg_temp_free_i64(tcg_res
);
6956 tcg_temp_free_i64(tcg_op
);
6958 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6959 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6960 int pass
, maxpasses
;
6965 maxpasses
= is_q
? 4 : 2;
6968 for (pass
= 0; pass
< maxpasses
; pass
++) {
6969 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6972 case 0x3f: /* FRECPX */
6973 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
6976 g_assert_not_reached();
6980 write_fp_sreg(s
, rd
, tcg_res
);
6982 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6985 tcg_temp_free_i32(tcg_res
);
6986 tcg_temp_free_i32(tcg_op
);
6987 if (!is_q
&& !is_scalar
) {
6988 clear_vec_high(s
, rd
);
6991 tcg_temp_free_ptr(fpst
);
6994 /* C3.6.12 AdvSIMD scalar two reg misc
6995 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6996 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6997 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
6998 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7000 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7002 int rd
= extract32(insn
, 0, 5);
7003 int rn
= extract32(insn
, 5, 5);
7004 int opcode
= extract32(insn
, 12, 5);
7005 int size
= extract32(insn
, 22, 2);
7006 bool u
= extract32(insn
, 29, 1);
7007 bool is_fcvt
= false;
7010 TCGv_ptr tcg_fpstatus
;
7013 case 0xa: /* CMLT */
7015 unallocated_encoding(s
);
7019 case 0x8: /* CMGT, CMGE */
7020 case 0x9: /* CMEQ, CMLE */
7021 case 0xb: /* ABS, NEG */
7023 unallocated_encoding(s
);
7030 /* Floating point: U, size[1] and opcode indicate operation;
7031 * size[0] indicates single or double precision.
7033 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7034 size
= extract32(size
, 0, 1) ? 3 : 2;
7036 case 0x2c: /* FCMGT (zero) */
7037 case 0x2d: /* FCMEQ (zero) */
7038 case 0x2e: /* FCMLT (zero) */
7039 case 0x6c: /* FCMGE (zero) */
7040 case 0x6d: /* FCMLE (zero) */
7041 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7043 case 0x1d: /* SCVTF */
7044 case 0x5d: /* UCVTF */
7046 bool is_signed
= (opcode
== 0x1d);
7047 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7050 case 0x3f: /* FRECPX */
7051 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7053 case 0x1a: /* FCVTNS */
7054 case 0x1b: /* FCVTMS */
7055 case 0x3a: /* FCVTPS */
7056 case 0x3b: /* FCVTZS */
7057 case 0x5a: /* FCVTNU */
7058 case 0x5b: /* FCVTMU */
7059 case 0x7a: /* FCVTPU */
7060 case 0x7b: /* FCVTZU */
7062 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7064 case 0x1c: /* FCVTAS */
7065 case 0x5c: /* FCVTAU */
7066 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7068 rmode
= FPROUNDING_TIEAWAY
;
7070 case 0x3d: /* FRECPE */
7071 case 0x56: /* FCVTXN, FCVTXN2 */
7072 case 0x7d: /* FRSQRTE */
7073 unsupported_encoding(s
, insn
);
7076 unallocated_encoding(s
);
7081 /* Other categories of encoding in this class:
7082 * + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64
7083 * + SQXTN/SQXTN2/SQXTUN/SQXTUN2/UQXTN/UQXTN2:
7084 * narrowing saturate ops: size 64/32/16 -> 32/16/8
7086 unsupported_encoding(s
, insn
);
7091 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7092 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7093 tcg_fpstatus
= get_fpstatus_ptr();
7095 TCGV_UNUSED_I32(tcg_rmode
);
7096 TCGV_UNUSED_PTR(tcg_fpstatus
);
7100 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7101 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7103 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7104 write_fp_dreg(s
, rd
, tcg_rd
);
7105 tcg_temp_free_i64(tcg_rd
);
7106 tcg_temp_free_i64(tcg_rn
);
7107 } else if (size
== 2) {
7108 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
7109 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7112 case 0x1a: /* FCVTNS */
7113 case 0x1b: /* FCVTMS */
7114 case 0x1c: /* FCVTAS */
7115 case 0x3a: /* FCVTPS */
7116 case 0x3b: /* FCVTZS */
7118 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7119 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7120 tcg_temp_free_i32(tcg_shift
);
7123 case 0x5a: /* FCVTNU */
7124 case 0x5b: /* FCVTMU */
7125 case 0x5c: /* FCVTAU */
7126 case 0x7a: /* FCVTPU */
7127 case 0x7b: /* FCVTZU */
7129 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7130 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7131 tcg_temp_free_i32(tcg_shift
);
7135 g_assert_not_reached();
7138 write_fp_sreg(s
, rd
, tcg_rd
);
7139 tcg_temp_free_i32(tcg_rd
);
7140 tcg_temp_free_i32(tcg_rn
);
7142 g_assert_not_reached();
7146 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7147 tcg_temp_free_i32(tcg_rmode
);
7148 tcg_temp_free_ptr(tcg_fpstatus
);
7152 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
7153 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
7154 int immh
, int immb
, int opcode
, int rn
, int rd
)
7156 int size
= 32 - clz32(immh
) - 1;
7157 int immhb
= immh
<< 3 | immb
;
7158 int shift
= 2 * (8 << size
) - immhb
;
7159 bool accumulate
= false;
7161 bool insert
= false;
7162 int dsize
= is_q
? 128 : 64;
7163 int esize
= 8 << size
;
7164 int elements
= dsize
/esize
;
7165 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
7166 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7167 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7171 if (extract32(immh
, 3, 1) && !is_q
) {
7172 unallocated_encoding(s
);
7176 if (size
> 3 && !is_q
) {
7177 unallocated_encoding(s
);
7182 case 0x02: /* SSRA / USRA (accumulate) */
7185 case 0x04: /* SRSHR / URSHR (rounding) */
7188 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7189 accumulate
= round
= true;
7191 case 0x08: /* SRI */
7197 uint64_t round_const
= 1ULL << (shift
- 1);
7198 tcg_round
= tcg_const_i64(round_const
);
7200 TCGV_UNUSED_I64(tcg_round
);
7203 for (i
= 0; i
< elements
; i
++) {
7204 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
7205 if (accumulate
|| insert
) {
7206 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
7210 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
7212 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7213 accumulate
, is_u
, size
, shift
);
7216 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7220 clear_vec_high(s
, rd
);
7224 tcg_temp_free_i64(tcg_round
);
7228 /* SHL/SLI - Vector shift left */
7229 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
7230 int immh
, int immb
, int opcode
, int rn
, int rd
)
7232 int size
= 32 - clz32(immh
) - 1;
7233 int immhb
= immh
<< 3 | immb
;
7234 int shift
= immhb
- (8 << size
);
7235 int dsize
= is_q
? 128 : 64;
7236 int esize
= 8 << size
;
7237 int elements
= dsize
/esize
;
7238 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7239 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7242 if (extract32(immh
, 3, 1) && !is_q
) {
7243 unallocated_encoding(s
);
7247 if (size
> 3 && !is_q
) {
7248 unallocated_encoding(s
);
7252 for (i
= 0; i
< elements
; i
++) {
7253 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
7255 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
7258 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
7260 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7264 clear_vec_high(s
, rd
);
7268 /* USHLL/SHLL - Vector shift left with widening */
7269 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
7270 int immh
, int immb
, int opcode
, int rn
, int rd
)
7272 int size
= 32 - clz32(immh
) - 1;
7273 int immhb
= immh
<< 3 | immb
;
7274 int shift
= immhb
- (8 << size
);
7276 int esize
= 8 << size
;
7277 int elements
= dsize
/esize
;
7278 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7279 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7283 unallocated_encoding(s
);
7287 /* For the LL variants the store is larger than the load,
7288 * so if rd == rn we would overwrite parts of our input.
7289 * So load everything right now and use shifts in the main loop.
7291 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
7293 for (i
= 0; i
< elements
; i
++) {
7294 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
7295 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
7296 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
7297 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
7301 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
7302 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
7303 int immh
, int immb
, int opcode
, int rn
, int rd
)
7305 int immhb
= immh
<< 3 | immb
;
7306 int size
= 32 - clz32(immh
) - 1;
7308 int esize
= 8 << size
;
7309 int elements
= dsize
/esize
;
7310 int shift
= (2 * esize
) - immhb
;
7311 bool round
= extract32(opcode
, 0, 1);
7312 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
7316 if (extract32(immh
, 3, 1)) {
7317 unallocated_encoding(s
);
7321 tcg_rn
= tcg_temp_new_i64();
7322 tcg_rd
= tcg_temp_new_i64();
7323 tcg_final
= tcg_temp_new_i64();
7324 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
7327 uint64_t round_const
= 1ULL << (shift
- 1);
7328 tcg_round
= tcg_const_i64(round_const
);
7330 TCGV_UNUSED_I64(tcg_round
);
7333 for (i
= 0; i
< elements
; i
++) {
7334 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
7335 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7336 false, true, size
+1, shift
);
7338 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7342 clear_vec_high(s
, rd
);
7343 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7345 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7349 tcg_temp_free_i64(tcg_round
);
7351 tcg_temp_free_i64(tcg_rn
);
7352 tcg_temp_free_i64(tcg_rd
);
7353 tcg_temp_free_i64(tcg_final
);
7358 /* C3.6.14 AdvSIMD shift by immediate
7359 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7360 * +---+---+---+-------------+------+------+--------+---+------+------+
7361 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7362 * +---+---+---+-------------+------+------+--------+---+------+------+
7364 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
7366 int rd
= extract32(insn
, 0, 5);
7367 int rn
= extract32(insn
, 5, 5);
7368 int opcode
= extract32(insn
, 11, 5);
7369 int immb
= extract32(insn
, 16, 3);
7370 int immh
= extract32(insn
, 19, 4);
7371 bool is_u
= extract32(insn
, 29, 1);
7372 bool is_q
= extract32(insn
, 30, 1);
7375 case 0x08: /* SRI */
7377 unallocated_encoding(s
);
7381 case 0x00: /* SSHR / USHR */
7382 case 0x02: /* SSRA / USRA (accumulate) */
7383 case 0x04: /* SRSHR / URSHR (rounding) */
7384 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7385 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7387 case 0x0a: /* SHL / SLI */
7388 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7390 case 0x10: /* SHRN */
7391 case 0x11: /* RSHRN / SQRSHRUN */
7393 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
7396 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
7399 case 0x12: /* SQSHRN / UQSHRN */
7400 case 0x13: /* SQRSHRN / UQRSHRN */
7401 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
7404 case 0x14: /* SSHLL / USHLL */
7405 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7407 case 0x1c: /* SCVTF / UCVTF */
7408 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
7411 case 0xc: /* SQSHLU */
7412 case 0xe: /* SQSHL, UQSHL */
7413 case 0x1f: /* FCVTZS/ FCVTZU */
7414 unsupported_encoding(s
, insn
);
7417 unallocated_encoding(s
);
7422 /* Generate code to do a "long" addition or subtraction, ie one done in
7423 * TCGv_i64 on vector lanes twice the width specified by size.
7425 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
7426 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
7428 static NeonGenTwo64OpFn
* const fns
[3][2] = {
7429 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
7430 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
7431 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
7433 NeonGenTwo64OpFn
*genfn
;
7436 genfn
= fns
[size
][is_sub
];
7437 genfn(tcg_res
, tcg_op1
, tcg_op2
);
7440 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
7441 int opcode
, int rd
, int rn
, int rm
)
7443 /* 3-reg-different widening insns: 64 x 64 -> 128 */
7444 TCGv_i64 tcg_res
[2];
7447 tcg_res
[0] = tcg_temp_new_i64();
7448 tcg_res
[1] = tcg_temp_new_i64();
7450 /* Does this op do an adding accumulate, a subtracting accumulate,
7451 * or no accumulate at all?
7469 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
7470 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
7473 /* size == 2 means two 32x32->64 operations; this is worth special
7474 * casing because we can generally handle it inline.
7477 for (pass
= 0; pass
< 2; pass
++) {
7478 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7479 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7480 TCGv_i64 tcg_passres
;
7481 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
7483 int elt
= pass
+ is_q
* 2;
7485 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
7486 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
7489 tcg_passres
= tcg_res
[pass
];
7491 tcg_passres
= tcg_temp_new_i64();
7495 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
7496 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7498 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
7499 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7501 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7502 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7504 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
7505 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
7507 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
7508 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
7509 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
7511 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
7512 tcg_temp_free_i64(tcg_tmp1
);
7513 tcg_temp_free_i64(tcg_tmp2
);
7516 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7517 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7518 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
7519 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7521 case 9: /* SQDMLAL, SQDMLAL2 */
7522 case 11: /* SQDMLSL, SQDMLSL2 */
7523 case 13: /* SQDMULL, SQDMULL2 */
7524 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7525 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
7526 tcg_passres
, tcg_passres
);
7529 g_assert_not_reached();
7532 if (opcode
== 9 || opcode
== 11) {
7533 /* saturating accumulate ops */
7535 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
7537 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
7538 tcg_res
[pass
], tcg_passres
);
7539 } else if (accop
> 0) {
7540 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
7541 } else if (accop
< 0) {
7542 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
7546 tcg_temp_free_i64(tcg_passres
);
7549 tcg_temp_free_i64(tcg_op1
);
7550 tcg_temp_free_i64(tcg_op2
);
7553 /* size 0 or 1, generally helper functions */
7554 for (pass
= 0; pass
< 2; pass
++) {
7555 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7556 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7557 TCGv_i64 tcg_passres
;
7558 int elt
= pass
+ is_q
* 2;
7560 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
7561 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
7564 tcg_passres
= tcg_res
[pass
];
7566 tcg_passres
= tcg_temp_new_i64();
7570 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
7571 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
7573 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
7574 static NeonGenWidenFn
* const widenfns
[2][2] = {
7575 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
7576 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
7578 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
7580 widenfn(tcg_op2_64
, tcg_op2
);
7581 widenfn(tcg_passres
, tcg_op1
);
7582 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
7583 tcg_passres
, tcg_op2_64
);
7584 tcg_temp_free_i64(tcg_op2_64
);
7587 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7588 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7591 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
7593 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7597 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
7599 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
7603 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7604 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7605 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
7608 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
7610 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
7614 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
7616 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7620 case 9: /* SQDMLAL, SQDMLAL2 */
7621 case 11: /* SQDMLSL, SQDMLSL2 */
7622 case 13: /* SQDMULL, SQDMULL2 */
7624 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7625 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
7626 tcg_passres
, tcg_passres
);
7628 case 14: /* PMULL */
7630 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
7633 g_assert_not_reached();
7635 tcg_temp_free_i32(tcg_op1
);
7636 tcg_temp_free_i32(tcg_op2
);
7639 if (opcode
== 9 || opcode
== 11) {
7640 /* saturating accumulate ops */
7642 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
7644 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
7648 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
7649 tcg_res
[pass
], tcg_passres
);
7651 tcg_temp_free_i64(tcg_passres
);
7656 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
7657 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
7658 tcg_temp_free_i64(tcg_res
[0]);
7659 tcg_temp_free_i64(tcg_res
[1]);
7662 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
7663 int opcode
, int rd
, int rn
, int rm
)
7665 TCGv_i64 tcg_res
[2];
7666 int part
= is_q
? 2 : 0;
7669 for (pass
= 0; pass
< 2; pass
++) {
7670 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7671 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7672 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
7673 static NeonGenWidenFn
* const widenfns
[3][2] = {
7674 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
7675 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
7676 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
7678 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
7680 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7681 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
7682 widenfn(tcg_op2_wide
, tcg_op2
);
7683 tcg_temp_free_i32(tcg_op2
);
7684 tcg_res
[pass
] = tcg_temp_new_i64();
7685 gen_neon_addl(size
, (opcode
== 3),
7686 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
7687 tcg_temp_free_i64(tcg_op1
);
7688 tcg_temp_free_i64(tcg_op2_wide
);
7691 for (pass
= 0; pass
< 2; pass
++) {
7692 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
7693 tcg_temp_free_i64(tcg_res
[pass
]);
7697 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
7699 tcg_gen_shri_i64(in
, in
, 32);
7700 tcg_gen_trunc_i64_i32(res
, in
);
7703 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
7705 tcg_gen_addi_i64(in
, in
, 1U << 31);
7706 do_narrow_high_u32(res
, in
);
7709 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
7710 int opcode
, int rd
, int rn
, int rm
)
7712 TCGv_i32 tcg_res
[2];
7713 int part
= is_q
? 2 : 0;
7716 for (pass
= 0; pass
< 2; pass
++) {
7717 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7718 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7719 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
7720 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
7721 { gen_helper_neon_narrow_high_u8
,
7722 gen_helper_neon_narrow_round_high_u8
},
7723 { gen_helper_neon_narrow_high_u16
,
7724 gen_helper_neon_narrow_round_high_u16
},
7725 { do_narrow_high_u32
, do_narrow_round_high_u32
},
7727 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
7729 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7730 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7732 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
7734 tcg_temp_free_i64(tcg_op1
);
7735 tcg_temp_free_i64(tcg_op2
);
7737 tcg_res
[pass
] = tcg_temp_new_i32();
7738 gennarrow(tcg_res
[pass
], tcg_wideres
);
7739 tcg_temp_free_i64(tcg_wideres
);
7742 for (pass
= 0; pass
< 2; pass
++) {
7743 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
7744 tcg_temp_free_i32(tcg_res
[pass
]);
7747 clear_vec_high(s
, rd
);
7751 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
7753 /* PMULL of 64 x 64 -> 128 is an odd special case because it
7754 * is the only three-reg-diff instruction which produces a
7755 * 128-bit wide result from a single operation. However since
7756 * it's possible to calculate the two halves more or less
7757 * separately we just use two helper calls.
7759 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7760 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7761 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7763 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
7764 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
7765 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
7766 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
7767 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
7768 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
7770 tcg_temp_free_i64(tcg_op1
);
7771 tcg_temp_free_i64(tcg_op2
);
7772 tcg_temp_free_i64(tcg_res
);
7775 /* C3.6.15 AdvSIMD three different
7776 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7777 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
7778 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7779 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
7781 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7783 /* Instructions in this group fall into three basic classes
7784 * (in each case with the operation working on each element in
7785 * the input vectors):
7786 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
7788 * (2) wide 64 x 128 -> 128
7789 * (3) narrowing 128 x 128 -> 64
7790 * Here we do initial decode, catch unallocated cases and
7791 * dispatch to separate functions for each class.
7793 int is_q
= extract32(insn
, 30, 1);
7794 int is_u
= extract32(insn
, 29, 1);
7795 int size
= extract32(insn
, 22, 2);
7796 int opcode
= extract32(insn
, 12, 4);
7797 int rm
= extract32(insn
, 16, 5);
7798 int rn
= extract32(insn
, 5, 5);
7799 int rd
= extract32(insn
, 0, 5);
7802 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
7803 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
7804 /* 64 x 128 -> 128 */
7806 unallocated_encoding(s
);
7809 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
7811 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
7812 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
7813 /* 128 x 128 -> 64 */
7815 unallocated_encoding(s
);
7818 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
7820 case 14: /* PMULL, PMULL2 */
7821 if (is_u
|| size
== 1 || size
== 2) {
7822 unallocated_encoding(s
);
7826 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)) {
7827 unallocated_encoding(s
);
7830 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
7834 case 9: /* SQDMLAL, SQDMLAL2 */
7835 case 11: /* SQDMLSL, SQDMLSL2 */
7836 case 13: /* SQDMULL, SQDMULL2 */
7837 if (is_u
|| size
== 0) {
7838 unallocated_encoding(s
);
7842 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
7843 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
7844 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7845 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7846 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7847 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7848 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
7849 /* 64 x 64 -> 128 */
7851 unallocated_encoding(s
);
7855 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
7858 /* opcode 15 not allocated */
7859 unallocated_encoding(s
);
7864 /* Logic op (opcode == 3) subgroup of C3.6.16. */
7865 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
7867 int rd
= extract32(insn
, 0, 5);
7868 int rn
= extract32(insn
, 5, 5);
7869 int rm
= extract32(insn
, 16, 5);
7870 int size
= extract32(insn
, 22, 2);
7871 bool is_u
= extract32(insn
, 29, 1);
7872 bool is_q
= extract32(insn
, 30, 1);
7873 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7874 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7875 TCGv_i64 tcg_res
[2];
7878 tcg_res
[0] = tcg_temp_new_i64();
7879 tcg_res
[1] = tcg_temp_new_i64();
7881 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
7882 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7883 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7888 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7891 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7894 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7897 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7902 /* B* ops need res loaded to operate on */
7903 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
7908 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7910 case 1: /* BSL bitwise select */
7911 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
7912 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
7913 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
7915 case 2: /* BIT, bitwise insert if true */
7916 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
7917 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
7918 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
7920 case 3: /* BIF, bitwise insert if false */
7921 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
7922 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
7923 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
7929 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
7931 tcg_gen_movi_i64(tcg_res
[1], 0);
7933 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
7935 tcg_temp_free_i64(tcg_op1
);
7936 tcg_temp_free_i64(tcg_op2
);
7937 tcg_temp_free_i64(tcg_res
[0]);
7938 tcg_temp_free_i64(tcg_res
[1]);
7941 /* Helper functions for 32 bit comparisons */
7942 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7944 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
7947 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7949 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
7952 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7954 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
7957 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
7959 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
7962 /* Pairwise op subgroup of C3.6.16.
7964 * This is called directly or via the handle_3same_float for float pairwise
7965 * operations where the opcode and size are calculated differently.
7967 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
7968 int size
, int rn
, int rm
, int rd
)
7973 /* Floating point operations need fpst */
7974 if (opcode
>= 0x58) {
7975 fpst
= get_fpstatus_ptr();
7977 TCGV_UNUSED_PTR(fpst
);
7980 /* These operations work on the concatenated rm:rn, with each pair of
7981 * adjacent elements being operated on to produce an element in the result.
7984 TCGv_i64 tcg_res
[2];
7986 for (pass
= 0; pass
< 2; pass
++) {
7987 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7988 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7989 int passreg
= (pass
== 0) ? rn
: rm
;
7991 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
7992 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
7993 tcg_res
[pass
] = tcg_temp_new_i64();
7996 case 0x17: /* ADDP */
7997 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
7999 case 0x58: /* FMAXNMP */
8000 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8002 case 0x5a: /* FADDP */
8003 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8005 case 0x5e: /* FMAXP */
8006 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8008 case 0x78: /* FMINNMP */
8009 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8011 case 0x7e: /* FMINP */
8012 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8015 g_assert_not_reached();
8018 tcg_temp_free_i64(tcg_op1
);
8019 tcg_temp_free_i64(tcg_op2
);
8022 for (pass
= 0; pass
< 2; pass
++) {
8023 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8024 tcg_temp_free_i64(tcg_res
[pass
]);
8027 int maxpass
= is_q
? 4 : 2;
8028 TCGv_i32 tcg_res
[4];
8030 for (pass
= 0; pass
< maxpass
; pass
++) {
8031 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8032 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8033 NeonGenTwoOpFn
*genfn
= NULL
;
8034 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8035 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8037 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8038 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8039 tcg_res
[pass
] = tcg_temp_new_i32();
8042 case 0x17: /* ADDP */
8044 static NeonGenTwoOpFn
* const fns
[3] = {
8045 gen_helper_neon_padd_u8
,
8046 gen_helper_neon_padd_u16
,
8052 case 0x14: /* SMAXP, UMAXP */
8054 static NeonGenTwoOpFn
* const fns
[3][2] = {
8055 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8056 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8057 { gen_max_s32
, gen_max_u32
},
8059 genfn
= fns
[size
][u
];
8062 case 0x15: /* SMINP, UMINP */
8064 static NeonGenTwoOpFn
* const fns
[3][2] = {
8065 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8066 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8067 { gen_min_s32
, gen_min_u32
},
8069 genfn
= fns
[size
][u
];
8072 /* The FP operations are all on single floats (32 bit) */
8073 case 0x58: /* FMAXNMP */
8074 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8076 case 0x5a: /* FADDP */
8077 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8079 case 0x5e: /* FMAXP */
8080 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8082 case 0x78: /* FMINNMP */
8083 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8085 case 0x7e: /* FMINP */
8086 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8089 g_assert_not_reached();
8092 /* FP ops called directly, otherwise call now */
8094 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8097 tcg_temp_free_i32(tcg_op1
);
8098 tcg_temp_free_i32(tcg_op2
);
8101 for (pass
= 0; pass
< maxpass
; pass
++) {
8102 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8103 tcg_temp_free_i32(tcg_res
[pass
]);
8106 clear_vec_high(s
, rd
);
8110 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
8111 tcg_temp_free_ptr(fpst
);
8115 /* Floating point op subgroup of C3.6.16. */
8116 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
8118 /* For floating point ops, the U, size[1] and opcode bits
8119 * together indicate the operation. size[0] indicates single
8122 int fpopcode
= extract32(insn
, 11, 5)
8123 | (extract32(insn
, 23, 1) << 5)
8124 | (extract32(insn
, 29, 1) << 6);
8125 int is_q
= extract32(insn
, 30, 1);
8126 int size
= extract32(insn
, 22, 1);
8127 int rm
= extract32(insn
, 16, 5);
8128 int rn
= extract32(insn
, 5, 5);
8129 int rd
= extract32(insn
, 0, 5);
8131 int datasize
= is_q
? 128 : 64;
8132 int esize
= 32 << size
;
8133 int elements
= datasize
/ esize
;
8135 if (size
== 1 && !is_q
) {
8136 unallocated_encoding(s
);
8141 case 0x58: /* FMAXNMP */
8142 case 0x5a: /* FADDP */
8143 case 0x5e: /* FMAXP */
8144 case 0x78: /* FMINNMP */
8145 case 0x7e: /* FMINP */
8146 if (size
&& !is_q
) {
8147 unallocated_encoding(s
);
8150 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
8153 case 0x1b: /* FMULX */
8154 case 0x1f: /* FRECPS */
8155 case 0x3f: /* FRSQRTS */
8156 case 0x5d: /* FACGE */
8157 case 0x7d: /* FACGT */
8158 case 0x19: /* FMLA */
8159 case 0x39: /* FMLS */
8160 case 0x18: /* FMAXNM */
8161 case 0x1a: /* FADD */
8162 case 0x1c: /* FCMEQ */
8163 case 0x1e: /* FMAX */
8164 case 0x38: /* FMINNM */
8165 case 0x3a: /* FSUB */
8166 case 0x3e: /* FMIN */
8167 case 0x5b: /* FMUL */
8168 case 0x5c: /* FCMGE */
8169 case 0x5f: /* FDIV */
8170 case 0x7a: /* FABD */
8171 case 0x7c: /* FCMGT */
8172 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
8175 unallocated_encoding(s
);
8180 /* Integer op subgroup of C3.6.16. */
8181 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
8183 int is_q
= extract32(insn
, 30, 1);
8184 int u
= extract32(insn
, 29, 1);
8185 int size
= extract32(insn
, 22, 2);
8186 int opcode
= extract32(insn
, 11, 5);
8187 int rm
= extract32(insn
, 16, 5);
8188 int rn
= extract32(insn
, 5, 5);
8189 int rd
= extract32(insn
, 0, 5);
8193 case 0x13: /* MUL, PMUL */
8194 if (u
&& size
!= 0) {
8195 unallocated_encoding(s
);
8199 case 0x0: /* SHADD, UHADD */
8200 case 0x2: /* SRHADD, URHADD */
8201 case 0x4: /* SHSUB, UHSUB */
8202 case 0xc: /* SMAX, UMAX */
8203 case 0xd: /* SMIN, UMIN */
8204 case 0xe: /* SABD, UABD */
8205 case 0xf: /* SABA, UABA */
8206 case 0x12: /* MLA, MLS */
8208 unallocated_encoding(s
);
8212 case 0x16: /* SQDMULH, SQRDMULH */
8213 if (size
== 0 || size
== 3) {
8214 unallocated_encoding(s
);
8219 if (size
== 3 && !is_q
) {
8220 unallocated_encoding(s
);
8227 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8228 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8229 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8230 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8232 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8233 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8235 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
8237 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8239 tcg_temp_free_i64(tcg_res
);
8240 tcg_temp_free_i64(tcg_op1
);
8241 tcg_temp_free_i64(tcg_op2
);
8244 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
8245 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8246 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8247 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8248 NeonGenTwoOpFn
*genfn
= NULL
;
8249 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
8251 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8252 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8255 case 0x0: /* SHADD, UHADD */
8257 static NeonGenTwoOpFn
* const fns
[3][2] = {
8258 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
8259 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
8260 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
8262 genfn
= fns
[size
][u
];
8265 case 0x1: /* SQADD, UQADD */
8267 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8268 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8269 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8270 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8272 genenvfn
= fns
[size
][u
];
8275 case 0x2: /* SRHADD, URHADD */
8277 static NeonGenTwoOpFn
* const fns
[3][2] = {
8278 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
8279 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
8280 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
8282 genfn
= fns
[size
][u
];
8285 case 0x4: /* SHSUB, UHSUB */
8287 static NeonGenTwoOpFn
* const fns
[3][2] = {
8288 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
8289 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
8290 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
8292 genfn
= fns
[size
][u
];
8295 case 0x5: /* SQSUB, UQSUB */
8297 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8298 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8299 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8300 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8302 genenvfn
= fns
[size
][u
];
8305 case 0x6: /* CMGT, CMHI */
8307 static NeonGenTwoOpFn
* const fns
[3][2] = {
8308 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
8309 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
8310 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
8312 genfn
= fns
[size
][u
];
8315 case 0x7: /* CMGE, CMHS */
8317 static NeonGenTwoOpFn
* const fns
[3][2] = {
8318 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
8319 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
8320 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
8322 genfn
= fns
[size
][u
];
8325 case 0x8: /* SSHL, USHL */
8327 static NeonGenTwoOpFn
* const fns
[3][2] = {
8328 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
8329 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
8330 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
8332 genfn
= fns
[size
][u
];
8335 case 0x9: /* SQSHL, UQSHL */
8337 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8338 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8339 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8340 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8342 genenvfn
= fns
[size
][u
];
8345 case 0xa: /* SRSHL, URSHL */
8347 static NeonGenTwoOpFn
* const fns
[3][2] = {
8348 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
8349 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
8350 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
8352 genfn
= fns
[size
][u
];
8355 case 0xb: /* SQRSHL, UQRSHL */
8357 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8358 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8359 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8360 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8362 genenvfn
= fns
[size
][u
];
8365 case 0xc: /* SMAX, UMAX */
8367 static NeonGenTwoOpFn
* const fns
[3][2] = {
8368 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
8369 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
8370 { gen_max_s32
, gen_max_u32
},
8372 genfn
= fns
[size
][u
];
8376 case 0xd: /* SMIN, UMIN */
8378 static NeonGenTwoOpFn
* const fns
[3][2] = {
8379 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
8380 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
8381 { gen_min_s32
, gen_min_u32
},
8383 genfn
= fns
[size
][u
];
8386 case 0xe: /* SABD, UABD */
8387 case 0xf: /* SABA, UABA */
8389 static NeonGenTwoOpFn
* const fns
[3][2] = {
8390 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
8391 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
8392 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
8394 genfn
= fns
[size
][u
];
8397 case 0x10: /* ADD, SUB */
8399 static NeonGenTwoOpFn
* const fns
[3][2] = {
8400 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
8401 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
8402 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
8404 genfn
= fns
[size
][u
];
8407 case 0x11: /* CMTST, CMEQ */
8409 static NeonGenTwoOpFn
* const fns
[3][2] = {
8410 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
8411 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
8412 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
8414 genfn
= fns
[size
][u
];
8417 case 0x13: /* MUL, PMUL */
8421 genfn
= gen_helper_neon_mul_p8
;
8424 /* fall through : MUL */
8425 case 0x12: /* MLA, MLS */
8427 static NeonGenTwoOpFn
* const fns
[3] = {
8428 gen_helper_neon_mul_u8
,
8429 gen_helper_neon_mul_u16
,
8435 case 0x16: /* SQDMULH, SQRDMULH */
8437 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8438 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8439 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8441 assert(size
== 1 || size
== 2);
8442 genenvfn
= fns
[size
- 1][u
];
8446 g_assert_not_reached();
8450 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
8452 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8455 if (opcode
== 0xf || opcode
== 0x12) {
8456 /* SABA, UABA, MLA, MLS: accumulating ops */
8457 static NeonGenTwoOpFn
* const fns
[3][2] = {
8458 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
8459 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
8460 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
8462 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
8464 genfn
= fns
[size
][is_sub
];
8465 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
8466 genfn(tcg_res
, tcg_res
, tcg_op1
);
8469 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8471 tcg_temp_free_i32(tcg_res
);
8472 tcg_temp_free_i32(tcg_op1
);
8473 tcg_temp_free_i32(tcg_op2
);
8478 clear_vec_high(s
, rd
);
8482 /* C3.6.16 AdvSIMD three same
8483 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8484 * +---+---+---+-----------+------+---+------+--------+---+------+------+
8485 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8486 * +---+---+---+-----------+------+---+------+--------+---+------+------+
8488 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
8490 int opcode
= extract32(insn
, 11, 5);
8493 case 0x3: /* logic ops */
8494 disas_simd_3same_logic(s
, insn
);
8496 case 0x17: /* ADDP */
8497 case 0x14: /* SMAXP, UMAXP */
8498 case 0x15: /* SMINP, UMINP */
8500 /* Pairwise operations */
8501 int is_q
= extract32(insn
, 30, 1);
8502 int u
= extract32(insn
, 29, 1);
8503 int size
= extract32(insn
, 22, 2);
8504 int rm
= extract32(insn
, 16, 5);
8505 int rn
= extract32(insn
, 5, 5);
8506 int rd
= extract32(insn
, 0, 5);
8507 if (opcode
== 0x17) {
8508 if (u
|| (size
== 3 && !is_q
)) {
8509 unallocated_encoding(s
);
8514 unallocated_encoding(s
);
8518 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
8522 /* floating point ops, sz[1] and U are part of opcode */
8523 disas_simd_3same_float(s
, insn
);
8526 disas_simd_3same_int(s
, insn
);
8531 static void handle_2misc_narrow(DisasContext
*s
, int opcode
, bool u
, bool is_q
,
8532 int size
, int rn
, int rd
)
8534 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
8535 * in the source becomes a size element in the destination).
8538 TCGv_i32 tcg_res
[2];
8539 int destelt
= is_q
? 2 : 0;
8541 for (pass
= 0; pass
< 2; pass
++) {
8542 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8543 NeonGenNarrowFn
*genfn
= NULL
;
8544 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
8546 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8547 tcg_res
[pass
] = tcg_temp_new_i32();
8550 case 0x12: /* XTN, SQXTUN */
8552 static NeonGenNarrowFn
* const xtnfns
[3] = {
8553 gen_helper_neon_narrow_u8
,
8554 gen_helper_neon_narrow_u16
,
8555 tcg_gen_trunc_i64_i32
,
8557 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
8558 gen_helper_neon_unarrow_sat8
,
8559 gen_helper_neon_unarrow_sat16
,
8560 gen_helper_neon_unarrow_sat32
,
8563 genenvfn
= sqxtunfns
[size
];
8565 genfn
= xtnfns
[size
];
8569 case 0x14: /* SQXTN, UQXTN */
8571 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
8572 { gen_helper_neon_narrow_sat_s8
,
8573 gen_helper_neon_narrow_sat_u8
},
8574 { gen_helper_neon_narrow_sat_s16
,
8575 gen_helper_neon_narrow_sat_u16
},
8576 { gen_helper_neon_narrow_sat_s32
,
8577 gen_helper_neon_narrow_sat_u32
},
8579 genenvfn
= fns
[size
][u
];
8582 case 0x16: /* FCVTN, FCVTN2 */
8583 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
8585 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
8587 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
8588 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
8589 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
8590 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
8591 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
8592 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
8593 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
8594 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
8595 tcg_temp_free_i32(tcg_lo
);
8596 tcg_temp_free_i32(tcg_hi
);
8600 g_assert_not_reached();
8604 genfn(tcg_res
[pass
], tcg_op
);
8605 } else if (genenvfn
) {
8606 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
8609 tcg_temp_free_i64(tcg_op
);
8612 for (pass
= 0; pass
< 2; pass
++) {
8613 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
8614 tcg_temp_free_i32(tcg_res
[pass
]);
8617 clear_vec_high(s
, rd
);
8621 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
8622 int size
, int rn
, int rd
)
8624 /* Handle 2-reg-misc ops which are widening (so each size element
8625 * in the source becomes a 2*size element in the destination.
8626 * The only instruction like this is FCVTL.
8631 /* 32 -> 64 bit fp conversion */
8632 TCGv_i64 tcg_res
[2];
8633 int srcelt
= is_q
? 2 : 0;
8635 for (pass
= 0; pass
< 2; pass
++) {
8636 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8637 tcg_res
[pass
] = tcg_temp_new_i64();
8639 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
8640 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
8641 tcg_temp_free_i32(tcg_op
);
8643 for (pass
= 0; pass
< 2; pass
++) {
8644 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8645 tcg_temp_free_i64(tcg_res
[pass
]);
8648 /* 16 -> 32 bit fp conversion */
8649 int srcelt
= is_q
? 4 : 0;
8650 TCGv_i32 tcg_res
[4];
8652 for (pass
= 0; pass
< 4; pass
++) {
8653 tcg_res
[pass
] = tcg_temp_new_i32();
8655 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
8656 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
8659 for (pass
= 0; pass
< 4; pass
++) {
8660 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8661 tcg_temp_free_i32(tcg_res
[pass
]);
8666 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
8667 bool is_q
, int size
, int rn
, int rd
)
8669 int op
= (opcode
<< 1) | u
;
8670 int opsz
= op
+ size
;
8671 int grp_size
= 3 - opsz
;
8672 int dsize
= is_q
? 128 : 64;
8676 unallocated_encoding(s
);
8681 /* Special case bytes, use bswap op on each group of elements */
8682 int groups
= dsize
/ (8 << grp_size
);
8684 for (i
= 0; i
< groups
; i
++) {
8685 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8687 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
8690 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
8693 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
8696 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
8699 g_assert_not_reached();
8701 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
8702 tcg_temp_free_i64(tcg_tmp
);
8705 clear_vec_high(s
, rd
);
8708 int revmask
= (1 << grp_size
) - 1;
8709 int esize
= 8 << size
;
8710 int elements
= dsize
/ esize
;
8711 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
8712 TCGv_i64 tcg_rd
= tcg_const_i64(0);
8713 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
8715 for (i
= 0; i
< elements
; i
++) {
8716 int e_rev
= (i
& 0xf) ^ revmask
;
8717 int off
= e_rev
* esize
;
8718 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8720 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
8721 tcg_rn
, off
- 64, esize
);
8723 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
8726 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
8727 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
8729 tcg_temp_free_i64(tcg_rd_hi
);
8730 tcg_temp_free_i64(tcg_rd
);
8731 tcg_temp_free_i64(tcg_rn
);
8735 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
8736 bool is_q
, int size
, int rn
, int rd
)
8738 /* Implement the pairwise operations from 2-misc:
8739 * SADDLP, UADDLP, SADALP, UADALP.
8740 * These all add pairs of elements in the input to produce a
8741 * double-width result element in the output (possibly accumulating).
8743 bool accum
= (opcode
== 0x6);
8744 int maxpass
= is_q
? 2 : 1;
8746 TCGv_i64 tcg_res
[2];
8749 /* 32 + 32 -> 64 op */
8750 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
8752 for (pass
= 0; pass
< maxpass
; pass
++) {
8753 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8754 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8756 tcg_res
[pass
] = tcg_temp_new_i64();
8758 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
8759 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
8760 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8762 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
8763 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8766 tcg_temp_free_i64(tcg_op1
);
8767 tcg_temp_free_i64(tcg_op2
);
8770 for (pass
= 0; pass
< maxpass
; pass
++) {
8771 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8772 NeonGenOneOpFn
*genfn
;
8773 static NeonGenOneOpFn
* const fns
[2][2] = {
8774 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
8775 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
8778 genfn
= fns
[size
][u
];
8780 tcg_res
[pass
] = tcg_temp_new_i64();
8782 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8783 genfn(tcg_res
[pass
], tcg_op
);
8786 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8788 gen_helper_neon_addl_u16(tcg_res
[pass
],
8789 tcg_res
[pass
], tcg_op
);
8791 gen_helper_neon_addl_u32(tcg_res
[pass
],
8792 tcg_res
[pass
], tcg_op
);
8795 tcg_temp_free_i64(tcg_op
);
8799 tcg_res
[1] = tcg_const_i64(0);
8801 for (pass
= 0; pass
< 2; pass
++) {
8802 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8803 tcg_temp_free_i64(tcg_res
[pass
]);
8807 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
8809 /* Implement SHLL and SHLL2 */
8811 int part
= is_q
? 2 : 0;
8812 TCGv_i64 tcg_res
[2];
8814 for (pass
= 0; pass
< 2; pass
++) {
8815 static NeonGenWidenFn
* const widenfns
[3] = {
8816 gen_helper_neon_widen_u8
,
8817 gen_helper_neon_widen_u16
,
8818 tcg_gen_extu_i32_i64
,
8820 NeonGenWidenFn
*widenfn
= widenfns
[size
];
8821 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8823 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
8824 tcg_res
[pass
] = tcg_temp_new_i64();
8825 widenfn(tcg_res
[pass
], tcg_op
);
8826 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
8828 tcg_temp_free_i32(tcg_op
);
8831 for (pass
= 0; pass
< 2; pass
++) {
8832 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8833 tcg_temp_free_i64(tcg_res
[pass
]);
8837 /* C3.6.17 AdvSIMD two reg misc
8838 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8839 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
8840 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8841 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
8843 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8845 int size
= extract32(insn
, 22, 2);
8846 int opcode
= extract32(insn
, 12, 5);
8847 bool u
= extract32(insn
, 29, 1);
8848 bool is_q
= extract32(insn
, 30, 1);
8849 int rn
= extract32(insn
, 5, 5);
8850 int rd
= extract32(insn
, 0, 5);
8851 bool need_fpstatus
= false;
8852 bool need_rmode
= false;
8855 TCGv_ptr tcg_fpstatus
;
8858 case 0x0: /* REV64, REV32 */
8859 case 0x1: /* REV16 */
8860 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
8862 case 0x5: /* CNT, NOT, RBIT */
8863 if (u
&& size
== 0) {
8864 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
8867 } else if (u
&& size
== 1) {
8870 } else if (!u
&& size
== 0) {
8874 unallocated_encoding(s
);
8876 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
8877 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
8879 unallocated_encoding(s
);
8882 handle_2misc_narrow(s
, opcode
, u
, is_q
, size
, rn
, rd
);
8884 case 0x4: /* CLS, CLZ */
8886 unallocated_encoding(s
);
8890 case 0x2: /* SADDLP, UADDLP */
8891 case 0x6: /* SADALP, UADALP */
8893 unallocated_encoding(s
);
8896 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
8898 case 0x13: /* SHLL, SHLL2 */
8899 if (u
== 0 || size
== 3) {
8900 unallocated_encoding(s
);
8903 handle_shll(s
, is_q
, size
, rn
, rd
);
8905 case 0xa: /* CMLT */
8907 unallocated_encoding(s
);
8911 case 0x8: /* CMGT, CMGE */
8912 case 0x9: /* CMEQ, CMLE */
8913 case 0xb: /* ABS, NEG */
8914 if (size
== 3 && !is_q
) {
8915 unallocated_encoding(s
);
8919 case 0x3: /* SUQADD, USQADD */
8920 case 0x7: /* SQABS, SQNEG */
8921 if (size
== 3 && !is_q
) {
8922 unallocated_encoding(s
);
8925 unsupported_encoding(s
, insn
);
8931 /* Floating point: U, size[1] and opcode indicate operation;
8932 * size[0] indicates single or double precision.
8934 int is_double
= extract32(size
, 0, 1);
8935 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8936 size
= is_double
? 3 : 2;
8938 case 0x2f: /* FABS */
8939 case 0x6f: /* FNEG */
8940 if (size
== 3 && !is_q
) {
8941 unallocated_encoding(s
);
8945 case 0x1d: /* SCVTF */
8946 case 0x5d: /* UCVTF */
8948 bool is_signed
= (opcode
== 0x1d) ? true : false;
8949 int elements
= is_double
? 2 : is_q
? 4 : 2;
8950 if (is_double
&& !is_q
) {
8951 unallocated_encoding(s
);
8954 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
8957 case 0x2c: /* FCMGT (zero) */
8958 case 0x2d: /* FCMEQ (zero) */
8959 case 0x2e: /* FCMLT (zero) */
8960 case 0x6c: /* FCMGE (zero) */
8961 case 0x6d: /* FCMLE (zero) */
8962 if (size
== 3 && !is_q
) {
8963 unallocated_encoding(s
);
8966 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
8968 case 0x7f: /* FSQRT */
8969 if (size
== 3 && !is_q
) {
8970 unallocated_encoding(s
);
8974 case 0x1a: /* FCVTNS */
8975 case 0x1b: /* FCVTMS */
8976 case 0x3a: /* FCVTPS */
8977 case 0x3b: /* FCVTZS */
8978 case 0x5a: /* FCVTNU */
8979 case 0x5b: /* FCVTMU */
8980 case 0x7a: /* FCVTPU */
8981 case 0x7b: /* FCVTZU */
8982 need_fpstatus
= true;
8984 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8985 if (size
== 3 && !is_q
) {
8986 unallocated_encoding(s
);
8990 case 0x5c: /* FCVTAU */
8991 case 0x1c: /* FCVTAS */
8992 need_fpstatus
= true;
8994 rmode
= FPROUNDING_TIEAWAY
;
8995 if (size
== 3 && !is_q
) {
8996 unallocated_encoding(s
);
9000 case 0x16: /* FCVTN, FCVTN2 */
9001 /* handle_2misc_narrow does a 2*size -> size operation, but these
9002 * instructions encode the source size rather than dest size.
9004 handle_2misc_narrow(s
, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9006 case 0x17: /* FCVTL, FCVTL2 */
9007 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9009 case 0x18: /* FRINTN */
9010 case 0x19: /* FRINTM */
9011 case 0x38: /* FRINTP */
9012 case 0x39: /* FRINTZ */
9014 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9016 case 0x59: /* FRINTX */
9017 case 0x79: /* FRINTI */
9018 need_fpstatus
= true;
9019 if (size
== 3 && !is_q
) {
9020 unallocated_encoding(s
);
9024 case 0x58: /* FRINTA */
9026 rmode
= FPROUNDING_TIEAWAY
;
9027 need_fpstatus
= true;
9028 if (size
== 3 && !is_q
) {
9029 unallocated_encoding(s
);
9033 case 0x3c: /* URECPE */
9034 case 0x3d: /* FRECPE */
9035 case 0x56: /* FCVTXN, FCVTXN2 */
9036 case 0x7c: /* URSQRTE */
9037 case 0x7d: /* FRSQRTE */
9038 unsupported_encoding(s
, insn
);
9041 unallocated_encoding(s
);
9047 unallocated_encoding(s
);
9051 if (need_fpstatus
) {
9052 tcg_fpstatus
= get_fpstatus_ptr();
9054 TCGV_UNUSED_PTR(tcg_fpstatus
);
9057 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9058 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9060 TCGV_UNUSED_I32(tcg_rmode
);
9064 /* All 64-bit element operations can be shared with scalar 2misc */
9067 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9068 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9069 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9071 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9073 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9074 tcg_rmode
, tcg_fpstatus
);
9076 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9078 tcg_temp_free_i64(tcg_res
);
9079 tcg_temp_free_i64(tcg_op
);
9084 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9085 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9086 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9089 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9092 /* Special cases for 32 bit elements */
9094 case 0xa: /* CMLT */
9095 /* 32 bit integer comparison against zero, result is
9096 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9101 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9102 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9104 case 0x8: /* CMGT, CMGE */
9105 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9107 case 0x9: /* CMEQ, CMLE */
9108 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9112 gen_helper_clz32(tcg_res
, tcg_op
);
9114 gen_helper_cls32(tcg_res
, tcg_op
);
9117 case 0xb: /* ABS, NEG */
9119 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9121 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9122 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9123 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
9124 tcg_zero
, tcg_op
, tcg_res
);
9125 tcg_temp_free_i32(tcg_zero
);
9128 case 0x2f: /* FABS */
9129 gen_helper_vfp_abss(tcg_res
, tcg_op
);
9131 case 0x6f: /* FNEG */
9132 gen_helper_vfp_negs(tcg_res
, tcg_op
);
9134 case 0x7f: /* FSQRT */
9135 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
9137 case 0x1a: /* FCVTNS */
9138 case 0x1b: /* FCVTMS */
9139 case 0x1c: /* FCVTAS */
9140 case 0x3a: /* FCVTPS */
9141 case 0x3b: /* FCVTZS */
9143 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9144 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
9145 tcg_shift
, tcg_fpstatus
);
9146 tcg_temp_free_i32(tcg_shift
);
9149 case 0x5a: /* FCVTNU */
9150 case 0x5b: /* FCVTMU */
9151 case 0x5c: /* FCVTAU */
9152 case 0x7a: /* FCVTPU */
9153 case 0x7b: /* FCVTZU */
9155 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9156 gen_helper_vfp_touls(tcg_res
, tcg_op
,
9157 tcg_shift
, tcg_fpstatus
);
9158 tcg_temp_free_i32(tcg_shift
);
9161 case 0x18: /* FRINTN */
9162 case 0x19: /* FRINTM */
9163 case 0x38: /* FRINTP */
9164 case 0x39: /* FRINTZ */
9165 case 0x58: /* FRINTA */
9166 case 0x79: /* FRINTI */
9167 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
9169 case 0x59: /* FRINTX */
9170 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
9173 g_assert_not_reached();
9176 /* Use helpers for 8 and 16 bit elements */
9178 case 0x5: /* CNT, RBIT */
9179 /* For these two insns size is part of the opcode specifier
9180 * (handled earlier); they always operate on byte elements.
9183 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
9185 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
9188 case 0x8: /* CMGT, CMGE */
9189 case 0x9: /* CMEQ, CMLE */
9190 case 0xa: /* CMLT */
9192 static NeonGenTwoOpFn
* const fns
[3][2] = {
9193 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
9194 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
9195 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
9197 NeonGenTwoOpFn
*genfn
;
9200 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9202 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
9203 comp
= (opcode
- 0x8) * 2 + u
;
9204 /* ...but LE, LT are implemented as reverse GE, GT */
9205 reverse
= (comp
> 2);
9209 genfn
= fns
[comp
][size
];
9211 genfn(tcg_res
, tcg_zero
, tcg_op
);
9213 genfn(tcg_res
, tcg_op
, tcg_zero
);
9215 tcg_temp_free_i32(tcg_zero
);
9218 case 0xb: /* ABS, NEG */
9220 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9222 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
9224 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
9226 tcg_temp_free_i32(tcg_zero
);
9229 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
9231 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
9235 case 0x4: /* CLS, CLZ */
9238 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
9240 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
9244 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
9246 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
9251 g_assert_not_reached();
9255 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9257 tcg_temp_free_i32(tcg_res
);
9258 tcg_temp_free_i32(tcg_op
);
9262 clear_vec_high(s
, rd
);
9266 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9267 tcg_temp_free_i32(tcg_rmode
);
9269 if (need_fpstatus
) {
9270 tcg_temp_free_ptr(tcg_fpstatus
);
9274 /* C3.6.13 AdvSIMD scalar x indexed element
9275 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
9276 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
9277 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
9278 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
9279 * C3.6.18 AdvSIMD vector x indexed element
9280 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
9281 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
9282 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
9283 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
9285 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
9287 /* This encoding has two kinds of instruction:
9288 * normal, where we perform elt x idxelt => elt for each
9289 * element in the vector
9290 * long, where we perform elt x idxelt and generate a result of
9291 * double the width of the input element
9292 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
9294 bool is_scalar
= extract32(insn
, 28, 1);
9295 bool is_q
= extract32(insn
, 30, 1);
9296 bool u
= extract32(insn
, 29, 1);
9297 int size
= extract32(insn
, 22, 2);
9298 int l
= extract32(insn
, 21, 1);
9299 int m
= extract32(insn
, 20, 1);
9300 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
9301 int rm
= extract32(insn
, 16, 4);
9302 int opcode
= extract32(insn
, 12, 4);
9303 int h
= extract32(insn
, 11, 1);
9304 int rn
= extract32(insn
, 5, 5);
9305 int rd
= extract32(insn
, 0, 5);
9306 bool is_long
= false;
9314 if (!u
|| is_scalar
) {
9315 unallocated_encoding(s
);
9319 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9320 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9321 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
9323 unallocated_encoding(s
);
9328 case 0x3: /* SQDMLAL, SQDMLAL2 */
9329 case 0x7: /* SQDMLSL, SQDMLSL2 */
9330 case 0xb: /* SQDMULL, SQDMULL2 */
9333 case 0xc: /* SQDMULH */
9334 case 0xd: /* SQRDMULH */
9336 unallocated_encoding(s
);
9341 if (u
|| is_scalar
) {
9342 unallocated_encoding(s
);
9346 case 0x1: /* FMLA */
9347 case 0x5: /* FMLS */
9349 unallocated_encoding(s
);
9353 case 0x9: /* FMUL, FMULX */
9354 if (!extract32(size
, 1, 1)) {
9355 unallocated_encoding(s
);
9361 unallocated_encoding(s
);
9366 /* low bit of size indicates single/double */
9367 size
= extract32(size
, 0, 1) ? 3 : 2;
9372 unallocated_encoding(s
);
9381 index
= h
<< 2 | l
<< 1 | m
;
9388 unallocated_encoding(s
);
9394 fpst
= get_fpstatus_ptr();
9396 TCGV_UNUSED_PTR(fpst
);
9400 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
9403 assert(is_fp
&& is_q
&& !is_long
);
9405 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
9407 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9408 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9409 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9411 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9414 case 0x5: /* FMLS */
9415 /* As usual for ARM, separate negation for fused multiply-add */
9416 gen_helper_vfp_negd(tcg_op
, tcg_op
);
9418 case 0x1: /* FMLA */
9419 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9420 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
9422 case 0x9: /* FMUL, FMULX */
9424 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9426 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9430 g_assert_not_reached();
9433 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9434 tcg_temp_free_i64(tcg_op
);
9435 tcg_temp_free_i64(tcg_res
);
9439 clear_vec_high(s
, rd
);
9442 tcg_temp_free_i64(tcg_idx
);
9443 } else if (!is_long
) {
9444 /* 32 bit floating point, or 16 or 32 bit integer.
9445 * For the 16 bit scalar case we use the usual Neon helpers and
9446 * rely on the fact that 0 op 0 == 0 with no side effects.
9448 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
9449 int pass
, maxpasses
;
9454 maxpasses
= is_q
? 4 : 2;
9457 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
9459 if (size
== 1 && !is_scalar
) {
9460 /* The simplest way to handle the 16x16 indexed ops is to duplicate
9461 * the index into both halves of the 32 bit tcg_idx and then use
9462 * the usual Neon helpers.
9464 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
9467 for (pass
= 0; pass
< maxpasses
; pass
++) {
9468 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9469 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9471 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
9478 static NeonGenTwoOpFn
* const fns
[2][2] = {
9479 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9480 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9482 NeonGenTwoOpFn
*genfn
;
9483 bool is_sub
= opcode
== 0x4;
9486 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
9488 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
9490 if (opcode
== 0x8) {
9493 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
9494 genfn
= fns
[size
- 1][is_sub
];
9495 genfn(tcg_res
, tcg_op
, tcg_res
);
9498 case 0x5: /* FMLS */
9499 /* As usual for ARM, separate negation for fused multiply-add */
9500 gen_helper_vfp_negs(tcg_op
, tcg_op
);
9502 case 0x1: /* FMLA */
9503 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9504 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
9506 case 0x9: /* FMUL, FMULX */
9508 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9510 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9513 case 0xc: /* SQDMULH */
9515 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
9518 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
9522 case 0xd: /* SQRDMULH */
9524 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
9527 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
9532 g_assert_not_reached();
9536 write_fp_sreg(s
, rd
, tcg_res
);
9538 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9541 tcg_temp_free_i32(tcg_op
);
9542 tcg_temp_free_i32(tcg_res
);
9545 tcg_temp_free_i32(tcg_idx
);
9548 clear_vec_high(s
, rd
);
9551 /* long ops: 16x16->32 or 32x32->64 */
9552 TCGv_i64 tcg_res
[2];
9554 bool satop
= extract32(opcode
, 0, 1);
9555 TCGMemOp memop
= MO_32
;
9562 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
9564 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
9566 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9567 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9568 TCGv_i64 tcg_passres
;
9574 passelt
= pass
+ (is_q
* 2);
9577 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
9579 tcg_res
[pass
] = tcg_temp_new_i64();
9581 if (opcode
== 0xa || opcode
== 0xb) {
9582 /* Non-accumulating ops */
9583 tcg_passres
= tcg_res
[pass
];
9585 tcg_passres
= tcg_temp_new_i64();
9588 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
9589 tcg_temp_free_i64(tcg_op
);
9592 /* saturating, doubling */
9593 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
9594 tcg_passres
, tcg_passres
);
9597 if (opcode
== 0xa || opcode
== 0xb) {
9601 /* Accumulating op: handle accumulate step */
9602 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9605 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9606 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9608 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9609 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9611 case 0x7: /* SQDMLSL, SQDMLSL2 */
9612 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
9614 case 0x3: /* SQDMLAL, SQDMLAL2 */
9615 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
9620 g_assert_not_reached();
9622 tcg_temp_free_i64(tcg_passres
);
9624 tcg_temp_free_i64(tcg_idx
);
9627 clear_vec_high(s
, rd
);
9630 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
9633 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
9636 /* The simplest way to handle the 16x16 indexed ops is to
9637 * duplicate the index into both halves of the 32 bit tcg_idx
9638 * and then use the usual Neon helpers.
9640 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
9643 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9644 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9645 TCGv_i64 tcg_passres
;
9648 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9650 read_vec_element_i32(s
, tcg_op
, rn
,
9651 pass
+ (is_q
* 2), MO_32
);
9654 tcg_res
[pass
] = tcg_temp_new_i64();
9656 if (opcode
== 0xa || opcode
== 0xb) {
9657 /* Non-accumulating ops */
9658 tcg_passres
= tcg_res
[pass
];
9660 tcg_passres
= tcg_temp_new_i64();
9663 if (memop
& MO_SIGN
) {
9664 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
9666 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
9669 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
9670 tcg_passres
, tcg_passres
);
9672 tcg_temp_free_i32(tcg_op
);
9674 if (opcode
== 0xa || opcode
== 0xb) {
9678 /* Accumulating op: handle accumulate step */
9679 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9682 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9683 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
9686 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9687 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
9690 case 0x7: /* SQDMLSL, SQDMLSL2 */
9691 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
9693 case 0x3: /* SQDMLAL, SQDMLAL2 */
9694 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
9699 g_assert_not_reached();
9701 tcg_temp_free_i64(tcg_passres
);
9703 tcg_temp_free_i32(tcg_idx
);
9706 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
9711 tcg_res
[1] = tcg_const_i64(0);
9714 for (pass
= 0; pass
< 2; pass
++) {
9715 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9716 tcg_temp_free_i64(tcg_res
[pass
]);
9720 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9721 tcg_temp_free_ptr(fpst
);
9725 /* C3.6.19 Crypto AES
9726 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
9727 * +-----------------+------+-----------+--------+-----+------+------+
9728 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
9729 * +-----------------+------+-----------+--------+-----+------+------+
9731 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
9733 unsupported_encoding(s
, insn
);
9736 /* C3.6.20 Crypto three-reg SHA
9737 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
9738 * +-----------------+------+---+------+---+--------+-----+------+------+
9739 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
9740 * +-----------------+------+---+------+---+--------+-----+------+------+
9742 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
9744 unsupported_encoding(s
, insn
);
9747 /* C3.6.21 Crypto two-reg SHA
9748 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
9749 * +-----------------+------+-----------+--------+-----+------+------+
9750 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
9751 * +-----------------+------+-----------+--------+-----+------+------+
9753 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
9755 unsupported_encoding(s
, insn
);
9758 /* C3.6 Data processing - SIMD, inc Crypto
9760 * As the decode gets a little complex we are using a table based
9761 * approach for this part of the decode.
9763 static const AArch64DecodeTable data_proc_simd
[] = {
9764 /* pattern , mask , fn */
9765 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
9766 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
9767 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
9768 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
9769 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
9770 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
9771 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
9772 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
9773 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
9774 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
9775 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
9776 { 0x2e000000, 0xbf208400, disas_simd_ext
},
9777 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
9778 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
9779 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
9780 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
9781 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
9782 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
9783 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
9784 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
9785 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
9786 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
9787 { 0x00000000, 0x00000000, NULL
}
9790 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
9792 /* Note that this is called with all non-FP cases from
9793 * table C3-6 so it must UNDEF for entries not specifically
9794 * allocated to instructions in that table.
9796 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
9800 unallocated_encoding(s
);
9804 /* C3.6 Data processing - SIMD and floating point */
9805 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
9807 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
9808 disas_data_proc_fp(s
, insn
);
9810 /* SIMD, including crypto */
9811 disas_data_proc_simd(s
, insn
);
9815 /* C3.1 A64 instruction index by encoding */
9816 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
9820 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
9824 switch (extract32(insn
, 25, 4)) {
9825 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
9826 unallocated_encoding(s
);
9828 case 0x8: case 0x9: /* Data processing - immediate */
9829 disas_data_proc_imm(s
, insn
);
9831 case 0xa: case 0xb: /* Branch, exception generation and system insns */
9832 disas_b_exc_sys(s
, insn
);
9837 case 0xe: /* Loads and stores */
9838 disas_ldst(s
, insn
);
9841 case 0xd: /* Data processing - register */
9842 disas_data_proc_reg(s
, insn
);
9845 case 0xf: /* Data processing - SIMD and floating point */
9846 disas_data_proc_simd_fp(s
, insn
);
9849 assert(FALSE
); /* all 15 cases should be handled above */
9853 /* if we allocated any temporaries, free them here */
9857 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
9858 TranslationBlock
*tb
,
9861 CPUState
*cs
= CPU(cpu
);
9862 CPUARMState
*env
= &cpu
->env
;
9863 DisasContext dc1
, *dc
= &dc1
;
9865 uint16_t *gen_opc_end
;
9867 target_ulong pc_start
;
9868 target_ulong next_page_start
;
9876 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
9878 dc
->is_jmp
= DISAS_NEXT
;
9880 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
9886 dc
->condexec_mask
= 0;
9887 dc
->condexec_cond
= 0;
9888 #if !defined(CONFIG_USER_ONLY)
9889 dc
->user
= (ARM_TBFLAG_AA64_EL(tb
->flags
) == 0);
9891 dc
->vfp_enabled
= 0;
9894 dc
->cp_regs
= cpu
->cp_regs
;
9895 dc
->current_pl
= arm_current_pl(env
);
9896 dc
->features
= env
->features
;
9898 init_tmp_a64_array(dc
);
9900 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
9903 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9904 if (max_insns
== 0) {
9905 max_insns
= CF_COUNT_MASK
;
9910 tcg_clear_temp_count();
9913 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
9914 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
9915 if (bp
->pc
== dc
->pc
) {
9916 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
9917 /* Advance PC so that clearing the breakpoint will
9918 invalidate this TB. */
9920 goto done_generating
;
9926 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
9930 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
9933 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
9934 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
9935 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
9938 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
9942 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
9943 tcg_gen_debug_insn_start(dc
->pc
);
9946 disas_a64_insn(env
, dc
);
9948 if (tcg_check_temp_count()) {
9949 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
9953 /* Translation stops when a conditional branch is encountered.
9954 * Otherwise the subsequent code could get translated several times.
9955 * Also stop translation when a page boundary is reached. This
9956 * ensures prefetch aborts occur at the right place.
9959 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
9960 !cs
->singlestep_enabled
&&
9962 dc
->pc
< next_page_start
&&
9963 num_insns
< max_insns
);
9965 if (tb
->cflags
& CF_LAST_IO
) {
9969 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
9970 /* Note that this means single stepping WFI doesn't halt the CPU.
9971 * For conditional branch insns this is harmless unreachable code as
9972 * gen_goto_tb() has already handled emitting the debug exception
9973 * (and thus a tb-jump is not possible when singlestepping).
9975 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
9976 if (dc
->is_jmp
!= DISAS_JUMP
) {
9977 gen_a64_set_pc_im(dc
->pc
);
9979 gen_exception(EXCP_DEBUG
);
9981 switch (dc
->is_jmp
) {
9983 gen_goto_tb(dc
, 1, dc
->pc
);
9987 gen_a64_set_pc_im(dc
->pc
);
9990 /* indicate that the hash table must be used to find the next TB */
9998 /* This is a special case because we don't want to just halt the CPU
9999 * if trying to debug across a WFI.
10001 gen_a64_set_pc_im(dc
->pc
);
10002 gen_helper_wfi(cpu_env
);
10008 gen_tb_end(tb
, num_insns
);
10009 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
10012 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
10013 qemu_log("----------------\n");
10014 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
10015 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
10016 4 | (dc
->bswap_code
<< 1));
10021 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10024 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10027 tb
->size
= dc
->pc
- pc_start
;
10028 tb
->icount
= num_insns
;