hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/ppc/mac.h"
  28 #include "hw/ppc/mac_dbdma.h"
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/dma.h"
  31
  32 #include <hw/ide/internal.h>
  33
  34 /* debug MACIO */
  35 // #define DEBUG_MACIO
  36
  37 #ifdef DEBUG_MACIO
  38 static const int debug_macio = 1;
  39 #else
  40 static const int debug_macio = 0;
  41 #endif
  42
  43 #define MACIO_DPRINTF(fmt, ...) do { \
  44         if (debug_macio) { \
  45             printf(fmt , ## __VA_ARGS__); \
  46         } \
  47     } while (0)
  48
  49
  50 /***********************************************************/
  51 /* MacIO based PowerPC IDE */
  52
  53 #define MACIO_PAGE_SIZE 4096
  54
  55 /*
  56  * Unaligned DMA read/write access functions required for OS X/Darwin which
  57  * don't perform DMA transactions on sector boundaries. These functions are
  58  * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
  59  * easy to remove if the unaligned block APIs are ever exposed.
  60  */
  61
  62 static void pmac_dma_read(BlockBackend *blk,
  63                           int64_t offset, unsigned int bytes,
  64                           void (*cb)(void *opaque, int ret), void *opaque)
  65 {
  66     DBDMA_io *io = opaque;
  67     MACIOIDEState *m = io->opaque;
  68     IDEState *s = idebus_active_if(&m->bus);
  69     dma_addr_t dma_addr, dma_len;
  70     void *mem;
  71     int64_t sector_num;
  72     int nsector;
  73     uint64_t align = BDRV_SECTOR_SIZE;
  74     size_t head_bytes, tail_bytes;
  75
  76     qemu_iovec_destroy(&io->iov);
  77     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
  78
  79     sector_num = (offset >> 9);
  80     nsector = (io->len >> 9);
  81
  82     MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
  83                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
  84                   sector_num, nsector);
  85
  86     dma_addr = io->addr;
  87     dma_len = io->len;
  88     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
  89                          DMA_DIRECTION_FROM_DEVICE);
  90
  91     if (offset & (align - 1)) {
  92         head_bytes = offset & (align - 1);
  93
  94         MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
  95                       "discarding %zu bytes\n", sector_num, head_bytes);
  96
  97         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
  98
  99         bytes += offset & (align - 1);
 100         offset = offset & ~(align - 1);
 101     }
 102
 103     qemu_iovec_add(&io->iov, mem, io->len);
 104
 105     if ((offset + bytes) & (align - 1)) {
 106         tail_bytes = (offset + bytes) & (align - 1);
 107
 108         MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
 109                       "discarding bytes %zu\n", sector_num, tail_bytes);
 110
 111         qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
 112         bytes = ROUND_UP(bytes, align);
 113     }
 114
 115     s->io_buffer_size -= io->len;
 116     s->io_buffer_index += io->len;
 117
 118     io->len = 0;
 119
 120     MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 "  "
 121                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 122
 123     s->bus->dma->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov,
 124                              (bytes >> 9), cb, io);
 125 }
 126
 127 static void pmac_dma_write(BlockBackend *blk,
 128                          int64_t offset, int bytes,
 129                          void (*cb)(void *opaque, int ret), void *opaque)
 130 {
 131     DBDMA_io *io = opaque;
 132     MACIOIDEState *m = io->opaque;
 133     IDEState *s = idebus_active_if(&m->bus);
 134     dma_addr_t dma_addr, dma_len;
 135     void *mem;
 136     int64_t sector_num;
 137     int nsector;
 138     uint64_t align = BDRV_SECTOR_SIZE;
 139     size_t head_bytes, tail_bytes;
 140     bool unaligned_head = false, unaligned_tail = false;
 141
 142     qemu_iovec_destroy(&io->iov);
 143     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
 144
 145     sector_num = (offset >> 9);
 146     nsector = (io->len >> 9);
 147
 148     MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
 149                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
 150                   sector_num, nsector);
 151
 152     dma_addr = io->addr;
 153     dma_len = io->len;
 154     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
 155                          DMA_DIRECTION_TO_DEVICE);
 156
 157     if (offset & (align - 1)) {
 158         head_bytes = offset & (align - 1);
 159         sector_num = ((offset & ~(align - 1)) >> 9);
 160
 161         MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
 162                       PRId64 "\n", sector_num);
 163
 164         blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
 165
 166         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
 167         qemu_iovec_add(&io->iov, mem, io->len);
 168
 169         bytes += offset & (align - 1);
 170         offset = offset & ~(align - 1);
 171
 172         unaligned_head = true;
 173     }
 174
 175     if ((offset + bytes) & (align - 1)) {
 176         tail_bytes = (offset + bytes) & (align - 1);
 177         sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
 178
 179         MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
 180                       PRId64 "\n", sector_num);
 181
 182         blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
 183
 184         if (!unaligned_head) {
 185             qemu_iovec_add(&io->iov, mem, io->len);
 186         }
 187
 188         qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
 189                        align - tail_bytes);
 190
 191         bytes = ROUND_UP(bytes, align);
 192
 193         unaligned_tail = true;
 194     }
 195
 196     if (!unaligned_head && !unaligned_tail) {
 197         qemu_iovec_add(&io->iov, mem, io->len);
 198     }
 199
 200     s->io_buffer_size -= io->len;
 201     s->io_buffer_index += io->len;
 202
 203     io->len = 0;
 204
 205     MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 "  "
 206                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 207
 208     s->bus->dma->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov,
 209                              (bytes >> 9), cb, io);
 210 }
 211
 212 static void pmac_dma_trim(BlockBackend *blk,
 213                         int64_t offset, int bytes,
 214                         void (*cb)(void *opaque, int ret), void *opaque)
 215 {
 216     DBDMA_io *io = opaque;
 217     MACIOIDEState *m = io->opaque;
 218     IDEState *s = idebus_active_if(&m->bus);
 219     dma_addr_t dma_addr, dma_len;
 220     void *mem;
 221
 222     qemu_iovec_destroy(&io->iov);
 223     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
 224
 225     dma_addr = io->addr;
 226     dma_len = io->len;
 227     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
 228                          DMA_DIRECTION_TO_DEVICE);
 229
 230     qemu_iovec_add(&io->iov, mem, io->len);
 231     s->io_buffer_size -= io->len;
 232     s->io_buffer_index += io->len;
 233     io->len = 0;
 234
 235     s->bus->dma->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov,
 236                              (bytes >> 9), cb, io);
 237 }
 238
 239 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
 240 {
 241     DBDMA_io *io = opaque;
 242     MACIOIDEState *m = io->opaque;
 243     IDEState *s = idebus_active_if(&m->bus);
 244     int64_t offset;
 245
 246     MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
 247
 248     if (ret < 0) {
 249         MACIO_DPRINTF("DMA error: %d\n", ret);
 250         ide_atapi_io_error(s, ret);
 251         goto done;
 252     }
 253
 254     if (!m->dma_active) {
 255         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 256                       s->nsector, io->len, s->status);
 257         /* data not ready yet, wait for the channel to get restarted */
 258         io->processing = false;
 259         return;
 260     }
 261
 262     if (s->io_buffer_size <= 0) {
 263         MACIO_DPRINTF("End of IDE transfer\n");
 264         ide_atapi_cmd_ok(s);
 265         m->dma_active = false;
 266         goto done;
 267     }
 268
 269     if (io->len == 0) {
 270         MACIO_DPRINTF("End of DMA transfer\n");
 271         goto done;
 272     }
 273
 274     if (s->lba == -1) {
 275         /* Non-block ATAPI transfer - just copy to RAM */
 276         s->io_buffer_size = MIN(s->io_buffer_size, io->len);
 277         cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
 278         ide_atapi_cmd_ok(s);
 279         m->dma_active = false;
 280         goto done;
 281     }
 282
 283     /* Calculate current offset */
 284     offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
 285
 286     pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
 287     return;
 288
 289 done:
 290     if (ret < 0) {
 291         block_acct_failed(blk_get_stats(s->blk), &s->acct);
 292     } else {
 293         block_acct_done(blk_get_stats(s->blk), &s->acct);
 294     }
 295
 296     ide_set_inactive(s, false);
 297     io->dma_end(opaque);
 298 }
 299
 300 static void pmac_ide_transfer_cb(void *opaque, int ret)
 301 {
 302     DBDMA_io *io = opaque;
 303     MACIOIDEState *m = io->opaque;
 304     IDEState *s = idebus_active_if(&m->bus);
 305     int64_t offset;
 306
 307     MACIO_DPRINTF("pmac_ide_transfer_cb\n");
 308
 309     if (ret < 0) {
 310         MACIO_DPRINTF("DMA error: %d\n", ret);
 311         ide_dma_error(s);
 312         goto done;
 313     }
 314
 315     if (!m->dma_active) {
 316         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 317                       s->nsector, io->len, s->status);
 318         /* data not ready yet, wait for the channel to get restarted */
 319         io->processing = false;
 320         return;
 321     }
 322
 323     if (s->io_buffer_size <= 0) {
 324         MACIO_DPRINTF("End of IDE transfer\n");
 325         s->status = READY_STAT | SEEK_STAT;
 326         ide_set_irq(s->bus);
 327         m->dma_active = false;
 328         goto done;
 329     }
 330
 331     if (io->len == 0) {
 332         MACIO_DPRINTF("End of DMA transfer\n");
 333         goto done;
 334     }
 335
 336     /* Calculate number of sectors */
 337     offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
 338
 339     switch (s->dma_cmd) {
 340     case IDE_DMA_READ:
 341         pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 342         break;
 343     case IDE_DMA_WRITE:
 344         pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 345         break;
 346     case IDE_DMA_TRIM:
 347         pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 348         break;
 349     }
 350
 351     return;
 352
 353 done:
 354     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 355         if (ret < 0) {
 356             block_acct_failed(blk_get_stats(s->blk), &s->acct);
 357         } else {
 358             block_acct_done(blk_get_stats(s->blk), &s->acct);
 359         }
 360     }
 361
 362     ide_set_inactive(s, false);
 363     io->dma_end(opaque);
 364 }
 365
 366 static void pmac_ide_transfer(DBDMA_io *io)
 367 {
 368     MACIOIDEState *m = io->opaque;
 369     IDEState *s = idebus_active_if(&m->bus);
 370
 371     MACIO_DPRINTF("\n");
 372
 373     if (s->drive_kind == IDE_CD) {
 374         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 375                          BLOCK_ACCT_READ);
 376
 377         pmac_ide_atapi_transfer_cb(io, 0);
 378         return;
 379     }
 380
 381     switch (s->dma_cmd) {
 382     case IDE_DMA_READ:
 383         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 384                          BLOCK_ACCT_READ);
 385         break;
 386     case IDE_DMA_WRITE:
 387         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 388                          BLOCK_ACCT_WRITE);
 389         break;
 390     default:
 391         break;
 392     }
 393
 394     pmac_ide_transfer_cb(io, 0);
 395 }
 396
 397 static void pmac_ide_flush(DBDMA_io *io)
 398 {
 399     MACIOIDEState *m = io->opaque;
 400     IDEState *s = idebus_active_if(&m->bus);
 401
 402     if (s->bus->dma->aiocb) {
 403         blk_drain_all();
 404     }
 405 }
 406
 407 /* PowerMac IDE memory IO */
 408 static void pmac_ide_writeb (void *opaque,
 409                              hwaddr addr, uint32_t val)
 410 {
 411     MACIOIDEState *d = opaque;
 412
 413     addr = (addr & 0xFFF) >> 4;
 414     switch (addr) {
 415     case 1 ... 7:
 416         ide_ioport_write(&d->bus, addr, val);
 417         break;
 418     case 8:
 419     case 22:
 420         ide_cmd_write(&d->bus, 0, val);
 421         break;
 422     default:
 423         break;
 424     }
 425 }
 426
 427 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
 428 {
 429     uint8_t retval;
 430     MACIOIDEState *d = opaque;
 431
 432     addr = (addr & 0xFFF) >> 4;
 433     switch (addr) {
 434     case 1 ... 7:
 435         retval = ide_ioport_read(&d->bus, addr);
 436         break;
 437     case 8:
 438     case 22:
 439         retval = ide_status_read(&d->bus, 0);
 440         break;
 441     default:
 442         retval = 0xFF;
 443         break;
 444     }
 445     return retval;
 446 }
 447
 448 static void pmac_ide_writew (void *opaque,
 449                              hwaddr addr, uint32_t val)
 450 {
 451     MACIOIDEState *d = opaque;
 452
 453     addr = (addr & 0xFFF) >> 4;
 454     val = bswap16(val);
 455     if (addr == 0) {
 456         ide_data_writew(&d->bus, 0, val);
 457     }
 458 }
 459
 460 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
 461 {
 462     uint16_t retval;
 463     MACIOIDEState *d = opaque;
 464
 465     addr = (addr & 0xFFF) >> 4;
 466     if (addr == 0) {
 467         retval = ide_data_readw(&d->bus, 0);
 468     } else {
 469         retval = 0xFFFF;
 470     }
 471     retval = bswap16(retval);
 472     return retval;
 473 }
 474
 475 static void pmac_ide_writel (void *opaque,
 476                              hwaddr addr, uint32_t val)
 477 {
 478     MACIOIDEState *d = opaque;
 479
 480     addr = (addr & 0xFFF) >> 4;
 481     val = bswap32(val);
 482     if (addr == 0) {
 483         ide_data_writel(&d->bus, 0, val);
 484     }
 485 }
 486
 487 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
 488 {
 489     uint32_t retval;
 490     MACIOIDEState *d = opaque;
 491
 492     addr = (addr & 0xFFF) >> 4;
 493     if (addr == 0) {
 494         retval = ide_data_readl(&d->bus, 0);
 495     } else {
 496         retval = 0xFFFFFFFF;
 497     }
 498     retval = bswap32(retval);
 499     return retval;
 500 }
 501
 502 static const MemoryRegionOps pmac_ide_ops = {
 503     .old_mmio = {
 504         .write = {
 505             pmac_ide_writeb,
 506             pmac_ide_writew,
 507             pmac_ide_writel,
 508         },
 509         .read = {
 510             pmac_ide_readb,
 511             pmac_ide_readw,
 512             pmac_ide_readl,
 513         },
 514     },
 515     .endianness = DEVICE_NATIVE_ENDIAN,
 516 };
 517
 518 static const VMStateDescription vmstate_pmac = {
 519     .name = "ide",
 520     .version_id = 3,
 521     .minimum_version_id = 0,
 522     .fields = (VMStateField[]) {
 523         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 524         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 525         VMSTATE_END_OF_LIST()
 526     }
 527 };
 528
 529 static void macio_ide_reset(DeviceState *dev)
 530 {
 531     MACIOIDEState *d = MACIO_IDE(dev);
 532
 533     ide_bus_reset(&d->bus);
 534 }
 535
 536 static int ide_nop_int(IDEDMA *dma, int x)
 537 {
 538     return 0;
 539 }
 540
 541 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
 542 {
 543     return 0;
 544 }
 545
 546 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
 547                             BlockCompletionFunc *cb)
 548 {
 549     MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
 550
 551     s->io_buffer_index = 0;
 552     if (s->drive_kind == IDE_CD) {
 553         s->io_buffer_size = s->packet_transfer_size;
 554     } else {
 555         s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
 556     }
 557
 558     MACIO_DPRINTF("\n\n------------ IDE transfer\n");
 559     MACIO_DPRINTF("buffer_size: %x   buffer_index: %x\n",
 560                   s->io_buffer_size, s->io_buffer_index);
 561     MACIO_DPRINTF("lba: %x    size: %x\n", s->lba, s->io_buffer_size);
 562     MACIO_DPRINTF("-------------------------\n");
 563
 564     m->dma_active = true;
 565     DBDMA_kick(m->dbdma);
 566 }
 567
 568 static const IDEDMAOps dbdma_ops = {
 569     .start_dma      = ide_dbdma_start,
 570     .prepare_buf    = ide_nop_int32,
 571     .rw_buf         = ide_nop_int,
 572 };
 573
 574 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
 575 {
 576     MACIOIDEState *s = MACIO_IDE(dev);
 577
 578     ide_init2(&s->bus, s->irq);
 579
 580     /* Register DMA callbacks */
 581     s->dma.ops = &dbdma_ops;
 582     s->bus.dma = &s->dma;
 583 }
 584
 585 static void macio_ide_initfn(Object *obj)
 586 {
 587     SysBusDevice *d = SYS_BUS_DEVICE(obj);
 588     MACIOIDEState *s = MACIO_IDE(obj);
 589
 590     ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
 591     memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
 592     sysbus_init_mmio(d, &s->mem);
 593     sysbus_init_irq(d, &s->irq);
 594     sysbus_init_irq(d, &s->dma_irq);
 595 }
 596
 597 static void macio_ide_class_init(ObjectClass *oc, void *data)
 598 {
 599     DeviceClass *dc = DEVICE_CLASS(oc);
 600
 601     dc->realize = macio_ide_realizefn;
 602     dc->reset = macio_ide_reset;
 603     dc->vmsd = &vmstate_pmac;
 604     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 605 }
 606
 607 static const TypeInfo macio_ide_type_info = {
 608     .name = TYPE_MACIO_IDE,
 609     .parent = TYPE_SYS_BUS_DEVICE,
 610     .instance_size = sizeof(MACIOIDEState),
 611     .instance_init = macio_ide_initfn,
 612     .class_init = macio_ide_class_init,
 613 };
 614
 615 static void macio_ide_register_types(void)
 616 {
 617     type_register_static(&macio_ide_type_info);
 618 }
 619
 620 /* hd_table must contain 2 block drivers */
 621 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
 622 {
 623     int i;
 624
 625     for (i = 0; i < 2; i++) {
 626         if (hd_table[i]) {
 627             ide_create_drive(&s->bus, i, hd_table[i]);
 628         }
 629     }
 630 }
 631
 632 void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
 633 {
 634     s->dbdma = dbdma;
 635     DBDMA_register_channel(dbdma, channel, s->dma_irq,
 636                            pmac_ide_transfer, pmac_ide_flush, s);
 637 }
 638
 639 type_init(macio_ide_register_types)