| blob | b20c38ca7337a6e24ec5580b47926cf8fa026920 |
1 /*
2 * New-style decoder for i386 instructions
3 *
4 * Copyright (c) 2022 Red Hat, Inc.
5 *
6 * Author: Paolo Bonzini <pbonzini@redhat.com>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
22 /*
23 * The decoder is mostly based on tables copied from the Intel SDM. As
24 * a result, most operand load and writeback is done entirely in common
25 * table-driven code using the same operand type (X86_TYPE_*) and
26 * size (X86_SIZE_*) codes used in the manual.
27 *
28 * The main difference is that the V, U and W types are extended to
29 * cover MMX as well; if an instruction is like
30 *
31 * por Pq, Qq
32 * 66 por Vx, Hx, Wx
33 *
34 * only the second row is included and the instruction is marked as a
35 * valid MMX instruction. The MMX flag directs the decoder to rewrite
36 * the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing
37 * "x" to "q" if there is no prefix.
38 *
39 * In addition, the ss/ps/sd/pd types are sometimes mushed together as "x"
40 * if the difference is expressed via prefixes. Individual instructions
41 * are separated by prefix in the generator functions.
42 *
43 * There are a couple cases in which instructions (e.g. MOVD) write the
44 * whole XMM or MM register but are established incorrectly in the manual
45 * as "d" or "q". These have to be fixed for the decoder to work correctly.
46 */
48 #define X86_OP_NONE { 0 },
50 #define X86_OP_GROUP3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
51 .decode = glue(decode_, op), \
52 .op0 = glue(X86_TYPE_, op0_), \
53 .s0 = glue(X86_SIZE_, s0_), \
54 .op1 = glue(X86_TYPE_, op1_), \
55 .s1 = glue(X86_SIZE_, s1_), \
56 .op2 = glue(X86_TYPE_, op2_), \
57 .s2 = glue(X86_SIZE_, s2_), \
58 .is_decode = true, \
59 ## __VA_ARGS__ \
60 }
62 #define X86_OP_GROUP2(op, op0, s0, op1, s1, ...) \
63 X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
64 #define X86_OP_GROUP0(op, ...) \
65 X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__)
67 #define X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
68 .gen = glue(gen_, op), \
69 .op0 = glue(X86_TYPE_, op0_), \
70 .s0 = glue(X86_SIZE_, s0_), \
71 .op1 = glue(X86_TYPE_, op1_), \
72 .s1 = glue(X86_SIZE_, s1_), \
73 .op2 = glue(X86_TYPE_, op2_), \
74 .s2 = glue(X86_SIZE_, s2_), \
75 ## __VA_ARGS__ \
76 }
78 #define X86_OP_ENTRY4(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) \
79 X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, \
80 .op3 = X86_TYPE_I, .s3 = X86_SIZE_b, \
81 ## __VA_ARGS__)
83 #define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \
84 X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
85 #define X86_OP_ENTRY0(op, ...) \
86 X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
88 #define cpuid(feat) .cpuid = X86_FEAT_##feat,
89 #define i64 .special = X86_SPECIAL_i64,
90 #define o64 .special = X86_SPECIAL_o64,
91 #define xchg .special = X86_SPECIAL_Locked,
92 #define mmx .special = X86_SPECIAL_MMX,
93 #define zext0 .special = X86_SPECIAL_ZExtOp0,
94 #define zext2 .special = X86_SPECIAL_ZExtOp2,
96 #define vex1 .vex_class = 1,
97 #define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar,
98 #define vex2 .vex_class = 2,
99 #define vex2_rep3 .vex_class = 2, .vex_special = X86_VEX_REPScalar,
100 #define vex3 .vex_class = 3,
101 #define vex4 .vex_class = 4,
102 #define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned,
103 #define vex5 .vex_class = 5,
104 #define vex6 .vex_class = 6,
105 #define vex7 .vex_class = 7,
106 #define vex8 .vex_class = 8,
107 #define vex11 .vex_class = 11,
108 #define vex12 .vex_class = 12,
109 #define vex13 .vex_class = 13,
111 #define avx2_256 .vex_special = X86_VEX_AVX2_256,
113 #define P_00 1
114 #define P_66 (1 << PREFIX_DATA)
115 #define P_F3 (1 << PREFIX_REPZ)
116 #define P_F2 (1 << PREFIX_REPNZ)
118 #define p_00 .valid_prefix = P_00,
119 #define p_66 .valid_prefix = P_66,
120 #define p_f3 .valid_prefix = P_F3,
121 #define p_f2 .valid_prefix = P_F2,
122 #define p_00_66 .valid_prefix = P_00 | P_66,
123 #define p_00_f3 .valid_prefix = P_00 | P_F3,
124 #define p_66_f2 .valid_prefix = P_66 | P_F2,
125 #define p_00_66_f3 .valid_prefix = P_00 | P_66 | P_F3,
126 #define p_66_f3_f2 .valid_prefix = P_66 | P_F3 | P_F2,
127 #define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2,
129 static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
130 {
131 if (!s->has_modrm) {
132 s->modrm = x86_ldub_code(env, s);
133 s->has_modrm = true;
134 }
135 return s->modrm;
136 }
138 static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4])
139 {
140 if (s->prefix & PREFIX_REPNZ) {
141 return &entries[3];
142 } else if (s->prefix & PREFIX_REPZ) {
143 return &entries[2];
144 } else if (s->prefix & PREFIX_DATA) {
145 return &entries[1];
146 } else {
147 return &entries[0];
148 }
149 }
151 static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
152 {
153 static const X86GenFunc group17_gen[8] = {
154 NULL, gen_BLSR, gen_BLSMSK, gen_BLSI,
155 };
156 int op = (get_modrm(s, env) >> 3) & 7;
157 entry->gen = group17_gen[op];
158 }
160 static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
161 {
162 static const X86OpEntry opcodes_0F6F[4] = {
163 X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex1 mmx), /* movq */
164 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */
165 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */
166 {},
167 };
168 *entry = *decode_by_prefix(s, opcodes_0F6F);
169 }
171 static const X86OpEntry opcodes_0F38_00toEF[240] = {
172 };
174 /* five rows for no prefix, 66, F3, F2, 66+F2 */
175 static const X86OpEntry opcodes_0F38_F0toFF[16][5] = {
176 [0] = {
177 X86_OP_ENTRY3(MOVBE, G,y, M,y, None,None, cpuid(MOVBE)),
178 X86_OP_ENTRY3(MOVBE, G,w, M,w, None,None, cpuid(MOVBE)),
179 {},
180 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
181 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
182 },
183 [1] = {
184 X86_OP_ENTRY3(MOVBE, M,y, G,y, None,None, cpuid(MOVBE)),
185 X86_OP_ENTRY3(MOVBE, M,w, G,w, None,None, cpuid(MOVBE)),
186 {},
187 X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)),
188 X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)),
189 },
190 [2] = {
191 X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)),
192 {},
193 {},
194 {},
195 {},
196 },
197 [3] = {
198 X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)),
199 {},
200 {},
201 {},
202 {},
203 },
204 [5] = {
205 X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)),
206 {},
207 X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 cpuid(BMI2)),
208 X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 cpuid(BMI2)),
209 {},
210 },
211 [6] = {
212 {},
213 X86_OP_ENTRY2(ADCX, G,y, E,y, cpuid(ADX)),
214 X86_OP_ENTRY2(ADOX, G,y, E,y, cpuid(ADX)),
215 X86_OP_ENTRY3(MULX, /* B,y, */ G,y, E,y, 2,y, vex13 cpuid(BMI2)),
216 {},
217 },
218 [7] = {
219 X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 cpuid(BMI1)),
220 X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
221 X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
222 X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
223 {},
224 },
225 };
227 static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
228 {
229 *b = x86_ldub_code(env, s);
230 if (*b < 0xf0) {
231 *entry = opcodes_0F38_00toEF[*b];
232 } else {
233 int row = 0;
234 if (s->prefix & PREFIX_REPZ) {
235 /* The REPZ (F3) prefix has priority over 66 */
236 row = 2;
237 } else {
238 row += s->prefix & PREFIX_REPNZ ? 3 : 0;
239 row += s->prefix & PREFIX_DATA ? 1 : 0;
240 }
241 *entry = opcodes_0F38_F0toFF[*b & 15][row];
242 }
243 }
245 static const X86OpEntry opcodes_0F3A[256] = {
246 [0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2),
247 };
249 static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
250 {
251 *b = x86_ldub_code(env, s);
252 *entry = opcodes_0F3A[*b];
253 }
255 static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
256 {
257 if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
258 entry->op1 = X86_TYPE_None;
259 entry->s1 = X86_SIZE_None;
260 }
261 switch (*b) {
262 case 0x51: entry->gen = gen_VSQRT; break;
263 case 0x52: entry->gen = gen_VRSQRT; break;
264 case 0x53: entry->gen = gen_VRCP; break;
265 case 0x5A: entry->gen = gen_VCVTfp2fp; break;
266 }
267 }
269 static void decode_0F5B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
270 {
271 static const X86OpEntry opcodes_0F5B[4] = {
272 X86_OP_ENTRY2(VCVTDQ2PS, V,x, W,x, vex2),
273 X86_OP_ENTRY2(VCVTPS2DQ, V,x, W,x, vex2),
274 X86_OP_ENTRY2(VCVTTPS2DQ, V,x, W,x, vex2),
275 {},
276 };
277 *entry = *decode_by_prefix(s, opcodes_0F5B);
278 }
280 static const X86OpEntry opcodes_0F[256] = {
281 [0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
282 [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
283 [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
284 [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
285 [0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */
286 [0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */
287 [0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */
288 [0x57] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 p_00_66), /* vxor */
290 [0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
291 [0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
292 [0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
293 [0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
294 [0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
295 [0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
296 [0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
297 [0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
299 [0x38] = X86_OP_GROUP0(0F38),
300 [0x3a] = X86_OP_GROUP0(0F3A),
302 [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
303 [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
304 [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex3 p_00_66_f3_f2),
305 [0x5b] = X86_OP_GROUP0(0F5B),
306 [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
307 [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
308 [0x5e] = X86_OP_ENTRY3(VDIV, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
309 [0x5f] = X86_OP_ENTRY3(VMAX, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
311 [0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
312 [0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
313 [0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
314 [0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
315 [0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
316 [0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
317 [0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
318 [0x6f] = X86_OP_GROUP0(0F6F),
320 /* Incorrectly missing from 2-17 */
321 [0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
322 [0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
323 [0xda] = X86_OP_ENTRY3(PMINUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
324 [0xdb] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
325 [0xdc] = X86_OP_ENTRY3(PADDUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
326 [0xdd] = X86_OP_ENTRY3(PADDUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
327 [0xde] = X86_OP_ENTRY3(PMAXUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
328 [0xdf] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
330 [0xe8] = X86_OP_ENTRY3(PSUBSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
331 [0xe9] = X86_OP_ENTRY3(PSUBSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
332 [0xea] = X86_OP_ENTRY3(PMINSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
333 [0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
334 [0xec] = X86_OP_ENTRY3(PADDSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
335 [0xed] = X86_OP_ENTRY3(PADDSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
336 [0xee] = X86_OP_ENTRY3(PMAXSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
337 [0xef] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
339 [0xf8] = X86_OP_ENTRY3(PSUBB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
340 [0xf9] = X86_OP_ENTRY3(PSUBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
341 [0xfa] = X86_OP_ENTRY3(PSUBD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
342 [0xfb] = X86_OP_ENTRY3(PSUBQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
343 [0xfc] = X86_OP_ENTRY3(PADDB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
344 [0xfd] = X86_OP_ENTRY3(PADDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
345 [0xfe] = X86_OP_ENTRY3(PADDD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
346 /* 0xff = UD0 */
347 };
349 static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
350 {
351 *entry = opcodes_0F[*b];
352 }
354 static void decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
355 {
356 *b = x86_ldub_code(env, s);
357 do_decode_0F(s, env, entry, b);
358 }
360 static const X86OpEntry opcodes_root[256] = {
361 [0x0F] = X86_OP_GROUP0(0F),
362 };
364 #undef mmx
365 #undef vex1
366 #undef vex2
367 #undef vex3
368 #undef vex4
369 #undef vex4_unal
370 #undef vex5
371 #undef vex6
372 #undef vex7
373 #undef vex8
374 #undef vex11
375 #undef vex12
376 #undef vex13
378 /*
379 * Decode the fixed part of the opcode and place the last
380 * in b.
381 */
382 static void decode_root(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
383 {
384 *entry = opcodes_root[*b];
385 }
388 static int decode_modrm(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
389 X86DecodedOp *op, X86OpType type)
390 {
391 int modrm = get_modrm(s, env);
392 if ((modrm >> 6) == 3) {
393 if (s->prefix & PREFIX_LOCK) {
394 decode->e.gen = gen_illegal;
395 return 0xff;
396 }
397 op->n = (modrm & 7);
398 if (type != X86_TYPE_Q && type != X86_TYPE_N) {
399 op->n |= REX_B(s);
400 }
401 } else {
402 op->has_ea = true;
403 op->n = -1;
404 decode->mem = gen_lea_modrm_0(env, s, get_modrm(s, env));
405 }
406 return modrm;
407 }
409 static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot)
410 {
411 switch (size) {
412 case X86_SIZE_b: /* byte */
413 *ot = MO_8;
414 return true;
416 case X86_SIZE_d: /* 32-bit */
417 case X86_SIZE_ss: /* SSE/AVX scalar single precision */
418 *ot = MO_32;
419 return true;
421 case X86_SIZE_p: /* Far pointer, return offset size */
422 case X86_SIZE_s: /* Descriptor, return offset size */
423 case X86_SIZE_v: /* 16/32/64-bit, based on operand size */
424 *ot = s->dflag;
425 return true;
427 case X86_SIZE_pi: /* MMX */
428 case X86_SIZE_q: /* 64-bit */
429 case X86_SIZE_sd: /* SSE/AVX scalar double precision */
430 *ot = MO_64;
431 return true;
433 case X86_SIZE_w: /* 16-bit */
434 *ot = MO_16;
435 return true;
437 case X86_SIZE_y: /* 32/64-bit, based on operand size */
438 *ot = s->dflag == MO_16 ? MO_32 : s->dflag;
439 return true;
441 case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */
442 *ot = s->dflag == MO_16 ? MO_16 : MO_32;
443 return true;
445 case X86_SIZE_dq: /* SSE/AVX 128-bit */
446 if (e->special == X86_SPECIAL_MMX &&
447 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
448 *ot = MO_64;
449 return true;
450 }
451 if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) {
452 return false;
453 }
454 *ot = MO_128;
455 return true;
457 case X86_SIZE_qq: /* AVX 256-bit */
458 if (!s->vex_l) {
459 return false;
460 }
461 *ot = MO_256;
462 return true;
464 case X86_SIZE_x: /* 128/256-bit, based on operand size */
465 if (e->special == X86_SPECIAL_MMX &&
466 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
467 *ot = MO_64;
468 return true;
469 }
470 /* fall through */
471 case X86_SIZE_ps: /* SSE/AVX packed single precision */
472 case X86_SIZE_pd: /* SSE/AVX packed double precision */
473 *ot = s->vex_l ? MO_256 : MO_128;
474 return true;
476 case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */
477 *ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag;
478 return true;
480 case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */
481 *ot = CODE64(s) ? MO_64 : s->dflag;
482 return true;
484 default:
485 *ot = -1;
486 return true;
487 }
488 }
490 static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
491 X86DecodedOp *op, X86OpType type, int b)
492 {
493 int modrm;
495 switch (type) {
496 case X86_TYPE_None: /* Implicit or absent */
497 case X86_TYPE_A: /* Implicit */
498 case X86_TYPE_F: /* EFLAGS/RFLAGS */
499 break;
501 case X86_TYPE_B: /* VEX.vvvv selects a GPR */
502 op->unit = X86_OP_INT;
503 op->n = s->vex_v;
504 break;
506 case X86_TYPE_C: /* REG in the modrm byte selects a control register */
507 op->unit = X86_OP_CR;
508 goto get_reg;
510 case X86_TYPE_D: /* REG in the modrm byte selects a debug register */
511 op->unit = X86_OP_DR;
512 goto get_reg;
514 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
515 op->unit = X86_OP_INT;
516 goto get_reg;
518 case X86_TYPE_S: /* reg selects a segment register */
519 op->unit = X86_OP_SEG;
520 goto get_reg;
522 case X86_TYPE_P:
523 op->unit = X86_OP_MMX;
524 goto get_reg;
526 case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */
527 if (decode->e.special == X86_SPECIAL_MMX &&
528 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
529 op->unit = X86_OP_MMX;
530 } else {
531 op->unit = X86_OP_SSE;
532 }
533 get_reg:
534 op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s);
535 break;
537 case X86_TYPE_E: /* ALU modrm operand */
538 op->unit = X86_OP_INT;
539 goto get_modrm;
541 case X86_TYPE_Q: /* MMX modrm operand */
542 op->unit = X86_OP_MMX;
543 goto get_modrm;
545 case X86_TYPE_W: /* XMM/YMM modrm operand */
546 if (decode->e.special == X86_SPECIAL_MMX &&
547 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
548 op->unit = X86_OP_MMX;
549 } else {
550 op->unit = X86_OP_SSE;
551 }
552 goto get_modrm;
554 case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */
555 op->unit = X86_OP_MMX;
556 goto get_modrm_reg;
558 case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */
559 if (decode->e.special == X86_SPECIAL_MMX &&
560 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
561 op->unit = X86_OP_MMX;
562 } else {
563 op->unit = X86_OP_SSE;
564 }
565 goto get_modrm_reg;
567 case X86_TYPE_R: /* R/M in the modrm byte selects a register */
568 op->unit = X86_OP_INT;
569 get_modrm_reg:
570 modrm = get_modrm(s, env);
571 if ((modrm >> 6) != 3) {
572 return false;
573 }
574 goto get_modrm;
576 case X86_TYPE_M: /* modrm byte selects a memory operand */
577 modrm = get_modrm(s, env);
578 if ((modrm >> 6) == 3) {
579 return false;
580 }
581 get_modrm:
582 decode_modrm(s, env, decode, op, type);
583 break;
585 case X86_TYPE_O: /* Absolute address encoded in the instruction */
586 op->unit = X86_OP_INT;
587 op->has_ea = true;
588 op->n = -1;
589 decode->mem = (AddressParts) {
590 .def_seg = R_DS,
591 .base = -1,
592 .index = -1,
593 .disp = insn_get_addr(env, s, s->aflag)
594 };
595 break;
597 case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */
598 if ((s->prefix & PREFIX_VEX)) {
599 op->unit = X86_OP_SSE;
600 op->n = s->vex_v;
601 break;
602 }
603 if (op == &decode->op[0]) {
604 /* shifts place the destination in VEX.vvvv, use modrm */
605 return decode_op(s, env, decode, op, decode->e.op1, b);
606 } else {
607 return decode_op(s, env, decode, op, decode->e.op0, b);
608 }
610 case X86_TYPE_I: /* Immediate */
611 op->unit = X86_OP_IMM;
612 decode->immediate = insn_get_signed(env, s, op->ot);
613 break;
615 case X86_TYPE_J: /* Relative offset for a jump */
616 op->unit = X86_OP_IMM;
617 decode->immediate = insn_get_signed(env, s, op->ot);
618 decode->immediate += s->pc - s->cs_base;
619 if (s->dflag == MO_16) {
620 decode->immediate &= 0xffff;
621 } else if (!CODE64(s)) {
622 decode->immediate &= 0xffffffffu;
623 }
624 break;
626 case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */
627 op->n = insn_get(env, s, op->ot) >> 4;
628 break;
630 case X86_TYPE_X: /* string source */
631 op->n = -1;
632 decode->mem = (AddressParts) {
633 .def_seg = R_DS,
634 .base = R_ESI,
635 .index = -1,
636 };
637 break;
639 case X86_TYPE_Y: /* string destination */
640 op->n = -1;
641 decode->mem = (AddressParts) {
642 .def_seg = R_ES,
643 .base = R_EDI,
644 .index = -1,
645 };
646 break;
648 case X86_TYPE_2op:
649 *op = decode->op[0];
650 break;
652 case X86_TYPE_LoBits:
653 op->n = (b & 7) | REX_B(s);
654 op->unit = X86_OP_INT;
655 break;
657 case X86_TYPE_0 ... X86_TYPE_7:
658 op->n = type - X86_TYPE_0;
659 op->unit = X86_OP_INT;
660 break;
662 case X86_TYPE_ES ... X86_TYPE_GS:
663 op->n = type - X86_TYPE_ES;
664 op->unit = X86_OP_SEG;
665 break;
666 }
668 return true;
669 }
671 static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e)
672 {
673 uint16_t sse_prefixes;
675 if (!e->valid_prefix) {
676 return true;
677 }
678 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
679 /* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */
680 s->prefix &= ~PREFIX_DATA;
681 }
683 /* Now, either zero or one bit is set in sse_prefixes. */
684 sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
685 return e->valid_prefix & (1 << sse_prefixes);
686 }
688 static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func,
689 X86DecodedInsn *decode)
690 {
691 X86OpEntry *e = &decode->e;
693 decode_func(s, env, e, &decode->b);
694 while (e->is_decode) {
695 e->is_decode = false;
696 e->decode(s, env, e, &decode->b);
697 }
699 if (!validate_sse_prefix(s, e)) {
700 return false;
701 }
703 /* First compute size of operands in order to initialize s->rip_offset. */
704 if (e->op0 != X86_TYPE_None) {
705 if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
706 return false;
707 }
708 if (e->op0 == X86_TYPE_I) {
709 s->rip_offset += 1 << decode->op[0].ot;
710 }
711 }
712 if (e->op1 != X86_TYPE_None) {
713 if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) {
714 return false;
715 }
716 if (e->op1 == X86_TYPE_I) {
717 s->rip_offset += 1 << decode->op[1].ot;
718 }
719 }
720 if (e->op2 != X86_TYPE_None) {
721 if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) {
722 return false;
723 }
724 if (e->op2 == X86_TYPE_I) {
725 s->rip_offset += 1 << decode->op[2].ot;
726 }
727 }
728 if (e->op3 != X86_TYPE_None) {
729 assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
730 s->rip_offset += 1;
731 }
733 if (e->op0 != X86_TYPE_None &&
734 !decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) {
735 return false;
736 }
738 if (e->op1 != X86_TYPE_None &&
739 !decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) {
740 return false;
741 }
743 if (e->op2 != X86_TYPE_None &&
744 !decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) {
745 return false;
746 }
748 if (e->op3 != X86_TYPE_None) {
749 decode->immediate = insn_get_signed(env, s, MO_8);
750 }
752 return true;
753 }
755 static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
756 {
757 switch (cpuid) {
758 case X86_FEAT_None:
759 return true;
760 case X86_FEAT_MOVBE:
761 return (s->cpuid_ext_features & CPUID_EXT_MOVBE);
762 case X86_FEAT_PCLMULQDQ:
763 return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ);
764 case X86_FEAT_SSE:
765 return (s->cpuid_ext_features & CPUID_SSE);
766 case X86_FEAT_SSE2:
767 return (s->cpuid_ext_features & CPUID_SSE2);
768 case X86_FEAT_SSE3:
769 return (s->cpuid_ext_features & CPUID_EXT_SSE3);
770 case X86_FEAT_SSSE3:
771 return (s->cpuid_ext_features & CPUID_EXT_SSSE3);
772 case X86_FEAT_SSE41:
773 return (s->cpuid_ext_features & CPUID_EXT_SSE41);
774 case X86_FEAT_SSE42:
775 return (s->cpuid_ext_features & CPUID_EXT_SSE42);
776 case X86_FEAT_AES:
777 if (!(s->cpuid_ext_features & CPUID_EXT_AES)) {
778 return false;
779 } else if (!(s->prefix & PREFIX_VEX)) {
780 return true;
781 } else if (!(s->cpuid_ext_features & CPUID_EXT_AVX)) {
782 return false;
783 } else {
784 return !s->vex_l || (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES);
785 }
787 case X86_FEAT_AVX:
788 return (s->cpuid_ext_features & CPUID_EXT_AVX);
790 case X86_FEAT_SSE4A:
791 return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A);
793 case X86_FEAT_ADX:
794 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX);
795 case X86_FEAT_BMI1:
796 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1);
797 case X86_FEAT_BMI2:
798 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2);
799 case X86_FEAT_AVX2:
800 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2);
801 }
802 g_assert_not_reached();
803 }
805 static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
806 {
807 X86OpEntry *e = &decode->e;
809 switch (e->vex_special) {
810 case X86_VEX_REPScalar:
811 /*
812 * Instructions which differ between 00/66 and F2/F3 in the
813 * exception classification and the size of the memory operand.
814 */
815 assert(e->vex_class == 1 || e->vex_class == 2);
816 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
817 e->vex_class = 3;
818 if (s->vex_l) {
819 goto illegal;
820 }
821 assert(decode->e.s2 == X86_SIZE_x);
822 if (decode->op[2].has_ea) {
823 decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64;
824 }
825 }
826 break;
828 case X86_VEX_SSEUnaligned:
829 /* handled in sse_needs_alignment. */
830 break;
832 case X86_VEX_AVX2_256:
833 if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) {
834 goto illegal;
835 }
836 }
838 /* TODO: instructions that require VEX.W=0 (Table 2-16) */
840 switch (e->vex_class) {
841 case 0:
842 if (s->prefix & PREFIX_VEX) {
843 goto illegal;
844 }
845 return true;
846 case 1:
847 case 2:
848 case 3:
849 case 4:
850 case 5:
851 case 7:
852 if (s->prefix & PREFIX_VEX) {
853 if (!(s->flags & HF_AVX_EN_MASK)) {
854 goto illegal;
855 }
856 } else {
857 if (!(s->flags & HF_OSFXSR_MASK)) {
858 goto illegal;
859 }
860 }
861 break;
862 case 12:
863 /* Must have a VSIB byte and no address prefix. */
864 assert(s->has_modrm);
865 if ((s->modrm & 7) != 4 || s->aflag == MO_16) {
866 goto illegal;
867 }
869 /* Check no overlap between registers. */
870 if (!decode->op[0].has_ea &&
871 (decode->op[0].n == decode->mem.index || decode->op[0].n == decode->op[1].n)) {
872 goto illegal;
873 }
874 assert(!decode->op[1].has_ea);
875 if (decode->op[1].n == decode->mem.index) {
876 goto illegal;
877 }
878 if (!decode->op[2].has_ea &&
879 (decode->op[2].n == decode->mem.index || decode->op[2].n == decode->op[1].n)) {
880 goto illegal;
881 }
882 /* fall through */
883 case 6:
884 case 11:
885 if (!(s->prefix & PREFIX_VEX)) {
886 goto illegal;
887 }
888 if (!(s->flags & HF_AVX_EN_MASK)) {
889 goto illegal;
890 }
891 break;
892 case 8:
893 if (!(s->prefix & PREFIX_VEX)) {
894 /* EMMS */
895 return true;
896 }
897 if (!(s->flags & HF_AVX_EN_MASK)) {
898 goto illegal;
899 }
900 break;
901 case 13:
902 if (!(s->prefix & PREFIX_VEX)) {
903 goto illegal;
904 }
905 if (s->vex_l) {
906 goto illegal;
907 }
908 /* All integer instructions use VEX.vvvv, so exit. */
909 return true;
910 }
912 if (s->vex_v != 0 &&
913 e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B &&
914 e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B &&
915 e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) {
916 goto illegal;
917 }
919 if (s->flags & HF_TS_MASK) {
920 goto nm_exception;
921 }
922 if (s->flags & HF_EM_MASK) {
923 goto illegal;
924 }
925 return true;
927 nm_exception:
928 gen_NM_exception(s);
929 return false;
930 illegal:
931 gen_illegal_opcode(s);
932 return false;
933 }
935 static void decode_temp_free(X86DecodedOp *op)
936 {
937 if (op->v_ptr) {
938 tcg_temp_free_ptr(op->v_ptr);
939 }
940 }
942 static void decode_temps_free(X86DecodedInsn *decode)
943 {
944 decode_temp_free(&decode->op[0]);
945 decode_temp_free(&decode->op[1]);
946 decode_temp_free(&decode->op[2]);
947 }
949 /*
950 * Convert one instruction. s->base.is_jmp is set if the translation must
951 * be stopped.
952 */
953 static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
954 {
955 CPUX86State *env = cpu->env_ptr;
956 bool first = true;
957 X86DecodedInsn decode;
958 X86DecodeFunc decode_func = decode_root;
960 #ifdef CONFIG_USER_ONLY
961 if (limit) { --limit; }
962 #endif
963 s->has_modrm = false;
965 next_byte:
966 if (first) {
967 first = false;
968 } else {
969 b = x86_ldub_code(env, s);
970 }
971 /* Collect prefixes. */
972 switch (b) {
973 case 0xf3:
974 s->prefix |= PREFIX_REPZ;
975 s->prefix &= ~PREFIX_REPNZ;
976 goto next_byte;
977 case 0xf2:
978 s->prefix |= PREFIX_REPNZ;
979 s->prefix &= ~PREFIX_REPZ;
980 goto next_byte;
981 case 0xf0:
982 s->prefix |= PREFIX_LOCK;
983 goto next_byte;
984 case 0x2e:
985 s->override = R_CS;
986 goto next_byte;
987 case 0x36:
988 s->override = R_SS;
989 goto next_byte;
990 case 0x3e:
991 s->override = R_DS;
992 goto next_byte;
993 case 0x26:
994 s->override = R_ES;
995 goto next_byte;
996 case 0x64:
997 s->override = R_FS;
998 goto next_byte;
999 case 0x65:
1000 s->override = R_GS;
1001 goto next_byte;
1002 case 0x66:
1003 s->prefix |= PREFIX_DATA;
1004 goto next_byte;
1005 case 0x67:
1006 s->prefix |= PREFIX_ADR;
1007 goto next_byte;
1008 #ifdef TARGET_X86_64
1009 case 0x40 ... 0x4f:
1010 if (CODE64(s)) {
1011 /* REX prefix */
1012 s->prefix |= PREFIX_REX;
1013 s->vex_w = (b >> 3) & 1;
1014 s->rex_r = (b & 0x4) << 1;
1015 s->rex_x = (b & 0x2) << 2;
1016 s->rex_b = (b & 0x1) << 3;
1017 goto next_byte;
1018 }
1019 break;
1020 #endif
1021 case 0xc5: /* 2-byte VEX */
1022 case 0xc4: /* 3-byte VEX */
1023 /*
1024 * VEX prefixes cannot be used except in 32-bit mode.
1025 * Otherwise the instruction is LES or LDS.
1026 */
1027 if (CODE32(s) && !VM86(s)) {
1028 static const int pp_prefix[4] = {
1029 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
1030 };
1031 int vex3, vex2 = x86_ldub_code(env, s);
1033 if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
1034 /*
1035 * 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
1036 * otherwise the instruction is LES or LDS.
1037 */
1038 s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
1039 break;
1040 }
1042 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
1043 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ
1044 | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) {
1045 goto illegal_op;
1046 }
1047 #ifdef TARGET_X86_64
1048 s->rex_r = (~vex2 >> 4) & 8;
1049 #endif
1050 if (b == 0xc5) {
1051 /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */
1052 vex3 = vex2;
1053 decode_func = decode_0F;
1054 } else {
1055 /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */
1056 vex3 = x86_ldub_code(env, s);
1057 #ifdef TARGET_X86_64
1058 s->rex_x = (~vex2 >> 3) & 8;
1059 s->rex_b = (~vex2 >> 2) & 8;
1060 #endif
1061 s->vex_w = (vex3 >> 7) & 1;
1062 switch (vex2 & 0x1f) {
1063 case 0x01: /* Implied 0f leading opcode bytes. */
1064 decode_func = decode_0F;
1065 break;
1066 case 0x02: /* Implied 0f 38 leading opcode bytes. */
1067 decode_func = decode_0F38;
1068 break;
1069 case 0x03: /* Implied 0f 3a leading opcode bytes. */
1070 decode_func = decode_0F3A;
1071 break;
1072 default: /* Reserved for future use. */
1073 goto unknown_op;
1074 }
1075 }
1076 s->vex_v = (~vex3 >> 3) & 0xf;
1077 s->vex_l = (vex3 >> 2) & 1;
1078 s->prefix |= pp_prefix[vex3 & 3] | PREFIX_VEX;
1079 }
1080 break;
1081 default:
1082 if (b >= 0x100) {
1083 b -= 0x100;
1084 decode_func = do_decode_0F;
1085 }
1086 break;
1087 }
1089 /* Post-process prefixes. */
1090 if (CODE64(s)) {
1091 /*
1092 * In 64-bit mode, the default data size is 32-bit. Select 64-bit
1093 * data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
1094 * over 0x66 if both are present.
1095 */
1096 s->dflag = (REX_W(s) ? MO_64 : s->prefix & PREFIX_DATA ? MO_16 : MO_32);
1097 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
1098 s->aflag = (s->prefix & PREFIX_ADR ? MO_32 : MO_64);
1099 } else {
1100 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
1101 if (CODE32(s) ^ ((s->prefix & PREFIX_DATA) != 0)) {
1102 s->dflag = MO_32;
1103 } else {
1104 s->dflag = MO_16;
1105 }
1106 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
1107 if (CODE32(s) ^ ((s->prefix & PREFIX_ADR) != 0)) {
1108 s->aflag = MO_32;
1109 } else {
1110 s->aflag = MO_16;
1111 }
1112 }
1114 memset(&decode, 0, sizeof(decode));
1115 decode.b = b;
1116 if (!decode_insn(s, env, decode_func, &decode)) {
1117 goto illegal_op;
1118 }
1119 if (!decode.e.gen) {
1120 goto unknown_op;
1121 }
1123 if (!has_cpuid_feature(s, decode.e.cpuid)) {
1124 goto illegal_op;
1125 }
1127 switch (decode.e.special) {
1128 case X86_SPECIAL_None:
1129 break;
1131 case X86_SPECIAL_Locked:
1132 if (decode.op[0].has_ea) {
1133 s->prefix |= PREFIX_LOCK;
1134 }
1135 break;
1137 case X86_SPECIAL_ProtMode:
1138 if (!PE(s) || VM86(s)) {
1139 goto illegal_op;
1140 }
1141 break;
1143 case X86_SPECIAL_i64:
1144 if (CODE64(s)) {
1145 goto illegal_op;
1146 }
1147 break;
1148 case X86_SPECIAL_o64:
1149 if (!CODE64(s)) {
1150 goto illegal_op;
1151 }
1152 break;
1154 case X86_SPECIAL_ZExtOp0:
1155 assert(decode.op[0].unit == X86_OP_INT);
1156 if (!decode.op[0].has_ea) {
1157 decode.op[0].ot = MO_32;
1158 }
1159 break;
1161 case X86_SPECIAL_ZExtOp2:
1162 assert(decode.op[2].unit == X86_OP_INT);
1163 if (!decode.op[2].has_ea) {
1164 decode.op[2].ot = MO_32;
1165 }
1166 break;
1168 case X86_SPECIAL_MMX:
1169 if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
1170 gen_helper_enter_mmx(cpu_env);
1171 }
1172 break;
1173 }
1175 if (!validate_vex(s, &decode)) {
1176 return;
1177 }
1178 if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
1179 gen_load_ea(s, &decode.mem, decode.e.vex_class == 12);
1180 }
1181 if (s->prefix & PREFIX_LOCK) {
1182 if (decode.op[0].unit != X86_OP_INT || !decode.op[0].has_ea) {
1183 goto illegal_op;
1184 }
1185 gen_load(s, &decode, 2, s->T1);
1186 decode.e.gen(s, env, &decode);
1187 } else {
1188 if (decode.op[0].unit == X86_OP_MMX) {
1189 compute_mmx_offset(&decode.op[0]);
1190 } else if (decode.op[0].unit == X86_OP_SSE) {
1191 compute_xmm_offset(&decode.op[0]);
1192 }
1193 gen_load(s, &decode, 1, s->T0);
1194 gen_load(s, &decode, 2, s->T1);
1195 decode.e.gen(s, env, &decode);
1196 gen_writeback(s, &decode, 0, s->T0);
1197 }
1198 decode_temps_free(&decode);
1199 return;
1200 illegal_op:
1201 gen_illegal_opcode(s);
1202 return;
1203 unknown_op:
1204 gen_unknown_opcode(env, s);
1205 }