hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int bus_num;
  40     int devfn_min;
  41     pci_set_irq_fn set_irq;
  42     pci_map_irq_fn map_irq;
  43     uint32_t config_reg; /* XXX: suppress */
  44     void *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47     PCIBus *next;
  48     /* The bus IRQ state is the logical OR of the connected devices.
  49        Keep a count of the number of devices with raised IRQs.  */
  50     int nirq;
  51     int *irq_count;
  52 };
  53
  54 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  55
  56 static struct BusInfo pci_bus_info = {
  57     .name       = "PCI",
  58     .size       = sizeof(PCIBus),
  59     .print_dev  = pcibus_dev_print,
  60     .props      = (Property[]) {
  61         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  62         DEFINE_PROP_END_OF_LIST()
  63     }
  64 };
  65
  66 static void pci_update_mappings(PCIDevice *d);
  67 static void pci_set_irq(void *opaque, int irq_num, int level);
  68
  69 target_phys_addr_t pci_mem_base;
  70 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  71 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  72 static PCIBus *first_bus;
  73
  74 static const VMStateDescription vmstate_pcibus = {
  75     .name = "PCIBUS",
  76     .version_id = 1,
  77     .minimum_version_id = 1,
  78     .minimum_version_id_old = 1,
  79     .fields      = (VMStateField []) {
  80         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  81         VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq),
  82         VMSTATE_END_OF_LIST()
  83     }
  84 };
  85
  86 static void pci_bus_reset(void *opaque)
  87 {
  88     PCIBus *bus = opaque;
  89     int i;
  90
  91     for (i = 0; i < bus->nirq; i++) {
  92         bus->irq_count[i] = 0;
  93     }
  94     for (i = 0; i < 256; i++) {
  95         if (bus->devices[i])
  96             memset(bus->devices[i]->irq_state, 0,
  97                    sizeof(bus->devices[i]->irq_state));
  98     }
  99 }
 100
 101 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 102                          const char *name, int devfn_min)
 103 {
 104     static int nbus = 0;
 105
 106     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 107     bus->devfn_min = devfn_min;
 108     bus->next = first_bus;
 109     first_bus = bus;
 110     vmstate_register(nbus++, &vmstate_pcibus, bus);
 111     qemu_register_reset(pci_bus_reset, bus);
 112 }
 113
 114 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 115 {
 116     PCIBus *bus;
 117
 118     bus = qemu_mallocz(sizeof(*bus));
 119     bus->qbus.qdev_allocated = 1;
 120     pci_bus_new_inplace(bus, parent, name, devfn_min);
 121     return bus;
 122 }
 123
 124 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 125                   void *irq_opaque, int nirq)
 126 {
 127     bus->set_irq = set_irq;
 128     bus->map_irq = map_irq;
 129     bus->irq_opaque = irq_opaque;
 130     bus->nirq = nirq;
 131     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 132 }
 133
 134 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 135                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 136                          void *irq_opaque, int devfn_min, int nirq)
 137 {
 138     PCIBus *bus;
 139
 140     bus = pci_bus_new(parent, name, devfn_min);
 141     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 142     return bus;
 143 }
 144
 145 static void pci_register_secondary_bus(PCIBus *bus,
 146                                        PCIDevice *dev,
 147                                        pci_map_irq_fn map_irq,
 148                                        const char *name)
 149 {
 150     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 151     bus->map_irq = map_irq;
 152     bus->parent_dev = dev;
 153     bus->next = dev->bus->next;
 154     dev->bus->next = bus;
 155 }
 156
 157 int pci_bus_num(PCIBus *s)
 158 {
 159     return s->bus_num;
 160 }
 161
 162 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 163 {
 164     PCIDevice *s = container_of(pv, PCIDevice, config);
 165     uint8_t config[size];
 166     int i;
 167
 168     qemu_get_buffer(f, config, size);
 169     for (i = 0; i < size; ++i)
 170         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 171             return -EINVAL;
 172     memcpy(s->config, config, size);
 173
 174     pci_update_mappings(s);
 175
 176     return 0;
 177 }
 178
 179 /* just put buffer */
 180 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 181 {
 182     const uint8_t *v = pv;
 183     qemu_put_buffer(f, v, size);
 184 }
 185
 186 static VMStateInfo vmstate_info_pci_config = {
 187     .name = "pci config",
 188     .get  = get_pci_config_device,
 189     .put  = put_pci_config_device,
 190 };
 191
 192 const VMStateDescription vmstate_pci_device = {
 193     .name = "PCIDevice",
 194     .version_id = 2,
 195     .minimum_version_id = 1,
 196     .minimum_version_id_old = 1,
 197     .fields      = (VMStateField []) {
 198         VMSTATE_INT32_LE(version_id, PCIDevice),
 199         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 200                        typeof_field(PCIDevice,config)),
 201         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2),
 202         VMSTATE_END_OF_LIST()
 203     }
 204 };
 205
 206 void pci_device_save(PCIDevice *s, QEMUFile *f)
 207 {
 208     vmstate_save_state(f, &vmstate_pci_device, s);
 209 }
 210
 211 int pci_device_load(PCIDevice *s, QEMUFile *f)
 212 {
 213     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 214 }
 215
 216 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 217 {
 218     uint16_t *id;
 219
 220     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 221     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 222     id[1] = cpu_to_le16(pci_default_sub_device_id);
 223     return 0;
 224 }
 225
 226 /*
 227  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 228  */
 229 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 230 {
 231     const char *p;
 232     char *e;
 233     unsigned long val;
 234     unsigned long dom = 0, bus = 0;
 235     unsigned slot = 0;
 236
 237     p = addr;
 238     val = strtoul(p, &e, 16);
 239     if (e == p)
 240         return -1;
 241     if (*e == ':') {
 242         bus = val;
 243         p = e + 1;
 244         val = strtoul(p, &e, 16);
 245         if (e == p)
 246             return -1;
 247         if (*e == ':') {
 248             dom = bus;
 249             bus = val;
 250             p = e + 1;
 251             val = strtoul(p, &e, 16);
 252             if (e == p)
 253                 return -1;
 254         }
 255     }
 256
 257     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 258         return -1;
 259
 260     slot = val;
 261
 262     if (*e)
 263         return -1;
 264
 265     /* Note: QEMU doesn't implement domains other than 0 */
 266     if (dom != 0 || pci_find_bus(bus) == NULL)
 267         return -1;
 268
 269     *domp = dom;
 270     *busp = bus;
 271     *slotp = slot;
 272     return 0;
 273 }
 274
 275 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 276                      unsigned *slotp)
 277 {
 278     /* strip legacy tag */
 279     if (!strncmp(addr, "pci_addr=", 9)) {
 280         addr += 9;
 281     }
 282     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 283         monitor_printf(mon, "Invalid pci address\n");
 284         return -1;
 285     }
 286     return 0;
 287 }
 288
 289 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 290 {
 291     int dom, bus;
 292     unsigned slot;
 293
 294     if (!devaddr) {
 295         *devfnp = -1;
 296         return pci_find_bus(0);
 297     }
 298
 299     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 300         return NULL;
 301     }
 302
 303     *devfnp = slot << 3;
 304     return pci_find_bus(bus);
 305 }
 306
 307 static void pci_init_cmask(PCIDevice *dev)
 308 {
 309     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 310     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 311     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 312     dev->cmask[PCI_REVISION_ID] = 0xff;
 313     dev->cmask[PCI_CLASS_PROG] = 0xff;
 314     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 315     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 316     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 317 }
 318
 319 static void pci_init_wmask(PCIDevice *dev)
 320 {
 321     int i;
 322     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 323     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 324     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 325                               | PCI_COMMAND_MASTER;
 326     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 327         dev->wmask[i] = 0xff;
 328 }
 329
 330 /* -1 for devfn means auto assign */
 331 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 332                                          const char *name, int devfn,
 333                                          PCIConfigReadFunc *config_read,
 334                                          PCIConfigWriteFunc *config_write)
 335 {
 336     if (devfn < 0) {
 337         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 338             if (!bus->devices[devfn])
 339                 goto found;
 340         }
 341         return NULL;
 342     found: ;
 343     } else if (bus->devices[devfn]) {
 344         return NULL;
 345     }
 346     pci_dev->bus = bus;
 347     pci_dev->devfn = devfn;
 348     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 349     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 350     pci_set_default_subsystem_id(pci_dev);
 351     pci_init_cmask(pci_dev);
 352     pci_init_wmask(pci_dev);
 353
 354     if (!config_read)
 355         config_read = pci_default_read_config;
 356     if (!config_write)
 357         config_write = pci_default_write_config;
 358     pci_dev->config_read = config_read;
 359     pci_dev->config_write = config_write;
 360     bus->devices[devfn] = pci_dev;
 361     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 362     pci_dev->version_id = 2; /* Current pci device vmstate version */
 363     return pci_dev;
 364 }
 365
 366 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 367                                int instance_size, int devfn,
 368                                PCIConfigReadFunc *config_read,
 369                                PCIConfigWriteFunc *config_write)
 370 {
 371     PCIDevice *pci_dev;
 372
 373     pci_dev = qemu_mallocz(instance_size);
 374     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 375                                      config_read, config_write);
 376     return pci_dev;
 377 }
 378 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 379 {
 380     return addr + pci_mem_base;
 381 }
 382
 383 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 384 {
 385     PCIIORegion *r;
 386     int i;
 387
 388     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 389         r = &pci_dev->io_regions[i];
 390         if (!r->size || r->addr == -1)
 391             continue;
 392         if (r->type == PCI_ADDRESS_SPACE_IO) {
 393             isa_unassign_ioport(r->addr, r->size);
 394         } else {
 395             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 396                                                      r->size,
 397                                                      IO_MEM_UNASSIGNED);
 398         }
 399     }
 400 }
 401
 402 int pci_unregister_device(PCIDevice *pci_dev)
 403 {
 404     int ret = 0;
 405
 406     if (pci_dev->unregister)
 407         ret = pci_dev->unregister(pci_dev);
 408     if (ret)
 409         return ret;
 410
 411     pci_unregister_io_regions(pci_dev);
 412
 413     qemu_free_irqs(pci_dev->irq);
 414     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 415     qdev_free(&pci_dev->qdev);
 416     return 0;
 417 }
 418
 419 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 420                             uint32_t size, int type,
 421                             PCIMapIORegionFunc *map_func)
 422 {
 423     PCIIORegion *r;
 424     uint32_t addr;
 425     uint32_t wmask;
 426
 427     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 428         return;
 429
 430     if (size & (size-1)) {
 431         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 432                     "type=0x%x, size=0x%x\n", type, size);
 433         exit(1);
 434     }
 435
 436     r = &pci_dev->io_regions[region_num];
 437     r->addr = -1;
 438     r->size = size;
 439     r->type = type;
 440     r->map_func = map_func;
 441
 442     wmask = ~(size - 1);
 443     if (region_num == PCI_ROM_SLOT) {
 444         addr = 0x30;
 445         /* ROM enable bit is writeable */
 446         wmask |= 1;
 447     } else {
 448         addr = 0x10 + region_num * 4;
 449     }
 450     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 451     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 452     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 453 }
 454
 455 static void pci_update_mappings(PCIDevice *d)
 456 {
 457     PCIIORegion *r;
 458     int cmd, i;
 459     uint32_t last_addr, new_addr, config_ofs;
 460
 461     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 462     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 463         r = &d->io_regions[i];
 464         if (i == PCI_ROM_SLOT) {
 465             config_ofs = 0x30;
 466         } else {
 467             config_ofs = 0x10 + i * 4;
 468         }
 469         if (r->size != 0) {
 470             if (r->type & PCI_ADDRESS_SPACE_IO) {
 471                 if (cmd & PCI_COMMAND_IO) {
 472                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 473                                                          config_ofs));
 474                     new_addr = new_addr & ~(r->size - 1);
 475                     last_addr = new_addr + r->size - 1;
 476                     /* NOTE: we have only 64K ioports on PC */
 477                     if (last_addr <= new_addr || new_addr == 0 ||
 478                         last_addr >= 0x10000) {
 479                         new_addr = -1;
 480                     }
 481                 } else {
 482                     new_addr = -1;
 483                 }
 484             } else {
 485                 if (cmd & PCI_COMMAND_MEMORY) {
 486                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 487                                                          config_ofs));
 488                     /* the ROM slot has a specific enable bit */
 489                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 490                         goto no_mem_map;
 491                     new_addr = new_addr & ~(r->size - 1);
 492                     last_addr = new_addr + r->size - 1;
 493                     /* NOTE: we do not support wrapping */
 494                     /* XXX: as we cannot support really dynamic
 495                        mappings, we handle specific values as invalid
 496                        mappings. */
 497                     if (last_addr <= new_addr || new_addr == 0 ||
 498                         last_addr == -1) {
 499                         new_addr = -1;
 500                     }
 501                 } else {
 502                 no_mem_map:
 503                     new_addr = -1;
 504                 }
 505             }
 506             /* now do the real mapping */
 507             if (new_addr != r->addr) {
 508                 if (r->addr != -1) {
 509                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 510                         int class;
 511                         /* NOTE: specific hack for IDE in PC case:
 512                            only one byte must be mapped. */
 513                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 514                         if (class == 0x0101 && r->size == 4) {
 515                             isa_unassign_ioport(r->addr + 2, 1);
 516                         } else {
 517                             isa_unassign_ioport(r->addr, r->size);
 518                         }
 519                     } else {
 520                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 521                                                      r->size,
 522                                                      IO_MEM_UNASSIGNED);
 523                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 524                     }
 525                 }
 526                 r->addr = new_addr;
 527                 if (r->addr != -1) {
 528                     r->map_func(d, i, r->addr, r->size, r->type);
 529                 }
 530             }
 531         }
 532     }
 533 }
 534
 535 uint32_t pci_default_read_config(PCIDevice *d,
 536                                  uint32_t address, int len)
 537 {
 538     uint32_t val;
 539
 540     switch(len) {
 541     default:
 542     case 4:
 543         if (address <= 0xfc) {
 544             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 545             break;
 546         }
 547         /* fall through */
 548     case 2:
 549         if (address <= 0xfe) {
 550             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 551             break;
 552         }
 553         /* fall through */
 554     case 1:
 555         val = d->config[address];
 556         break;
 557     }
 558     return val;
 559 }
 560
 561 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 562 {
 563     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 564     int i;
 565
 566     /* not efficient, but simple */
 567     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 568     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 569         uint8_t wmask = d->wmask[addr];
 570         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 571     }
 572     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 573         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 574             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 575         pci_update_mappings(d);
 576 }
 577
 578 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 579 {
 580     PCIBus *s = opaque;
 581     PCIDevice *pci_dev;
 582     int config_addr, bus_num;
 583
 584 #if 0
 585     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 586                 addr, val, len);
 587 #endif
 588     bus_num = (addr >> 16) & 0xff;
 589     while (s && s->bus_num != bus_num)
 590         s = s->next;
 591     if (!s)
 592         return;
 593     pci_dev = s->devices[(addr >> 8) & 0xff];
 594     if (!pci_dev)
 595         return;
 596     config_addr = addr & 0xff;
 597     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 598                 pci_dev->name, config_addr, val, len);
 599     pci_dev->config_write(pci_dev, config_addr, val, len);
 600 }
 601
 602 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 603 {
 604     PCIBus *s = opaque;
 605     PCIDevice *pci_dev;
 606     int config_addr, bus_num;
 607     uint32_t val;
 608
 609     bus_num = (addr >> 16) & 0xff;
 610     while (s && s->bus_num != bus_num)
 611         s= s->next;
 612     if (!s)
 613         goto fail;
 614     pci_dev = s->devices[(addr >> 8) & 0xff];
 615     if (!pci_dev) {
 616     fail:
 617         switch(len) {
 618         case 1:
 619             val = 0xff;
 620             break;
 621         case 2:
 622             val = 0xffff;
 623             break;
 624         default:
 625         case 4:
 626             val = 0xffffffff;
 627             break;
 628         }
 629         goto the_end;
 630     }
 631     config_addr = addr & 0xff;
 632     val = pci_dev->config_read(pci_dev, config_addr, len);
 633     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 634                 pci_dev->name, config_addr, val, len);
 635  the_end:
 636 #if 0
 637     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 638                 addr, val, len);
 639 #endif
 640     return val;
 641 }
 642
 643 /***********************************************************/
 644 /* generic PCI irq support */
 645
 646 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 647 static void pci_set_irq(void *opaque, int irq_num, int level)
 648 {
 649     PCIDevice *pci_dev = opaque;
 650     PCIBus *bus;
 651     int change;
 652
 653     change = level - pci_dev->irq_state[irq_num];
 654     if (!change)
 655         return;
 656
 657     pci_dev->irq_state[irq_num] = level;
 658     for (;;) {
 659         bus = pci_dev->bus;
 660         irq_num = bus->map_irq(pci_dev, irq_num);
 661         if (bus->set_irq)
 662             break;
 663         pci_dev = bus->parent_dev;
 664     }
 665     bus->irq_count[irq_num] += change;
 666     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 667 }
 668
 669 /***********************************************************/
 670 /* monitor info on PCI */
 671
 672 typedef struct {
 673     uint16_t class;
 674     const char *desc;
 675 } pci_class_desc;
 676
 677 static const pci_class_desc pci_class_descriptions[] =
 678 {
 679     { 0x0100, "SCSI controller"},
 680     { 0x0101, "IDE controller"},
 681     { 0x0102, "Floppy controller"},
 682     { 0x0103, "IPI controller"},
 683     { 0x0104, "RAID controller"},
 684     { 0x0106, "SATA controller"},
 685     { 0x0107, "SAS controller"},
 686     { 0x0180, "Storage controller"},
 687     { 0x0200, "Ethernet controller"},
 688     { 0x0201, "Token Ring controller"},
 689     { 0x0202, "FDDI controller"},
 690     { 0x0203, "ATM controller"},
 691     { 0x0280, "Network controller"},
 692     { 0x0300, "VGA controller"},
 693     { 0x0301, "XGA controller"},
 694     { 0x0302, "3D controller"},
 695     { 0x0380, "Display controller"},
 696     { 0x0400, "Video controller"},
 697     { 0x0401, "Audio controller"},
 698     { 0x0402, "Phone"},
 699     { 0x0480, "Multimedia controller"},
 700     { 0x0500, "RAM controller"},
 701     { 0x0501, "Flash controller"},
 702     { 0x0580, "Memory controller"},
 703     { 0x0600, "Host bridge"},
 704     { 0x0601, "ISA bridge"},
 705     { 0x0602, "EISA bridge"},
 706     { 0x0603, "MC bridge"},
 707     { 0x0604, "PCI bridge"},
 708     { 0x0605, "PCMCIA bridge"},
 709     { 0x0606, "NUBUS bridge"},
 710     { 0x0607, "CARDBUS bridge"},
 711     { 0x0608, "RACEWAY bridge"},
 712     { 0x0680, "Bridge"},
 713     { 0x0c03, "USB controller"},
 714     { 0, NULL}
 715 };
 716
 717 static void pci_info_device(PCIDevice *d)
 718 {
 719     Monitor *mon = cur_mon;
 720     int i, class;
 721     PCIIORegion *r;
 722     const pci_class_desc *desc;
 723
 724     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 725                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 726     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 727     monitor_printf(mon, "    ");
 728     desc = pci_class_descriptions;
 729     while (desc->desc && class != desc->class)
 730         desc++;
 731     if (desc->desc) {
 732         monitor_printf(mon, "%s", desc->desc);
 733     } else {
 734         monitor_printf(mon, "Class %04x", class);
 735     }
 736     monitor_printf(mon, ": PCI device %04x:%04x\n",
 737            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 738            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 739
 740     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 741         monitor_printf(mon, "      IRQ %d.\n",
 742                        d->config[PCI_INTERRUPT_LINE]);
 743     }
 744     if (class == 0x0604) {
 745         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 746     }
 747     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 748         r = &d->io_regions[i];
 749         if (r->size != 0) {
 750             monitor_printf(mon, "      BAR%d: ", i);
 751             if (r->type & PCI_ADDRESS_SPACE_IO) {
 752                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 753                                r->addr, r->addr + r->size - 1);
 754             } else {
 755                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 756                                r->addr, r->addr + r->size - 1);
 757             }
 758         }
 759     }
 760     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 761     if (class == 0x0604 && d->config[0x19] != 0) {
 762         pci_for_each_device(d->config[0x19], pci_info_device);
 763     }
 764 }
 765
 766 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 767 {
 768     PCIBus *bus = first_bus;
 769     PCIDevice *d;
 770     int devfn;
 771
 772     while (bus && bus->bus_num != bus_num)
 773         bus = bus->next;
 774     if (bus) {
 775         for(devfn = 0; devfn < 256; devfn++) {
 776             d = bus->devices[devfn];
 777             if (d)
 778                 fn(d);
 779         }
 780     }
 781 }
 782
 783 void pci_info(Monitor *mon)
 784 {
 785     pci_for_each_device(0, pci_info_device);
 786 }
 787
 788 PCIDevice *pci_create(const char *name, const char *devaddr)
 789 {
 790     PCIBus *bus;
 791     int devfn;
 792     DeviceState *dev;
 793
 794     bus = pci_get_bus_devfn(&devfn, devaddr);
 795     if (!bus) {
 796         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 797                 devaddr, name);
 798         exit(1);
 799     }
 800
 801     dev = qdev_create(&bus->qbus, name);
 802     qdev_prop_set_uint32(dev, "addr", devfn);
 803     return (PCIDevice *)dev;
 804 }
 805
 806 static const char * const pci_nic_models[] = {
 807     "ne2k_pci",
 808     "i82551",
 809     "i82557b",
 810     "i82559er",
 811     "rtl8139",
 812     "e1000",
 813     "pcnet",
 814     "virtio",
 815     NULL
 816 };
 817
 818 static const char * const pci_nic_names[] = {
 819     "ne2k_pci",
 820     "i82551",
 821     "i82557b",
 822     "i82559er",
 823     "rtl8139",
 824     "e1000",
 825     "pcnet",
 826     "virtio-net-pci",
 827     NULL
 828 };
 829
 830 int pci_nic_supported(const char *model)
 831 {
 832     int i;
 833
 834     for (i = 0; pci_nic_names[i]; i++)
 835         if (strcmp(model, pci_nic_names[i]) == 0)
 836             return 1;
 837
 838     return 0;
 839 }
 840
 841 /* Initialize a PCI NIC.  */
 842 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 843                         const char *default_devaddr)
 844 {
 845     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 846     PCIDevice *pci_dev;
 847     DeviceState *dev;
 848     int i;
 849
 850     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 851
 852     for (i = 0; pci_nic_models[i]; i++) {
 853         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 854             pci_dev = pci_create(pci_nic_names[i], devaddr);
 855             dev = &pci_dev->qdev;
 856             if (nd->id)
 857                 dev->id = qemu_strdup(nd->id);
 858             dev->nd = nd;
 859             qdev_init(dev);
 860             nd->private = dev;
 861             return pci_dev;
 862         }
 863     }
 864
 865     return NULL;
 866 }
 867
 868 typedef struct {
 869     PCIDevice dev;
 870     PCIBus bus;
 871     uint32_t vid;
 872     uint32_t did;
 873 } PCIBridge;
 874
 875 static void pci_bridge_write_config(PCIDevice *d,
 876                              uint32_t address, uint32_t val, int len)
 877 {
 878     PCIBridge *s = (PCIBridge *)d;
 879
 880     pci_default_write_config(d, address, val, len);
 881     s->bus.bus_num = d->config[PCI_SECONDARY_BUS];
 882 }
 883
 884 PCIBus *pci_find_bus(int bus_num)
 885 {
 886     PCIBus *bus = first_bus;
 887
 888     while (bus && bus->bus_num != bus_num)
 889         bus = bus->next;
 890
 891     return bus;
 892 }
 893
 894 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 895 {
 896     PCIBus *bus = pci_find_bus(bus_num);
 897
 898     if (!bus)
 899         return NULL;
 900
 901     return bus->devices[PCI_DEVFN(slot, function)];
 902 }
 903
 904 static int pci_bridge_initfn(PCIDevice *dev)
 905 {
 906     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
 907
 908     pci_config_set_vendor_id(s->dev.config, s->vid);
 909     pci_config_set_device_id(s->dev.config, s->did);
 910
 911     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 912     s->dev.config[0x05] = 0x00;
 913     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 914     s->dev.config[0x07] = 0x00; // status = fast devsel
 915     s->dev.config[0x08] = 0x00; // revision
 916     s->dev.config[0x09] = 0x00; // programming i/f
 917     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 918     s->dev.config[0x0D] = 0x10; // latency_timer
 919     s->dev.config[PCI_HEADER_TYPE] =
 920         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 921     s->dev.config[0x1E] = 0xa0; // secondary status
 922     return 0;
 923 }
 924
 925 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 926                         pci_map_irq_fn map_irq, const char *name)
 927 {
 928     PCIDevice *dev;
 929     PCIBridge *s;
 930
 931     dev = pci_create_noinit(bus, devfn, "pci-bridge");
 932     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
 933     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
 934     qdev_init(&dev->qdev);
 935
 936     s = DO_UPCAST(PCIBridge, dev, dev);
 937     pci_register_secondary_bus(&s->bus, &s->dev, map_irq, name);
 938     return &s->bus;
 939 }
 940
 941 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 942 {
 943     PCIDevice *pci_dev = (PCIDevice *)qdev;
 944     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 945     PCIBus *bus;
 946     int devfn;
 947
 948     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 949     devfn = pci_dev->devfn;
 950     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 951                                      info->config_read, info->config_write);
 952     assert(pci_dev);
 953     return info->init(pci_dev);
 954 }
 955
 956 void pci_qdev_register(PCIDeviceInfo *info)
 957 {
 958     info->qdev.init = pci_qdev_init;
 959     info->qdev.bus_info = &pci_bus_info;
 960     qdev_register(&info->qdev);
 961 }
 962
 963 void pci_qdev_register_many(PCIDeviceInfo *info)
 964 {
 965     while (info->qdev.name) {
 966         pci_qdev_register(info);
 967         info++;
 968     }
 969 }
 970
 971 PCIDevice *pci_create_noinit(PCIBus *bus, int devfn, const char *name)
 972 {
 973     DeviceState *dev;
 974
 975     dev = qdev_create(&bus->qbus, name);
 976     qdev_prop_set_uint32(dev, "addr", devfn);
 977     return DO_UPCAST(PCIDevice, qdev, dev);
 978 }
 979
 980 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 981 {
 982     PCIDevice *dev = pci_create_noinit(bus, devfn, name);
 983     qdev_init(&dev->qdev);
 984     return dev;
 985 }
 986
 987 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 988 {
 989     int offset = PCI_CONFIG_HEADER_SIZE;
 990     int i;
 991     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 992         if (pdev->used[i])
 993             offset = i + 1;
 994         else if (i - offset + 1 == size)
 995             return offset;
 996     return 0;
 997 }
 998
 999 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1000                                         uint8_t *prev_p)
1001 {
1002     uint8_t next, prev;
1003
1004     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1005         return 0;
1006
1007     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1008          prev = next + PCI_CAP_LIST_NEXT)
1009         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1010             break;
1011
1012     if (prev_p)
1013         *prev_p = prev;
1014     return next;
1015 }
1016
1017 /* Reserve space and add capability to the linked list in pci config space */
1018 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1019 {
1020     uint8_t offset = pci_find_space(pdev, size);
1021     uint8_t *config = pdev->config + offset;
1022     if (!offset)
1023         return -ENOSPC;
1024     config[PCI_CAP_LIST_ID] = cap_id;
1025     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1026     pdev->config[PCI_CAPABILITY_LIST] = offset;
1027     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1028     memset(pdev->used + offset, 0xFF, size);
1029     /* Make capability read-only by default */
1030     memset(pdev->wmask + offset, 0, size);
1031     /* Check capability by default */
1032     memset(pdev->cmask + offset, 0xFF, size);
1033     return offset;
1034 }
1035
1036 /* Unlink capability from the pci config space. */
1037 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1038 {
1039     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1040     if (!offset)
1041         return;
1042     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1043     /* Make capability writeable again */
1044     memset(pdev->wmask + offset, 0xff, size);
1045     /* Clear cmask as device-specific registers can't be checked */
1046     memset(pdev->cmask + offset, 0, size);
1047     memset(pdev->used + offset, 0, size);
1048
1049     if (!pdev->config[PCI_CAPABILITY_LIST])
1050         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1051 }
1052
1053 /* Reserve space for capability at a known offset (to call after load). */
1054 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1055 {
1056     memset(pdev->used + offset, 0xff, size);
1057 }
1058
1059 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1060 {
1061     return pci_find_capability_list(pdev, cap_id, NULL);
1062 }
1063
1064 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1065 {
1066     PCIDevice *d = (PCIDevice *)dev;
1067     const pci_class_desc *desc;
1068     char ctxt[64];
1069     PCIIORegion *r;
1070     int i, class;
1071
1072     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1073     desc = pci_class_descriptions;
1074     while (desc->desc && class != desc->class)
1075         desc++;
1076     if (desc->desc) {
1077         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1078     } else {
1079         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1080     }
1081
1082     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1083                    "pci id %04x:%04x (sub %04x:%04x)\n",
1084                    indent, "", ctxt,
1085                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1086                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1087                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1088                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1089                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1090     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1091         r = &d->io_regions[i];
1092         if (!r->size)
1093             continue;
1094         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1095                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1096                        r->addr, r->addr + r->size - 1);
1097     }
1098 }
1099
1100 static PCIDeviceInfo bridge_info = {
1101     .qdev.name    = "pci-bridge",
1102     .qdev.size    = sizeof(PCIBridge),
1103     .init         = pci_bridge_initfn,
1104     .config_write = pci_bridge_write_config,
1105     .qdev.props   = (Property[]) {
1106         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1107         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1108         DEFINE_PROP_END_OF_LIST(),
1109     }
1110 };
1111
1112 static void pci_register_devices(void)
1113 {
1114     pci_qdev_register(&bridge_info);
1115 }
1116
1117 device_init(pci_register_devices)