hw/pci_host.c

   1 /*
   2  * pci_host.c
   3  *
   4  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21
  22 #include "pci.h"
  23 #include "pci_host.h"
  24
  25 /* debug PCI */
  26 //#define DEBUG_PCI
  27
  28 #ifdef DEBUG_PCI
  29 #define PCI_DPRINTF(fmt, ...) \
  30 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
  31 #else
  32 #define PCI_DPRINTF(fmt, ...)
  33 #endif
  34
  35 /*
  36  * PCI address
  37  * bit 16 - 24: bus number
  38  * bit  8 - 15: devfun number
  39  * bit  0 -  7: offset in configuration space of a given pci device
  40  */
  41
  42 /* the helper functio to get a PCIDeice* for a given pci address */
  43 static inline PCIDevice *pci_addr_to_dev(PCIBus *bus, uint32_t addr)
  44 {
  45     uint8_t bus_num = (addr >> 16) & 0xff;
  46     uint8_t devfn = (addr >> 8) & 0xff;
  47     return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
  48 }
  49
  50 static inline uint32_t pci_addr_to_config(uint32_t addr)
  51 {
  52     return addr & (PCI_CONFIG_SPACE_SIZE - 1);
  53 }
  54
  55 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
  56 {
  57     PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
  58     uint32_t config_addr = pci_addr_to_config(addr);
  59
  60     if (!pci_dev)
  61         return;
  62
  63     PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRI32x" len=%d\n",
  64                 __func__, pci_dev->name, config_addr, val, len);
  65     pci_dev->config_write(pci_dev, config_addr, val, len);
  66 }
  67
  68 uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
  69 {
  70     PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
  71     uint32_t config_addr = pci_addr_to_config(addr);
  72     uint32_t val;
  73
  74     if (!pci_dev) {
  75         switch(len) {
  76         case 1:
  77             val = 0xff;
  78             break;
  79         case 2:
  80             val = 0xffff;
  81             break;
  82         default:
  83         case 4:
  84             val = 0xffffffff;
  85             break;
  86         }
  87     } else {
  88         val = pci_dev->config_read(pci_dev, config_addr, len);
  89         PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
  90                     __func__, pci_dev->name, config_addr, val, len);
  91     }
  92
  93     return val;
  94 }
  95
  96 static void pci_host_config_writel(void *opaque, target_phys_addr_t addr,
  97                                    uint32_t val)
  98 {
  99     PCIHostState *s = opaque;
 100
 101 #ifdef TARGET_WORDS_BIGENDIAN
 102     val = bswap32(val);
 103 #endif
 104     PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
 105                 __func__, addr, val);
 106     s->config_reg = val;
 107 }
 108
 109 static uint32_t pci_host_config_readl(void *opaque, target_phys_addr_t addr)
 110 {
 111     PCIHostState *s = opaque;
 112     uint32_t val = s->config_reg;
 113
 114 #ifdef TARGET_WORDS_BIGENDIAN
 115     val = bswap32(val);
 116 #endif
 117     PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
 118                 __func__, addr, val);
 119     return val;
 120 }
 121
 122 static CPUWriteMemoryFunc * const pci_host_config_write[] = {
 123     &pci_host_config_writel,
 124     &pci_host_config_writel,
 125     &pci_host_config_writel,
 126 };
 127
 128 static CPUReadMemoryFunc * const pci_host_config_read[] = {
 129     &pci_host_config_readl,
 130     &pci_host_config_readl,
 131     &pci_host_config_readl,
 132 };
 133
 134 int pci_host_config_register_io_memory(PCIHostState *s)
 135 {
 136     return cpu_register_io_memory(pci_host_config_read,
 137                                   pci_host_config_write, s);
 138 }
 139
 140 static void pci_host_config_writel_noswap(void *opaque,
 141                                           target_phys_addr_t addr,
 142                                           uint32_t val)
 143 {
 144     PCIHostState *s = opaque;
 145
 146     PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
 147                 __func__, addr, val);
 148     s->config_reg = val;
 149 }
 150
 151 static uint32_t pci_host_config_readl_noswap(void *opaque,
 152                                              target_phys_addr_t addr)
 153 {
 154     PCIHostState *s = opaque;
 155     uint32_t val = s->config_reg;
 156
 157     PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
 158                 __func__, addr, val);
 159     return val;
 160 }
 161
 162 static CPUWriteMemoryFunc * const pci_host_config_write_noswap[] = {
 163     &pci_host_config_writel_noswap,
 164     &pci_host_config_writel_noswap,
 165     &pci_host_config_writel_noswap,
 166 };
 167
 168 static CPUReadMemoryFunc * const pci_host_config_read_noswap[] = {
 169     &pci_host_config_readl_noswap,
 170     &pci_host_config_readl_noswap,
 171     &pci_host_config_readl_noswap,
 172 };
 173
 174 int pci_host_config_register_io_memory_noswap(PCIHostState *s)
 175 {
 176     return cpu_register_io_memory(pci_host_config_read_noswap,
 177                                   pci_host_config_write_noswap, s);
 178 }
 179
 180 static void pci_host_config_writel_ioport(void *opaque,
 181                                           uint32_t addr, uint32_t val)
 182 {
 183     PCIHostState *s = opaque;
 184
 185     PCI_DPRINTF("%s addr %"PRIx32 " val %"PRIx32"\n", __func__, addr, val);
 186     s->config_reg = val;
 187 }
 188
 189 static uint32_t pci_host_config_readl_ioport(void *opaque, uint32_t addr)
 190 {
 191     PCIHostState *s = opaque;
 192     uint32_t val = s->config_reg;
 193
 194     PCI_DPRINTF("%s addr %"PRIx32" val %"PRIx32"\n", __func__, addr, val);
 195     return val;
 196 }
 197
 198 void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s)
 199 {
 200     register_ioport_write(ioport, 4, 4, pci_host_config_writel_ioport, s);
 201     register_ioport_read(ioport, 4, 4, pci_host_config_readl_ioport, s);
 202 }
 203
 204 #define PCI_ADDR_T      target_phys_addr_t
 205 #define PCI_HOST_SUFFIX _mmio
 206
 207 #include "pci_host_template.h"
 208
 209 static CPUWriteMemoryFunc * const pci_host_data_write_mmio[] = {
 210     pci_host_data_writeb_mmio,
 211     pci_host_data_writew_mmio,
 212     pci_host_data_writel_mmio,
 213 };
 214
 215 static CPUReadMemoryFunc * const pci_host_data_read_mmio[] = {
 216     pci_host_data_readb_mmio,
 217     pci_host_data_readw_mmio,
 218     pci_host_data_readl_mmio,
 219 };
 220
 221 int pci_host_data_register_io_memory(PCIHostState *s)
 222 {
 223     return cpu_register_io_memory(pci_host_data_read_mmio,
 224                                   pci_host_data_write_mmio,
 225                                   s);
 226 }
 227
 228 #undef PCI_ADDR_T
 229 #undef PCI_HOST_SUFFIX
 230
 231 #define PCI_ADDR_T      uint32_t
 232 #define PCI_HOST_SUFFIX _ioport
 233
 234 #include "pci_host_template.h"
 235
 236 void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
 237 {
 238     register_ioport_write(ioport, 4, 1, pci_host_data_writeb_ioport, s);
 239     register_ioport_write(ioport, 4, 2, pci_host_data_writew_ioport, s);
 240     register_ioport_write(ioport, 4, 4, pci_host_data_writel_ioport, s);
 241     register_ioport_read(ioport, 4, 1, pci_host_data_readb_ioport, s);
 242     register_ioport_read(ioport, 4, 2, pci_host_data_readw_ioport, s);
 243     register_ioport_read(ioport, 4, 4, pci_host_data_readl_ioport, s);
 244 }