mainstone: convert to memory API
[qemu.git] / hw / pl061.c
blobd13746cfe5c557593f45a104ad24ece8acc7f05b
1 /*
2 * Arm PrimeCell PL061 General Purpose IO with additional
3 * Luminary Micro Stellaris bits.
5 * Copyright (c) 2007 CodeSourcery.
6 * Written by Paul Brook
8 * This code is licensed under the GPL.
9 */
11 #include "sysbus.h"
13 //#define DEBUG_PL061 1
15 #ifdef DEBUG_PL061
16 #define DPRINTF(fmt, ...) \
17 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
18 #define BADF(fmt, ...) \
19 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
20 #else
21 #define DPRINTF(fmt, ...) do {} while(0)
22 #define BADF(fmt, ...) \
23 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
24 #endif
26 static const uint8_t pl061_id[12] =
27 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
28 static const uint8_t pl061_id_luminary[12] =
29 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
31 typedef struct {
32 SysBusDevice busdev;
33 uint32_t locked;
34 uint32_t data;
35 uint32_t old_data;
36 uint32_t dir;
37 uint32_t isense;
38 uint32_t ibe;
39 uint32_t iev;
40 uint32_t im;
41 uint32_t istate;
42 uint32_t afsel;
43 uint32_t dr2r;
44 uint32_t dr4r;
45 uint32_t dr8r;
46 uint32_t odr;
47 uint32_t pur;
48 uint32_t pdr;
49 uint32_t slr;
50 uint32_t den;
51 uint32_t cr;
52 uint32_t float_high;
53 uint32_t amsel;
54 qemu_irq irq;
55 qemu_irq out[8];
56 const unsigned char *id;
57 } pl061_state;
59 static const VMStateDescription vmstate_pl061 = {
60 .name = "pl061",
61 .version_id = 2,
62 .minimum_version_id = 1,
63 .fields = (VMStateField[]) {
64 VMSTATE_UINT32(locked, pl061_state),
65 VMSTATE_UINT32(data, pl061_state),
66 VMSTATE_UINT32(old_data, pl061_state),
67 VMSTATE_UINT32(dir, pl061_state),
68 VMSTATE_UINT32(isense, pl061_state),
69 VMSTATE_UINT32(ibe, pl061_state),
70 VMSTATE_UINT32(iev, pl061_state),
71 VMSTATE_UINT32(im, pl061_state),
72 VMSTATE_UINT32(istate, pl061_state),
73 VMSTATE_UINT32(afsel, pl061_state),
74 VMSTATE_UINT32(dr2r, pl061_state),
75 VMSTATE_UINT32(dr4r, pl061_state),
76 VMSTATE_UINT32(dr8r, pl061_state),
77 VMSTATE_UINT32(odr, pl061_state),
78 VMSTATE_UINT32(pur, pl061_state),
79 VMSTATE_UINT32(pdr, pl061_state),
80 VMSTATE_UINT32(slr, pl061_state),
81 VMSTATE_UINT32(den, pl061_state),
82 VMSTATE_UINT32(cr, pl061_state),
83 VMSTATE_UINT32(float_high, pl061_state),
84 VMSTATE_UINT32_V(amsel, pl061_state, 2),
85 VMSTATE_END_OF_LIST()
89 static void pl061_update(pl061_state *s)
91 uint8_t changed;
92 uint8_t mask;
93 uint8_t out;
94 int i;
96 /* Outputs float high. */
97 /* FIXME: This is board dependent. */
98 out = (s->data & s->dir) | ~s->dir;
99 changed = s->old_data ^ out;
100 if (!changed)
101 return;
103 s->old_data = out;
104 for (i = 0; i < 8; i++) {
105 mask = 1 << i;
106 if ((changed & mask) && s->out) {
107 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
108 qemu_set_irq(s->out[i], (out & mask) != 0);
112 /* FIXME: Implement input interrupts. */
115 static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
117 pl061_state *s = (pl061_state *)opaque;
119 if (offset >= 0xfd0 && offset < 0x1000) {
120 return s->id[(offset - 0xfd0) >> 2];
122 if (offset < 0x400) {
123 return s->data & (offset >> 2);
125 switch (offset) {
126 case 0x400: /* Direction */
127 return s->dir;
128 case 0x404: /* Interrupt sense */
129 return s->isense;
130 case 0x408: /* Interrupt both edges */
131 return s->ibe;
132 case 0x40c: /* Interrupt event */
133 return s->iev;
134 case 0x410: /* Interrupt mask */
135 return s->im;
136 case 0x414: /* Raw interrupt status */
137 return s->istate;
138 case 0x418: /* Masked interrupt status */
139 return s->istate | s->im;
140 case 0x420: /* Alternate function select */
141 return s->afsel;
142 case 0x500: /* 2mA drive */
143 return s->dr2r;
144 case 0x504: /* 4mA drive */
145 return s->dr4r;
146 case 0x508: /* 8mA drive */
147 return s->dr8r;
148 case 0x50c: /* Open drain */
149 return s->odr;
150 case 0x510: /* Pull-up */
151 return s->pur;
152 case 0x514: /* Pull-down */
153 return s->pdr;
154 case 0x518: /* Slew rate control */
155 return s->slr;
156 case 0x51c: /* Digital enable */
157 return s->den;
158 case 0x520: /* Lock */
159 return s->locked;
160 case 0x524: /* Commit */
161 return s->cr;
162 case 0x528: /* Analog mode select */
163 return s->amsel;
164 default:
165 hw_error("pl061_read: Bad offset %x\n", (int)offset);
166 return 0;
170 static void pl061_write(void *opaque, target_phys_addr_t offset,
171 uint32_t value)
173 pl061_state *s = (pl061_state *)opaque;
174 uint8_t mask;
176 if (offset < 0x400) {
177 mask = (offset >> 2) & s->dir;
178 s->data = (s->data & ~mask) | (value & mask);
179 pl061_update(s);
180 return;
182 switch (offset) {
183 case 0x400: /* Direction */
184 s->dir = value & 0xff;
185 break;
186 case 0x404: /* Interrupt sense */
187 s->isense = value & 0xff;
188 break;
189 case 0x408: /* Interrupt both edges */
190 s->ibe = value & 0xff;
191 break;
192 case 0x40c: /* Interrupt event */
193 s->iev = value & 0xff;
194 break;
195 case 0x410: /* Interrupt mask */
196 s->im = value & 0xff;
197 break;
198 case 0x41c: /* Interrupt clear */
199 s->istate &= ~value;
200 break;
201 case 0x420: /* Alternate function select */
202 mask = s->cr;
203 s->afsel = (s->afsel & ~mask) | (value & mask);
204 break;
205 case 0x500: /* 2mA drive */
206 s->dr2r = value & 0xff;
207 break;
208 case 0x504: /* 4mA drive */
209 s->dr4r = value & 0xff;
210 break;
211 case 0x508: /* 8mA drive */
212 s->dr8r = value & 0xff;
213 break;
214 case 0x50c: /* Open drain */
215 s->odr = value & 0xff;
216 break;
217 case 0x510: /* Pull-up */
218 s->pur = value & 0xff;
219 break;
220 case 0x514: /* Pull-down */
221 s->pdr = value & 0xff;
222 break;
223 case 0x518: /* Slew rate control */
224 s->slr = value & 0xff;
225 break;
226 case 0x51c: /* Digital enable */
227 s->den = value & 0xff;
228 break;
229 case 0x520: /* Lock */
230 s->locked = (value != 0xacce551);
231 break;
232 case 0x524: /* Commit */
233 if (!s->locked)
234 s->cr = value & 0xff;
235 break;
236 case 0x528:
237 s->amsel = value & 0xff;
238 break;
239 default:
240 hw_error("pl061_write: Bad offset %x\n", (int)offset);
242 pl061_update(s);
245 static void pl061_reset(pl061_state *s)
247 s->locked = 1;
248 s->cr = 0xff;
251 static void pl061_set_irq(void * opaque, int irq, int level)
253 pl061_state *s = (pl061_state *)opaque;
254 uint8_t mask;
256 mask = 1 << irq;
257 if ((s->dir & mask) == 0) {
258 s->data &= ~mask;
259 if (level)
260 s->data |= mask;
261 pl061_update(s);
265 static CPUReadMemoryFunc * const pl061_readfn[] = {
266 pl061_read,
267 pl061_read,
268 pl061_read
271 static CPUWriteMemoryFunc * const pl061_writefn[] = {
272 pl061_write,
273 pl061_write,
274 pl061_write
277 static int pl061_init(SysBusDevice *dev, const unsigned char *id)
279 int iomemtype;
280 pl061_state *s = FROM_SYSBUS(pl061_state, dev);
281 s->id = id;
282 iomemtype = cpu_register_io_memory(pl061_readfn,
283 pl061_writefn, s,
284 DEVICE_NATIVE_ENDIAN);
285 sysbus_init_mmio(dev, 0x1000, iomemtype);
286 sysbus_init_irq(dev, &s->irq);
287 qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
288 qdev_init_gpio_out(&dev->qdev, s->out, 8);
289 pl061_reset(s);
290 return 0;
293 static int pl061_init_luminary(SysBusDevice *dev)
295 return pl061_init(dev, pl061_id_luminary);
298 static int pl061_init_arm(SysBusDevice *dev)
300 return pl061_init(dev, pl061_id);
303 static SysBusDeviceInfo pl061_info = {
304 .init = pl061_init_arm,
305 .qdev.name = "pl061",
306 .qdev.size = sizeof(pl061_state),
307 .qdev.vmsd = &vmstate_pl061,
310 static SysBusDeviceInfo pl061_luminary_info = {
311 .init = pl061_init_luminary,
312 .qdev.name = "pl061_luminary",
313 .qdev.size = sizeof(pl061_state),
314 .qdev.vmsd = &vmstate_pl061,
317 static void pl061_register_devices(void)
319 sysbus_register_withprop(&pl061_info);
320 sysbus_register_withprop(&pl061_luminary_info);
323 device_init(pl061_register_devices)