user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/bitops.h"
  24
  25 #undef EAX
  26 #undef ECX
  27 #undef EDX
  28 #undef EBX
  29 #undef ESP
  30 #undef EBP
  31 #undef ESI
  32 #undef EDI
  33 #undef EIP
  34 #include <signal.h>
  35 #ifdef __linux__
  36 #include <sys/ucontext.h>
  37 #endif
  38
  39 //#define DEBUG_SIGNAL
  40
  41 static void exception_action(CPUArchState *env1)
  42 {
  43 #if defined(TARGET_I386)
  44     raise_exception_err(env1, env1->exception_index, env1->error_code);
  45 #else
  46     cpu_loop_exit(env1);
  47 #endif
  48 }
  49
  50 /* exit the current TB from a signal handler. The host registers are
  51    restored in a state compatible with the CPU emulator
  52  */
  53 void cpu_resume_from_signal(CPUArchState *env1, void *puc)
  54 {
  55 #ifdef __linux__
  56     struct ucontext *uc = puc;
  57 #elif defined(__OpenBSD__)
  58     struct sigcontext *uc = puc;
  59 #endif
  60
  61     if (puc) {
  62         /* XXX: use siglongjmp ? */
  63 #ifdef __linux__
  64 #ifdef __ia64
  65         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  66 #else
  67         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  68 #endif
  69 #elif defined(__OpenBSD__)
  70         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  71 #endif
  72     }
  73     env1->exception_index = -1;
  74     siglongjmp(env1->jmp_env, 1);
  75 }
  76
  77 /* 'pc' is the host PC at which the exception was raised. 'address' is
  78    the effective address of the memory exception. 'is_write' is 1 if a
  79    write caused the exception and otherwise 0'. 'old_set' is the
  80    signal set which should be restored */
  81 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
  82                                     int is_write, sigset_t *old_set,
  83                                     void *puc)
  84 {
  85     int ret;
  86
  87 #if defined(DEBUG_SIGNAL)
  88     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  89                 pc, address, is_write, *(unsigned long *)old_set);
  90 #endif
  91     /* XXX: locking issue */
  92     if (is_write && h2g_valid(address)
  93         && page_unprotect(h2g(address), pc, puc)) {
  94         return 1;
  95     }
  96
  97     /* see if it is an MMU fault */
  98     ret = cpu_handle_mmu_fault(cpu_single_env, address, is_write,
  99                                MMU_USER_IDX);
 100     if (ret < 0) {
 101         return 0; /* not an MMU fault */
 102     }
 103     if (ret == 0) {
 104         return 1; /* the MMU fault was handled without causing real CPU fault */
 105     }
 106     /* now we have a real cpu fault */
 107     cpu_restore_state(cpu_single_env, pc);
 108
 109     /* we restore the process signal mask as the sigreturn should
 110        do it (XXX: use sigsetjmp) */
 111     sigprocmask(SIG_SETMASK, old_set, NULL);
 112     exception_action(cpu_single_env);
 113
 114     /* never comes here */
 115     return 1;
 116 }
 117
 118 #if defined(__i386__)
 119
 120 #if defined(__APPLE__)
 121 #include <sys/ucontext.h>
 122
 123 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
 124 #define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 125 #define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 126 #define MASK_sig(context)    ((context)->uc_sigmask)
 127 #elif defined(__NetBSD__)
 128 #include <ucontext.h>
 129
 130 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 131 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 132 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 133 #define MASK_sig(context)    ((context)->uc_sigmask)
 134 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 135 #include <ucontext.h>
 136
 137 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 138 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 139 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 140 #define MASK_sig(context)    ((context)->uc_sigmask)
 141 #elif defined(__OpenBSD__)
 142 #define EIP_sig(context)     ((context)->sc_eip)
 143 #define TRAP_sig(context)    ((context)->sc_trapno)
 144 #define ERROR_sig(context)   ((context)->sc_err)
 145 #define MASK_sig(context)    ((context)->sc_mask)
 146 #else
 147 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 148 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 149 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 150 #define MASK_sig(context)    ((context)->uc_sigmask)
 151 #endif
 152
 153 int cpu_signal_handler(int host_signum, void *pinfo,
 154                        void *puc)
 155 {
 156     siginfo_t *info = pinfo;
 157 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 158     ucontext_t *uc = puc;
 159 #elif defined(__OpenBSD__)
 160     struct sigcontext *uc = puc;
 161 #else
 162     struct ucontext *uc = puc;
 163 #endif
 164     unsigned long pc;
 165     int trapno;
 166
 167 #ifndef REG_EIP
 168 /* for glibc 2.1 */
 169 #define REG_EIP    EIP
 170 #define REG_ERR    ERR
 171 #define REG_TRAPNO TRAPNO
 172 #endif
 173     pc = EIP_sig(uc);
 174     trapno = TRAP_sig(uc);
 175     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 176                              trapno == 0xe ?
 177                              (ERROR_sig(uc) >> 1) & 1 : 0,
 178                              &MASK_sig(uc), puc);
 179 }
 180
 181 #elif defined(__x86_64__)
 182
 183 #ifdef __NetBSD__
 184 #define PC_sig(context)       _UC_MACHINE_PC(context)
 185 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 186 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 187 #define MASK_sig(context)     ((context)->uc_sigmask)
 188 #elif defined(__OpenBSD__)
 189 #define PC_sig(context)       ((context)->sc_rip)
 190 #define TRAP_sig(context)     ((context)->sc_trapno)
 191 #define ERROR_sig(context)    ((context)->sc_err)
 192 #define MASK_sig(context)     ((context)->sc_mask)
 193 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 194 #include <ucontext.h>
 195
 196 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 197 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 198 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 199 #define MASK_sig(context)     ((context)->uc_sigmask)
 200 #else
 201 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 202 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 203 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 204 #define MASK_sig(context)     ((context)->uc_sigmask)
 205 #endif
 206
 207 int cpu_signal_handler(int host_signum, void *pinfo,
 208                        void *puc)
 209 {
 210     siginfo_t *info = pinfo;
 211     unsigned long pc;
 212 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 213     ucontext_t *uc = puc;
 214 #elif defined(__OpenBSD__)
 215     struct sigcontext *uc = puc;
 216 #else
 217     struct ucontext *uc = puc;
 218 #endif
 219
 220     pc = PC_sig(uc);
 221     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 222                              TRAP_sig(uc) == 0xe ?
 223                              (ERROR_sig(uc) >> 1) & 1 : 0,
 224                              &MASK_sig(uc), puc);
 225 }
 226
 227 #elif defined(_ARCH_PPC)
 228
 229 /***********************************************************************
 230  * signal context platform-specific definitions
 231  * From Wine
 232  */
 233 #ifdef linux
 234 /* All Registers access - only for local access */
 235 #define REG_sig(reg_name, context)              \
 236     ((context)->uc_mcontext.regs->reg_name)
 237 /* Gpr Registers access  */
 238 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 239 /* Program counter */
 240 #define IAR_sig(context)                       REG_sig(nip, context)
 241 /* Machine State Register (Supervisor) */
 242 #define MSR_sig(context)                       REG_sig(msr, context)
 243 /* Count register */
 244 #define CTR_sig(context)                       REG_sig(ctr, context)
 245 /* User's integer exception register */
 246 #define XER_sig(context)                       REG_sig(xer, context)
 247 /* Link register */
 248 #define LR_sig(context)                        REG_sig(link, context)
 249 /* Condition register */
 250 #define CR_sig(context)                        REG_sig(ccr, context)
 251
 252 /* Float Registers access  */
 253 #define FLOAT_sig(reg_num, context)                                     \
 254     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 255 #define FPSCR_sig(context) \
 256     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 257 /* Exception Registers access */
 258 #define DAR_sig(context)                       REG_sig(dar, context)
 259 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 260 #define TRAP_sig(context)                      REG_sig(trap, context)
 261 #endif /* linux */
 262
 263 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 264 #include <ucontext.h>
 265 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 266 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 267 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 268 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 269 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 270 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 271 /* Exception Registers access */
 272 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 273 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 274 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 275 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 276
 277 #ifdef __APPLE__
 278 #include <sys/ucontext.h>
 279 typedef struct ucontext SIGCONTEXT;
 280 /* All Registers access - only for local access */
 281 #define REG_sig(reg_name, context)              \
 282     ((context)->uc_mcontext->ss.reg_name)
 283 #define FLOATREG_sig(reg_name, context)         \
 284     ((context)->uc_mcontext->fs.reg_name)
 285 #define EXCEPREG_sig(reg_name, context)         \
 286     ((context)->uc_mcontext->es.reg_name)
 287 #define VECREG_sig(reg_name, context)           \
 288     ((context)->uc_mcontext->vs.reg_name)
 289 /* Gpr Registers access */
 290 #define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 291 /* Program counter */
 292 #define IAR_sig(context)                       REG_sig(srr0, context)
 293 /* Machine State Register (Supervisor) */
 294 #define MSR_sig(context)                       REG_sig(srr1, context)
 295 #define CTR_sig(context)                       REG_sig(ctr, context)
 296 /* Link register */
 297 #define XER_sig(context)                       REG_sig(xer, context)
 298 /* User's integer exception register */
 299 #define LR_sig(context)                        REG_sig(lr, context)
 300 /* Condition register */
 301 #define CR_sig(context)                        REG_sig(cr, context)
 302 /* Float Registers access */
 303 #define FLOAT_sig(reg_num, context)             \
 304     FLOATREG_sig(fpregs[reg_num], context)
 305 #define FPSCR_sig(context)                      \
 306     ((double)FLOATREG_sig(fpscr, context))
 307 /* Exception Registers access */
 308 /* Fault registers for coredump */
 309 #define DAR_sig(context)                       EXCEPREG_sig(dar, context)
 310 #define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 311 /* number of powerpc exception taken */
 312 #define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
 313 #endif /* __APPLE__ */
 314
 315 int cpu_signal_handler(int host_signum, void *pinfo,
 316                        void *puc)
 317 {
 318     siginfo_t *info = pinfo;
 319 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 320     ucontext_t *uc = puc;
 321 #else
 322     struct ucontext *uc = puc;
 323 #endif
 324     unsigned long pc;
 325     int is_write;
 326
 327     pc = IAR_sig(uc);
 328     is_write = 0;
 329 #if 0
 330     /* ppc 4xx case */
 331     if (DSISR_sig(uc) & 0x00800000) {
 332         is_write = 1;
 333     }
 334 #else
 335     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 336         is_write = 1;
 337     }
 338 #endif
 339     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 340                              is_write, &uc->uc_sigmask, puc);
 341 }
 342
 343 #elif defined(__alpha__)
 344
 345 int cpu_signal_handler(int host_signum, void *pinfo,
 346                            void *puc)
 347 {
 348     siginfo_t *info = pinfo;
 349     struct ucontext *uc = puc;
 350     uint32_t *pc = uc->uc_mcontext.sc_pc;
 351     uint32_t insn = *pc;
 352     int is_write = 0;
 353
 354     /* XXX: need kernel patch to get write flag faster */
 355     switch (insn >> 26) {
 356     case 0x0d: /* stw */
 357     case 0x0e: /* stb */
 358     case 0x0f: /* stq_u */
 359     case 0x24: /* stf */
 360     case 0x25: /* stg */
 361     case 0x26: /* sts */
 362     case 0x27: /* stt */
 363     case 0x2c: /* stl */
 364     case 0x2d: /* stq */
 365     case 0x2e: /* stl_c */
 366     case 0x2f: /* stq_c */
 367         is_write = 1;
 368     }
 369
 370     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 371                              is_write, &uc->uc_sigmask, puc);
 372 }
 373 #elif defined(__sparc__)
 374
 375 int cpu_signal_handler(int host_signum, void *pinfo,
 376                        void *puc)
 377 {
 378     siginfo_t *info = pinfo;
 379     int is_write;
 380     uint32_t insn;
 381 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 382     uint32_t *regs = (uint32_t *)(info + 1);
 383     void *sigmask = (regs + 20);
 384     /* XXX: is there a standard glibc define ? */
 385     unsigned long pc = regs[1];
 386 #else
 387 #ifdef __linux__
 388     struct sigcontext *sc = puc;
 389     unsigned long pc = sc->sigc_regs.tpc;
 390     void *sigmask = (void *)sc->sigc_mask;
 391 #elif defined(__OpenBSD__)
 392     struct sigcontext *uc = puc;
 393     unsigned long pc = uc->sc_pc;
 394     void *sigmask = (void *)(long)uc->sc_mask;
 395 #endif
 396 #endif
 397
 398     /* XXX: need kernel patch to get write flag faster */
 399     is_write = 0;
 400     insn = *(uint32_t *)pc;
 401     if ((insn >> 30) == 3) {
 402         switch ((insn >> 19) & 0x3f) {
 403         case 0x05: /* stb */
 404         case 0x15: /* stba */
 405         case 0x06: /* sth */
 406         case 0x16: /* stha */
 407         case 0x04: /* st */
 408         case 0x14: /* sta */
 409         case 0x07: /* std */
 410         case 0x17: /* stda */
 411         case 0x0e: /* stx */
 412         case 0x1e: /* stxa */
 413         case 0x24: /* stf */
 414         case 0x34: /* stfa */
 415         case 0x27: /* stdf */
 416         case 0x37: /* stdfa */
 417         case 0x26: /* stqf */
 418         case 0x36: /* stqfa */
 419         case 0x25: /* stfsr */
 420         case 0x3c: /* casa */
 421         case 0x3e: /* casxa */
 422             is_write = 1;
 423             break;
 424         }
 425     }
 426     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 427                              is_write, sigmask, NULL);
 428 }
 429
 430 #elif defined(__arm__)
 431
 432 int cpu_signal_handler(int host_signum, void *pinfo,
 433                        void *puc)
 434 {
 435     siginfo_t *info = pinfo;
 436     struct ucontext *uc = puc;
 437     unsigned long pc;
 438     int is_write;
 439
 440 #if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 441     pc = uc->uc_mcontext.gregs[R15];
 442 #else
 443     pc = uc->uc_mcontext.arm_pc;
 444 #endif
 445
 446     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 447      * later processor; on v5 we will always report this as a read).
 448      */
 449     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 450     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 451                              is_write,
 452                              &uc->uc_sigmask, puc);
 453 }
 454
 455 #elif defined(__aarch64__)
 456
 457 int cpu_signal_handler(int host_signum, void *pinfo,
 458                        void *puc)
 459 {
 460     siginfo_t *info = pinfo;
 461     struct ucontext *uc = puc;
 462     uint64_t pc;
 463     int is_write = 0; /* XXX how to determine? */
 464
 465     pc = uc->uc_mcontext.pc;
 466     return handle_cpu_signal(pc, (uint64_t)info->si_addr,
 467                              is_write, &uc->uc_sigmask, puc);
 468 }
 469
 470 #elif defined(__mc68000)
 471
 472 int cpu_signal_handler(int host_signum, void *pinfo,
 473                        void *puc)
 474 {
 475     siginfo_t *info = pinfo;
 476     struct ucontext *uc = puc;
 477     unsigned long pc;
 478     int is_write;
 479
 480     pc = uc->uc_mcontext.gregs[16];
 481     /* XXX: compute is_write */
 482     is_write = 0;
 483     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 484                              is_write,
 485                              &uc->uc_sigmask, puc);
 486 }
 487
 488 #elif defined(__ia64)
 489
 490 #ifndef __ISR_VALID
 491   /* This ought to be in <bits/siginfo.h>... */
 492 # define __ISR_VALID    1
 493 #endif
 494
 495 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 496 {
 497     siginfo_t *info = pinfo;
 498     struct ucontext *uc = puc;
 499     unsigned long ip;
 500     int is_write = 0;
 501
 502     ip = uc->uc_mcontext.sc_ip;
 503     switch (host_signum) {
 504     case SIGILL:
 505     case SIGFPE:
 506     case SIGSEGV:
 507     case SIGBUS:
 508     case SIGTRAP:
 509         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 510             /* ISR.W (write-access) is bit 33:  */
 511             is_write = (info->si_isr >> 33) & 1;
 512         }
 513         break;
 514
 515     default:
 516         break;
 517     }
 518     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
 519                              is_write,
 520                              (sigset_t *)&uc->uc_sigmask, puc);
 521 }
 522
 523 #elif defined(__s390__)
 524
 525 int cpu_signal_handler(int host_signum, void *pinfo,
 526                        void *puc)
 527 {
 528     siginfo_t *info = pinfo;
 529     struct ucontext *uc = puc;
 530     unsigned long pc;
 531     uint16_t *pinsn;
 532     int is_write = 0;
 533
 534     pc = uc->uc_mcontext.psw.addr;
 535
 536     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 537        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 538        from the hardware which does in fact contain the is_write value.
 539        The rt signal handler, as far as I can tell, does not give this value
 540        at all.  Not that we could get to it from here even if it were.  */
 541     /* ??? This is not even close to complete, since it ignores all
 542        of the read-modify-write instructions.  */
 543     pinsn = (uint16_t *)pc;
 544     switch (pinsn[0] >> 8) {
 545     case 0x50: /* ST */
 546     case 0x42: /* STC */
 547     case 0x40: /* STH */
 548         is_write = 1;
 549         break;
 550     case 0xc4: /* RIL format insns */
 551         switch (pinsn[0] & 0xf) {
 552         case 0xf: /* STRL */
 553         case 0xb: /* STGRL */
 554         case 0x7: /* STHRL */
 555             is_write = 1;
 556         }
 557         break;
 558     case 0xe3: /* RXY format insns */
 559         switch (pinsn[2] & 0xff) {
 560         case 0x50: /* STY */
 561         case 0x24: /* STG */
 562         case 0x72: /* STCY */
 563         case 0x70: /* STHY */
 564         case 0x8e: /* STPQ */
 565         case 0x3f: /* STRVH */
 566         case 0x3e: /* STRV */
 567         case 0x2f: /* STRVG */
 568             is_write = 1;
 569         }
 570         break;
 571     }
 572     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 573                              is_write, &uc->uc_sigmask, puc);
 574 }
 575
 576 #elif defined(__mips__)
 577
 578 int cpu_signal_handler(int host_signum, void *pinfo,
 579                        void *puc)
 580 {
 581     siginfo_t *info = pinfo;
 582     struct ucontext *uc = puc;
 583     greg_t pc = uc->uc_mcontext.pc;
 584     int is_write;
 585
 586     /* XXX: compute is_write */
 587     is_write = 0;
 588     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 589                              is_write, &uc->uc_sigmask, puc);
 590 }
 591
 592 #elif defined(__hppa__)
 593
 594 int cpu_signal_handler(int host_signum, void *pinfo,
 595                        void *puc)
 596 {
 597     siginfo_t *info = pinfo;
 598     struct ucontext *uc = puc;
 599     unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
 600     uint32_t insn = *(uint32_t *)pc;
 601     int is_write = 0;
 602
 603     /* XXX: need kernel patch to get write flag faster.  */
 604     switch (insn >> 26) {
 605     case 0x1a: /* STW */
 606     case 0x19: /* STH */
 607     case 0x18: /* STB */
 608     case 0x1b: /* STWM */
 609         is_write = 1;
 610         break;
 611
 612     case 0x09: /* CSTWX, FSTWX, FSTWS */
 613     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 614         /* Distinguish from coprocessor load ... */
 615         is_write = (insn >> 9) & 1;
 616         break;
 617
 618     case 0x03:
 619         switch ((insn >> 6) & 15) {
 620         case 0xa: /* STWS */
 621         case 0x9: /* STHS */
 622         case 0x8: /* STBS */
 623         case 0xe: /* STWAS */
 624         case 0xc: /* STBYS */
 625             is_write = 1;
 626         }
 627         break;
 628     }
 629
 630     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 631                              is_write, &uc->uc_sigmask, puc);
 632 }
 633
 634 #else
 635
 636 #error host CPU specific signal handler needed
 637
 638 #endif