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usb-ehci: add queue data struct
[qemu.git] / hw / usb-ehci.c
blob3656a353d3ee91f283acd331f913b50c3018e85c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33 #include "trace.h"
34
35 #define EHCI_DEBUG 0
36
37 #if EHCI_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
42
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
45
46 #define MMIO_SIZE 0x1000
47
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
59
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87 /*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
93
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
99
100 #define CONFIGFLAG OPREGBASE + 0x0040
101
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
105 /*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109 #define PORTSC_RO_MASK 0x007021c5
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
140
141 /* Internal periodic / asynchronous schedule state machine states
142 */
143 typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159 } EHCI_STATES;
160
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173 /* EHCI spec version 1.0 Section 3.3
174 */
175 typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIQueue EHCIQueue;
338 typedef struct EHCIState EHCIState;
339
340 enum async_state {
341 EHCI_ASYNC_NONE = 0,
342 EHCI_ASYNC_INFLIGHT,
343 EHCI_ASYNC_FINISHED,
344 };
345
346 struct EHCIQueue {
347 EHCIState *ehci;
348
349 /* cached data from guest - needs to be flushed
350 * when guest removes an entry (doorbell, handshake sequence)
351 */
352 EHCIqh qh; // copy of current QH (being worked on)
353 uint32_t qhaddr; // address QH read from
354 EHCIqtd qtd; // copy of current QTD (being worked on)
355 uint32_t qtdaddr; // address QTD read from
356
357 USBPacket packet;
358 uint8_t buffer[BUFF_SIZE];
359 int pid;
360 uint32_t tbytes;
361 enum async_state async;
362 int usb_status;
363 };
364
365 struct EHCIState {
366 PCIDevice dev;
367 USBBus bus;
368 qemu_irq irq;
369 target_phys_addr_t mem_base;
370 int mem;
371 int num_ports;
372 /*
373 * EHCI spec version 1.0 Section 2.3
374 * Host Controller Operational Registers
375 */
376 union {
377 uint8_t mmio[MMIO_SIZE];
378 struct {
379 uint8_t cap[OPREGBASE];
380 uint32_t usbcmd;
381 uint32_t usbsts;
382 uint32_t usbintr;
383 uint32_t frindex;
384 uint32_t ctrldssegment;
385 uint32_t periodiclistbase;
386 uint32_t asynclistaddr;
387 uint32_t notused[9];
388 uint32_t configflag;
389 uint32_t portsc[NB_PORTS];
390 };
391 };
392
393 /*
394 * Internal states, shadow registers, etc
395 */
396 uint32_t sofv;
397 QEMUTimer *frame_timer;
398 int attach_poll_counter;
399 int astate; // Current state in asynchronous schedule
400 int pstate; // Current state in periodic schedule
401 USBPort ports[NB_PORTS];
402 uint32_t usbsts_pending;
403 EHCIQueue queue;
404
405 uint32_t a_fetch_addr; // which address to look at next
406 uint32_t p_fetch_addr; // which address to look at next
407
408 USBPacket ipacket;
409 uint8_t ibuffer[BUFF_SIZE];
410 int isoch_pause;
411
412 uint32_t last_run_usec;
413 uint32_t frame_end_usec;
414 };
415
416 #define SET_LAST_RUN_CLOCK(s) \
417 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
418
419 /* nifty macros from Arnon's EHCI version */
420 #define get_field(data, field) \
421 (((data) & field##_MASK) >> field##_SH)
422
423 #define set_field(data, newval, field) do { \
424 uint32_t val = *data; \
425 val &= ~ field##_MASK; \
426 val |= ((newval) << field##_SH) & field##_MASK; \
427 *data = val; \
428 } while(0)
429
430 static const char *ehci_state_names[] = {
431 [ EST_INACTIVE ] = "INACTIVE",
432 [ EST_ACTIVE ] = "ACTIVE",
433 [ EST_EXECUTING ] = "EXECUTING",
434 [ EST_SLEEPING ] = "SLEEPING",
435 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
436 [ EST_FETCHENTRY ] = "FETCH ENTRY",
437 [ EST_FETCHQH ] = "FETCH QH",
438 [ EST_FETCHITD ] = "FETCH ITD",
439 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
440 [ EST_FETCHQTD ] = "FETCH QTD",
441 [ EST_EXECUTE ] = "EXECUTE",
442 [ EST_WRITEBACK ] = "WRITEBACK",
443 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
444 };
445
446 static const char *ehci_mmio_names[] = {
447 [ CAPLENGTH ] = "CAPLENGTH",
448 [ HCIVERSION ] = "HCIVERSION",
449 [ HCSPARAMS ] = "HCSPARAMS",
450 [ HCCPARAMS ] = "HCCPARAMS",
451 [ USBCMD ] = "USBCMD",
452 [ USBSTS ] = "USBSTS",
453 [ USBINTR ] = "USBINTR",
454 [ FRINDEX ] = "FRINDEX",
455 [ PERIODICLISTBASE ] = "P-LIST BASE",
456 [ ASYNCLISTADDR ] = "A-LIST ADDR",
457 [ PORTSC_BEGIN ] = "PORTSC #0",
458 [ PORTSC_BEGIN + 4] = "PORTSC #1",
459 [ PORTSC_BEGIN + 8] = "PORTSC #2",
460 [ PORTSC_BEGIN + 12] = "PORTSC #3",
461 [ CONFIGFLAG ] = "CONFIGFLAG",
462 };
463
464 static const char *nr2str(const char **n, size_t len, uint32_t nr)
465 {
466 if (nr < len && n[nr] != NULL) {
467 return n[nr];
468 } else {
469 return "unknown";
470 }
471 }
472
473 static const char *state2str(uint32_t state)
474 {
475 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
476 }
477
478 static const char *addr2str(target_phys_addr_t addr)
479 {
480 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
481 }
482
483 static void ehci_trace_usbsts(uint32_t mask, int state)
484 {
485 /* interrupts */
486 if (mask & USBSTS_INT) {
487 trace_usb_ehci_usbsts("INT", state);
488 }
489 if (mask & USBSTS_ERRINT) {
490 trace_usb_ehci_usbsts("ERRINT", state);
491 }
492 if (mask & USBSTS_PCD) {
493 trace_usb_ehci_usbsts("PCD", state);
494 }
495 if (mask & USBSTS_FLR) {
496 trace_usb_ehci_usbsts("FLR", state);
497 }
498 if (mask & USBSTS_HSE) {
499 trace_usb_ehci_usbsts("HSE", state);
500 }
501 if (mask & USBSTS_IAA) {
502 trace_usb_ehci_usbsts("IAA", state);
503 }
504
505 /* status */
506 if (mask & USBSTS_HALT) {
507 trace_usb_ehci_usbsts("HALT", state);
508 }
509 if (mask & USBSTS_REC) {
510 trace_usb_ehci_usbsts("REC", state);
511 }
512 if (mask & USBSTS_PSS) {
513 trace_usb_ehci_usbsts("PSS", state);
514 }
515 if (mask & USBSTS_ASS) {
516 trace_usb_ehci_usbsts("ASS", state);
517 }
518 }
519
520 static inline void ehci_set_usbsts(EHCIState *s, int mask)
521 {
522 if ((s->usbsts & mask) == mask) {
523 return;
524 }
525 ehci_trace_usbsts(mask, 1);
526 s->usbsts |= mask;
527 }
528
529 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
530 {
531 if ((s->usbsts & mask) == 0) {
532 return;
533 }
534 ehci_trace_usbsts(mask, 0);
535 s->usbsts &= ~mask;
536 }
537
538 static inline void ehci_set_interrupt(EHCIState *s, int intr)
539 {
540 int level = 0;
541
542 // TODO honour interrupt threshold requests
543
544 ehci_set_usbsts(s, intr);
545
546 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
547 level = 1;
548 }
549
550 qemu_set_irq(s->irq, level);
551 }
552
553 static inline void ehci_record_interrupt(EHCIState *s, int intr)
554 {
555 s->usbsts_pending |= intr;
556 }
557
558 static inline void ehci_commit_interrupt(EHCIState *s)
559 {
560 if (!s->usbsts_pending) {
561 return;
562 }
563 ehci_set_interrupt(s, s->usbsts_pending);
564 s->usbsts_pending = 0;
565 }
566
567 static void ehci_set_state(EHCIState *s, int async, int state)
568 {
569 if (async) {
570 trace_usb_ehci_state("async", state2str(state));
571 s->astate = state;
572 } else {
573 trace_usb_ehci_state("periodic", state2str(state));
574 s->pstate = state;
575 }
576 }
577
578 static int ehci_get_state(EHCIState *s, int async)
579 {
580 return async ? s->astate : s->pstate;
581 }
582
583 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
584 {
585 if (async) {
586 s->a_fetch_addr = addr;
587 } else {
588 s->p_fetch_addr = addr;
589 }
590 }
591
592 static int ehci_get_fetch_addr(EHCIState *s, int async)
593 {
594 return async ? s->a_fetch_addr : s->p_fetch_addr;
595 }
596
597 static void ehci_trace_qh(EHCIState *s, target_phys_addr_t addr, EHCIqh *qh)
598 {
599 trace_usb_ehci_qh(addr, qh->next,
600 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
601 get_field(qh->epchar, QH_EPCHAR_RL),
602 get_field(qh->epchar, QH_EPCHAR_MPLEN),
603 get_field(qh->epchar, QH_EPCHAR_EPS),
604 get_field(qh->epchar, QH_EPCHAR_EP),
605 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
606 (bool)(qh->epchar & QH_EPCHAR_C),
607 (bool)(qh->epchar & QH_EPCHAR_H),
608 (bool)(qh->epchar & QH_EPCHAR_DTC),
609 (bool)(qh->epchar & QH_EPCHAR_I));
610 }
611
612 static void ehci_trace_qtd(EHCIState *s, target_phys_addr_t addr, EHCIqtd *qtd)
613 {
614 trace_usb_ehci_qtd(addr, qtd->next, qtd->altnext,
615 get_field(qtd->token, QTD_TOKEN_TBYTES),
616 get_field(qtd->token, QTD_TOKEN_CPAGE),
617 get_field(qtd->token, QTD_TOKEN_CERR),
618 get_field(qtd->token, QTD_TOKEN_PID),
619 (bool)(qtd->token & QTD_TOKEN_IOC),
620 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
621 (bool)(qtd->token & QTD_TOKEN_HALT),
622 (bool)(qtd->token & QTD_TOKEN_BABBLE),
623 (bool)(qtd->token & QTD_TOKEN_XACTERR));
624 }
625
626 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
627 {
628 trace_usb_ehci_itd(addr, itd->next);
629 }
630
631 /* Attach or detach a device on root hub */
632
633 static void ehci_attach(USBPort *port)
634 {
635 EHCIState *s = port->opaque;
636 uint32_t *portsc = &s->portsc[port->index];
637
638 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
639
640 *portsc |= PORTSC_CONNECT;
641 *portsc |= PORTSC_CSC;
642
643 /*
644 * If a high speed device is attached then we own this port(indicated
645 * by zero in the PORTSC_POWNER bit field) so set the status bit
646 * and set an interrupt if enabled.
647 */
648 if ( !(*portsc & PORTSC_POWNER)) {
649 ehci_set_interrupt(s, USBSTS_PCD);
650 }
651 }
652
653 static void ehci_detach(USBPort *port)
654 {
655 EHCIState *s = port->opaque;
656 uint32_t *portsc = &s->portsc[port->index];
657
658 trace_usb_ehci_port_detach(port->index);
659
660 *portsc &= ~PORTSC_CONNECT;
661 *portsc |= PORTSC_CSC;
662
663 /*
664 * If a high speed device is attached then we own this port(indicated
665 * by zero in the PORTSC_POWNER bit field) so set the status bit
666 * and set an interrupt if enabled.
667 */
668 if ( !(*portsc & PORTSC_POWNER)) {
669 ehci_set_interrupt(s, USBSTS_PCD);
670 }
671 }
672
673 /* 4.1 host controller initialization */
674 static void ehci_reset(void *opaque)
675 {
676 EHCIState *s = opaque;
677 uint8_t *pci_conf;
678 int i;
679
680 trace_usb_ehci_reset();
681 pci_conf = s->dev.config;
682
683 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
684
685 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
686 s->usbsts = USBSTS_HALT;
687
688 s->astate = EST_INACTIVE;
689 s->pstate = EST_INACTIVE;
690 s->isoch_pause = -1;
691 s->attach_poll_counter = 0;
692
693 for(i = 0; i < NB_PORTS; i++) {
694 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
695
696 if (s->ports[i].dev) {
697 usb_attach(&s->ports[i], s->ports[i].dev);
698 }
699 }
700 }
701
702 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
703 {
704 EHCIState *s = ptr;
705 uint32_t val;
706
707 val = s->mmio[addr];
708
709 return val;
710 }
711
712 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
713 {
714 EHCIState *s = ptr;
715 uint32_t val;
716
717 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
718
719 return val;
720 }
721
722 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
723 {
724 EHCIState *s = ptr;
725 uint32_t val;
726
727 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
728 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
729
730 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
731 return val;
732 }
733
734 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
735 {
736 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
737 exit(1);
738 }
739
740 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
741 {
742 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
743 exit(1);
744 }
745
746 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
747 {
748 uint32_t *portsc = &s->portsc[port];
749 int rwc;
750 USBDevice *dev = s->ports[port].dev;
751
752 rwc = val & PORTSC_RWC_MASK;
753 val &= PORTSC_RO_MASK;
754
755 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
756
757 *portsc &= ~rwc;
758
759 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
760 trace_usb_ehci_port_reset(port, 1);
761 }
762
763 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
764 trace_usb_ehci_port_reset(port, 0);
765 usb_attach(&s->ports[port], dev);
766
767 // TODO how to handle reset of ports with no device
768 if (dev) {
769 usb_send_msg(dev, USB_MSG_RESET);
770 }
771
772 if (s->ports[port].dev) {
773 *portsc &= ~PORTSC_CSC;
774 }
775
776 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
777 * to SW that this port has a high speed device attached
778 *
779 * TODO - when to disable?
780 */
781 val |= PORTSC_PED;
782 val |= PORTSC_PEDC;
783 }
784
785 *portsc &= ~PORTSC_RO_MASK;
786 *portsc |= val;
787 }
788
789 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
790 {
791 EHCIState *s = ptr;
792 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
793 uint32_t old = *mmio;
794 int i;
795
796 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
797
798 /* Only aligned reads are allowed on OHCI */
799 if (addr & 3) {
800 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
801 TARGET_FMT_plx "\n", addr);
802 return;
803 }
804
805 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
806 handle_port_status_write(s, (addr-PORTSC)/4, val);
807 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
808 return;
809 }
810
811 if (addr < OPREGBASE) {
812 fprintf(stderr, "usb-ehci: write attempt to read-only register"
813 TARGET_FMT_plx "\n", addr);
814 return;
815 }
816
817
818 /* Do any register specific pre-write processing here. */
819 switch(addr) {
820 case USBCMD:
821 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
822 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
823 SET_LAST_RUN_CLOCK(s);
824 ehci_clear_usbsts(s, USBSTS_HALT);
825 }
826
827 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
828 qemu_del_timer(s->frame_timer);
829 // TODO - should finish out some stuff before setting halt
830 ehci_set_usbsts(s, USBSTS_HALT);
831 }
832
833 if (val & USBCMD_HCRESET) {
834 ehci_reset(s);
835 val &= ~USBCMD_HCRESET;
836 }
837
838 /* not supporting dynamic frame list size at the moment */
839 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
840 fprintf(stderr, "attempt to set frame list size -- value %d\n",
841 val & USBCMD_FLS);
842 val &= ~USBCMD_FLS;
843 }
844 break;
845
846 case USBSTS:
847 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
848 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
849 val = s->usbsts;
850 ehci_set_interrupt(s, 0);
851 break;
852
853 case USBINTR:
854 val &= USBINTR_MASK;
855 break;
856
857 case FRINDEX:
858 s->sofv = val >> 3;
859 break;
860
861 case CONFIGFLAG:
862 val &= 0x1;
863 if (val) {
864 for(i = 0; i < NB_PORTS; i++)
865 s->portsc[i] &= ~PORTSC_POWNER;
866 }
867 break;
868
869 case PERIODICLISTBASE:
870 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
871 fprintf(stderr,
872 "ehci: PERIODIC list base register set while periodic schedule\n"
873 " is enabled and HC is enabled\n");
874 }
875 break;
876
877 case ASYNCLISTADDR:
878 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
879 fprintf(stderr,
880 "ehci: ASYNC list address register set while async schedule\n"
881 " is enabled and HC is enabled\n");
882 }
883 break;
884 }
885
886 *mmio = val;
887 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
888 }
889
890
891 // TODO : Put in common header file, duplication from usb-ohci.c
892
893 /* Get an array of dwords from main memory */
894 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
895 {
896 int i;
897
898 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
899 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
900 *buf = le32_to_cpu(*buf);
901 }
902
903 return 1;
904 }
905
906 /* Put an array of dwords in to main memory */
907 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
908 {
909 int i;
910
911 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
912 uint32_t tmp = cpu_to_le32(*buf);
913 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
914 }
915
916 return 1;
917 }
918
919 // 4.10.2
920
921 static int ehci_qh_do_overlay(EHCIQueue *q)
922 {
923 int i;
924 int dtoggle;
925 int ping;
926 int eps;
927 int reload;
928
929 // remember values in fields to preserve in qh after overlay
930
931 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
932 ping = q->qh.token & QTD_TOKEN_PING;
933
934 q->qh.current_qtd = q->qtdaddr;
935 q->qh.next_qtd = q->qtd.next;
936 q->qh.altnext_qtd = q->qtd.altnext;
937 q->qh.token = q->qtd.token;
938
939
940 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
941 if (eps == EHCI_QH_EPS_HIGH) {
942 q->qh.token &= ~QTD_TOKEN_PING;
943 q->qh.token |= ping;
944 }
945
946 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
947 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
948
949 for (i = 0; i < 5; i++) {
950 q->qh.bufptr[i] = q->qtd.bufptr[i];
951 }
952
953 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
954 // preserve QH DT bit
955 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
956 q->qh.token |= dtoggle;
957 }
958
959 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
960 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
961
962 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
963
964 return 0;
965 }
966
967 static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw)
968 {
969 int bufpos = 0;
970 int cpage, offset;
971 uint32_t head;
972 uint32_t tail;
973
974
975 if (!bytes) {
976 return 0;
977 }
978
979 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
980 if (cpage > 4) {
981 fprintf(stderr, "cpage out of range (%d)\n", cpage);
982 return USB_RET_PROCERR;
983 }
984
985 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
986
987 do {
988 /* start and end of this page */
989 head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
990 tail = head + ~QTD_BUFPTR_MASK + 1;
991 /* add offset into page */
992 head |= offset;
993
994 if (bytes <= (tail - head)) {
995 tail = head + bytes;
996 }
997
998 trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos);
999 cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw);
1000
1001 bufpos += (tail - head);
1002 bytes -= (tail - head);
1003
1004 if (bytes > 0) {
1005 cpage++;
1006 offset = 0;
1007 }
1008 } while (bytes > 0);
1009
1010 /* save cpage */
1011 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1012
1013 /* save offset into cpage */
1014 offset = tail - head;
1015 q->qh.bufptr[0] &= ~QTD_BUFPTR_MASK;
1016 q->qh.bufptr[0] |= offset;
1017
1018 return 0;
1019 }
1020
1021 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
1022 {
1023 EHCIQueue *q = container_of(packet, EHCIQueue, packet);
1024
1025 DPRINTF("Async packet complete\n");
1026 assert(q->async == EHIC_ASYNC_INFLIGHT);
1027 q->async = EHCI_ASYNC_FINISHED;
1028 q->usb_status = packet->len;
1029 }
1030
1031 static void ehci_execute_complete(EHCIQueue *q)
1032 {
1033 int c_err, reload;
1034
1035 if (q->async == EHCI_ASYNC_INFLIGHT) {
1036 DPRINTF("not done yet\n");
1037 return;
1038 }
1039 q->async = EHCI_ASYNC_NONE;
1040
1041 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1042 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1043
1044 if (q->usb_status < 0) {
1045 err:
1046 /* TO-DO: put this is in a function that can be invoked below as well */
1047 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1048 c_err--;
1049 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1050
1051 switch(q->usb_status) {
1052 case USB_RET_NODEV:
1053 fprintf(stderr, "USB no device\n");
1054 break;
1055 case USB_RET_STALL:
1056 fprintf(stderr, "USB stall\n");
1057 q->qh.token |= QTD_TOKEN_HALT;
1058 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1059 break;
1060 case USB_RET_NAK:
1061 /* 4.10.3 */
1062 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1063 if ((q->pid == USB_TOKEN_IN) && reload) {
1064 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1065 nakcnt--;
1066 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1067 } else if (!reload) {
1068 return;
1069 }
1070 break;
1071 case USB_RET_BABBLE:
1072 fprintf(stderr, "USB babble TODO\n");
1073 q->qh.token |= QTD_TOKEN_BABBLE;
1074 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1075 break;
1076 default:
1077 /* should not be triggerable */
1078 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1079 assert(0);
1080 break;
1081 }
1082 } else {
1083 // DPRINTF("Short packet condition\n");
1084 // TODO check 4.12 for splits
1085
1086 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1087 q->usb_status = USB_RET_BABBLE;
1088 goto err;
1089 }
1090
1091 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1092 if (ehci_buffer_rw(q, q->usb_status, 1) != 0) {
1093 q->usb_status = USB_RET_PROCERR;
1094 return;
1095 }
1096 q->tbytes -= q->usb_status;
1097 } else {
1098 q->tbytes = 0;
1099 }
1100
1101 DPRINTF("updating tbytes to %d\n", q->tbytes);
1102 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1103 }
1104
1105 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1106 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1107
1108 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1109 ehci_record_interrupt(q->ehci, USBSTS_INT);
1110 }
1111 }
1112
1113 // 4.10.3
1114
1115 static int ehci_execute(EHCIQueue *q)
1116 {
1117 USBPort *port;
1118 USBDevice *dev;
1119 int ret;
1120 int i;
1121 int endp;
1122 int devadr;
1123
1124 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1125 fprintf(stderr, "Attempting to execute inactive QH\n");
1126 return USB_RET_PROCERR;
1127 }
1128
1129 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1130 if (q->tbytes > BUFF_SIZE) {
1131 fprintf(stderr, "Request for more bytes than allowed\n");
1132 return USB_RET_PROCERR;
1133 }
1134
1135 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1136 switch(q->pid) {
1137 case 0: q->pid = USB_TOKEN_OUT; break;
1138 case 1: q->pid = USB_TOKEN_IN; break;
1139 case 2: q->pid = USB_TOKEN_SETUP; break;
1140 default: fprintf(stderr, "bad token\n"); break;
1141 }
1142
1143 if ((q->tbytes && q->pid != USB_TOKEN_IN) &&
1144 (ehci_buffer_rw(q, q->tbytes, 0) != 0)) {
1145 return USB_RET_PROCERR;
1146 }
1147
1148 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1149 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1150
1151 ret = USB_RET_NODEV;
1152
1153 // TO-DO: associating device with ehci port
1154 for(i = 0; i < NB_PORTS; i++) {
1155 port = &q->ehci->ports[i];
1156 dev = port->dev;
1157
1158 // TODO sometime we will also need to check if we are the port owner
1159
1160 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1161 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1162 i, q->ehci->portsc[i]);
1163 continue;
1164 }
1165
1166 q->packet.pid = q->pid;
1167 q->packet.devaddr = devadr;
1168 q->packet.devep = endp;
1169 q->packet.data = q->buffer;
1170 q->packet.len = q->tbytes;
1171
1172 ret = usb_handle_packet(dev, &q->packet);
1173
1174 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1175 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1176 q->packet.len, q->tbytes, endp, ret);
1177
1178 if (ret != USB_RET_NODEV) {
1179 break;
1180 }
1181 }
1182
1183 if (ret > BUFF_SIZE) {
1184 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1185 return USB_RET_PROCERR;
1186 }
1187
1188 if (ret == USB_RET_ASYNC) {
1189 q->async = EHCI_ASYNC_INFLIGHT;
1190 }
1191
1192 return ret;
1193 }
1194
1195 /* 4.7.2
1196 */
1197
1198 static int ehci_process_itd(EHCIState *ehci,
1199 EHCIitd *itd)
1200 {
1201 USBPort *port;
1202 USBDevice *dev;
1203 int ret;
1204 int i, j;
1205 int ptr;
1206 int pid;
1207 int pg;
1208 int len;
1209 int dir;
1210 int devadr;
1211 int endp;
1212 int maxpkt;
1213
1214 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1215 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1216 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1217 maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1218
1219 for(i = 0; i < 8; i++) {
1220 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1221 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1222 ehci->frindex >> 3, i);
1223
1224 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1225 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1226 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1227 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1228
1229 if (len > BUFF_SIZE) {
1230 return USB_RET_PROCERR;
1231 }
1232
1233 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1234
1235 if (!dir) {
1236 cpu_physical_memory_rw(ptr, &ehci->ibuffer[0], len, 0);
1237 pid = USB_TOKEN_OUT;
1238 } else
1239 pid = USB_TOKEN_IN;
1240
1241 ret = USB_RET_NODEV;
1242
1243 for (j = 0; j < NB_PORTS; j++) {
1244 port = &ehci->ports[j];
1245 dev = port->dev;
1246
1247 // TODO sometime we will also need to check if we are the port owner
1248
1249 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1250 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1251 j, ehci->portsc[j]);
1252 continue;
1253 }
1254
1255 ehci->ipacket.pid = pid;
1256 ehci->ipacket.devaddr = devadr;
1257 ehci->ipacket.devep = endp;
1258 ehci->ipacket.data = ehci->ibuffer;
1259 ehci->ipacket.len = len;
1260
1261 DPRINTF("calling usb_handle_packet\n");
1262 ret = usb_handle_packet(dev, &ehci->ipacket);
1263
1264 if (ret != USB_RET_NODEV) {
1265 break;
1266 }
1267 }
1268
1269 /* In isoch, there is no facility to indicate a NAK so let's
1270 * instead just complete a zero-byte transaction. Setting
1271 * DBERR seems too draconian.
1272 */
1273
1274 if (ret == USB_RET_NAK) {
1275 if (ehci->isoch_pause > 0) {
1276 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1277 ehci->isoch_pause--;
1278 return 0;
1279 } else if (ehci->isoch_pause == -1) {
1280 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1281 // Pause frindex for up to 50 msec waiting for data from
1282 // remote
1283 ehci->isoch_pause = 50;
1284 return 0;
1285 } else {
1286 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1287 ret = 0;
1288 }
1289 } else {
1290 DPRINTF("ISOCH: received ACK, clearing pause\n");
1291 ehci->isoch_pause = -1;
1292 }
1293
1294 if (ret >= 0) {
1295 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1296
1297 if (itd->transact[i] & ITD_XACT_IOC) {
1298 ehci_record_interrupt(ehci, USBSTS_INT);
1299 }
1300 }
1301
1302 if (ret >= 0 && dir) {
1303 cpu_physical_memory_rw(ptr, &ehci->ibuffer[0], len, 1);
1304
1305 if (ret != len) {
1306 DPRINTF("ISOCH IN expected %d, got %d\n",
1307 len, ret);
1308 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1309 }
1310 }
1311 }
1312 }
1313 return 0;
1314 }
1315
1316 /* This state is the entry point for asynchronous schedule
1317 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1318 */
1319 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1320 {
1321 EHCIqh qh;
1322 int i = 0;
1323 int again = 0;
1324 uint32_t entry = ehci->asynclistaddr;
1325
1326 /* set reclamation flag at start event (4.8.6) */
1327 if (async) {
1328 ehci_set_usbsts(ehci, USBSTS_REC);
1329 }
1330
1331 /* Find the head of the list (4.9.1.1) */
1332 for(i = 0; i < MAX_QH; i++) {
1333 get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1334 ehci_trace_qh(ehci, NLPTR_GET(entry), &qh);
1335
1336 if (qh.epchar & QH_EPCHAR_H) {
1337 if (async) {
1338 entry |= (NLPTR_TYPE_QH << 1);
1339 }
1340
1341 ehci_set_fetch_addr(ehci, async, entry);
1342 ehci_set_state(ehci, async, EST_FETCHENTRY);
1343 again = 1;
1344 goto out;
1345 }
1346
1347 entry = qh.next;
1348 if (entry == ehci->asynclistaddr) {
1349 break;
1350 }
1351 }
1352
1353 /* no head found for list. */
1354
1355 ehci_set_state(ehci, async, EST_ACTIVE);
1356
1357 out:
1358 return again;
1359 }
1360
1361
1362 /* This state is the entry point for periodic schedule processing as
1363 * well as being a continuation state for async processing.
1364 */
1365 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1366 {
1367 int again = 0;
1368 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1369
1370 #if EHCI_DEBUG == 0
1371 if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
1372 if (async) {
1373 DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
1374 goto out;
1375 } else {
1376 DPRINTF("FETCHENTRY: WARNING "
1377 "- frame timer elapsed during periodic\n");
1378 }
1379 }
1380 #endif
1381 if (entry < 0x1000) {
1382 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1383 ehci_set_state(ehci, async, EST_ACTIVE);
1384 goto out;
1385 }
1386
1387 /* section 4.8, only QH in async schedule */
1388 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1389 fprintf(stderr, "non queue head request in async schedule\n");
1390 return -1;
1391 }
1392
1393 switch (NLPTR_TYPE_GET(entry)) {
1394 case NLPTR_TYPE_QH:
1395 ehci_set_state(ehci, async, EST_FETCHQH);
1396 again = 1;
1397 break;
1398
1399 case NLPTR_TYPE_ITD:
1400 ehci_set_state(ehci, async, EST_FETCHITD);
1401 again = 1;
1402 break;
1403
1404 default:
1405 // TODO: handle siTD and FSTN types
1406 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1407 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1408 return -1;
1409 }
1410
1411 out:
1412 return again;
1413 }
1414
1415 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1416 {
1417 uint32_t entry;
1418 EHCIQueue *q;
1419 int reload;
1420
1421 entry = ehci_get_fetch_addr(ehci, async);
1422 q = &ehci->queue; /* temporary */
1423 q->qhaddr = entry;
1424
1425 get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1426 ehci_trace_qh(ehci, NLPTR_GET(q->qhaddr), &q->qh);
1427
1428 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1429
1430 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1431 if (ehci->usbsts & USBSTS_REC) {
1432 ehci_clear_usbsts(ehci, USBSTS_REC);
1433 } else {
1434 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1435 " - done processing\n", q->qhaddr);
1436 ehci_set_state(ehci, async, EST_ACTIVE);
1437 q = NULL;
1438 goto out;
1439 }
1440 }
1441
1442 #if EHCI_DEBUG
1443 if (q->qhaddr != q->qh.next) {
1444 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1445 q->qhaddr,
1446 q->qh.epchar & QH_EPCHAR_H,
1447 q->qh.token & QTD_TOKEN_HALT,
1448 q->qh.token & QTD_TOKEN_ACTIVE,
1449 q->qh.next);
1450 }
1451 #endif
1452
1453 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1454 if (reload) {
1455 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1456 }
1457
1458 if (q->qh.token & QTD_TOKEN_HALT) {
1459 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1460
1461 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1462 q->qtdaddr = q->qh.current_qtd;
1463 ehci_set_state(ehci, async, EST_FETCHQTD);
1464
1465 } else {
1466 /* EHCI spec version 1.0 Section 4.10.2 */
1467 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1468 }
1469
1470 out:
1471 return q;
1472 }
1473
1474 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1475 {
1476 uint32_t entry;
1477 EHCIitd itd;
1478
1479 assert(!async);
1480 entry = ehci_get_fetch_addr(ehci, async);
1481
1482 get_dwords(NLPTR_GET(entry),(uint32_t *) &itd,
1483 sizeof(EHCIitd) >> 2);
1484 ehci_trace_itd(ehci, entry, &itd);
1485
1486 if (ehci_process_itd(ehci, &itd) != 0) {
1487 return -1;
1488 }
1489
1490 put_dwords(NLPTR_GET(entry), (uint32_t *) &itd,
1491 sizeof(EHCIitd) >> 2);
1492 ehci_set_fetch_addr(ehci, async, itd.next);
1493 ehci_set_state(ehci, async, EST_FETCHENTRY);
1494
1495 return 1;
1496 }
1497
1498 /* Section 4.10.2 - paragraph 3 */
1499 static int ehci_state_advqueue(EHCIQueue *q, int async)
1500 {
1501 #if 0
1502 /* TO-DO: 4.10.2 - paragraph 2
1503 * if I-bit is set to 1 and QH is not active
1504 * go to horizontal QH
1505 */
1506 if (I-bit set) {
1507 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1508 goto out;
1509 }
1510 #endif
1511
1512 /*
1513 * want data and alt-next qTD is valid
1514 */
1515 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1516 (q->qh.altnext_qtd > 0x1000) &&
1517 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1518 q->qtdaddr = q->qh.altnext_qtd;
1519 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1520
1521 /*
1522 * next qTD is valid
1523 */
1524 } else if ((q->qh.next_qtd > 0x1000) &&
1525 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1526 q->qtdaddr = q->qh.next_qtd;
1527 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1528
1529 /*
1530 * no valid qTD, try next QH
1531 */
1532 } else {
1533 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1534 }
1535
1536 return 1;
1537 }
1538
1539 /* Section 4.10.2 - paragraph 4 */
1540 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1541 {
1542 int again = 0;
1543
1544 get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2);
1545 ehci_trace_qtd(q->ehci, NLPTR_GET(q->qtdaddr), &q->qtd);
1546
1547 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1548 ehci_set_state(q->ehci, async, EST_EXECUTE);
1549 again = 1;
1550 } else {
1551 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1552 again = 1;
1553 }
1554
1555 return again;
1556 }
1557
1558 static int ehci_state_horizqh(EHCIQueue *q, int async)
1559 {
1560 int again = 0;
1561
1562 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1563 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1564 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1565 again = 1;
1566 } else {
1567 ehci_set_state(q->ehci, async, EST_ACTIVE);
1568 }
1569
1570 return again;
1571 }
1572
1573 static int ehci_state_execute(EHCIQueue *q, int async)
1574 {
1575 int again = 0;
1576 int reload, nakcnt;
1577 int smask;
1578
1579 if (ehci_qh_do_overlay(q) != 0) {
1580 return -1;
1581 }
1582
1583 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1584
1585 if (!smask) {
1586 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1587 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1588 if (reload && !nakcnt) {
1589 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1590 again = 1;
1591 goto out;
1592 }
1593 }
1594
1595 // TODO verify enough time remains in the uframe as in 4.4.1.1
1596 // TODO write back ptr to async list when done or out of time
1597 // TODO Windows does not seem to ever set the MULT field
1598
1599 if (!async) {
1600 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1601 if (!transactCtr) {
1602 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1603 again = 1;
1604 goto out;
1605 }
1606 }
1607
1608 if (async) {
1609 ehci_set_usbsts(q->ehci, USBSTS_REC);
1610 }
1611
1612 q->usb_status = ehci_execute(q);
1613 if (q->usb_status == USB_RET_PROCERR) {
1614 again = -1;
1615 goto out;
1616 }
1617 ehci_set_state(q->ehci, async, EST_EXECUTING);
1618
1619 if (q->usb_status != USB_RET_ASYNC) {
1620 again = 1;
1621 }
1622
1623 out:
1624 return again;
1625 }
1626
1627 static int ehci_state_executing(EHCIQueue *q, int async)
1628 {
1629 int again = 0;
1630 int reload, nakcnt;
1631
1632 ehci_execute_complete(q);
1633 if (q->usb_status == USB_RET_ASYNC) {
1634 goto out;
1635 }
1636 if (q->usb_status == USB_RET_PROCERR) {
1637 again = -1;
1638 goto out;
1639 }
1640
1641 // 4.10.3
1642 if (!async) {
1643 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1644 transactCtr--;
1645 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1646 // 4.10.3, bottom of page 82, should exit this state when transaction
1647 // counter decrements to 0
1648 }
1649
1650 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1651 if (reload) {
1652 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1653 if (q->usb_status == USB_RET_NAK) {
1654 if (nakcnt) {
1655 nakcnt--;
1656 }
1657 } else {
1658 nakcnt = reload;
1659 }
1660 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1661 }
1662
1663 /*
1664 * Write the qh back to guest physical memory. This step isn't
1665 * in the EHCI spec but we need to do it since we don't share
1666 * physical memory with our guest VM.
1667 */
1668 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1669
1670 /* 4.10.5 */
1671 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1672 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1673 } else {
1674 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1675 }
1676
1677 again = 1;
1678
1679 out:
1680 return again;
1681 }
1682
1683
1684 static int ehci_state_writeback(EHCIQueue *q, int async)
1685 {
1686 int again = 0;
1687
1688 /* Write back the QTD from the QH area */
1689 ehci_trace_qtd(q->ehci, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1690 put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd,
1691 sizeof(EHCIqtd) >> 2);
1692
1693 /* TODO confirm next state. For now, keep going if async
1694 * but stop after one qtd if periodic
1695 */
1696 //if (async) {
1697 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1698 again = 1;
1699 //} else {
1700 // ehci_set_state(ehci, async, EST_ACTIVE);
1701 //}
1702 return again;
1703 }
1704
1705 /*
1706 * This is the state machine that is common to both async and periodic
1707 */
1708
1709 static void ehci_advance_state(EHCIState *ehci,
1710 int async)
1711 {
1712 EHCIQueue *q = NULL;
1713 int again;
1714 int iter = 0;
1715
1716 do {
1717 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1718 iter++;
1719 /* if we are roaming a lot of QH without executing a qTD
1720 * something is wrong with the linked list. TO-DO: why is
1721 * this hack needed?
1722 */
1723 if (iter > MAX_ITERATIONS) {
1724 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1725 ehci_set_state(ehci, async, EST_ACTIVE);
1726 break;
1727 }
1728 }
1729 switch(ehci_get_state(ehci, async)) {
1730 case EST_WAITLISTHEAD:
1731 again = ehci_state_waitlisthead(ehci, async);
1732 break;
1733
1734 case EST_FETCHENTRY:
1735 again = ehci_state_fetchentry(ehci, async);
1736 break;
1737
1738 case EST_FETCHQH:
1739 q = ehci_state_fetchqh(ehci, async);
1740 again = q ? 1 : 0;
1741 break;
1742
1743 case EST_FETCHITD:
1744 again = ehci_state_fetchitd(ehci, async);
1745 break;
1746
1747 case EST_ADVANCEQUEUE:
1748 again = ehci_state_advqueue(q, async);
1749 break;
1750
1751 case EST_FETCHQTD:
1752 again = ehci_state_fetchqtd(q, async);
1753 break;
1754
1755 case EST_HORIZONTALQH:
1756 again = ehci_state_horizqh(q, async);
1757 break;
1758
1759 case EST_EXECUTE:
1760 iter = 0;
1761 again = ehci_state_execute(q, async);
1762 break;
1763
1764 case EST_EXECUTING:
1765 q = &ehci->queue; /* temporary */
1766 again = ehci_state_executing(q, async);
1767 break;
1768
1769 case EST_WRITEBACK:
1770 again = ehci_state_writeback(q, async);
1771 break;
1772
1773 default:
1774 fprintf(stderr, "Bad state!\n");
1775 again = -1;
1776 break;
1777 }
1778
1779 if (again < 0) {
1780 fprintf(stderr, "processing error - resetting ehci HC\n");
1781 ehci_reset(ehci);
1782 again = 0;
1783 }
1784 }
1785 while (again);
1786
1787 ehci_commit_interrupt(ehci);
1788 }
1789
1790 static void ehci_advance_async_state(EHCIState *ehci)
1791 {
1792 int async = 1;
1793
1794 switch(ehci_get_state(ehci, async)) {
1795 case EST_INACTIVE:
1796 if (!(ehci->usbcmd & USBCMD_ASE)) {
1797 break;
1798 }
1799 ehci_set_usbsts(ehci, USBSTS_ASS);
1800 ehci_set_state(ehci, async, EST_ACTIVE);
1801 // No break, fall through to ACTIVE
1802
1803 case EST_ACTIVE:
1804 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1805 ehci_clear_usbsts(ehci, USBSTS_ASS);
1806 ehci_set_state(ehci, async, EST_INACTIVE);
1807 break;
1808 }
1809
1810 /* If the doorbell is set, the guest wants to make a change to the
1811 * schedule. The host controller needs to release cached data.
1812 * (section 4.8.2)
1813 */
1814 if (ehci->usbcmd & USBCMD_IAAD) {
1815 DPRINTF("ASYNC: doorbell request acknowledged\n");
1816 ehci->usbcmd &= ~USBCMD_IAAD;
1817 ehci_set_interrupt(ehci, USBSTS_IAA);
1818 break;
1819 }
1820
1821 /* make sure guest has acknowledged */
1822 /* TO-DO: is this really needed? */
1823 if (ehci->usbsts & USBSTS_IAA) {
1824 DPRINTF("IAA status bit still set.\n");
1825 break;
1826 }
1827
1828 /* check that address register has been set */
1829 if (ehci->asynclistaddr == 0) {
1830 break;
1831 }
1832
1833 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
1834 /* fall through */
1835
1836 case EST_FETCHENTRY:
1837 /* fall through */
1838
1839 case EST_EXECUTING:
1840 ehci_advance_state(ehci, async);
1841 break;
1842
1843 default:
1844 /* this should only be due to a developer mistake */
1845 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1846 "Resetting to active\n", ehci->astate);
1847 assert(0);
1848 }
1849 }
1850
1851 static void ehci_advance_periodic_state(EHCIState *ehci)
1852 {
1853 uint32_t entry;
1854 uint32_t list;
1855 int async = 0;
1856
1857 // 4.6
1858
1859 switch(ehci_get_state(ehci, async)) {
1860 case EST_INACTIVE:
1861 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
1862 ehci_set_usbsts(ehci, USBSTS_PSS);
1863 ehci_set_state(ehci, async, EST_ACTIVE);
1864 // No break, fall through to ACTIVE
1865 } else
1866 break;
1867
1868 case EST_ACTIVE:
1869 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
1870 ehci_clear_usbsts(ehci, USBSTS_PSS);
1871 ehci_set_state(ehci, async, EST_INACTIVE);
1872 break;
1873 }
1874
1875 list = ehci->periodiclistbase & 0xfffff000;
1876 /* check that register has been set */
1877 if (list == 0) {
1878 break;
1879 }
1880 list |= ((ehci->frindex & 0x1ff8) >> 1);
1881
1882 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1883 entry = le32_to_cpu(entry);
1884
1885 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1886 ehci->frindex / 8, list, entry);
1887 ehci_set_fetch_addr(ehci, async,entry);
1888 ehci_set_state(ehci, async, EST_FETCHENTRY);
1889 ehci_advance_state(ehci, async);
1890 break;
1891
1892 case EST_EXECUTING:
1893 DPRINTF("PERIODIC state adv for executing\n");
1894 ehci_advance_state(ehci, async);
1895 break;
1896
1897 default:
1898 /* this should only be due to a developer mistake */
1899 fprintf(stderr, "ehci: Bad periodic state %d. "
1900 "Resetting to active\n", ehci->pstate);
1901 assert(0);
1902 }
1903 }
1904
1905 static void ehci_frame_timer(void *opaque)
1906 {
1907 EHCIState *ehci = opaque;
1908 int64_t expire_time, t_now;
1909 int usec_elapsed;
1910 int frames;
1911 int usec_now;
1912 int i;
1913 int skipped_frames = 0;
1914
1915
1916 t_now = qemu_get_clock_ns(vm_clock);
1917 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1918 if (expire_time == t_now) {
1919 expire_time++;
1920 }
1921
1922 usec_now = t_now / 1000;
1923 usec_elapsed = usec_now - ehci->last_run_usec;
1924 frames = usec_elapsed / FRAME_TIMER_USEC;
1925 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
1926
1927 for (i = 0; i < frames; i++) {
1928 if ( !(ehci->usbsts & USBSTS_HALT)) {
1929 if (ehci->isoch_pause <= 0) {
1930 ehci->frindex += 8;
1931 }
1932
1933 if (ehci->frindex > 0x00001fff) {
1934 ehci->frindex = 0;
1935 ehci_set_interrupt(ehci, USBSTS_FLR);
1936 }
1937
1938 ehci->sofv = (ehci->frindex - 1) >> 3;
1939 ehci->sofv &= 0x000003ff;
1940 }
1941
1942 if (frames - i > 10) {
1943 skipped_frames++;
1944 } else {
1945 // TODO could this cause periodic frames to get skipped if async
1946 // active?
1947 if (ehci_get_state(ehci, 1) != EST_EXECUTING) {
1948 ehci_advance_periodic_state(ehci);
1949 }
1950 }
1951
1952 ehci->last_run_usec += FRAME_TIMER_USEC;
1953 }
1954
1955 #if 0
1956 if (skipped_frames) {
1957 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
1958 }
1959 #endif
1960
1961 /* Async is not inside loop since it executes everything it can once
1962 * called
1963 */
1964 if (ehci_get_state(ehci, 0) != EST_EXECUTING) {
1965 ehci_advance_async_state(ehci);
1966 }
1967
1968 qemu_mod_timer(ehci->frame_timer, expire_time);
1969 }
1970
1971 static CPUReadMemoryFunc *ehci_readfn[3]={
1972 ehci_mem_readb,
1973 ehci_mem_readw,
1974 ehci_mem_readl
1975 };
1976
1977 static CPUWriteMemoryFunc *ehci_writefn[3]={
1978 ehci_mem_writeb,
1979 ehci_mem_writew,
1980 ehci_mem_writel
1981 };
1982
1983 static void ehci_map(PCIDevice *pci_dev, int region_num,
1984 pcibus_t addr, pcibus_t size, int type)
1985 {
1986 EHCIState *s =(EHCIState *)pci_dev;
1987
1988 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
1989 region_num, addr, size, s->mem);
1990 s->mem_base = addr;
1991 cpu_register_physical_memory(addr, size, s->mem);
1992 }
1993
1994 static int usb_ehci_initfn(PCIDevice *dev);
1995
1996 static USBPortOps ehci_port_ops = {
1997 .attach = ehci_attach,
1998 .detach = ehci_detach,
1999 .complete = ehci_async_complete_packet,
2000 };
2001
2002 static PCIDeviceInfo ehci_info = {
2003 .qdev.name = "usb-ehci",
2004 .qdev.size = sizeof(EHCIState),
2005 .init = usb_ehci_initfn,
2006 };
2007
2008 static int usb_ehci_initfn(PCIDevice *dev)
2009 {
2010 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2011 uint8_t *pci_conf = s->dev.config;
2012 int i;
2013
2014 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
2015 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
2016 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
2017 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2018 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
2019 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
2020
2021 /* capabilities pointer */
2022 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2023 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2024
2025 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2026 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2027 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2028
2029 // pci_conf[0x50] = 0x01; // power management caps
2030
2031 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2032 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2033 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2034
2035 pci_conf[0x64] = 0x00;
2036 pci_conf[0x65] = 0x00;
2037 pci_conf[0x66] = 0x00;
2038 pci_conf[0x67] = 0x00;
2039 pci_conf[0x68] = 0x01;
2040 pci_conf[0x69] = 0x00;
2041 pci_conf[0x6a] = 0x00;
2042 pci_conf[0x6b] = 0x00; // USBLEGSUP
2043 pci_conf[0x6c] = 0x00;
2044 pci_conf[0x6d] = 0x00;
2045 pci_conf[0x6e] = 0x00;
2046 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2047
2048 // 2.2 host controller interface version
2049 s->mmio[0x00] = (uint8_t) OPREGBASE;
2050 s->mmio[0x01] = 0x00;
2051 s->mmio[0x02] = 0x00;
2052 s->mmio[0x03] = 0x01; // HC version
2053 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2054 s->mmio[0x05] = 0x00; // No companion ports at present
2055 s->mmio[0x06] = 0x00;
2056 s->mmio[0x07] = 0x00;
2057 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2058 s->mmio[0x09] = 0x68; // EECP
2059 s->mmio[0x0a] = 0x00;
2060 s->mmio[0x0b] = 0x00;
2061
2062 s->irq = s->dev.irq[3];
2063
2064 usb_bus_new(&s->bus, &s->dev.qdev);
2065 for(i = 0; i < NB_PORTS; i++) {
2066 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2067 USB_SPEED_MASK_HIGH);
2068 usb_port_location(&s->ports[i], NULL, i+1);
2069 s->ports[i].dev = 0;
2070 }
2071
2072 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2073 s->queue.ehci = s;
2074
2075 qemu_register_reset(ehci_reset, s);
2076
2077 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2078 DEVICE_LITTLE_ENDIAN);
2079
2080 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2081 ehci_map);
2082
2083 fprintf(stderr, "*** EHCI support is under development ***\n");
2084
2085 return 0;
2086 }
2087
2088 static void ehci_register(void)
2089 {
2090 pci_qdev_register(&ehci_info);
2091 }
2092 device_init(ehci_register);
2093
2094 /*
2095 * vim: expandtab ts=4
2096 */
QEmu