2 * libqos AHCI functions
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "libqos/ahci.h"
29 #include "libqos/pci-pc.h"
31 #include "qemu-common.h"
32 #include "qemu/host-utils.h"
34 #include "hw/pci/pci_ids.h"
35 #include "hw/pci/pci_regs.h"
37 typedef struct AHCICommandProp
{
38 uint8_t cmd
; /* Command Code */
39 bool data
; /* Data transfer command? */
48 uint64_t size
; /* Static transfer size, for commands like IDENTIFY. */
49 uint32_t interrupts
; /* Expected interrupts for this command. */
52 AHCICommandProp ahci_command_properties
[] = {
53 { .cmd
= CMD_READ_PIO
, .data
= true, .pio
= true,
54 .lba28
= true, .read
= true },
55 { .cmd
= CMD_WRITE_PIO
, .data
= true, .pio
= true,
56 .lba28
= true, .write
= true },
57 { .cmd
= CMD_READ_PIO_EXT
, .data
= true, .pio
= true,
58 .lba48
= true, .read
= true },
59 { .cmd
= CMD_WRITE_PIO_EXT
, .data
= true, .pio
= true,
60 .lba48
= true, .write
= true },
61 { .cmd
= CMD_READ_DMA
, .data
= true, .dma
= true,
62 .lba28
= true, .read
= true },
63 { .cmd
= CMD_WRITE_DMA
, .data
= true, .dma
= true,
64 .lba28
= true, .write
= true },
65 { .cmd
= CMD_READ_DMA_EXT
, .data
= true, .dma
= true,
66 .lba48
= true, .read
= true },
67 { .cmd
= CMD_WRITE_DMA_EXT
, .data
= true, .dma
= true,
68 .lba48
= true, .write
= true },
69 { .cmd
= CMD_IDENTIFY
, .data
= true, .pio
= true,
70 .size
= 512, .read
= true },
71 { .cmd
= CMD_READ_MAX
, .lba28
= true },
72 { .cmd
= CMD_READ_MAX_EXT
, .lba48
= true },
73 { .cmd
= CMD_FLUSH_CACHE
, .data
= false }
77 * Allocate space in the guest using information in the AHCIQState object.
79 uint64_t ahci_alloc(AHCIQState
*ahci
, size_t bytes
)
82 g_assert(ahci
->parent
);
83 return qmalloc(ahci
->parent
, bytes
);
86 void ahci_free(AHCIQState
*ahci
, uint64_t addr
)
89 g_assert(ahci
->parent
);
90 qfree(ahci
->parent
, addr
);
94 * Locate, verify, and return a handle to the AHCI device.
96 QPCIDevice
*get_ahci_device(uint32_t *fingerprint
)
99 uint32_t ahci_fingerprint
;
102 pcibus
= qpci_init_pc();
104 /* Find the AHCI PCI device and verify it's the right one. */
105 ahci
= qpci_device_find(pcibus
, QPCI_DEVFN(0x1F, 0x02));
106 g_assert(ahci
!= NULL
);
108 ahci_fingerprint
= qpci_config_readl(ahci
, PCI_VENDOR_ID
);
110 switch (ahci_fingerprint
) {
111 case AHCI_INTEL_ICH9
:
114 /* Unknown device. */
115 g_assert_not_reached();
119 *fingerprint
= ahci_fingerprint
;
124 void free_ahci_device(QPCIDevice
*dev
)
126 QPCIBus
*pcibus
= dev
? dev
->bus
: NULL
;
128 /* libqos doesn't have a function for this, so free it manually */
130 qpci_free_pc(pcibus
);
133 /* Free all memory in-use by the AHCI device. */
134 void ahci_clean_mem(AHCIQState
*ahci
)
138 for (port
= 0; port
< 32; ++port
) {
139 if (ahci
->port
[port
].fb
) {
140 ahci_free(ahci
, ahci
->port
[port
].fb
);
142 if (ahci
->port
[port
].clb
) {
143 for (slot
= 0; slot
< 32; slot
++) {
144 ahci_destroy_command(ahci
, port
, slot
);
146 ahci_free(ahci
, ahci
->port
[port
].clb
);
151 /*** Logical Device Initialization ***/
154 * Start the PCI device and sanity-check default operation.
156 void ahci_pci_enable(AHCIQState
*ahci
)
160 start_ahci_device(ahci
);
162 switch (ahci
->fingerprint
) {
163 case AHCI_INTEL_ICH9
:
164 /* ICH9 has a register at PCI 0x92 that
165 * acts as a master port enabler mask. */
166 reg
= qpci_config_readb(ahci
->dev
, 0x92);
168 qpci_config_writeb(ahci
->dev
, 0x92, reg
);
169 /* 0...0111111b -- bit significant, ports 0-5 enabled. */
170 ASSERT_BIT_SET(qpci_config_readb(ahci
->dev
, 0x92), 0x3F);
177 * Map BAR5/ABAR, and engage the PCI device.
179 void start_ahci_device(AHCIQState
*ahci
)
181 /* Map AHCI's ABAR (BAR5) */
182 ahci
->hba_base
= qpci_iomap(ahci
->dev
, 5, &ahci
->barsize
);
183 g_assert(ahci
->hba_base
);
185 /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
186 qpci_device_enable(ahci
->dev
);
190 * Test and initialize the AHCI's HBA memory areas.
191 * Initialize and start any ports with devices attached.
192 * Bring the HBA into the idle state.
194 void ahci_hba_enable(AHCIQState
*ahci
)
196 /* Bits of interest in this section:
197 * GHC.AE Global Host Control / AHCI Enable
198 * PxCMD.ST Port Command: Start
199 * PxCMD.SUD "Spin Up Device"
200 * PxCMD.POD "Power On Device"
201 * PxCMD.FRE "FIS Receive Enable"
202 * PxCMD.FR "FIS Receive Running"
203 * PxCMD.CR "Command List Running"
205 uint32_t reg
, ports_impl
;
207 uint8_t num_cmd_slots
;
209 g_assert(ahci
!= NULL
);
211 /* Set GHC.AE to 1 */
212 ahci_set(ahci
, AHCI_GHC
, AHCI_GHC_AE
);
213 reg
= ahci_rreg(ahci
, AHCI_GHC
);
214 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
216 /* Cache CAP and CAP2. */
217 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
218 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
220 /* Read CAP.NCS, how many command slots do we have? */
221 num_cmd_slots
= ((ahci
->cap
& AHCI_CAP_NCS
) >> ctzl(AHCI_CAP_NCS
)) + 1;
222 g_test_message("Number of Command Slots: %u", num_cmd_slots
);
224 /* Determine which ports are implemented. */
225 ports_impl
= ahci_rreg(ahci
, AHCI_PI
);
227 for (i
= 0; ports_impl
; ports_impl
>>= 1, ++i
) {
228 if (!(ports_impl
& 0x01)) {
232 g_test_message("Initializing port %u", i
);
234 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_CMD
);
235 if (BITCLR(reg
, AHCI_PX_CMD_ST
| AHCI_PX_CMD_CR
|
236 AHCI_PX_CMD_FRE
| AHCI_PX_CMD_FR
)) {
237 g_test_message("port is idle");
239 g_test_message("port needs to be idled");
240 ahci_px_clr(ahci
, i
, AHCI_PX_CMD
,
241 (AHCI_PX_CMD_ST
| AHCI_PX_CMD_FRE
));
242 /* The port has 500ms to disengage. */
244 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_CMD
);
245 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
246 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
247 g_test_message("port is now idle");
248 /* The spec does allow for possibly needing a PORT RESET
249 * or HBA reset if we fail to idle the port. */
252 /* Allocate Memory for the Command List Buffer & FIS Buffer */
253 /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
254 ahci
->port
[i
].clb
= ahci_alloc(ahci
, num_cmd_slots
* 0x20);
255 qmemset(ahci
->port
[i
].clb
, 0x00, 0x100);
256 g_test_message("CLB: 0x%08" PRIx64
, ahci
->port
[i
].clb
);
257 ahci_px_wreg(ahci
, i
, AHCI_PX_CLB
, ahci
->port
[i
].clb
);
258 g_assert_cmphex(ahci
->port
[i
].clb
, ==,
259 ahci_px_rreg(ahci
, i
, AHCI_PX_CLB
));
261 /* PxFB space ... 0x100, as in 4.2.1 p 35 */
262 ahci
->port
[i
].fb
= ahci_alloc(ahci
, 0x100);
263 qmemset(ahci
->port
[i
].fb
, 0x00, 0x100);
264 g_test_message("FB: 0x%08" PRIx64
, ahci
->port
[i
].fb
);
265 ahci_px_wreg(ahci
, i
, AHCI_PX_FB
, ahci
->port
[i
].fb
);
266 g_assert_cmphex(ahci
->port
[i
].fb
, ==,
267 ahci_px_rreg(ahci
, i
, AHCI_PX_FB
));
269 /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
270 ahci_px_wreg(ahci
, i
, AHCI_PX_SERR
, 0xFFFFFFFF);
271 ahci_px_wreg(ahci
, i
, AHCI_PX_IS
, 0xFFFFFFFF);
272 ahci_wreg(ahci
, AHCI_IS
, (1 << i
));
274 /* Verify Interrupts Cleared */
275 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_SERR
);
276 g_assert_cmphex(reg
, ==, 0);
278 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_IS
);
279 g_assert_cmphex(reg
, ==, 0);
281 reg
= ahci_rreg(ahci
, AHCI_IS
);
282 ASSERT_BIT_CLEAR(reg
, (1 << i
));
284 /* Enable All Interrupts: */
285 ahci_px_wreg(ahci
, i
, AHCI_PX_IE
, 0xFFFFFFFF);
286 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_IE
);
287 g_assert_cmphex(reg
, ==, ~((uint32_t)AHCI_PX_IE_RESERVED
));
289 /* Enable the FIS Receive Engine. */
290 ahci_px_set(ahci
, i
, AHCI_PX_CMD
, AHCI_PX_CMD_FRE
);
291 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_CMD
);
292 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_FR
);
294 /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
295 * physical presence, a device is present and may be started. However,
296 * PxSERR.DIAG.X /may/ need to be cleared a priori. */
297 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_SERR
);
298 if (BITSET(reg
, AHCI_PX_SERR_DIAG_X
)) {
299 ahci_px_set(ahci
, i
, AHCI_PX_SERR
, AHCI_PX_SERR_DIAG_X
);
302 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_TFD
);
303 if (BITCLR(reg
, AHCI_PX_TFD_STS_BSY
| AHCI_PX_TFD_STS_DRQ
)) {
304 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_SSTS
);
305 if ((reg
& AHCI_PX_SSTS_DET
) == SSTS_DET_ESTABLISHED
) {
306 /* Device Found: set PxCMD.ST := 1 */
307 ahci_px_set(ahci
, i
, AHCI_PX_CMD
, AHCI_PX_CMD_ST
);
308 ASSERT_BIT_SET(ahci_px_rreg(ahci
, i
, AHCI_PX_CMD
),
310 g_test_message("Started Device %u", i
);
311 } else if ((reg
& AHCI_PX_SSTS_DET
)) {
312 /* Device present, but in some unknown state. */
313 g_assert_not_reached();
319 ahci_set(ahci
, AHCI_GHC
, AHCI_GHC_IE
);
320 reg
= ahci_rreg(ahci
, AHCI_GHC
);
321 ASSERT_BIT_SET(reg
, AHCI_GHC_IE
);
323 /* TODO: The device should now be idling and waiting for commands.
324 * In the future, a small test-case to inspect the Register D2H FIS
325 * and clear the initial interrupts might be good. */
329 * Pick the first implemented and running port
331 unsigned ahci_port_select(AHCIQState
*ahci
)
336 ports
= ahci_rreg(ahci
, AHCI_PI
);
337 for (i
= 0; i
< 32; ports
>>= 1, ++i
) {
342 if (!(ports
& 0x01)) {
346 reg
= ahci_px_rreg(ahci
, i
, AHCI_PX_CMD
);
347 if (BITSET(reg
, AHCI_PX_CMD_ST
)) {
356 * Clear a port's interrupts and status information prior to a test.
358 void ahci_port_clear(AHCIQState
*ahci
, uint8_t port
)
362 /* Clear out this port's interrupts (ignore the init register d2h fis) */
363 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
364 ahci_px_wreg(ahci
, port
, AHCI_PX_IS
, reg
);
365 g_assert_cmphex(ahci_px_rreg(ahci
, port
, AHCI_PX_IS
), ==, 0);
367 /* Wipe the FIS-Receive Buffer */
368 qmemset(ahci
->port
[port
].fb
, 0x00, 0x100);
372 * Check a port for errors.
374 void ahci_port_check_error(AHCIQState
*ahci
, uint8_t port
)
378 /* The upper 9 bits of the IS register all indicate errors. */
379 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
381 g_assert_cmphex(reg
, ==, 0);
383 /* The Sata Error Register should be empty. */
384 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
385 g_assert_cmphex(reg
, ==, 0);
387 /* The TFD also has two error sections. */
388 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
389 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_ERR
);
390 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
393 void ahci_port_check_interrupts(AHCIQState
*ahci
, uint8_t port
,
398 /* Check for expected interrupts */
399 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
400 ASSERT_BIT_SET(reg
, intr_mask
);
402 /* Clear expected interrupts and assert all interrupts now cleared. */
403 ahci_px_wreg(ahci
, port
, AHCI_PX_IS
, intr_mask
);
404 g_assert_cmphex(ahci_px_rreg(ahci
, port
, AHCI_PX_IS
), ==, 0);
407 void ahci_port_check_nonbusy(AHCIQState
*ahci
, uint8_t port
, uint8_t slot
)
411 /* Assert that the command slot is no longer busy (NCQ) */
412 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
413 ASSERT_BIT_CLEAR(reg
, (1 << slot
));
416 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
417 ASSERT_BIT_CLEAR(reg
, (1 << slot
));
419 /* And assert that we are generally not busy. */
420 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
421 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
422 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_DRQ
);
425 void ahci_port_check_d2h_sanity(AHCIQState
*ahci
, uint8_t port
, uint8_t slot
)
427 RegD2HFIS
*d2h
= g_malloc0(0x20);
430 memread(ahci
->port
[port
].fb
+ 0x40, d2h
, 0x20);
431 g_assert_cmphex(d2h
->fis_type
, ==, 0x34);
433 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
434 g_assert_cmphex((reg
& AHCI_PX_TFD_ERR
) >> 8, ==, d2h
->error
);
435 g_assert_cmphex((reg
& AHCI_PX_TFD_STS
), ==, d2h
->status
);
440 void ahci_port_check_pio_sanity(AHCIQState
*ahci
, uint8_t port
,
441 uint8_t slot
, size_t buffsize
)
443 PIOSetupFIS
*pio
= g_malloc0(0x20);
445 /* We cannot check the Status or E_Status registers, because
446 * the status may have again changed between the PIO Setup FIS
447 * and the conclusion of the command with the D2H Register FIS. */
448 memread(ahci
->port
[port
].fb
+ 0x20, pio
, 0x20);
449 g_assert_cmphex(pio
->fis_type
, ==, 0x5f);
451 /* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire
452 * transfer size in a uint16_t field. The maximum transfer size can
453 * eclipse this; the field is meant to convey the size of data per
454 * each Data FIS, not the entire operation as a whole. For now,
455 * we will sanity check the broken case where applicable. */
456 if (buffsize
<= UINT16_MAX
) {
457 g_assert_cmphex(le16_to_cpu(pio
->tx_count
), ==, buffsize
);
463 void ahci_port_check_cmd_sanity(AHCIQState
*ahci
, uint8_t port
,
464 uint8_t slot
, size_t buffsize
)
466 AHCICommandHeader cmd
;
468 ahci_get_command_header(ahci
, port
, slot
, &cmd
);
469 g_assert_cmphex(buffsize
, ==, cmd
.prdbc
);
472 /* Get the command in #slot of port #port. */
473 void ahci_get_command_header(AHCIQState
*ahci
, uint8_t port
,
474 uint8_t slot
, AHCICommandHeader
*cmd
)
476 uint64_t ba
= ahci
->port
[port
].clb
;
477 ba
+= slot
* sizeof(AHCICommandHeader
);
478 memread(ba
, cmd
, sizeof(AHCICommandHeader
));
480 cmd
->flags
= le16_to_cpu(cmd
->flags
);
481 cmd
->prdtl
= le16_to_cpu(cmd
->prdtl
);
482 cmd
->prdbc
= le32_to_cpu(cmd
->prdbc
);
483 cmd
->ctba
= le64_to_cpu(cmd
->ctba
);
486 /* Set the command in #slot of port #port. */
487 void ahci_set_command_header(AHCIQState
*ahci
, uint8_t port
,
488 uint8_t slot
, AHCICommandHeader
*cmd
)
490 AHCICommandHeader tmp
= { .flags
= 0 };
491 uint64_t ba
= ahci
->port
[port
].clb
;
492 ba
+= slot
* sizeof(AHCICommandHeader
);
494 tmp
.flags
= cpu_to_le16(cmd
->flags
);
495 tmp
.prdtl
= cpu_to_le16(cmd
->prdtl
);
496 tmp
.prdbc
= cpu_to_le32(cmd
->prdbc
);
497 tmp
.ctba
= cpu_to_le64(cmd
->ctba
);
499 memwrite(ba
, &tmp
, sizeof(AHCICommandHeader
));
502 void ahci_destroy_command(AHCIQState
*ahci
, uint8_t port
, uint8_t slot
)
504 AHCICommandHeader cmd
;
506 /* Obtain the Nth Command Header */
507 ahci_get_command_header(ahci
, port
, slot
, &cmd
);
509 /* No address in it, so just return -- it's empty. */
514 ahci_free(ahci
, cmd
.ctba
);
517 /* NULL the header. */
518 memset(&cmd
, 0x00, sizeof(cmd
));
519 ahci_set_command_header(ahci
, port
, slot
, &cmd
);
520 ahci
->port
[port
].ctba
[slot
] = 0;
521 ahci
->port
[port
].prdtl
[slot
] = 0;
524 void ahci_write_fis(AHCIQState
*ahci
, RegH2DFIS
*fis
, uint64_t addr
)
526 RegH2DFIS tmp
= *fis
;
528 /* The auxiliary FIS fields are defined per-command and are not
529 * currently implemented in libqos/ahci.o, but may or may not need
532 /* All other FIS fields are 8 bit and do not need to be flipped. */
533 tmp
.count
= cpu_to_le16(tmp
.count
);
535 memwrite(addr
, &tmp
, sizeof(tmp
));
538 unsigned ahci_pick_cmd(AHCIQState
*ahci
, uint8_t port
)
544 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
546 /* Pick the least recently used command slot that's available */
547 for (i
= 0; i
< 32; ++i
) {
548 j
= ((ahci
->port
[port
].next
+ i
) % 32);
549 if (reg
& (1 << j
)) {
552 ahci_destroy_command(ahci
, port
, i
);
553 ahci
->port
[port
].next
= (j
+ 1) % 32;
557 g_test_message("All command slots were busy.");
558 g_assert_not_reached();
561 inline unsigned size_to_prdtl(unsigned bytes
, unsigned bytes_per_prd
)
563 /* Each PRD can describe up to 4MiB */
564 g_assert_cmphex(bytes_per_prd
, <=, 4096 * 1024);
565 g_assert_cmphex(bytes_per_prd
& 0x01, ==, 0x00);
566 return (bytes
+ bytes_per_prd
- 1) / bytes_per_prd
;
569 /* Issue a command, expecting it to fail and STOP the VM */
570 AHCICommand
*ahci_guest_io_halt(AHCIQState
*ahci
, uint8_t port
,
571 uint8_t ide_cmd
, uint64_t buffer
,
572 size_t bufsize
, uint64_t sector
)
576 cmd
= ahci_command_create(ide_cmd
);
577 ahci_command_adjust(cmd
, sector
, buffer
, bufsize
, 0);
578 ahci_command_commit(ahci
, cmd
, port
);
579 ahci_command_issue_async(ahci
, cmd
);
580 qmp_eventwait("STOP");
585 /* Resume a previously failed command and verify/finalize */
586 void ahci_guest_io_resume(AHCIQState
*ahci
, AHCICommand
*cmd
)
588 /* Complete the command */
589 qmp_async("{'execute':'cont' }");
590 qmp_eventwait("RESUME");
591 ahci_command_wait(ahci
, cmd
);
592 ahci_command_verify(ahci
, cmd
);
593 ahci_command_free(cmd
);
596 /* Given a guest buffer address, perform an IO operation */
597 void ahci_guest_io(AHCIQState
*ahci
, uint8_t port
, uint8_t ide_cmd
,
598 uint64_t buffer
, size_t bufsize
, uint64_t sector
)
601 cmd
= ahci_command_create(ide_cmd
);
602 ahci_command_set_buffer(cmd
, buffer
);
603 ahci_command_set_size(cmd
, bufsize
);
605 ahci_command_set_offset(cmd
, sector
);
607 ahci_command_commit(ahci
, cmd
, port
);
608 ahci_command_issue(ahci
, cmd
);
609 ahci_command_verify(ahci
, cmd
);
610 ahci_command_free(cmd
);
614 /* Test Management Data */
622 AHCICommandProp
*props
;
623 /* Data to be transferred to the guest */
624 AHCICommandHeader header
;
629 static AHCICommandProp
*ahci_command_find(uint8_t command_name
)
633 for (i
= 0; i
< ARRAY_SIZE(ahci_command_properties
); i
++) {
634 if (ahci_command_properties
[i
].cmd
== command_name
) {
635 return &ahci_command_properties
[i
];
642 /* Given a HOST buffer, create a buffer address and perform an IO operation. */
643 void ahci_io(AHCIQState
*ahci
, uint8_t port
, uint8_t ide_cmd
,
644 void *buffer
, size_t bufsize
, uint64_t sector
)
647 AHCICommandProp
*props
;
649 props
= ahci_command_find(ide_cmd
);
651 ptr
= ahci_alloc(ahci
, bufsize
);
655 memwrite(ptr
, buffer
, bufsize
);
658 ahci_guest_io(ahci
, port
, ide_cmd
, ptr
, bufsize
, sector
);
661 memread(ptr
, buffer
, bufsize
);
664 ahci_free(ahci
, ptr
);
668 * Initializes a basic command header in memory.
669 * We assume that this is for an ATA command using RegH2DFIS.
671 static void command_header_init(AHCICommand
*cmd
)
673 AHCICommandHeader
*hdr
= &cmd
->header
;
674 AHCICommandProp
*props
= cmd
->props
;
676 hdr
->flags
= 5; /* RegH2DFIS is 5 DW long. Must be < 32 */
677 hdr
->flags
|= CMDH_CLR_BSY
; /* Clear the BSY bit when done */
679 hdr
->flags
|= CMDH_WRITE
;
682 hdr
->flags
|= CMDH_ATAPI
;
684 /* Other flags: PREFETCH, RESET, and BIST */
685 hdr
->prdtl
= size_to_prdtl(cmd
->xbytes
, cmd
->prd_size
);
690 static void command_table_init(AHCICommand
*cmd
)
692 RegH2DFIS
*fis
= &(cmd
->fis
);
694 fis
->fis_type
= REG_H2D_FIS
;
695 fis
->flags
= REG_H2D_FIS_CMD
; /* "Command" bit */
696 fis
->command
= cmd
->name
;
697 cmd
->fis
.feature_low
= 0x00;
698 cmd
->fis
.feature_high
= 0x00;
699 if (cmd
->props
->lba28
|| cmd
->props
->lba48
) {
700 cmd
->fis
.device
= ATA_DEVICE_LBA
;
702 cmd
->fis
.count
= (cmd
->xbytes
/ AHCI_SECTOR_SIZE
);
704 cmd
->fis
.control
= 0x00;
705 memset(cmd
->fis
.aux
, 0x00, ARRAY_SIZE(cmd
->fis
.aux
));
708 AHCICommand
*ahci_command_create(uint8_t command_name
)
710 AHCICommandProp
*props
= ahci_command_find(command_name
);
714 cmd
= g_malloc0(sizeof(AHCICommand
));
715 g_assert(!(props
->dma
&& props
->pio
));
716 g_assert(!(props
->lba28
&& props
->lba48
));
717 g_assert(!(props
->read
&& props
->write
));
718 g_assert(!props
->size
|| props
->data
);
720 /* Defaults and book-keeping */
722 cmd
->name
= command_name
;
723 cmd
->xbytes
= props
->size
;
724 cmd
->prd_size
= 4096;
725 cmd
->buffer
= 0xabad1dea;
727 cmd
->interrupts
= AHCI_PX_IS_DHRS
;
728 /* BUG: We expect the DPS interrupt for data commands */
729 /* cmd->interrupts |= props->data ? AHCI_PX_IS_DPS : 0; */
730 /* BUG: We expect the DMA Setup interrupt for DMA commands */
731 /* cmd->interrupts |= props->dma ? AHCI_PX_IS_DSS : 0; */
732 cmd
->interrupts
|= props
->pio
? AHCI_PX_IS_PSS
: 0;
734 command_header_init(cmd
);
735 command_table_init(cmd
);
740 void ahci_command_free(AHCICommand
*cmd
)
745 void ahci_command_set_flags(AHCICommand
*cmd
, uint16_t cmdh_flags
)
747 cmd
->header
.flags
|= cmdh_flags
;
750 void ahci_command_clr_flags(AHCICommand
*cmd
, uint16_t cmdh_flags
)
752 cmd
->header
.flags
&= ~cmdh_flags
;
755 void ahci_command_set_offset(AHCICommand
*cmd
, uint64_t lba_sect
)
757 RegH2DFIS
*fis
= &(cmd
->fis
);
758 if (cmd
->props
->lba28
) {
759 g_assert_cmphex(lba_sect
, <=, 0xFFFFFFF);
760 } else if (cmd
->props
->lba48
) {
761 g_assert_cmphex(lba_sect
, <=, 0xFFFFFFFFFFFF);
763 /* Can't set offset if we don't know the format. */
764 g_assert_not_reached();
767 /* LBA28 uses the low nibble of the device/control register for LBA24:27 */
768 fis
->lba_lo
[0] = (lba_sect
& 0xFF);
769 fis
->lba_lo
[1] = (lba_sect
>> 8) & 0xFF;
770 fis
->lba_lo
[2] = (lba_sect
>> 16) & 0xFF;
771 if (cmd
->props
->lba28
) {
772 fis
->device
= (fis
->device
& 0xF0) || (lba_sect
>> 24) & 0x0F;
774 fis
->lba_hi
[0] = (lba_sect
>> 24) & 0xFF;
775 fis
->lba_hi
[1] = (lba_sect
>> 32) & 0xFF;
776 fis
->lba_hi
[2] = (lba_sect
>> 40) & 0xFF;
779 void ahci_command_set_buffer(AHCICommand
*cmd
, uint64_t buffer
)
781 cmd
->buffer
= buffer
;
784 void ahci_command_set_sizes(AHCICommand
*cmd
, uint64_t xbytes
,
787 /* Each PRD can describe up to 4MiB, and must not be odd. */
788 g_assert_cmphex(prd_size
, <=, 4096 * 1024);
789 g_assert_cmphex(prd_size
& 0x01, ==, 0x00);
790 cmd
->prd_size
= prd_size
;
791 cmd
->xbytes
= xbytes
;
792 cmd
->fis
.count
= (cmd
->xbytes
/ AHCI_SECTOR_SIZE
);
793 cmd
->header
.prdtl
= size_to_prdtl(cmd
->xbytes
, cmd
->prd_size
);
796 void ahci_command_set_size(AHCICommand
*cmd
, uint64_t xbytes
)
798 ahci_command_set_sizes(cmd
, xbytes
, cmd
->prd_size
);
801 void ahci_command_set_prd_size(AHCICommand
*cmd
, unsigned prd_size
)
803 ahci_command_set_sizes(cmd
, cmd
->xbytes
, prd_size
);
806 void ahci_command_adjust(AHCICommand
*cmd
, uint64_t offset
, uint64_t buffer
,
807 uint64_t xbytes
, unsigned prd_size
)
809 ahci_command_set_sizes(cmd
, xbytes
, prd_size
);
810 ahci_command_set_buffer(cmd
, buffer
);
811 ahci_command_set_offset(cmd
, offset
);
814 void ahci_command_commit(AHCIQState
*ahci
, AHCICommand
*cmd
, uint8_t port
)
817 uint64_t table_size
, table_ptr
, remaining
;
820 /* This command is now tied to this port/command slot */
822 cmd
->slot
= ahci_pick_cmd(ahci
, port
);
824 /* Create a buffer for the command table */
825 prdtl
= size_to_prdtl(cmd
->xbytes
, cmd
->prd_size
);
826 table_size
= CMD_TBL_SIZ(prdtl
);
827 table_ptr
= ahci_alloc(ahci
, table_size
);
829 /* AHCI 1.3: Must be aligned to 0x80 */
830 g_assert((table_ptr
& 0x7F) == 0x00);
831 cmd
->header
.ctba
= table_ptr
;
833 /* Commit the command header and command FIS */
834 ahci_set_command_header(ahci
, port
, cmd
->slot
, &(cmd
->header
));
835 ahci_write_fis(ahci
, &(cmd
->fis
), table_ptr
);
837 /* Construct and write the PRDs to the command table */
838 g_assert_cmphex(prdtl
, ==, cmd
->header
.prdtl
);
839 remaining
= cmd
->xbytes
;
840 for (i
= 0; i
< prdtl
; ++i
) {
841 prd
.dba
= cpu_to_le64(cmd
->buffer
+ (cmd
->prd_size
* i
));
843 if (remaining
> cmd
->prd_size
) {
844 /* Note that byte count is 0-based. */
845 prd
.dbc
= cpu_to_le32(cmd
->prd_size
- 1);
846 remaining
-= cmd
->prd_size
;
848 /* Again, dbc is 0-based. */
849 prd
.dbc
= cpu_to_le32(remaining
- 1);
852 prd
.dbc
|= cpu_to_le32(0x80000000); /* Request DPS Interrupt */
854 /* Commit the PRD entry to the Command Table */
855 memwrite(table_ptr
+ 0x80 + (i
* sizeof(PRD
)),
859 /* Bookmark the PRDTL and CTBA values */
860 ahci
->port
[port
].ctba
[cmd
->slot
] = table_ptr
;
861 ahci
->port
[port
].prdtl
[cmd
->slot
] = prdtl
;
864 void ahci_command_issue_async(AHCIQState
*ahci
, AHCICommand
*cmd
)
866 if (cmd
->props
->ncq
) {
867 ahci_px_wreg(ahci
, cmd
->port
, AHCI_PX_SACT
, (1 << cmd
->slot
));
870 ahci_px_wreg(ahci
, cmd
->port
, AHCI_PX_CI
, (1 << cmd
->slot
));
873 void ahci_command_wait(AHCIQState
*ahci
, AHCICommand
*cmd
)
875 /* We can't rely on STS_BSY until the command has started processing.
876 * Therefore, we also use the Command Issue bit as indication of
877 * a command in-flight. */
878 while (BITSET(ahci_px_rreg(ahci
, cmd
->port
, AHCI_PX_TFD
),
879 AHCI_PX_TFD_STS_BSY
) ||
880 BITSET(ahci_px_rreg(ahci
, cmd
->port
, AHCI_PX_CI
), (1 << cmd
->slot
))) {
885 void ahci_command_issue(AHCIQState
*ahci
, AHCICommand
*cmd
)
887 ahci_command_issue_async(ahci
, cmd
);
888 ahci_command_wait(ahci
, cmd
);
891 void ahci_command_verify(AHCIQState
*ahci
, AHCICommand
*cmd
)
893 uint8_t slot
= cmd
->slot
;
894 uint8_t port
= cmd
->port
;
896 ahci_port_check_error(ahci
, port
);
897 ahci_port_check_interrupts(ahci
, port
, cmd
->interrupts
);
898 ahci_port_check_nonbusy(ahci
, port
, slot
);
899 ahci_port_check_cmd_sanity(ahci
, port
, slot
, cmd
->xbytes
);
900 ahci_port_check_d2h_sanity(ahci
, port
, slot
);
901 if (cmd
->props
->pio
) {
902 ahci_port_check_pio_sanity(ahci
, port
, slot
, cmd
->xbytes
);
906 uint8_t ahci_command_slot(AHCICommand
*cmd
)