2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
9 * Based on i386/tcg-target.c and mips/tcg-target.c
11 * Permission is hereby granted, free of charge, to any person obtaining a copy
12 * of this software and associated documentation files (the "Software"), to deal
13 * in the Software without restriction, including without limitation the rights
14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15 * copies of the Software, and to permit persons to whom the Software is
16 * furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice shall be included in
19 * all copies or substantial portions of the Software.
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "../tcg-ldst.c.inc"
31 #include "../tcg-pool.c.inc"
33 #ifdef CONFIG_DEBUG_TCG
34 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
70 static const int tcg_target_reg_alloc_order[] = {
71 /* Call saved registers */
72 /* TCG_REG_S0 reservered for TCG_AREG0 */
85 /* Call clobbered registers */
94 /* Argument registers */
105 static const int tcg_target_call_iarg_regs[] = {
116 static const int tcg_target_call_oarg_regs[] = {
121 #define TCG_CT_CONST_ZERO 0x100
122 #define TCG_CT_CONST_S12 0x200
123 #define TCG_CT_CONST_N12 0x400
124 #define TCG_CT_CONST_M12 0x800
126 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
128 * For softmmu, we need to avoid conflicts with the first 5
129 * argument registers to call the helper. Some of these are
130 * also used for the tlb lookup.
132 #ifdef CONFIG_SOFTMMU
133 #define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
135 #define SOFTMMU_RESERVE_REGS 0
139 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
141 if (TCG_TARGET_REG_BITS == 32) {
142 return sextract32(val, pos, len);
144 return sextract64(val, pos, len);
148 /* test if a constant matches the constraint */
149 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
151 if (ct & TCG_CT_CONST) {
154 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
157 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
160 if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
163 if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
170 * RISC-V Base ISA opcodes (IM)
186 OPC_DIVU = 0x2005033,
198 OPC_MULH = 0x2001033,
199 OPC_MULHSU = 0x2002033,
200 OPC_MULHU = 0x2003033,
204 OPC_REMU = 0x2007033,
214 OPC_SRA = 0x40005033,
215 OPC_SRAI = 0x40005013,
218 OPC_SUB = 0x40000033,
223 #if TCG_TARGET_REG_BITS == 64
226 OPC_DIVUW = 0x200503b,
227 OPC_DIVW = 0x200403b,
228 OPC_MULW = 0x200003b,
229 OPC_REMUW = 0x200703b,
230 OPC_REMW = 0x200603b,
233 OPC_SRAIW = 0x4000501b,
234 OPC_SRAW = 0x4000503b,
237 OPC_SUBW = 0x4000003b,
239 /* Simplify code throughout by defining aliases for RV32. */
240 OPC_ADDIW = OPC_ADDI,
242 OPC_DIVUW = OPC_DIVU,
245 OPC_REMUW = OPC_REMU,
247 OPC_SLLIW = OPC_SLLI,
249 OPC_SRAIW = OPC_SRAI,
251 OPC_SRLIW = OPC_SRLI,
256 OPC_FENCE = 0x0000000f,
260 * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
265 static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
267 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
272 static int32_t encode_imm12(uint32_t imm)
274 return (imm & 0xfff) << 20;
277 static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
279 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
284 static int32_t encode_simm12(uint32_t imm)
288 ret |= (imm & 0xFE0) << 20;
289 ret |= (imm & 0x1F) << 7;
294 static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
296 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
301 static int32_t encode_sbimm12(uint32_t imm)
305 ret |= (imm & 0x1000) << 19;
306 ret |= (imm & 0x7e0) << 20;
307 ret |= (imm & 0x1e) << 7;
308 ret |= (imm & 0x800) >> 4;
313 static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
315 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
320 static int32_t encode_uimm20(uint32_t imm)
322 return imm & 0xfffff000;
325 static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
327 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
332 static int32_t encode_ujimm20(uint32_t imm)
336 ret |= (imm & 0x0007fe) << (21 - 1);
337 ret |= (imm & 0x000800) << (20 - 11);
338 ret |= (imm & 0x0ff000) << (12 - 12);
339 ret |= (imm & 0x100000) << (31 - 20);
344 static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
346 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
350 * RISC-V instruction emitters
353 static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
354 TCGReg rd, TCGReg rs1, TCGReg rs2)
356 tcg_out32(s, encode_r(opc, rd, rs1, rs2));
359 static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
360 TCGReg rd, TCGReg rs1, TCGArg imm)
362 tcg_out32(s, encode_i(opc, rd, rs1, imm));
365 static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
366 TCGReg rs1, TCGReg rs2, uint32_t imm)
368 tcg_out32(s, encode_s(opc, rs1, rs2, imm));
371 static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
372 TCGReg rs1, TCGReg rs2, uint32_t imm)
374 tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
377 static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
378 TCGReg rd, uint32_t imm)
380 tcg_out32(s, encode_u(opc, rd, imm));
383 static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
384 TCGReg rd, uint32_t imm)
386 tcg_out32(s, encode_uj(opc, rd, imm));
389 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
392 for (i = 0; i < count; ++i) {
393 p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
401 static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
403 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
404 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
406 tcg_debug_assert((offset & 1) == 0);
407 if (offset == sextreg(offset, 0, 12)) {
408 *src_rw |= encode_sbimm12(offset);
415 static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
417 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
418 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
420 tcg_debug_assert((offset & 1) == 0);
421 if (offset == sextreg(offset, 0, 20)) {
422 *src_rw |= encode_ujimm20(offset);
429 static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
431 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
432 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
433 int32_t lo = sextreg(offset, 0, 12);
434 int32_t hi = offset - lo;
436 if (offset == hi + lo) {
437 src_rw[0] |= encode_uimm20(hi);
438 src_rw[1] |= encode_imm12(lo);
445 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
446 intptr_t value, intptr_t addend)
448 tcg_debug_assert(addend == 0);
451 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
453 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
455 return reloc_call(code_ptr, (tcg_insn_unit *)value);
457 g_assert_not_reached();
465 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
473 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
476 g_assert_not_reached();
481 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
484 tcg_target_long lo, hi, tmp;
487 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
491 lo = sextreg(val, 0, 12);
493 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
498 if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
499 tcg_out_opc_upper(s, OPC_LUI, rd, hi);
501 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
506 /* We can only be here if TCG_TARGET_REG_BITS != 32 */
507 tmp = tcg_pcrel_diff(s, (void *)val);
508 if (tmp == (int32_t)tmp) {
509 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
510 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
511 ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val);
512 tcg_debug_assert(ret == true);
516 /* Look for a single 20-bit section. */
519 if (tmp == sextreg(tmp, 0, 20)) {
520 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
522 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
524 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
529 /* Look for a few high zero bits, with lots of bits set in the middle. */
532 if (tmp == sextreg(tmp, 12, 20) << 12) {
533 tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
534 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
536 } else if (tmp == sextreg(tmp, 0, 12)) {
537 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
538 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
542 /* Drop into the constant pool. */
543 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
544 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
545 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
548 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
550 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
553 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
555 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
556 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
559 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
561 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
562 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
565 static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
567 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
568 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
571 static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
573 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
574 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
577 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
579 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
582 static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
583 TCGReg addr, intptr_t offset)
585 intptr_t imm12 = sextreg(offset, 0, 12);
587 if (offset != imm12) {
588 intptr_t diff = offset - (uintptr_t)s->code_ptr;
590 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
591 imm12 = sextreg(diff, 0, 12);
592 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
594 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
595 if (addr != TCG_REG_ZERO) {
596 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
607 tcg_out_opc_store(s, opc, addr, data, imm12);
616 tcg_out_opc_imm(s, opc, data, addr, imm12);
619 g_assert_not_reached();
623 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
624 TCGReg arg1, intptr_t arg2)
626 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
627 tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
630 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
631 TCGReg arg1, intptr_t arg2)
633 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
634 tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
637 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
638 TCGReg base, intptr_t ofs)
641 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
647 static void tcg_out_addsub2(TCGContext *s,
648 TCGReg rl, TCGReg rh,
649 TCGReg al, TCGReg ah,
650 TCGArg bl, TCGArg bh,
651 bool cbl, bool cbh, bool is_sub, bool is32bit)
653 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
654 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
655 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
656 TCGReg th = TCG_REG_TMP1;
658 /* If we have a negative constant such that negating it would
659 make the high part zero, we can (usually) eliminate one insn. */
660 if (cbl && cbh && bh == -1 && bl != 0) {
666 /* By operating on the high part first, we get to use the final
667 carry operation to move back from the temporary. */
669 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
670 } else if (bh != 0 || ah == rl) {
671 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
676 /* Note that tcg optimization should eliminate the bl == 0 case. */
679 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
680 tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
682 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
683 tcg_out_opc_reg(s, opc_sub, rl, al, bl);
685 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
688 tcg_out_opc_imm(s, opc_addi, rl, al, bl);
689 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
690 } else if (rl == al && rl == bl) {
691 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
692 tcg_out_opc_reg(s, opc_addi, rl, al, bl);
694 tcg_out_opc_reg(s, opc_add, rl, al, bl);
695 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
696 rl, (rl == bl ? al : bl));
698 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
702 static const struct {
705 } tcg_brcond_to_riscv[] = {
706 [TCG_COND_EQ] = { OPC_BEQ, false },
707 [TCG_COND_NE] = { OPC_BNE, false },
708 [TCG_COND_LT] = { OPC_BLT, false },
709 [TCG_COND_GE] = { OPC_BGE, false },
710 [TCG_COND_LE] = { OPC_BGE, true },
711 [TCG_COND_GT] = { OPC_BLT, true },
712 [TCG_COND_LTU] = { OPC_BLTU, false },
713 [TCG_COND_GEU] = { OPC_BGEU, false },
714 [TCG_COND_LEU] = { OPC_BGEU, true },
715 [TCG_COND_GTU] = { OPC_BLTU, true }
718 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
719 TCGReg arg2, TCGLabel *l)
721 RISCVInsn op = tcg_brcond_to_riscv[cond].op;
723 tcg_debug_assert(op != 0);
725 if (tcg_brcond_to_riscv[cond].swap) {
731 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
732 tcg_out_opc_branch(s, op, arg1, arg2, 0);
735 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
736 TCGReg arg1, TCGReg arg2)
740 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
741 tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
744 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
745 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
748 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
751 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
752 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
755 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
756 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
759 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
762 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
765 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
766 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
769 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
770 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
773 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
776 g_assert_not_reached();
781 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
782 TCGReg bl, TCGReg bh, TCGLabel *l)
785 g_assert_not_reached();
788 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
789 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
792 g_assert_not_reached();
795 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
797 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
798 ptrdiff_t offset = tcg_pcrel_diff(s, arg);
801 tcg_debug_assert((offset & 1) == 0);
802 if (offset == sextreg(offset, 0, 20)) {
803 /* short jump: -2097150 to 2097152 */
804 tcg_out_opc_jump(s, OPC_JAL, link, offset);
805 } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) {
806 /* long jump: -2147483646 to 2147483648 */
807 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
808 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
809 ret = reloc_call(s->code_ptr - 2, arg);
810 tcg_debug_assert(ret == true);
811 } else if (TCG_TARGET_REG_BITS == 64) {
812 /* far jump: 64-bit */
813 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
814 tcg_target_long base = (tcg_target_long)arg - imm;
815 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
816 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
818 g_assert_not_reached();
822 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
824 tcg_out_call_int(s, arg, false);
827 static void tcg_out_mb(TCGContext *s, TCGArg a0)
829 tcg_insn_unit insn = OPC_FENCE;
831 if (a0 & TCG_MO_LD_LD) {
834 if (a0 & TCG_MO_ST_LD) {
837 if (a0 & TCG_MO_LD_ST) {
840 if (a0 & TCG_MO_ST_ST) {
850 #if defined(CONFIG_SOFTMMU)
851 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
852 * MemOpIdx oi, uintptr_t ra)
854 static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
855 [MO_UB] = helper_ret_ldub_mmu,
856 [MO_SB] = helper_ret_ldsb_mmu,
858 [MO_UW] = helper_be_lduw_mmu,
859 [MO_SW] = helper_be_ldsw_mmu,
860 [MO_UL] = helper_be_ldul_mmu,
861 #if TCG_TARGET_REG_BITS == 64
862 [MO_SL] = helper_be_ldsl_mmu,
864 [MO_UQ] = helper_be_ldq_mmu,
866 [MO_UW] = helper_le_lduw_mmu,
867 [MO_SW] = helper_le_ldsw_mmu,
868 [MO_UL] = helper_le_ldul_mmu,
869 #if TCG_TARGET_REG_BITS == 64
870 [MO_SL] = helper_le_ldsl_mmu,
872 [MO_UQ] = helper_le_ldq_mmu,
876 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
877 * uintxx_t val, MemOpIdx oi,
880 static void * const qemu_st_helpers[MO_SIZE + 1] = {
881 [MO_8] = helper_ret_stb_mmu,
883 [MO_16] = helper_be_stw_mmu,
884 [MO_32] = helper_be_stl_mmu,
885 [MO_64] = helper_be_stq_mmu,
887 [MO_16] = helper_le_stw_mmu,
888 [MO_32] = helper_le_stl_mmu,
889 [MO_64] = helper_le_stq_mmu,
893 /* We don't support oversize guests */
894 QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
896 /* We expect to use a 12-bit negative offset from ENV. */
897 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
898 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
900 static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
902 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
903 bool ok = reloc_jimm20(s->code_ptr - 1, target);
904 tcg_debug_assert(ok);
907 static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
908 TCGReg addrh, MemOpIdx oi,
909 tcg_insn_unit **label_ptr, bool is_load)
911 MemOp opc = get_memop(oi);
912 unsigned s_bits = opc & MO_SIZE;
913 unsigned a_bits = get_alignment_bits(opc);
914 tcg_target_long compare_mask;
915 int mem_index = get_mmuidx(oi);
916 int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
917 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
918 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
919 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
921 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs);
922 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs);
924 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,
925 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
926 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
927 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
929 /* Load the tlb comparator and the addend. */
930 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
931 is_load ? offsetof(CPUTLBEntry, addr_read)
932 : offsetof(CPUTLBEntry, addr_write));
933 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
934 offsetof(CPUTLBEntry, addend));
936 /* We don't support unaligned accesses. */
937 if (a_bits < s_bits) {
940 /* Clear the non-page, non-alignment bits from the address. */
941 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
942 if (compare_mask == sextreg(compare_mask, 0, 12)) {
943 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask);
945 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
946 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
949 /* Compare masked address with the TLB entry. */
950 label_ptr[0] = s->code_ptr;
951 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
953 /* TLB Hit - translate address using addend. */
954 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
955 tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
956 addrl = TCG_REG_TMP0;
958 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
961 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
963 TCGReg datalo, TCGReg datahi,
964 TCGReg addrlo, TCGReg addrhi,
965 void *raddr, tcg_insn_unit **label_ptr)
967 TCGLabelQemuLdst *label = new_ldst_label(s);
969 label->is_ld = is_ld;
972 label->datalo_reg = datalo;
973 label->datahi_reg = datahi;
974 label->addrlo_reg = addrlo;
975 label->addrhi_reg = addrhi;
976 label->raddr = tcg_splitwx_to_rx(raddr);
977 label->label_ptr[0] = label_ptr[0];
980 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
983 MemOp opc = get_memop(oi);
984 TCGReg a0 = tcg_target_call_iarg_regs[0];
985 TCGReg a1 = tcg_target_call_iarg_regs[1];
986 TCGReg a2 = tcg_target_call_iarg_regs[2];
987 TCGReg a3 = tcg_target_call_iarg_regs[3];
989 /* We don't support oversize guests */
990 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
991 g_assert_not_reached();
994 /* resolve label address */
995 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
999 /* call load helper */
1000 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
1001 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
1002 tcg_out_movi(s, TCG_TYPE_PTR, a2, oi);
1003 tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);
1005 tcg_out_call(s, qemu_ld_helpers[opc & MO_SSIZE]);
1006 tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
1008 tcg_out_goto(s, l->raddr);
1012 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1014 MemOpIdx oi = l->oi;
1015 MemOp opc = get_memop(oi);
1016 MemOp s_bits = opc & MO_SIZE;
1017 TCGReg a0 = tcg_target_call_iarg_regs[0];
1018 TCGReg a1 = tcg_target_call_iarg_regs[1];
1019 TCGReg a2 = tcg_target_call_iarg_regs[2];
1020 TCGReg a3 = tcg_target_call_iarg_regs[3];
1021 TCGReg a4 = tcg_target_call_iarg_regs[4];
1023 /* We don't support oversize guests */
1024 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1025 g_assert_not_reached();
1028 /* resolve label address */
1029 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1033 /* call store helper */
1034 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
1035 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
1036 tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);
1039 tcg_out_ext8u(s, a2, a2);
1042 tcg_out_ext16u(s, a2, a2);
1047 tcg_out_movi(s, TCG_TYPE_PTR, a3, oi);
1048 tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr);
1050 tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]);
1052 tcg_out_goto(s, l->raddr);
1057 static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg,
1060 unsigned a_mask = (1 << a_bits) - 1;
1061 TCGLabelQemuLdst *l = new_ldst_label(s);
1064 l->addrlo_reg = addr_reg;
1066 /* We are expecting a_bits to max out at 7, so we can always use andi. */
1067 tcg_debug_assert(a_bits < 12);
1068 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask);
1070 l->label_ptr[0] = s->code_ptr;
1071 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
1073 l->raddr = tcg_splitwx_to_rx(s->code_ptr);
1076 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
1078 /* resolve label address */
1079 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1083 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg);
1084 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
1086 /* tail call, with the return address back inline. */
1087 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr);
1088 tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld
1089 : helper_unaligned_st), true);
1093 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1095 return tcg_out_fail_alignment(s, l);
1098 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1100 return tcg_out_fail_alignment(s, l);
1103 #endif /* CONFIG_SOFTMMU */
1105 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1106 TCGReg base, MemOp opc, bool is_64)
1108 /* Byte swapping is left to middle-end expansion. */
1109 tcg_debug_assert((opc & MO_BSWAP) == 0);
1111 switch (opc & (MO_SSIZE)) {
1113 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1116 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1119 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1122 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1125 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1126 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1131 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1134 /* Prefer to load from offset 0 first, but allow for overlap. */
1135 if (TCG_TARGET_REG_BITS == 64) {
1136 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1137 } else if (lo != base) {
1138 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1139 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1141 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1142 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1146 g_assert_not_reached();
1150 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1152 TCGReg addr_regl, addr_regh __attribute__((unused));
1153 TCGReg data_regl, data_regh;
1156 #if defined(CONFIG_SOFTMMU)
1157 tcg_insn_unit *label_ptr[1];
1161 TCGReg base = TCG_REG_TMP0;
1163 data_regl = *args++;
1164 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1165 addr_regl = *args++;
1166 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1168 opc = get_memop(oi);
1170 #if defined(CONFIG_SOFTMMU)
1171 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
1172 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1173 add_qemu_ldst_label(s, 1, oi,
1174 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1175 data_regl, data_regh, addr_regl, addr_regh,
1176 s->code_ptr, label_ptr);
1178 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1179 tcg_out_ext32u(s, base, addr_regl);
1182 a_bits = get_alignment_bits(opc);
1184 tcg_out_test_alignment(s, true, addr_regl, a_bits);
1186 if (guest_base != 0) {
1187 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1189 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1193 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1194 TCGReg base, MemOp opc)
1196 /* Byte swapping is left to middle-end expansion. */
1197 tcg_debug_assert((opc & MO_BSWAP) == 0);
1199 switch (opc & (MO_SSIZE)) {
1201 tcg_out_opc_store(s, OPC_SB, base, lo, 0);
1204 tcg_out_opc_store(s, OPC_SH, base, lo, 0);
1207 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1210 if (TCG_TARGET_REG_BITS == 64) {
1211 tcg_out_opc_store(s, OPC_SD, base, lo, 0);
1213 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1214 tcg_out_opc_store(s, OPC_SW, base, hi, 4);
1218 g_assert_not_reached();
1222 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1224 TCGReg addr_regl, addr_regh __attribute__((unused));
1225 TCGReg data_regl, data_regh;
1228 #if defined(CONFIG_SOFTMMU)
1229 tcg_insn_unit *label_ptr[1];
1233 TCGReg base = TCG_REG_TMP0;
1235 data_regl = *args++;
1236 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1237 addr_regl = *args++;
1238 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1240 opc = get_memop(oi);
1242 #if defined(CONFIG_SOFTMMU)
1243 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
1244 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1245 add_qemu_ldst_label(s, 0, oi,
1246 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1247 data_regl, data_regh, addr_regl, addr_regh,
1248 s->code_ptr, label_ptr);
1250 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1251 tcg_out_ext32u(s, base, addr_regl);
1254 a_bits = get_alignment_bits(opc);
1256 tcg_out_test_alignment(s, false, addr_regl, a_bits);
1258 if (guest_base != 0) {
1259 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1261 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1265 static const tcg_insn_unit *tb_ret_addr;
1267 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1268 const TCGArg args[TCG_MAX_OP_ARGS],
1269 const int const_args[TCG_MAX_OP_ARGS])
1271 TCGArg a0 = args[0];
1272 TCGArg a1 = args[1];
1273 TCGArg a2 = args[2];
1274 int c2 = const_args[2];
1277 case INDEX_op_exit_tb:
1278 /* Reuse the zeroing that exists for goto_ptr. */
1280 tcg_out_call_int(s, tcg_code_gen_epilogue, true);
1282 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1283 tcg_out_call_int(s, tb_ret_addr, true);
1287 case INDEX_op_goto_tb:
1288 assert(s->tb_jmp_insn_offset == 0);
1289 /* indirect jump method */
1290 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
1291 (uintptr_t)(s->tb_jmp_target_addr + a0));
1292 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1293 set_jmp_reset_offset(s, a0);
1296 case INDEX_op_goto_ptr:
1297 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1301 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
1302 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
1305 case INDEX_op_ld8u_i32:
1306 case INDEX_op_ld8u_i64:
1307 tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
1309 case INDEX_op_ld8s_i32:
1310 case INDEX_op_ld8s_i64:
1311 tcg_out_ldst(s, OPC_LB, a0, a1, a2);
1313 case INDEX_op_ld16u_i32:
1314 case INDEX_op_ld16u_i64:
1315 tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
1317 case INDEX_op_ld16s_i32:
1318 case INDEX_op_ld16s_i64:
1319 tcg_out_ldst(s, OPC_LH, a0, a1, a2);
1321 case INDEX_op_ld32u_i64:
1322 tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
1324 case INDEX_op_ld_i32:
1325 case INDEX_op_ld32s_i64:
1326 tcg_out_ldst(s, OPC_LW, a0, a1, a2);
1328 case INDEX_op_ld_i64:
1329 tcg_out_ldst(s, OPC_LD, a0, a1, a2);
1332 case INDEX_op_st8_i32:
1333 case INDEX_op_st8_i64:
1334 tcg_out_ldst(s, OPC_SB, a0, a1, a2);
1336 case INDEX_op_st16_i32:
1337 case INDEX_op_st16_i64:
1338 tcg_out_ldst(s, OPC_SH, a0, a1, a2);
1340 case INDEX_op_st_i32:
1341 case INDEX_op_st32_i64:
1342 tcg_out_ldst(s, OPC_SW, a0, a1, a2);
1344 case INDEX_op_st_i64:
1345 tcg_out_ldst(s, OPC_SD, a0, a1, a2);
1348 case INDEX_op_add_i32:
1350 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
1352 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
1355 case INDEX_op_add_i64:
1357 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
1359 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
1363 case INDEX_op_sub_i32:
1365 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
1367 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
1370 case INDEX_op_sub_i64:
1372 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
1374 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
1378 case INDEX_op_and_i32:
1379 case INDEX_op_and_i64:
1381 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
1383 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
1387 case INDEX_op_or_i32:
1388 case INDEX_op_or_i64:
1390 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
1392 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
1396 case INDEX_op_xor_i32:
1397 case INDEX_op_xor_i64:
1399 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
1401 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
1405 case INDEX_op_not_i32:
1406 case INDEX_op_not_i64:
1407 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
1410 case INDEX_op_neg_i32:
1411 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
1413 case INDEX_op_neg_i64:
1414 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
1417 case INDEX_op_mul_i32:
1418 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
1420 case INDEX_op_mul_i64:
1421 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1424 case INDEX_op_div_i32:
1425 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
1427 case INDEX_op_div_i64:
1428 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
1431 case INDEX_op_divu_i32:
1432 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
1434 case INDEX_op_divu_i64:
1435 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
1438 case INDEX_op_rem_i32:
1439 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
1441 case INDEX_op_rem_i64:
1442 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
1445 case INDEX_op_remu_i32:
1446 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
1448 case INDEX_op_remu_i64:
1449 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
1452 case INDEX_op_shl_i32:
1454 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
1456 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
1459 case INDEX_op_shl_i64:
1461 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
1463 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
1467 case INDEX_op_shr_i32:
1469 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
1471 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
1474 case INDEX_op_shr_i64:
1476 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
1478 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
1482 case INDEX_op_sar_i32:
1484 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
1486 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
1489 case INDEX_op_sar_i64:
1491 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
1493 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
1497 case INDEX_op_add2_i32:
1498 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1499 const_args[4], const_args[5], false, true);
1501 case INDEX_op_add2_i64:
1502 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1503 const_args[4], const_args[5], false, false);
1505 case INDEX_op_sub2_i32:
1506 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1507 const_args[4], const_args[5], true, true);
1509 case INDEX_op_sub2_i64:
1510 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1511 const_args[4], const_args[5], true, false);
1514 case INDEX_op_brcond_i32:
1515 case INDEX_op_brcond_i64:
1516 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1518 case INDEX_op_brcond2_i32:
1519 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
1522 case INDEX_op_setcond_i32:
1523 case INDEX_op_setcond_i64:
1524 tcg_out_setcond(s, args[3], a0, a1, a2);
1526 case INDEX_op_setcond2_i32:
1527 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
1530 case INDEX_op_qemu_ld_i32:
1531 tcg_out_qemu_ld(s, args, false);
1533 case INDEX_op_qemu_ld_i64:
1534 tcg_out_qemu_ld(s, args, true);
1536 case INDEX_op_qemu_st_i32:
1537 tcg_out_qemu_st(s, args, false);
1539 case INDEX_op_qemu_st_i64:
1540 tcg_out_qemu_st(s, args, true);
1543 case INDEX_op_ext8u_i32:
1544 case INDEX_op_ext8u_i64:
1545 tcg_out_ext8u(s, a0, a1);
1548 case INDEX_op_ext16u_i32:
1549 case INDEX_op_ext16u_i64:
1550 tcg_out_ext16u(s, a0, a1);
1553 case INDEX_op_ext32u_i64:
1554 case INDEX_op_extu_i32_i64:
1555 tcg_out_ext32u(s, a0, a1);
1558 case INDEX_op_ext8s_i32:
1559 case INDEX_op_ext8s_i64:
1560 tcg_out_ext8s(s, a0, a1);
1563 case INDEX_op_ext16s_i32:
1564 case INDEX_op_ext16s_i64:
1565 tcg_out_ext16s(s, a0, a1);
1568 case INDEX_op_ext32s_i64:
1569 case INDEX_op_extrl_i64_i32:
1570 case INDEX_op_ext_i32_i64:
1571 tcg_out_ext32s(s, a0, a1);
1574 case INDEX_op_extrh_i64_i32:
1575 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
1578 case INDEX_op_mulsh_i32:
1579 case INDEX_op_mulsh_i64:
1580 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
1583 case INDEX_op_muluh_i32:
1584 case INDEX_op_muluh_i64:
1585 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
1592 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1593 case INDEX_op_mov_i64:
1594 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1596 g_assert_not_reached();
1600 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
1603 case INDEX_op_goto_ptr:
1606 case INDEX_op_ld8u_i32:
1607 case INDEX_op_ld8s_i32:
1608 case INDEX_op_ld16u_i32:
1609 case INDEX_op_ld16s_i32:
1610 case INDEX_op_ld_i32:
1611 case INDEX_op_not_i32:
1612 case INDEX_op_neg_i32:
1613 case INDEX_op_ld8u_i64:
1614 case INDEX_op_ld8s_i64:
1615 case INDEX_op_ld16u_i64:
1616 case INDEX_op_ld16s_i64:
1617 case INDEX_op_ld32s_i64:
1618 case INDEX_op_ld32u_i64:
1619 case INDEX_op_ld_i64:
1620 case INDEX_op_not_i64:
1621 case INDEX_op_neg_i64:
1622 case INDEX_op_ext8u_i32:
1623 case INDEX_op_ext8u_i64:
1624 case INDEX_op_ext16u_i32:
1625 case INDEX_op_ext16u_i64:
1626 case INDEX_op_ext32u_i64:
1627 case INDEX_op_extu_i32_i64:
1628 case INDEX_op_ext8s_i32:
1629 case INDEX_op_ext8s_i64:
1630 case INDEX_op_ext16s_i32:
1631 case INDEX_op_ext16s_i64:
1632 case INDEX_op_ext32s_i64:
1633 case INDEX_op_extrl_i64_i32:
1634 case INDEX_op_extrh_i64_i32:
1635 case INDEX_op_ext_i32_i64:
1636 return C_O1_I1(r, r);
1638 case INDEX_op_st8_i32:
1639 case INDEX_op_st16_i32:
1640 case INDEX_op_st_i32:
1641 case INDEX_op_st8_i64:
1642 case INDEX_op_st16_i64:
1643 case INDEX_op_st32_i64:
1644 case INDEX_op_st_i64:
1645 return C_O0_I2(rZ, r);
1647 case INDEX_op_add_i32:
1648 case INDEX_op_and_i32:
1649 case INDEX_op_or_i32:
1650 case INDEX_op_xor_i32:
1651 case INDEX_op_add_i64:
1652 case INDEX_op_and_i64:
1653 case INDEX_op_or_i64:
1654 case INDEX_op_xor_i64:
1655 return C_O1_I2(r, r, rI);
1657 case INDEX_op_sub_i32:
1658 case INDEX_op_sub_i64:
1659 return C_O1_I2(r, rZ, rN);
1661 case INDEX_op_mul_i32:
1662 case INDEX_op_mulsh_i32:
1663 case INDEX_op_muluh_i32:
1664 case INDEX_op_div_i32:
1665 case INDEX_op_divu_i32:
1666 case INDEX_op_rem_i32:
1667 case INDEX_op_remu_i32:
1668 case INDEX_op_setcond_i32:
1669 case INDEX_op_mul_i64:
1670 case INDEX_op_mulsh_i64:
1671 case INDEX_op_muluh_i64:
1672 case INDEX_op_div_i64:
1673 case INDEX_op_divu_i64:
1674 case INDEX_op_rem_i64:
1675 case INDEX_op_remu_i64:
1676 case INDEX_op_setcond_i64:
1677 return C_O1_I2(r, rZ, rZ);
1679 case INDEX_op_shl_i32:
1680 case INDEX_op_shr_i32:
1681 case INDEX_op_sar_i32:
1682 case INDEX_op_shl_i64:
1683 case INDEX_op_shr_i64:
1684 case INDEX_op_sar_i64:
1685 return C_O1_I2(r, r, ri);
1687 case INDEX_op_brcond_i32:
1688 case INDEX_op_brcond_i64:
1689 return C_O0_I2(rZ, rZ);
1691 case INDEX_op_add2_i32:
1692 case INDEX_op_add2_i64:
1693 case INDEX_op_sub2_i32:
1694 case INDEX_op_sub2_i64:
1695 return C_O2_I4(r, r, rZ, rZ, rM, rM);
1697 case INDEX_op_brcond2_i32:
1698 return C_O0_I4(rZ, rZ, rZ, rZ);
1700 case INDEX_op_setcond2_i32:
1701 return C_O1_I4(r, rZ, rZ, rZ, rZ);
1703 case INDEX_op_qemu_ld_i32:
1704 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
1705 ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
1706 case INDEX_op_qemu_st_i32:
1707 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
1708 ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
1709 case INDEX_op_qemu_ld_i64:
1710 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
1711 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
1712 : C_O2_I2(r, r, L, L));
1713 case INDEX_op_qemu_st_i64:
1714 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
1715 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
1716 : C_O0_I4(LZ, LZ, L, L));
1719 g_assert_not_reached();
1723 static const int tcg_target_callee_save_regs[] = {
1724 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
1736 TCG_REG_RA, /* should be last for ABI compliance */
1739 /* Stack frame parameters. */
1740 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
1741 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
1742 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1743 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
1744 + TCG_TARGET_STACK_ALIGN - 1) \
1745 & -TCG_TARGET_STACK_ALIGN)
1746 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
1748 /* We're expecting to be able to use an immediate for frame allocation. */
1749 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
1751 /* Generate global QEMU prologue and epilogue code */
1752 static void tcg_target_qemu_prologue(TCGContext *s)
1756 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
1759 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
1760 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1761 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1762 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1765 #if !defined(CONFIG_SOFTMMU)
1766 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1767 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1770 /* Call generated code */
1771 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1772 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1774 /* Return path for goto_ptr. Set return value to 0 */
1775 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
1776 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
1779 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
1780 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1781 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1782 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1785 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
1786 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
1789 static void tcg_target_init(TCGContext *s)
1791 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
1792 if (TCG_TARGET_REG_BITS == 64) {
1793 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
1796 tcg_target_call_clobber_regs = -1u;
1797 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
1798 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
1799 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
1800 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
1801 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
1802 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
1803 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
1804 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
1805 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
1806 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
1807 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
1808 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
1810 s->reserved_regs = 0;
1811 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
1812 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
1813 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
1814 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
1815 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
1816 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
1817 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
1822 uint8_t fde_def_cfa[4];
1823 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
1826 #define ELF_HOST_MACHINE EM_RISCV
1828 static const DebugFrame debug_frame = {
1829 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
1832 .h.cie.code_align = 1,
1833 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
1834 .h.cie.return_column = TCG_REG_RA,
1836 /* Total FDE size does not include the "len" member. */
1837 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1840 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
1841 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
1845 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
1846 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
1847 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
1848 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
1849 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
1850 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
1851 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
1852 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
1853 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
1854 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
1855 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
1856 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
1860 void tcg_register_jit(const void *buf, size_t buf_size)
1862 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));