target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31 #include "kvm_x86.h"
  32
  33 #ifdef CONFIG_KVM_PARA
  34 #include <linux/kvm_para.h>
  35 #endif
  36 //
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 static int lm_capable_kernel;
  58
  59 #ifdef KVM_CAP_EXT_CPUID
  60
  61 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  62 {
  63     struct kvm_cpuid2 *cpuid;
  64     int r, size;
  65
  66     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  67     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  68     cpuid->nent = max;
  69     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  70     if (r == 0 && cpuid->nent >= max) {
  71         r = -E2BIG;
  72     }
  73     if (r < 0) {
  74         if (r == -E2BIG) {
  75             qemu_free(cpuid);
  76             return NULL;
  77         } else {
  78             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  79                     strerror(-r));
  80             exit(1);
  81         }
  82     }
  83     return cpuid;
  84 }
  85
  86 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  87                                       uint32_t index, int reg)
  88 {
  89     struct kvm_cpuid2 *cpuid;
  90     int i, max;
  91     uint32_t ret = 0;
  92     uint32_t cpuid_1_edx;
  93
  94     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  95         return -1U;
  96     }
  97
  98     max = 1;
  99     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 100         max *= 2;
 101     }
 102
 103     for (i = 0; i < cpuid->nent; ++i) {
 104         if (cpuid->entries[i].function == function &&
 105             cpuid->entries[i].index == index) {
 106             switch (reg) {
 107             case R_EAX:
 108                 ret = cpuid->entries[i].eax;
 109                 break;
 110             case R_EBX:
 111                 ret = cpuid->entries[i].ebx;
 112                 break;
 113             case R_ECX:
 114                 ret = cpuid->entries[i].ecx;
 115                 break;
 116             case R_EDX:
 117                 ret = cpuid->entries[i].edx;
 118                 switch (function) {
 119                 case 1:
 120                     /* KVM before 2.6.30 misreports the following features */
 121                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 122                     break;
 123                 case 0x80000001:
 124                     /* On Intel, kvm returns cpuid according to the Intel spec,
 125                      * so add missing bits according to the AMD spec:
 126                      */
 127                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 128                     ret |= cpuid_1_edx & 0x183f7ff;
 129                     break;
 130                 }
 131                 break;
 132             }
 133         }
 134     }
 135
 136     qemu_free(cpuid);
 137
 138     return ret;
 139 }
 140
 141 #else
 142
 143 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 144                                       uint32_t index, int reg)
 145 {
 146     return -1U;
 147 }
 148
 149 #endif
 150
 151 #ifdef CONFIG_KVM_PARA
 152 struct kvm_para_features {
 153         int cap;
 154         int feature;
 155 } para_features[] = {
 156 #ifdef KVM_CAP_CLOCKSOURCE
 157         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 158 #endif
 159 #ifdef KVM_CAP_NOP_IO_DELAY
 160         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 161 #endif
 162 #ifdef KVM_CAP_PV_MMU
 163         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 164 #endif
 165 #ifdef KVM_CAP_ASYNC_PF
 166         { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 167 #endif
 168         { -1, -1 }
 169 };
 170
 171 static int get_para_features(CPUState *env)
 172 {
 173         int i, features = 0;
 174
 175         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 176                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 177                         features |= (1 << para_features[i].feature);
 178         }
 179
 180         return features;
 181 }
 182 #endif
 183
 184 #ifdef KVM_CAP_MCE
 185 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 186                                      int *max_banks)
 187 {
 188     int r;
 189
 190     r = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
 191     if (r > 0) {
 192         *max_banks = r;
 193         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 194     }
 195     return -ENOSYS;
 196 }
 197
 198 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 199 {
 200     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 201 }
 202
 203 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 204 {
 205     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 206 }
 207
 208 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 209 {
 210     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 211     int r;
 212
 213     kmsrs->nmsrs = n;
 214     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 215     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 216     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 217     free(kmsrs);
 218     return r;
 219 }
 220
 221 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 222 static int kvm_mce_in_exception(CPUState *env)
 223 {
 224     struct kvm_msr_entry msr_mcg_status = {
 225         .index = MSR_MCG_STATUS,
 226     };
 227     int r;
 228
 229     r = kvm_get_msr(env, &msr_mcg_status, 1);
 230     if (r == -1 || r == 0) {
 231         return -1;
 232     }
 233     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 234 }
 235
 236 struct kvm_x86_mce_data
 237 {
 238     CPUState *env;
 239     struct kvm_x86_mce *mce;
 240     int abort_on_error;
 241 };
 242
 243 static void kvm_do_inject_x86_mce(void *_data)
 244 {
 245     struct kvm_x86_mce_data *data = _data;
 246     int r;
 247
 248     /* If there is an MCE exception being processed, ignore this SRAO MCE */
 249     if ((data->env->mcg_cap & MCG_SER_P) &&
 250         !(data->mce->status & MCI_STATUS_AR)) {
 251         r = kvm_mce_in_exception(data->env);
 252         if (r == -1) {
 253             fprintf(stderr, "Failed to get MCE status\n");
 254         } else if (r) {
 255             return;
 256         }
 257     }
 258
 259     r = kvm_set_mce(data->env, data->mce);
 260     if (r < 0) {
 261         perror("kvm_set_mce FAILED");
 262         if (data->abort_on_error) {
 263             abort();
 264         }
 265     }
 266 }
 267 #endif
 268
 269 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 270                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 271                         int abort_on_error)
 272 {
 273 #ifdef KVM_CAP_MCE
 274     struct kvm_x86_mce mce = {
 275         .bank = bank,
 276         .status = status,
 277         .mcg_status = mcg_status,
 278         .addr = addr,
 279         .misc = misc,
 280     };
 281     struct kvm_x86_mce_data data = {
 282             .env = cenv,
 283             .mce = &mce,
 284     };
 285
 286     if (!cenv->mcg_cap) {
 287         fprintf(stderr, "MCE support is not enabled!\n");
 288         return;
 289     }
 290
 291     on_vcpu(cenv, kvm_do_inject_x86_mce, &data);
 292 #else
 293     if (abort_on_error)
 294         abort();
 295 #endif
 296 }
 297
 298 static int _kvm_arch_init_vcpu(CPUState *env);
 299
 300 int kvm_arch_init_vcpu(CPUState *env)
 301 {
 302     int r;
 303     struct {
 304         struct kvm_cpuid2 cpuid;
 305         struct kvm_cpuid_entry2 entries[100];
 306     } __attribute__((packed)) cpuid_data;
 307     uint32_t limit, i, j, cpuid_i;
 308     uint32_t unused;
 309     struct kvm_cpuid_entry2 *c;
 310 #ifdef KVM_CPUID_SIGNATURE
 311     uint32_t signature[3];
 312 #endif
 313
 314     r = _kvm_arch_init_vcpu(env);
 315     if (r < 0) {
 316         return r;
 317     }
 318
 319 #ifdef OBSOLETE_KVM_IMPL
 320
 321     env->mp_state = KVM_MP_STATE_RUNNABLE;
 322
 323 #endif
 324
 325     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 326
 327     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 328     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 329     env->cpuid_ext_features |= i;
 330
 331     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 332                                                              0, R_EDX);
 333     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 334                                                              0, R_ECX);
 335     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 336                                                              0, R_EDX);
 337
 338
 339     cpuid_i = 0;
 340
 341 #ifdef CONFIG_KVM_PARA
 342     /* Paravirtualization CPUIDs */
 343     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 344     c = &cpuid_data.entries[cpuid_i++];
 345     memset(c, 0, sizeof(*c));
 346     c->function = KVM_CPUID_SIGNATURE;
 347     c->eax = 0;
 348     c->ebx = signature[0];
 349     c->ecx = signature[1];
 350     c->edx = signature[2];
 351
 352     c = &cpuid_data.entries[cpuid_i++];
 353     memset(c, 0, sizeof(*c));
 354     c->function = KVM_CPUID_FEATURES;
 355     c->eax = env->cpuid_kvm_features & get_para_features(env);
 356 #endif
 357
 358     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 359
 360     for (i = 0; i <= limit; i++) {
 361         c = &cpuid_data.entries[cpuid_i++];
 362
 363         switch (i) {
 364         case 2: {
 365             /* Keep reading function 2 till all the input is received */
 366             int times;
 367
 368             c->function = i;
 369             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 370                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 371             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 372             times = c->eax & 0xff;
 373
 374             for (j = 1; j < times; ++j) {
 375                 c = &cpuid_data.entries[cpuid_i++];
 376                 c->function = i;
 377                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 378                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 379             }
 380             break;
 381         }
 382         case 4:
 383         case 0xb:
 384         case 0xd:
 385             for (j = 0; ; j++) {
 386                 c->function = i;
 387                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 388                 c->index = j;
 389                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 390
 391                 if (i == 4 && c->eax == 0)
 392                     break;
 393                 if (i == 0xb && !(c->ecx & 0xff00))
 394                     break;
 395                 if (i == 0xd && c->eax == 0)
 396                     break;
 397
 398                 c = &cpuid_data.entries[cpuid_i++];
 399             }
 400             break;
 401         default:
 402             c->function = i;
 403             c->flags = 0;
 404             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 405             break;
 406         }
 407     }
 408     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 409
 410     for (i = 0x80000000; i <= limit; i++) {
 411         c = &cpuid_data.entries[cpuid_i++];
 412
 413         c->function = i;
 414         c->flags = 0;
 415         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 416     }
 417
 418     cpuid_data.cpuid.nent = cpuid_i;
 419
 420 #ifdef KVM_CAP_MCE
 421     if (((env->cpuid_version >> 8)&0xF) >= 6
 422         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 423         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 424         uint64_t mcg_cap;
 425         int banks;
 426
 427         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks))
 428             perror("kvm_get_mce_cap_supported FAILED");
 429         else {
 430             if (banks > MCE_BANKS_DEF)
 431                 banks = MCE_BANKS_DEF;
 432             mcg_cap &= MCE_CAP_DEF;
 433             mcg_cap |= banks;
 434             if (kvm_setup_mce(env, &mcg_cap))
 435                 perror("kvm_setup_mce FAILED");
 436             else
 437                 env->mcg_cap = mcg_cap;
 438         }
 439     }
 440 #endif
 441
 442     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 443 }
 444
 445 static void kvm_clear_vapic(CPUState *env)
 446 {
 447 #ifdef KVM_SET_VAPIC_ADDR
 448     struct kvm_vapic_addr va = {
 449         .vapic_addr = 0,
 450     };
 451
 452     kvm_vcpu_ioctl(env, KVM_SET_VAPIC_ADDR, &va);
 453 #endif
 454 }
 455
 456 void kvm_arch_reset_vcpu(CPUState *env)
 457 {
 458     kvm_clear_vapic(env);
 459     env->exception_injected = -1;
 460     env->interrupt_injected = -1;
 461     env->nmi_injected = 0;
 462     env->nmi_pending = 0;
 463     /* Legal xcr0 for loading */
 464     env->xcr0 = 1;
 465     if (kvm_irqchip_in_kernel()) {
 466         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 467                                           KVM_MP_STATE_UNINITIALIZED;
 468     } else {
 469         env->mp_state = KVM_MP_STATE_RUNNABLE;
 470     }
 471 }
 472
 473 int has_msr_star;
 474 int has_msr_hsave_pa;
 475
 476 static void kvm_supported_msrs(CPUState *env)
 477 {
 478     static int kvm_supported_msrs;
 479     int ret;
 480
 481     /* first time */
 482     if (kvm_supported_msrs == 0) {
 483         struct kvm_msr_list msr_list, *kvm_msr_list;
 484
 485         kvm_supported_msrs = -1;
 486
 487         /* Obtain MSR list from KVM.  These are the MSRs that we must
 488          * save/restore */
 489         msr_list.nmsrs = 0;
 490         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 491         if (ret < 0 && ret != -E2BIG) {
 492             return;
 493         }
 494         /* Old kernel modules had a bug and could write beyond the provided
 495            memory. Allocate at least a safe amount of 1K. */
 496         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 497                                               msr_list.nmsrs *
 498                                               sizeof(msr_list.indices[0])));
 499
 500         kvm_msr_list->nmsrs = msr_list.nmsrs;
 501         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 502         if (ret >= 0) {
 503             int i;
 504
 505             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 506                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 507                     has_msr_star = 1;
 508                     continue;
 509                 }
 510                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 511                     has_msr_hsave_pa = 1;
 512                     continue;
 513                 }
 514             }
 515         }
 516
 517         free(kvm_msr_list);
 518     }
 519
 520     return;
 521 }
 522
 523 static int kvm_has_msr_hsave_pa(CPUState *env)
 524 {
 525     kvm_supported_msrs(env);
 526     return has_msr_hsave_pa;
 527 }
 528
 529 static int kvm_has_msr_star(CPUState *env)
 530 {
 531     kvm_supported_msrs(env);
 532     return has_msr_star;
 533 }
 534
 535 #ifdef OBSOLETE_KVM_IMPL
 536 static int kvm_init_identity_map_page(KVMState *s)
 537 {
 538 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 539     int ret;
 540     uint64_t addr = 0xfffbc000;
 541
 542     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 543         return 0;
 544     }
 545
 546     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 547     if (ret < 0) {
 548         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 549         return ret;
 550     }
 551 #endif
 552     return 0;
 553 }
 554
 555 int kvm_arch_init(KVMState *s, int smp_cpus)
 556 {
 557     int ret;
 558
 559     struct utsname utsname;
 560
 561     uname(&utsname);
 562     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 563
 564     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 565      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 566      * must be part of guest physical memory, we need to allocate it.  Older
 567      * versions of KVM just assumed that it would be at the end of physical
 568      * memory but that doesn't work with more than 4GB of memory.  We simply
 569      * refuse to work with those older versions of KVM. */
 570     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 571     if (ret <= 0) {
 572         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 573         return ret;
 574     }
 575
 576     /* this address is 3 pages before the bios, and the bios should present
 577      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 578      * this?
 579      */
 580     /*
 581      * Tell fw_cfg to notify the BIOS to reserve the range.
 582      */
 583     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 584         perror("e820_add_entry() table is full");
 585         exit(1);
 586     }
 587     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 588     if (ret < 0) {
 589         return ret;
 590     }
 591
 592     return kvm_init_identity_map_page(s);
 593 }
 594
 595 #endif
 596
 597 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 598 {
 599     lhs->selector = rhs->selector;
 600     lhs->base = rhs->base;
 601     lhs->limit = rhs->limit;
 602     lhs->type = 3;
 603     lhs->present = 1;
 604     lhs->dpl = 3;
 605     lhs->db = 0;
 606     lhs->s = 1;
 607     lhs->l = 0;
 608     lhs->g = 0;
 609     lhs->avl = 0;
 610     lhs->unusable = 0;
 611 }
 612
 613 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 614 {
 615     unsigned flags = rhs->flags;
 616     lhs->selector = rhs->selector;
 617     lhs->base = rhs->base;
 618     lhs->limit = rhs->limit;
 619     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 620     lhs->present = (flags & DESC_P_MASK) != 0;
 621     lhs->dpl = rhs->selector & 3;
 622     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 623     lhs->s = (flags & DESC_S_MASK) != 0;
 624     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 625     lhs->g = (flags & DESC_G_MASK) != 0;
 626     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 627     lhs->unusable = 0;
 628 }
 629
 630 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 631 {
 632     lhs->selector = rhs->selector;
 633     lhs->base = rhs->base;
 634     lhs->limit = rhs->limit;
 635     lhs->flags =
 636         (rhs->type << DESC_TYPE_SHIFT)
 637         | (rhs->present * DESC_P_MASK)
 638         | (rhs->dpl << DESC_DPL_SHIFT)
 639         | (rhs->db << DESC_B_SHIFT)
 640         | (rhs->s * DESC_S_MASK)
 641         | (rhs->l << DESC_L_SHIFT)
 642         | (rhs->g * DESC_G_MASK)
 643         | (rhs->avl * DESC_AVL_MASK);
 644 }
 645
 646
 647 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 648 {
 649     if (set)
 650         *kvm_reg = *qemu_reg;
 651     else
 652         *qemu_reg = *kvm_reg;
 653 }
 654
 655 static int kvm_getput_regs(CPUState *env, int set)
 656 {
 657     struct kvm_regs regs;
 658     int ret = 0;
 659
 660     if (!set) {
 661         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 662         if (ret < 0)
 663             return ret;
 664     }
 665
 666     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 667     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 668     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 669     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 670     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 671     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 672     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 673     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 674 #ifdef TARGET_X86_64
 675     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 676     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 677     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 678     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 679     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 680     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 681     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 682     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 683 #endif
 684
 685     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 686     kvm_getput_reg(&regs.rip, &env->eip, set);
 687
 688     if (set)
 689         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 690
 691     return ret;
 692 }
 693
 694 static int kvm_put_fpu(CPUState *env)
 695 {
 696     struct kvm_fpu fpu;
 697     int i;
 698
 699     memset(&fpu, 0, sizeof fpu);
 700     fpu.fsw = env->fpus & ~(7 << 11);
 701     fpu.fsw |= (env->fpstt & 7) << 11;
 702     fpu.fcw = env->fpuc;
 703     for (i = 0; i < 8; ++i)
 704         fpu.ftwx |= (!env->fptags[i]) << i;
 705     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 706     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 707     fpu.mxcsr = env->mxcsr;
 708
 709     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 710 }
 711
 712 #ifdef KVM_CAP_XSAVE
 713 #define XSAVE_CWD_RIP     2
 714 #define XSAVE_CWD_RDP     4
 715 #define XSAVE_MXCSR       6
 716 #define XSAVE_ST_SPACE    8
 717 #define XSAVE_XMM_SPACE   40
 718 #define XSAVE_XSTATE_BV   128
 719 #define XSAVE_YMMH_SPACE  144
 720 #endif
 721
 722 static int kvm_put_xsave(CPUState *env)
 723 {
 724 #ifdef KVM_CAP_XSAVE
 725     int i, r;
 726     struct kvm_xsave* xsave;
 727     uint16_t cwd, swd, twd, fop;
 728
 729     if (!kvm_has_xsave())
 730         return kvm_put_fpu(env);
 731
 732     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 733     memset(xsave, 0, sizeof(struct kvm_xsave));
 734     cwd = swd = twd = fop = 0;
 735     swd = env->fpus & ~(7 << 11);
 736     swd |= (env->fpstt & 7) << 11;
 737     cwd = env->fpuc;
 738     for (i = 0; i < 8; ++i)
 739         twd |= (!env->fptags[i]) << i;
 740     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 741     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 742     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 743             sizeof env->fpregs);
 744     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 745             sizeof env->xmm_regs);
 746     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 747     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 748     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 749             sizeof env->ymmh_regs);
 750     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 751     qemu_free(xsave);
 752     return r;
 753 #else
 754     return kvm_put_fpu(env);
 755 #endif
 756 }
 757
 758 static int kvm_put_xcrs(CPUState *env)
 759 {
 760 #ifdef KVM_CAP_XCRS
 761     struct kvm_xcrs xcrs;
 762
 763     if (!kvm_has_xcrs())
 764         return 0;
 765
 766     xcrs.nr_xcrs = 1;
 767     xcrs.flags = 0;
 768     xcrs.xcrs[0].xcr = 0;
 769     xcrs.xcrs[0].value = env->xcr0;
 770     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 771 #else
 772     return 0;
 773 #endif
 774 }
 775
 776 static int kvm_put_sregs(CPUState *env)
 777 {
 778     struct kvm_sregs sregs;
 779
 780     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 781     if (env->interrupt_injected >= 0) {
 782         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 783                 (uint64_t)1 << (env->interrupt_injected % 64);
 784     }
 785
 786     if ((env->eflags & VM_MASK)) {
 787             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 788             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 789             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 790             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 791             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 792             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 793     } else {
 794             set_seg(&sregs.cs, &env->segs[R_CS]);
 795             set_seg(&sregs.ds, &env->segs[R_DS]);
 796             set_seg(&sregs.es, &env->segs[R_ES]);
 797             set_seg(&sregs.fs, &env->segs[R_FS]);
 798             set_seg(&sregs.gs, &env->segs[R_GS]);
 799             set_seg(&sregs.ss, &env->segs[R_SS]);
 800
 801             if (env->cr[0] & CR0_PE_MASK) {
 802                 /* force ss cpl to cs cpl */
 803                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 804                         (sregs.cs.selector & 3);
 805                 sregs.ss.dpl = sregs.ss.selector & 3;
 806             }
 807     }
 808
 809     set_seg(&sregs.tr, &env->tr);
 810     set_seg(&sregs.ldt, &env->ldt);
 811
 812     sregs.idt.limit = env->idt.limit;
 813     sregs.idt.base = env->idt.base;
 814     sregs.gdt.limit = env->gdt.limit;
 815     sregs.gdt.base = env->gdt.base;
 816
 817     sregs.cr0 = env->cr[0];
 818     sregs.cr2 = env->cr[2];
 819     sregs.cr3 = env->cr[3];
 820     sregs.cr4 = env->cr[4];
 821
 822     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 823     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 824
 825     sregs.efer = env->efer;
 826
 827     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 828 }
 829
 830 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 831                               uint32_t index, uint64_t value)
 832 {
 833     entry->index = index;
 834     entry->data = value;
 835 }
 836
 837 static int kvm_put_msrs(CPUState *env, int level)
 838 {
 839     struct {
 840         struct kvm_msrs info;
 841         struct kvm_msr_entry entries[100];
 842     } msr_data;
 843     struct kvm_msr_entry *msrs = msr_data.entries;
 844     int n = 0;
 845
 846     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 847     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 848     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 849     if (kvm_has_msr_star(env))
 850         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 851     if (kvm_has_msr_hsave_pa(env))
 852         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 853 #ifdef TARGET_X86_64
 854     if (lm_capable_kernel) {
 855         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 856         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 857         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 858         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 859     }
 860 #endif
 861     if (level == KVM_PUT_FULL_STATE) {
 862         /*
 863          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 864          * writeback. Until this is fixed, we only write the offset to SMP
 865          * guests after migration, desynchronizing the VCPUs, but avoiding
 866          * huge jump-backs that would occur without any writeback at all.
 867          */
 868         if (smp_cpus == 1 || env->tsc != 0) {
 869             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 870         }
 871         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 872                           env->system_time_msr);
 873         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 874 #ifdef KVM_CAP_ASYNC_PF
 875         kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
 876 #endif
 877     }
 878 #ifdef KVM_CAP_MCE
 879     if (env->mcg_cap) {
 880         int i;
 881         if (level == KVM_PUT_RESET_STATE)
 882             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 883         else if (level == KVM_PUT_FULL_STATE) {
 884             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 885             kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 886             for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
 887                 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 888         }
 889     }
 890 #endif
 891
 892     msr_data.info.nmsrs = n;
 893
 894     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 895
 896 }
 897
 898 static int kvm_get_fpu(CPUState *env)
 899 {
 900     struct kvm_fpu fpu;
 901     int i, ret;
 902
 903     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 904     if (ret < 0)
 905         return ret;
 906
 907     env->fpstt = (fpu.fsw >> 11) & 7;
 908     env->fpus = fpu.fsw;
 909     env->fpuc = fpu.fcw;
 910     for (i = 0; i < 8; ++i)
 911         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 912     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 913     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 914     env->mxcsr = fpu.mxcsr;
 915
 916     return 0;
 917 }
 918
 919 static int kvm_get_xsave(CPUState *env)
 920 {
 921 #ifdef KVM_CAP_XSAVE
 922     struct kvm_xsave* xsave;
 923     int ret, i;
 924     uint16_t cwd, swd, twd, fop;
 925
 926     if (!kvm_has_xsave())
 927         return kvm_get_fpu(env);
 928
 929     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 930     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 931     if (ret < 0) {
 932         qemu_free(xsave);
 933         return ret;
 934     }
 935
 936     cwd = (uint16_t)xsave->region[0];
 937     swd = (uint16_t)(xsave->region[0] >> 16);
 938     twd = (uint16_t)xsave->region[1];
 939     fop = (uint16_t)(xsave->region[1] >> 16);
 940     env->fpstt = (swd >> 11) & 7;
 941     env->fpus = swd;
 942     env->fpuc = cwd;
 943     for (i = 0; i < 8; ++i)
 944         env->fptags[i] = !((twd >> i) & 1);
 945     env->mxcsr = xsave->region[XSAVE_MXCSR];
 946     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 947             sizeof env->fpregs);
 948     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 949             sizeof env->xmm_regs);
 950     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 951     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 952             sizeof env->ymmh_regs);
 953     qemu_free(xsave);
 954     return 0;
 955 #else
 956     return kvm_get_fpu(env);
 957 #endif
 958 }
 959
 960 static int kvm_get_xcrs(CPUState *env)
 961 {
 962 #ifdef KVM_CAP_XCRS
 963     int i, ret;
 964     struct kvm_xcrs xcrs;
 965
 966     if (!kvm_has_xcrs())
 967         return 0;
 968
 969     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 970     if (ret < 0)
 971         return ret;
 972
 973     for (i = 0; i < xcrs.nr_xcrs; i++)
 974         /* Only support xcr0 now */
 975         if (xcrs.xcrs[0].xcr == 0) {
 976             env->xcr0 = xcrs.xcrs[0].value;
 977             break;
 978         }
 979     return 0;
 980 #else
 981     return 0;
 982 #endif
 983 }
 984
 985 static int kvm_get_sregs(CPUState *env)
 986 {
 987     struct kvm_sregs sregs;
 988     uint32_t hflags;
 989     int bit, i, ret;
 990
 991     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 992     if (ret < 0)
 993         return ret;
 994
 995     /* There can only be one pending IRQ set in the bitmap at a time, so try
 996        to find it and save its number instead (-1 for none). */
 997     env->interrupt_injected = -1;
 998     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 999         if (sregs.interrupt_bitmap[i]) {
1000             bit = ctz64(sregs.interrupt_bitmap[i]);
1001             env->interrupt_injected = i * 64 + bit;
1002             break;
1003         }
1004     }
1005
1006     get_seg(&env->segs[R_CS], &sregs.cs);
1007     get_seg(&env->segs[R_DS], &sregs.ds);
1008     get_seg(&env->segs[R_ES], &sregs.es);
1009     get_seg(&env->segs[R_FS], &sregs.fs);
1010     get_seg(&env->segs[R_GS], &sregs.gs);
1011     get_seg(&env->segs[R_SS], &sregs.ss);
1012
1013     get_seg(&env->tr, &sregs.tr);
1014     get_seg(&env->ldt, &sregs.ldt);
1015
1016     env->idt.limit = sregs.idt.limit;
1017     env->idt.base = sregs.idt.base;
1018     env->gdt.limit = sregs.gdt.limit;
1019     env->gdt.base = sregs.gdt.base;
1020
1021     env->cr[0] = sregs.cr0;
1022     env->cr[2] = sregs.cr2;
1023     env->cr[3] = sregs.cr3;
1024     env->cr[4] = sregs.cr4;
1025
1026     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1027
1028     env->efer = sregs.efer;
1029     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1030
1031 #define HFLAG_COPY_MASK ~( \
1032                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1033                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1034                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1035                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1036
1037
1038
1039     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1040     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1041     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1042             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1043     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1044     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1045             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1046
1047     if (env->efer & MSR_EFER_LMA) {
1048         hflags |= HF_LMA_MASK;
1049     }
1050
1051     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1052         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1053     } else {
1054         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1055                 (DESC_B_SHIFT - HF_CS32_SHIFT);
1056         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1057                 (DESC_B_SHIFT - HF_SS32_SHIFT);
1058         if (!(env->cr[0] & CR0_PE_MASK) ||
1059                    (env->eflags & VM_MASK) ||
1060                    !(hflags & HF_CS32_MASK)) {
1061                 hflags |= HF_ADDSEG_MASK;
1062             } else {
1063                 hflags |= ((env->segs[R_DS].base |
1064                                 env->segs[R_ES].base |
1065                                 env->segs[R_SS].base) != 0) <<
1066                     HF_ADDSEG_SHIFT;
1067             }
1068     }
1069     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1070
1071     return 0;
1072 }
1073
1074 static int kvm_get_msrs(CPUState *env)
1075 {
1076     struct {
1077         struct kvm_msrs info;
1078         struct kvm_msr_entry entries[100];
1079     } msr_data;
1080     struct kvm_msr_entry *msrs = msr_data.entries;
1081     int ret, i, n;
1082
1083     n = 0;
1084     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1085     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1086     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1087     if (kvm_has_msr_star(env))
1088         msrs[n++].index = MSR_STAR;
1089     if (kvm_has_msr_hsave_pa(env))
1090         msrs[n++].index = MSR_VM_HSAVE_PA;
1091     msrs[n++].index = MSR_IA32_TSC;
1092     msrs[n++].index = MSR_VM_HSAVE_PA;
1093 #ifdef TARGET_X86_64
1094     if (lm_capable_kernel) {
1095         msrs[n++].index = MSR_CSTAR;
1096         msrs[n++].index = MSR_KERNELGSBASE;
1097         msrs[n++].index = MSR_FMASK;
1098         msrs[n++].index = MSR_LSTAR;
1099     }
1100 #endif
1101     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1102     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1103 #ifdef KVM_CAP_ASYNC_PF
1104     msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1105 #endif
1106
1107 #ifdef KVM_CAP_MCE
1108     if (env->mcg_cap) {
1109         msrs[n++].index = MSR_MCG_STATUS;
1110         msrs[n++].index = MSR_MCG_CTL;
1111         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
1112             msrs[n++].index = MSR_MC0_CTL + i;
1113     }
1114 #endif
1115
1116     msr_data.info.nmsrs = n;
1117     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1118     if (ret < 0)
1119         return ret;
1120
1121     for (i = 0; i < ret; i++) {
1122         switch (msrs[i].index) {
1123         case MSR_IA32_SYSENTER_CS:
1124             env->sysenter_cs = msrs[i].data;
1125             break;
1126         case MSR_IA32_SYSENTER_ESP:
1127             env->sysenter_esp = msrs[i].data;
1128             break;
1129         case MSR_IA32_SYSENTER_EIP:
1130             env->sysenter_eip = msrs[i].data;
1131             break;
1132         case MSR_STAR:
1133             env->star = msrs[i].data;
1134             break;
1135 #ifdef TARGET_X86_64
1136         case MSR_CSTAR:
1137             env->cstar = msrs[i].data;
1138             break;
1139         case MSR_KERNELGSBASE:
1140             env->kernelgsbase = msrs[i].data;
1141             break;
1142         case MSR_FMASK:
1143             env->fmask = msrs[i].data;
1144             break;
1145         case MSR_LSTAR:
1146             env->lstar = msrs[i].data;
1147             break;
1148 #endif
1149         case MSR_IA32_TSC:
1150             env->tsc = msrs[i].data;
1151             break;
1152         case MSR_VM_HSAVE_PA:
1153             env->vm_hsave = msrs[i].data;
1154             break;
1155         case MSR_KVM_SYSTEM_TIME:
1156             env->system_time_msr = msrs[i].data;
1157             break;
1158         case MSR_KVM_WALL_CLOCK:
1159             env->wall_clock_msr = msrs[i].data;
1160             break;
1161 #ifdef KVM_CAP_MCE
1162         case MSR_MCG_STATUS:
1163             env->mcg_status = msrs[i].data;
1164             break;
1165         case MSR_MCG_CTL:
1166             env->mcg_ctl = msrs[i].data;
1167             break;
1168 #endif
1169         default:
1170 #ifdef KVM_CAP_MCE
1171             if (msrs[i].index >= MSR_MC0_CTL &&
1172                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1173                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1174             }
1175 #endif
1176             break;
1177 #ifdef KVM_CAP_ASYNC_PF
1178         case MSR_KVM_ASYNC_PF_EN:
1179             env->async_pf_en_msr = msrs[i].data;
1180             break;
1181 #endif
1182         }
1183     }
1184
1185     return 0;
1186 }
1187
1188 #ifdef OBSOLETE_KVM_IMPL
1189 static int kvm_put_mp_state(CPUState *env)
1190 {
1191     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1192
1193     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1194 }
1195
1196 static int kvm_get_mp_state(CPUState *env)
1197 {
1198     struct kvm_mp_state mp_state;
1199     int ret;
1200
1201     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1202     if (ret < 0) {
1203         return ret;
1204     }
1205     env->mp_state = mp_state.mp_state;
1206     return 0;
1207 }
1208 #endif
1209
1210 static int kvm_put_vcpu_events(CPUState *env, int level)
1211 {
1212 #ifdef KVM_CAP_VCPU_EVENTS
1213     struct kvm_vcpu_events events;
1214
1215     if (!kvm_has_vcpu_events()) {
1216         return 0;
1217     }
1218
1219     events.exception.injected = (env->exception_injected >= 0);
1220     events.exception.nr = env->exception_injected;
1221     events.exception.has_error_code = env->has_error_code;
1222     events.exception.error_code = env->error_code;
1223
1224     events.interrupt.injected = (env->interrupt_injected >= 0);
1225     events.interrupt.nr = env->interrupt_injected;
1226     events.interrupt.soft = env->soft_interrupt;
1227
1228     events.nmi.injected = env->nmi_injected;
1229     events.nmi.pending = env->nmi_pending;
1230     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1231
1232     events.sipi_vector = env->sipi_vector;
1233
1234     events.flags = 0;
1235     if (level >= KVM_PUT_RESET_STATE) {
1236         events.flags |=
1237             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1238     }
1239
1240     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1241 #else
1242     return 0;
1243 #endif
1244 }
1245
1246 static int kvm_get_vcpu_events(CPUState *env)
1247 {
1248 #ifdef KVM_CAP_VCPU_EVENTS
1249     struct kvm_vcpu_events events;
1250     int ret;
1251
1252     if (!kvm_has_vcpu_events()) {
1253         return 0;
1254     }
1255
1256     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1257     if (ret < 0) {
1258        return ret;
1259     }
1260     env->exception_injected =
1261        events.exception.injected ? events.exception.nr : -1;
1262     env->has_error_code = events.exception.has_error_code;
1263     env->error_code = events.exception.error_code;
1264
1265     env->interrupt_injected =
1266         events.interrupt.injected ? events.interrupt.nr : -1;
1267     env->soft_interrupt = events.interrupt.soft;
1268
1269     env->nmi_injected = events.nmi.injected;
1270     env->nmi_pending = events.nmi.pending;
1271     if (events.nmi.masked) {
1272         env->hflags2 |= HF2_NMI_MASK;
1273     } else {
1274         env->hflags2 &= ~HF2_NMI_MASK;
1275     }
1276
1277     env->sipi_vector = events.sipi_vector;
1278 #endif
1279
1280     return 0;
1281 }
1282
1283 static int kvm_guest_debug_workarounds(CPUState *env)
1284 {
1285     int ret = 0;
1286 #ifdef KVM_CAP_SET_GUEST_DEBUG
1287     unsigned long reinject_trap = 0;
1288
1289     if (!kvm_has_vcpu_events()) {
1290         if (env->exception_injected == 1) {
1291             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1292         } else if (env->exception_injected == 3) {
1293             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1294         }
1295         env->exception_injected = -1;
1296     }
1297
1298     /*
1299      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1300      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1301      * by updating the debug state once again if single-stepping is on.
1302      * Another reason to call kvm_update_guest_debug here is a pending debug
1303      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1304      * reinject them via SET_GUEST_DEBUG.
1305      */
1306     if (reinject_trap ||
1307         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1308         ret = kvm_update_guest_debug(env, reinject_trap);
1309     }
1310 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1311     return ret;
1312 }
1313
1314 static int kvm_put_debugregs(CPUState *env)
1315 {
1316 #ifdef KVM_CAP_DEBUGREGS
1317     struct kvm_debugregs dbgregs;
1318     int i;
1319
1320     if (!kvm_has_debugregs()) {
1321         return 0;
1322     }
1323
1324     for (i = 0; i < 4; i++) {
1325         dbgregs.db[i] = env->dr[i];
1326     }
1327     dbgregs.dr6 = env->dr[6];
1328     dbgregs.dr7 = env->dr[7];
1329     dbgregs.flags = 0;
1330
1331     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1332 #else
1333     return 0;
1334 #endif
1335 }
1336
1337 static int kvm_get_debugregs(CPUState *env)
1338 {
1339 #ifdef KVM_CAP_DEBUGREGS
1340     struct kvm_debugregs dbgregs;
1341     int i, ret;
1342
1343     if (!kvm_has_debugregs()) {
1344         return 0;
1345     }
1346
1347     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1348     if (ret < 0) {
1349        return ret;
1350     }
1351     for (i = 0; i < 4; i++) {
1352         env->dr[i] = dbgregs.db[i];
1353     }
1354     env->dr[4] = env->dr[6] = dbgregs.dr6;
1355     env->dr[5] = env->dr[7] = dbgregs.dr7;
1356 #endif
1357
1358     return 0;
1359 }
1360
1361 #ifdef OBSOLETE_KVM_IMPL
1362 int kvm_arch_put_registers(CPUState *env, int level)
1363 {
1364     int ret;
1365
1366     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1367
1368     ret = kvm_getput_regs(env, 1);
1369     if (ret < 0)
1370         return ret;
1371
1372     ret = kvm_put_xsave(env);
1373     if (ret < 0)
1374         return ret;
1375
1376     ret = kvm_put_xcrs(env);
1377     if (ret < 0)
1378         return ret;
1379
1380     ret = kvm_put_sregs(env);
1381     if (ret < 0)
1382         return ret;
1383
1384     ret = kvm_put_msrs(env, level);
1385     if (ret < 0)
1386         return ret;
1387
1388     if (level >= KVM_PUT_RESET_STATE) {
1389         ret = kvm_put_mp_state(env);
1390         if (ret < 0)
1391             return ret;
1392     }
1393
1394     ret = kvm_put_vcpu_events(env, level);
1395     if (ret < 0)
1396         return ret;
1397
1398     /* must be last */
1399     ret = kvm_guest_debug_workarounds(env);
1400     if (ret < 0)
1401         return ret;
1402
1403     ret = kvm_put_debugregs(env);
1404     if (ret < 0)
1405         return ret;
1406
1407     return 0;
1408 }
1409
1410 int kvm_arch_get_registers(CPUState *env)
1411 {
1412     int ret;
1413
1414     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1415
1416     ret = kvm_getput_regs(env, 0);
1417     if (ret < 0)
1418         return ret;
1419
1420     ret = kvm_get_xsave(env);
1421     if (ret < 0)
1422         return ret;
1423
1424     ret = kvm_get_xcrs(env);
1425     if (ret < 0)
1426         return ret;
1427
1428     ret = kvm_get_sregs(env);
1429     if (ret < 0)
1430         return ret;
1431
1432     ret = kvm_get_msrs(env);
1433     if (ret < 0)
1434         return ret;
1435
1436     ret = kvm_get_mp_state(env);
1437     if (ret < 0)
1438         return ret;
1439
1440     ret = kvm_get_vcpu_events(env);
1441     if (ret < 0)
1442         return ret;
1443
1444     ret = kvm_get_debugregs(env);
1445     if (ret < 0)
1446         return ret;
1447
1448     return 0;
1449 }
1450
1451 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1452 {
1453     /* Try to inject an interrupt if the guest can accept it */
1454     if (run->ready_for_interrupt_injection &&
1455         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1456         (env->eflags & IF_MASK)) {
1457         int irq;
1458
1459         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1460         irq = cpu_get_pic_interrupt(env);
1461         if (irq >= 0) {
1462             struct kvm_interrupt intr;
1463             intr.irq = irq;
1464             /* FIXME: errors */
1465             DPRINTF("injected interrupt %d\n", irq);
1466             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1467         }
1468     }
1469
1470     /* If we have an interrupt but the guest is not ready to receive an
1471      * interrupt, request an interrupt window exit.  This will
1472      * cause a return to userspace as soon as the guest is ready to
1473      * receive interrupts. */
1474     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1475         run->request_interrupt_window = 1;
1476     else
1477         run->request_interrupt_window = 0;
1478
1479     DPRINTF("setting tpr\n");
1480     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1481
1482     return 0;
1483 }
1484 #endif
1485
1486 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1487 {
1488     if (run->if_flag)
1489         env->eflags |= IF_MASK;
1490     else
1491         env->eflags &= ~IF_MASK;
1492
1493     cpu_set_apic_tpr(env->apic_state, run->cr8);
1494     cpu_set_apic_base(env->apic_state, run->apic_base);
1495
1496     return 0;
1497 }
1498
1499 #ifdef OBSOLETE_KVM_IMPL
1500
1501 int kvm_arch_process_irqchip_events(CPUState *env)
1502 {
1503     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1504         kvm_cpu_synchronize_state(env);
1505         do_cpu_init(env);
1506         env->exception_index = EXCP_HALTED;
1507     }
1508
1509     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1510         kvm_cpu_synchronize_state(env);
1511         do_cpu_sipi(env);
1512     }
1513
1514     return env->halted;
1515 }
1516
1517 static int kvm_handle_halt(CPUState *env)
1518 {
1519     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1520           (env->eflags & IF_MASK)) &&
1521         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1522         env->halted = 1;
1523         env->exception_index = EXCP_HLT;
1524         return 0;
1525     }
1526
1527     return 1;
1528 }
1529
1530 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1531 {
1532     int ret = 0;
1533
1534     switch (run->exit_reason) {
1535     case KVM_EXIT_HLT:
1536         DPRINTF("handle_hlt\n");
1537         ret = kvm_handle_halt(env);
1538         break;
1539     }
1540
1541     return ret;
1542 }
1543 #endif
1544
1545 #ifdef KVM_CAP_SET_GUEST_DEBUG
1546 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1547 {
1548     static const uint8_t int3 = 0xcc;
1549
1550     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1551         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1552         return -EINVAL;
1553     return 0;
1554 }
1555
1556 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1557 {
1558     uint8_t int3;
1559
1560     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1561         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1562         return -EINVAL;
1563     return 0;
1564 }
1565
1566 static struct {
1567     target_ulong addr;
1568     int len;
1569     int type;
1570 } hw_breakpoint[4];
1571
1572 static int nb_hw_breakpoint;
1573
1574 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1575 {
1576     int n;
1577
1578     for (n = 0; n < nb_hw_breakpoint; n++)
1579         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1580             (hw_breakpoint[n].len == len || len == -1))
1581             return n;
1582     return -1;
1583 }
1584
1585 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1586                                   target_ulong len, int type)
1587 {
1588     switch (type) {
1589     case GDB_BREAKPOINT_HW:
1590         len = 1;
1591         break;
1592     case GDB_WATCHPOINT_WRITE:
1593     case GDB_WATCHPOINT_ACCESS:
1594         switch (len) {
1595         case 1:
1596             break;
1597         case 2:
1598         case 4:
1599         case 8:
1600             if (addr & (len - 1))
1601                 return -EINVAL;
1602             break;
1603         default:
1604             return -EINVAL;
1605         }
1606         break;
1607     default:
1608         return -ENOSYS;
1609     }
1610
1611     if (nb_hw_breakpoint == 4)
1612         return -ENOBUFS;
1613
1614     if (find_hw_breakpoint(addr, len, type) >= 0)
1615         return -EEXIST;
1616
1617     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1618     hw_breakpoint[nb_hw_breakpoint].len = len;
1619     hw_breakpoint[nb_hw_breakpoint].type = type;
1620     nb_hw_breakpoint++;
1621
1622     return 0;
1623 }
1624
1625 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1626                                   target_ulong len, int type)
1627 {
1628     int n;
1629
1630     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1631     if (n < 0)
1632         return -ENOENT;
1633
1634     nb_hw_breakpoint--;
1635     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1636
1637     return 0;
1638 }
1639
1640 void kvm_arch_remove_all_hw_breakpoints(void)
1641 {
1642     nb_hw_breakpoint = 0;
1643 }
1644
1645 static CPUWatchpoint hw_watchpoint;
1646
1647 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1648 {
1649     int handle = 0;
1650     int n;
1651
1652     if (arch_info->exception == 1) {
1653         if (arch_info->dr6 & (1 << 14)) {
1654             if (cpu_single_env->singlestep_enabled)
1655                 handle = 1;
1656         } else {
1657             for (n = 0; n < 4; n++)
1658                 if (arch_info->dr6 & (1 << n))
1659                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1660                     case 0x0:
1661                         handle = 1;
1662                         break;
1663                     case 0x1:
1664                         handle = 1;
1665                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1666                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1667                         hw_watchpoint.flags = BP_MEM_WRITE;
1668                         break;
1669                     case 0x3:
1670                         handle = 1;
1671                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1672                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1673                         hw_watchpoint.flags = BP_MEM_ACCESS;
1674                         break;
1675                     }
1676         }
1677     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1678         handle = 1;
1679
1680     if (!handle) {
1681         cpu_synchronize_state(cpu_single_env);
1682         assert(cpu_single_env->exception_injected == -1);
1683
1684         cpu_single_env->exception_injected = arch_info->exception;
1685         cpu_single_env->has_error_code = 0;
1686     }
1687
1688     return handle;
1689 }
1690
1691 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1692 {
1693     const uint8_t type_code[] = {
1694         [GDB_BREAKPOINT_HW] = 0x0,
1695         [GDB_WATCHPOINT_WRITE] = 0x1,
1696         [GDB_WATCHPOINT_ACCESS] = 0x3
1697     };
1698     const uint8_t len_code[] = {
1699         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1700     };
1701     int n;
1702
1703     if (kvm_sw_breakpoints_active(env))
1704         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1705
1706     if (nb_hw_breakpoint > 0) {
1707         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1708         dbg->arch.debugreg[7] = 0x0600;
1709         for (n = 0; n < nb_hw_breakpoint; n++) {
1710             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1711             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1712                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1713                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1714         }
1715     }
1716     /* Legal xcr0 for loading */
1717     env->xcr0 = 1;
1718 }
1719 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1720
1721 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1722 {
1723       return !(env->cr[0] & CR0_PE_MASK) ||
1724               ((env->segs[R_CS].selector  & 3) != 3);
1725 }
1726
1727 static void hardware_memory_error(void)
1728 {
1729     fprintf(stderr, "Hardware memory error!\n");
1730     exit(1);
1731 }
1732
1733 #ifdef KVM_CAP_MCE
1734 static void kvm_mce_broadcast_rest(CPUState *env)
1735 {
1736     CPUState *cenv;
1737     int family, model, cpuver = env->cpuid_version;
1738
1739     family = (cpuver >> 8) & 0xf;
1740     model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0xf);
1741
1742     /* Broadcast MCA signal for processor version 06H_EH and above */
1743     if ((family == 6 && model >= 14) || family > 6) {
1744         for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1745             if (cenv == env) {
1746                 continue;
1747             }
1748             kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC,
1749                                MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1);
1750         }
1751     }
1752 }
1753 #endif
1754
1755 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1756 {
1757 #if defined(KVM_CAP_MCE)
1758     struct kvm_x86_mce mce = {
1759             .bank = 9,
1760     };
1761     void *vaddr;
1762     ram_addr_t ram_addr;
1763     target_phys_addr_t paddr;
1764     int r;
1765
1766     if ((env->mcg_cap & MCG_SER_P) && addr
1767         && (code == BUS_MCEERR_AR
1768             || code == BUS_MCEERR_AO)) {
1769         if (code == BUS_MCEERR_AR) {
1770             /* Fake an Intel architectural Data Load SRAR UCR */
1771             mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1772                 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1773                 | MCI_STATUS_AR | 0x134;
1774             mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1775             mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
1776         } else {
1777             /*
1778              * If there is an MCE excpetion being processed, ignore
1779              * this SRAO MCE
1780              */
1781             r = kvm_mce_in_exception(env);
1782             if (r == -1) {
1783                 fprintf(stderr, "Failed to get MCE status\n");
1784             } else if (r) {
1785                 return 0;
1786             }
1787             /* Fake an Intel architectural Memory scrubbing UCR */
1788             mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1789                 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1790                 | 0xc0;
1791             mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1792             mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
1793         }
1794         vaddr = (void *)addr;
1795         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1796             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1797             fprintf(stderr, "Hardware memory error for memory used by "
1798                     "QEMU itself instead of guest system!\n");
1799             /* Hope we are lucky for AO MCE */
1800             if (code == BUS_MCEERR_AO) {
1801                 return 0;
1802             } else {
1803                 hardware_memory_error();
1804             }
1805         }
1806         mce.addr = paddr;
1807         r = kvm_set_mce(env, &mce);
1808         if (r < 0) {
1809             fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1810             abort();
1811         }
1812         kvm_mce_broadcast_rest(env);
1813     } else
1814 #endif
1815     {
1816         if (code == BUS_MCEERR_AO) {
1817             return 0;
1818         } else if (code == BUS_MCEERR_AR) {
1819             hardware_memory_error();
1820         } else {
1821             return 1;
1822         }
1823     }
1824     return 0;
1825 }
1826
1827 int kvm_on_sigbus(int code, void *addr)
1828 {
1829 #if defined(KVM_CAP_MCE)
1830     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1831         uint64_t status;
1832         void *vaddr;
1833         ram_addr_t ram_addr;
1834         target_phys_addr_t paddr;
1835
1836         /* Hope we are lucky for AO MCE */
1837         vaddr = addr;
1838         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1839             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1840             fprintf(stderr, "Hardware memory error for memory used by "
1841                     "QEMU itself instead of guest system!: %p\n", addr);
1842             return 0;
1843         }
1844         status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1845             | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1846             | 0xc0;
1847         kvm_inject_x86_mce(first_cpu, 9, status,
1848                            MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr,
1849                            (MCM_ADDR_PHYS << 6) | 0xc, 1);
1850         kvm_mce_broadcast_rest(first_cpu);
1851     } else
1852 #endif
1853     {
1854         if (code == BUS_MCEERR_AO) {
1855             return 0;
1856         } else if (code == BUS_MCEERR_AR) {
1857             hardware_memory_error();
1858         } else {
1859             return 1;
1860         }
1861     }
1862     return 0;
1863 }
1864
1865 #include "qemu-kvm-x86.c"