target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "ioport.h"
  29
  30 #ifdef CONFIG_KVM_PARA
  31 #include <linux/kvm_para.h>
  32 #endif
  33 //
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifdef KVM_CAP_EXT_CPUID
  48
  49 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  50 {
  51     struct kvm_cpuid2 *cpuid;
  52     int r, size;
  53
  54     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  55     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  56     cpuid->nent = max;
  57     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  58     if (r == 0 && cpuid->nent >= max) {
  59         r = -E2BIG;
  60     }
  61     if (r < 0) {
  62         if (r == -E2BIG) {
  63             qemu_free(cpuid);
  64             return NULL;
  65         } else {
  66             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  67                     strerror(-r));
  68             exit(1);
  69         }
  70     }
  71     return cpuid;
  72 }
  73
  74 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  75                                       uint32_t index, int reg)
  76 {
  77     struct kvm_cpuid2 *cpuid;
  78     int i, max;
  79     uint32_t ret = 0;
  80     uint32_t cpuid_1_edx;
  81
  82     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  83         return -1U;
  84     }
  85
  86     max = 1;
  87     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  88         max *= 2;
  89     }
  90
  91     for (i = 0; i < cpuid->nent; ++i) {
  92         if (cpuid->entries[i].function == function &&
  93             cpuid->entries[i].index == index) {
  94             switch (reg) {
  95             case R_EAX:
  96                 ret = cpuid->entries[i].eax;
  97                 break;
  98             case R_EBX:
  99                 ret = cpuid->entries[i].ebx;
 100                 break;
 101             case R_ECX:
 102                 ret = cpuid->entries[i].ecx;
 103                 break;
 104             case R_EDX:
 105                 ret = cpuid->entries[i].edx;
 106                 switch (function) {
 107                 case 1:
 108                     /* KVM before 2.6.30 misreports the following features */
 109                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 110                     break;
 111                 case 0x80000001:
 112                     /* On Intel, kvm returns cpuid according to the Intel spec,
 113                      * so add missing bits according to the AMD spec:
 114                      */
 115                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 116                     ret |= cpuid_1_edx & 0x183f7ff;
 117                     break;
 118                 }
 119                 break;
 120             }
 121         }
 122     }
 123
 124     qemu_free(cpuid);
 125
 126     return ret;
 127 }
 128
 129 #else
 130
 131 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 132                                       uint32_t index, int reg)
 133 {
 134     return -1U;
 135 }
 136
 137 #endif
 138
 139 #ifdef CONFIG_KVM_PARA
 140 struct kvm_para_features {
 141         int cap;
 142         int feature;
 143 } para_features[] = {
 144 #ifdef KVM_CAP_CLOCKSOURCE
 145         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 146 #endif
 147 #ifdef KVM_CAP_NOP_IO_DELAY
 148         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 149 #endif
 150 #ifdef KVM_CAP_PV_MMU
 151         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 152 #endif
 153         { -1, -1 }
 154 };
 155
 156 static int get_para_features(CPUState *env)
 157 {
 158         int i, features = 0;
 159
 160         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 161                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 162                         features |= (1 << para_features[i].feature);
 163         }
 164
 165         return features;
 166 }
 167 #endif
 168
 169 static int _kvm_arch_init_vcpu(CPUState *env);
 170
 171 int kvm_arch_init_vcpu(CPUState *env)
 172 {
 173     int r;
 174     struct {
 175         struct kvm_cpuid2 cpuid;
 176         struct kvm_cpuid_entry2 entries[100];
 177     } __attribute__((packed)) cpuid_data;
 178     uint32_t limit, i, j, cpuid_i;
 179     uint32_t unused;
 180     struct kvm_cpuid_entry2 *c;
 181 #ifdef KVM_CPUID_SIGNATURE
 182     uint32_t signature[3];
 183 #endif
 184
 185     r = _kvm_arch_init_vcpu(env);
 186     if (r < 0) {
 187         return r;
 188     }
 189
 190 #ifdef KVM_UPSTREAM
 191
 192     env->mp_state = KVM_MP_STATE_RUNNABLE;
 193
 194 #endif
 195
 196     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 197
 198     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 199     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 200     env->cpuid_ext_features |= i;
 201
 202     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 203                                                              0, R_EDX);
 204     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 205                                                              0, R_ECX);
 206
 207     cpuid_i = 0;
 208
 209 #ifdef CONFIG_KVM_PARA
 210     /* Paravirtualization CPUIDs */
 211     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 212     c = &cpuid_data.entries[cpuid_i++];
 213     memset(c, 0, sizeof(*c));
 214     c->function = KVM_CPUID_SIGNATURE;
 215     c->eax = 0;
 216     c->ebx = signature[0];
 217     c->ecx = signature[1];
 218     c->edx = signature[2];
 219
 220     c = &cpuid_data.entries[cpuid_i++];
 221     memset(c, 0, sizeof(*c));
 222     c->function = KVM_CPUID_FEATURES;
 223     c->eax = env->cpuid_kvm_features & get_para_features(env);
 224 #endif
 225
 226     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 227
 228     for (i = 0; i <= limit; i++) {
 229         c = &cpuid_data.entries[cpuid_i++];
 230
 231         switch (i) {
 232         case 2: {
 233             /* Keep reading function 2 till all the input is received */
 234             int times;
 235
 236             c->function = i;
 237             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 238                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 239             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 240             times = c->eax & 0xff;
 241
 242             for (j = 1; j < times; ++j) {
 243                 c = &cpuid_data.entries[cpuid_i++];
 244                 c->function = i;
 245                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 246                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 247             }
 248             break;
 249         }
 250         case 4:
 251         case 0xb:
 252         case 0xd:
 253             for (j = 0; ; j++) {
 254                 c->function = i;
 255                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 256                 c->index = j;
 257                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 258
 259                 if (i == 4 && c->eax == 0)
 260                     break;
 261                 if (i == 0xb && !(c->ecx & 0xff00))
 262                     break;
 263                 if (i == 0xd && c->eax == 0)
 264                     break;
 265
 266                 c = &cpuid_data.entries[cpuid_i++];
 267             }
 268             break;
 269         default:
 270             c->function = i;
 271             c->flags = 0;
 272             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 273             break;
 274         }
 275     }
 276     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 277
 278     for (i = 0x80000000; i <= limit; i++) {
 279         c = &cpuid_data.entries[cpuid_i++];
 280
 281         c->function = i;
 282         c->flags = 0;
 283         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 284     }
 285
 286     cpuid_data.cpuid.nent = cpuid_i;
 287
 288     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 289 }
 290
 291 void kvm_arch_reset_vcpu(CPUState *env)
 292 {
 293     env->exception_injected = -1;
 294     env->interrupt_injected = -1;
 295     env->nmi_injected = 0;
 296     env->nmi_pending = 0;
 297     /* Legal xcr0 for loading */
 298     env->xcr0 = 1;
 299     if (kvm_irqchip_in_kernel()) {
 300         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 301                                           KVM_MP_STATE_UNINITIALIZED;
 302     } else {
 303         env->mp_state = KVM_MP_STATE_RUNNABLE;
 304     }
 305 }
 306 #ifdef KVM_UPSTREAM
 307
 308 static int kvm_has_msr_star(CPUState *env)
 309 {
 310     static int has_msr_star;
 311     int ret;
 312
 313     /* first time */
 314     if (has_msr_star == 0) {
 315         struct kvm_msr_list msr_list, *kvm_msr_list;
 316
 317         has_msr_star = -1;
 318
 319         /* Obtain MSR list from KVM.  These are the MSRs that we must
 320          * save/restore */
 321         msr_list.nmsrs = 0;
 322         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 323         if (ret < 0 && ret != -E2BIG) {
 324             return 0;
 325         }
 326         /* Old kernel modules had a bug and could write beyond the provided
 327            memory. Allocate at least a safe amount of 1K. */
 328         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 329                                               msr_list.nmsrs *
 330                                               sizeof(msr_list.indices[0])));
 331
 332         kvm_msr_list->nmsrs = msr_list.nmsrs;
 333         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 334         if (ret >= 0) {
 335             int i;
 336
 337             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 338                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 339                     has_msr_star = 1;
 340                     break;
 341                 }
 342             }
 343         }
 344
 345         free(kvm_msr_list);
 346     }
 347
 348     if (has_msr_star == 1)
 349         return 1;
 350     return 0;
 351 }
 352
 353 static int kvm_init_identity_map_page(KVMState *s)
 354 {
 355 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 356     int ret;
 357     uint64_t addr = 0xfffbc000;
 358
 359     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 360         return 0;
 361     }
 362
 363     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 364     if (ret < 0) {
 365         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 366         return ret;
 367     }
 368 #endif
 369     return 0;
 370 }
 371
 372 int kvm_arch_init(KVMState *s, int smp_cpus)
 373 {
 374     int ret;
 375
 376     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 377      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 378      * must be part of guest physical memory, we need to allocate it.  Older
 379      * versions of KVM just assumed that it would be at the end of physical
 380      * memory but that doesn't work with more than 4GB of memory.  We simply
 381      * refuse to work with those older versions of KVM. */
 382     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 383     if (ret <= 0) {
 384         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 385         return ret;
 386     }
 387
 388     /* this address is 3 pages before the bios, and the bios should present
 389      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 390      * this?
 391      */
 392     /*
 393      * Tell fw_cfg to notify the BIOS to reserve the range.
 394      */
 395     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 396         perror("e820_add_entry() table is full");
 397         exit(1);
 398     }
 399     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 400     if (ret < 0) {
 401         return ret;
 402     }
 403
 404     return kvm_init_identity_map_page(s);
 405 }
 406
 407 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 408 {
 409     lhs->selector = rhs->selector;
 410     lhs->base = rhs->base;
 411     lhs->limit = rhs->limit;
 412     lhs->type = 3;
 413     lhs->present = 1;
 414     lhs->dpl = 3;
 415     lhs->db = 0;
 416     lhs->s = 1;
 417     lhs->l = 0;
 418     lhs->g = 0;
 419     lhs->avl = 0;
 420     lhs->unusable = 0;
 421 }
 422
 423 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 424 {
 425     unsigned flags = rhs->flags;
 426     lhs->selector = rhs->selector;
 427     lhs->base = rhs->base;
 428     lhs->limit = rhs->limit;
 429     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 430     lhs->present = (flags & DESC_P_MASK) != 0;
 431     lhs->dpl = rhs->selector & 3;
 432     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 433     lhs->s = (flags & DESC_S_MASK) != 0;
 434     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 435     lhs->g = (flags & DESC_G_MASK) != 0;
 436     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 437     lhs->unusable = 0;
 438 }
 439
 440 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 441 {
 442     lhs->selector = rhs->selector;
 443     lhs->base = rhs->base;
 444     lhs->limit = rhs->limit;
 445     lhs->flags =
 446         (rhs->type << DESC_TYPE_SHIFT)
 447         | (rhs->present * DESC_P_MASK)
 448         | (rhs->dpl << DESC_DPL_SHIFT)
 449         | (rhs->db << DESC_B_SHIFT)
 450         | (rhs->s * DESC_S_MASK)
 451         | (rhs->l << DESC_L_SHIFT)
 452         | (rhs->g * DESC_G_MASK)
 453         | (rhs->avl * DESC_AVL_MASK);
 454 }
 455
 456 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 457 {
 458     if (set)
 459         *kvm_reg = *qemu_reg;
 460     else
 461         *qemu_reg = *kvm_reg;
 462 }
 463
 464 static int kvm_getput_regs(CPUState *env, int set)
 465 {
 466     struct kvm_regs regs;
 467     int ret = 0;
 468
 469     if (!set) {
 470         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 471         if (ret < 0)
 472             return ret;
 473     }
 474
 475     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 476     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 477     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 478     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 479     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 480     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 481     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 482     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 483 #ifdef TARGET_X86_64
 484     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 485     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 486     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 487     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 488     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 489     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 490     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 491     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 492 #endif
 493
 494     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 495     kvm_getput_reg(&regs.rip, &env->eip, set);
 496
 497     if (set)
 498         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 499
 500     return ret;
 501 }
 502
 503 static int kvm_put_fpu(CPUState *env)
 504 {
 505     struct kvm_fpu fpu;
 506     int i;
 507
 508     memset(&fpu, 0, sizeof fpu);
 509     fpu.fsw = env->fpus & ~(7 << 11);
 510     fpu.fsw |= (env->fpstt & 7) << 11;
 511     fpu.fcw = env->fpuc;
 512     for (i = 0; i < 8; ++i)
 513         fpu.ftwx |= (!env->fptags[i]) << i;
 514     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 515     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 516     fpu.mxcsr = env->mxcsr;
 517
 518     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 519 }
 520
 521 #ifdef KVM_CAP_XSAVE
 522 #define XSAVE_CWD_RIP     2
 523 #define XSAVE_CWD_RDP     4
 524 #define XSAVE_MXCSR       6
 525 #define XSAVE_ST_SPACE    8
 526 #define XSAVE_XMM_SPACE   40
 527 #define XSAVE_XSTATE_BV   128
 528 #define XSAVE_YMMH_SPACE  144
 529 #endif
 530
 531 static int kvm_put_xsave(CPUState *env)
 532 {
 533 #ifdef KVM_CAP_XSAVE
 534     int i;
 535     struct kvm_xsave* xsave;
 536     uint16_t cwd, swd, twd, fop;
 537
 538     if (!kvm_has_xsave())
 539         return kvm_put_fpu(env);
 540
 541     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 542     memset(xsave, 0, sizeof(struct kvm_xsave));
 543     cwd = swd = twd = fop = 0;
 544     swd = env->fpus & ~(7 << 11);
 545     swd |= (env->fpstt & 7) << 11;
 546     cwd = env->fpuc;
 547     for (i = 0; i < 8; ++i)
 548         twd |= (!env->fptags[i]) << i;
 549     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 550     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 551     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 552             sizeof env->fpregs);
 553     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 554             sizeof env->xmm_regs);
 555     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 556     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 557     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 558             sizeof env->ymmh_regs);
 559     return kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 560 #else
 561     return kvm_put_fpu(env);
 562 #endif
 563 }
 564
 565 static int kvm_put_xcrs(CPUState *env)
 566 {
 567 #ifdef KVM_CAP_XCRS
 568     struct kvm_xcrs xcrs;
 569
 570     if (!kvm_has_xcrs())
 571         return 0;
 572
 573     xcrs.nr_xcrs = 1;
 574     xcrs.flags = 0;
 575     xcrs.xcrs[0].xcr = 0;
 576     xcrs.xcrs[0].value = env->xcr0;
 577     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 578 #else
 579     return 0;
 580 #endif
 581 }
 582
 583 static int kvm_put_sregs(CPUState *env)
 584 {
 585     struct kvm_sregs sregs;
 586
 587     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 588     if (env->interrupt_injected >= 0) {
 589         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 590                 (uint64_t)1 << (env->interrupt_injected % 64);
 591     }
 592
 593     if ((env->eflags & VM_MASK)) {
 594             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 595             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 596             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 597             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 598             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 599             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 600     } else {
 601             set_seg(&sregs.cs, &env->segs[R_CS]);
 602             set_seg(&sregs.ds, &env->segs[R_DS]);
 603             set_seg(&sregs.es, &env->segs[R_ES]);
 604             set_seg(&sregs.fs, &env->segs[R_FS]);
 605             set_seg(&sregs.gs, &env->segs[R_GS]);
 606             set_seg(&sregs.ss, &env->segs[R_SS]);
 607
 608             if (env->cr[0] & CR0_PE_MASK) {
 609                 /* force ss cpl to cs cpl */
 610                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 611                         (sregs.cs.selector & 3);
 612                 sregs.ss.dpl = sregs.ss.selector & 3;
 613             }
 614     }
 615
 616     set_seg(&sregs.tr, &env->tr);
 617     set_seg(&sregs.ldt, &env->ldt);
 618
 619     sregs.idt.limit = env->idt.limit;
 620     sregs.idt.base = env->idt.base;
 621     sregs.gdt.limit = env->gdt.limit;
 622     sregs.gdt.base = env->gdt.base;
 623
 624     sregs.cr0 = env->cr[0];
 625     sregs.cr2 = env->cr[2];
 626     sregs.cr3 = env->cr[3];
 627     sregs.cr4 = env->cr[4];
 628
 629     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 630     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 631
 632     sregs.efer = env->efer;
 633
 634     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 635 }
 636
 637 #endif
 638
 639 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 640                               uint32_t index, uint64_t value)
 641 {
 642     entry->index = index;
 643     entry->data = value;
 644 }
 645
 646 #ifdef KVM_UPSTREAM
 647 static int kvm_put_msrs(CPUState *env, int level)
 648 {
 649     struct {
 650         struct kvm_msrs info;
 651         struct kvm_msr_entry entries[100];
 652     } msr_data;
 653     struct kvm_msr_entry *msrs = msr_data.entries;
 654     int n = 0;
 655
 656     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 657     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 658     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 659     if (kvm_has_msr_star(env))
 660         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 661     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 662 #ifdef TARGET_X86_64
 663     /* FIXME if lm capable */
 664     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 665     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 666     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 667     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 668 #endif
 669     if (level == KVM_PUT_FULL_STATE) {
 670         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 671         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 672                           env->system_time_msr);
 673         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 674     }
 675
 676     msr_data.info.nmsrs = n;
 677
 678     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 679
 680 }
 681
 682
 683 static int kvm_get_fpu(CPUState *env)
 684 {
 685     struct kvm_fpu fpu;
 686     int i, ret;
 687
 688     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 689     if (ret < 0)
 690         return ret;
 691
 692     env->fpstt = (fpu.fsw >> 11) & 7;
 693     env->fpus = fpu.fsw;
 694     env->fpuc = fpu.fcw;
 695     for (i = 0; i < 8; ++i)
 696         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 697     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 698     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 699     env->mxcsr = fpu.mxcsr;
 700
 701     return 0;
 702 }
 703
 704 static int kvm_get_xsave(CPUState *env)
 705 {
 706 #ifdef KVM_CAP_XSAVE
 707     struct kvm_xsave* xsave;
 708     int ret, i;
 709     uint16_t cwd, swd, twd, fop;
 710
 711     if (!kvm_has_xsave())
 712         return kvm_get_fpu(env);
 713
 714     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 715     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 716     if (ret < 0)
 717         return ret;
 718
 719     cwd = (uint16_t)xsave->region[0];
 720     swd = (uint16_t)(xsave->region[0] >> 16);
 721     twd = (uint16_t)xsave->region[1];
 722     fop = (uint16_t)(xsave->region[1] >> 16);
 723     env->fpstt = (swd >> 11) & 7;
 724     env->fpus = swd;
 725     env->fpuc = cwd;
 726     for (i = 0; i < 8; ++i)
 727         env->fptags[i] = !((twd >> i) & 1);
 728     env->mxcsr = xsave->region[XSAVE_MXCSR];
 729     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 730             sizeof env->fpregs);
 731     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 732             sizeof env->xmm_regs);
 733     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 734     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 735             sizeof env->ymmh_regs);
 736     return 0;
 737 #else
 738     return kvm_get_fpu(env);
 739 #endif
 740 }
 741
 742 static int kvm_get_xcrs(CPUState *env)
 743 {
 744 #ifdef KVM_CAP_XCRS
 745     int i, ret;
 746     struct kvm_xcrs xcrs;
 747
 748     if (!kvm_has_xcrs())
 749         return 0;
 750
 751     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 752     if (ret < 0)
 753         return ret;
 754
 755     for (i = 0; i < xcrs.nr_xcrs; i++)
 756         /* Only support xcr0 now */
 757         if (xcrs.xcrs[0].xcr == 0) {
 758             env->xcr0 = xcrs.xcrs[0].value;
 759             break;
 760         }
 761     return 0;
 762 #else
 763     return 0;
 764 #endif
 765 }
 766
 767 static int kvm_get_sregs(CPUState *env)
 768 {
 769     struct kvm_sregs sregs;
 770     uint32_t hflags;
 771     int bit, i, ret;
 772
 773     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 774     if (ret < 0)
 775         return ret;
 776
 777     /* There can only be one pending IRQ set in the bitmap at a time, so try
 778        to find it and save its number instead (-1 for none). */
 779     env->interrupt_injected = -1;
 780     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 781         if (sregs.interrupt_bitmap[i]) {
 782             bit = ctz64(sregs.interrupt_bitmap[i]);
 783             env->interrupt_injected = i * 64 + bit;
 784             break;
 785         }
 786     }
 787
 788     get_seg(&env->segs[R_CS], &sregs.cs);
 789     get_seg(&env->segs[R_DS], &sregs.ds);
 790     get_seg(&env->segs[R_ES], &sregs.es);
 791     get_seg(&env->segs[R_FS], &sregs.fs);
 792     get_seg(&env->segs[R_GS], &sregs.gs);
 793     get_seg(&env->segs[R_SS], &sregs.ss);
 794
 795     get_seg(&env->tr, &sregs.tr);
 796     get_seg(&env->ldt, &sregs.ldt);
 797
 798     env->idt.limit = sregs.idt.limit;
 799     env->idt.base = sregs.idt.base;
 800     env->gdt.limit = sregs.gdt.limit;
 801     env->gdt.base = sregs.gdt.base;
 802
 803     env->cr[0] = sregs.cr0;
 804     env->cr[2] = sregs.cr2;
 805     env->cr[3] = sregs.cr3;
 806     env->cr[4] = sregs.cr4;
 807
 808     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 809
 810     env->efer = sregs.efer;
 811     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 812
 813 #define HFLAG_COPY_MASK ~( \
 814                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 815                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 816                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 817                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 818
 819
 820
 821     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 822     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 823     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 824             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 825     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 826     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 827             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 828
 829     if (env->efer & MSR_EFER_LMA) {
 830         hflags |= HF_LMA_MASK;
 831     }
 832
 833     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 834         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 835     } else {
 836         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 837                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 838         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 839                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 840         if (!(env->cr[0] & CR0_PE_MASK) ||
 841                    (env->eflags & VM_MASK) ||
 842                    !(hflags & HF_CS32_MASK)) {
 843                 hflags |= HF_ADDSEG_MASK;
 844             } else {
 845                 hflags |= ((env->segs[R_DS].base |
 846                                 env->segs[R_ES].base |
 847                                 env->segs[R_SS].base) != 0) <<
 848                     HF_ADDSEG_SHIFT;
 849             }
 850     }
 851     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 852
 853     return 0;
 854 }
 855
 856 static int kvm_get_msrs(CPUState *env)
 857 {
 858     struct {
 859         struct kvm_msrs info;
 860         struct kvm_msr_entry entries[100];
 861     } msr_data;
 862     struct kvm_msr_entry *msrs = msr_data.entries;
 863     int ret, i, n;
 864
 865     n = 0;
 866     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 867     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 868     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 869     if (kvm_has_msr_star(env))
 870         msrs[n++].index = MSR_STAR;
 871     msrs[n++].index = MSR_IA32_TSC;
 872     msrs[n++].index = MSR_VM_HSAVE_PA;
 873 #ifdef TARGET_X86_64
 874     /* FIXME lm_capable_kernel */
 875     msrs[n++].index = MSR_CSTAR;
 876     msrs[n++].index = MSR_KERNELGSBASE;
 877     msrs[n++].index = MSR_FMASK;
 878     msrs[n++].index = MSR_LSTAR;
 879 #endif
 880     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 881     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 882
 883     msr_data.info.nmsrs = n;
 884     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 885     if (ret < 0)
 886         return ret;
 887
 888     for (i = 0; i < ret; i++) {
 889         switch (msrs[i].index) {
 890         case MSR_IA32_SYSENTER_CS:
 891             env->sysenter_cs = msrs[i].data;
 892             break;
 893         case MSR_IA32_SYSENTER_ESP:
 894             env->sysenter_esp = msrs[i].data;
 895             break;
 896         case MSR_IA32_SYSENTER_EIP:
 897             env->sysenter_eip = msrs[i].data;
 898             break;
 899         case MSR_STAR:
 900             env->star = msrs[i].data;
 901             break;
 902 #ifdef TARGET_X86_64
 903         case MSR_CSTAR:
 904             env->cstar = msrs[i].data;
 905             break;
 906         case MSR_KERNELGSBASE:
 907             env->kernelgsbase = msrs[i].data;
 908             break;
 909         case MSR_FMASK:
 910             env->fmask = msrs[i].data;
 911             break;
 912         case MSR_LSTAR:
 913             env->lstar = msrs[i].data;
 914             break;
 915 #endif
 916         case MSR_IA32_TSC:
 917             env->tsc = msrs[i].data;
 918             break;
 919         case MSR_KVM_SYSTEM_TIME:
 920             env->system_time_msr = msrs[i].data;
 921             break;
 922         case MSR_KVM_WALL_CLOCK:
 923             env->wall_clock_msr = msrs[i].data;
 924             break;
 925         case MSR_VM_HSAVE_PA:
 926             env->vm_hsave = msrs[i].data;
 927             break;
 928         }
 929     }
 930
 931     return 0;
 932 }
 933
 934 static int kvm_put_mp_state(CPUState *env)
 935 {
 936     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 937
 938     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 939 }
 940
 941 static int kvm_get_mp_state(CPUState *env)
 942 {
 943     struct kvm_mp_state mp_state;
 944     int ret;
 945
 946     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 947     if (ret < 0) {
 948         return ret;
 949     }
 950     env->mp_state = mp_state.mp_state;
 951     return 0;
 952 }
 953 #endif
 954
 955 static int kvm_put_vcpu_events(CPUState *env, int level)
 956 {
 957 #ifdef KVM_CAP_VCPU_EVENTS
 958     struct kvm_vcpu_events events;
 959
 960     if (!kvm_has_vcpu_events()) {
 961         return 0;
 962     }
 963
 964     events.exception.injected = (env->exception_injected >= 0);
 965     events.exception.nr = env->exception_injected;
 966     events.exception.has_error_code = env->has_error_code;
 967     events.exception.error_code = env->error_code;
 968
 969     events.interrupt.injected = (env->interrupt_injected >= 0);
 970     events.interrupt.nr = env->interrupt_injected;
 971     events.interrupt.soft = env->soft_interrupt;
 972
 973     events.nmi.injected = env->nmi_injected;
 974     events.nmi.pending = env->nmi_pending;
 975     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 976
 977     events.sipi_vector = env->sipi_vector;
 978
 979     events.flags = 0;
 980     if (level >= KVM_PUT_RESET_STATE) {
 981         events.flags |=
 982             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 983     }
 984
 985     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 986 #else
 987     return 0;
 988 #endif
 989 }
 990
 991 static int kvm_get_vcpu_events(CPUState *env)
 992 {
 993 #ifdef KVM_CAP_VCPU_EVENTS
 994     struct kvm_vcpu_events events;
 995     int ret;
 996
 997     if (!kvm_has_vcpu_events()) {
 998         return 0;
 999     }
1000
1001     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1002     if (ret < 0) {
1003        return ret;
1004     }
1005     env->exception_injected =
1006        events.exception.injected ? events.exception.nr : -1;
1007     env->has_error_code = events.exception.has_error_code;
1008     env->error_code = events.exception.error_code;
1009
1010     env->interrupt_injected =
1011         events.interrupt.injected ? events.interrupt.nr : -1;
1012     env->soft_interrupt = events.interrupt.soft;
1013
1014     env->nmi_injected = events.nmi.injected;
1015     env->nmi_pending = events.nmi.pending;
1016     if (events.nmi.masked) {
1017         env->hflags2 |= HF2_NMI_MASK;
1018     } else {
1019         env->hflags2 &= ~HF2_NMI_MASK;
1020     }
1021
1022     env->sipi_vector = events.sipi_vector;
1023 #endif
1024
1025     return 0;
1026 }
1027
1028 static int kvm_guest_debug_workarounds(CPUState *env)
1029 {
1030     int ret = 0;
1031 #ifdef KVM_CAP_SET_GUEST_DEBUG
1032     unsigned long reinject_trap = 0;
1033
1034     if (!kvm_has_vcpu_events()) {
1035         if (env->exception_injected == 1) {
1036             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1037         } else if (env->exception_injected == 3) {
1038             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1039         }
1040         env->exception_injected = -1;
1041     }
1042
1043     /*
1044      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1045      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1046      * by updating the debug state once again if single-stepping is on.
1047      * Another reason to call kvm_update_guest_debug here is a pending debug
1048      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1049      * reinject them via SET_GUEST_DEBUG.
1050      */
1051     if (reinject_trap ||
1052         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1053         ret = kvm_update_guest_debug(env, reinject_trap);
1054     }
1055 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1056     return ret;
1057 }
1058
1059 static int kvm_put_debugregs(CPUState *env)
1060 {
1061 #ifdef KVM_CAP_DEBUGREGS
1062     struct kvm_debugregs dbgregs;
1063     int i;
1064
1065     if (!kvm_has_debugregs()) {
1066         return 0;
1067     }
1068
1069     for (i = 0; i < 4; i++) {
1070         dbgregs.db[i] = env->dr[i];
1071     }
1072     dbgregs.dr6 = env->dr[6];
1073     dbgregs.dr7 = env->dr[7];
1074     dbgregs.flags = 0;
1075
1076     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1077 #else
1078     return 0;
1079 #endif
1080 }
1081
1082 static int kvm_get_debugregs(CPUState *env)
1083 {
1084 #ifdef KVM_CAP_DEBUGREGS
1085     struct kvm_debugregs dbgregs;
1086     int i, ret;
1087
1088     if (!kvm_has_debugregs()) {
1089         return 0;
1090     }
1091
1092     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1093     if (ret < 0) {
1094        return ret;
1095     }
1096     for (i = 0; i < 4; i++) {
1097         env->dr[i] = dbgregs.db[i];
1098     }
1099     env->dr[4] = env->dr[6] = dbgregs.dr6;
1100     env->dr[5] = env->dr[7] = dbgregs.dr7;
1101 #endif
1102
1103     return 0;
1104 }
1105
1106 #ifdef KVM_UPSTREAM
1107 int kvm_arch_put_registers(CPUState *env, int level)
1108 {
1109     int ret;
1110
1111     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1112
1113     ret = kvm_getput_regs(env, 1);
1114     if (ret < 0)
1115         return ret;
1116
1117     ret = kvm_put_xsave(env);
1118     if (ret < 0)
1119         return ret;
1120
1121     ret = kvm_put_xcrs(env);
1122     if (ret < 0)
1123         return ret;
1124
1125     ret = kvm_put_sregs(env);
1126     if (ret < 0)
1127         return ret;
1128
1129     ret = kvm_put_msrs(env, level);
1130     if (ret < 0)
1131         return ret;
1132
1133     if (level >= KVM_PUT_RESET_STATE) {
1134         ret = kvm_put_mp_state(env);
1135         if (ret < 0)
1136             return ret;
1137     }
1138
1139     ret = kvm_put_vcpu_events(env, level);
1140     if (ret < 0)
1141         return ret;
1142
1143     /* must be last */
1144     ret = kvm_guest_debug_workarounds(env);
1145     if (ret < 0)
1146         return ret;
1147
1148     ret = kvm_put_debugregs(env);
1149     if (ret < 0)
1150         return ret;
1151
1152     return 0;
1153 }
1154
1155 int kvm_arch_get_registers(CPUState *env)
1156 {
1157     int ret;
1158
1159     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1160
1161     ret = kvm_getput_regs(env, 0);
1162     if (ret < 0)
1163         return ret;
1164
1165     ret = kvm_get_xsave(env);
1166     if (ret < 0)
1167         return ret;
1168
1169     ret = kvm_get_xcrs(env);
1170     if (ret < 0)
1171         return ret;
1172
1173     ret = kvm_get_sregs(env);
1174     if (ret < 0)
1175         return ret;
1176
1177     ret = kvm_get_msrs(env);
1178     if (ret < 0)
1179         return ret;
1180
1181     ret = kvm_get_mp_state(env);
1182     if (ret < 0)
1183         return ret;
1184
1185     ret = kvm_get_vcpu_events(env);
1186     if (ret < 0)
1187         return ret;
1188
1189     ret = kvm_get_debugregs(env);
1190     if (ret < 0)
1191         return ret;
1192
1193     return 0;
1194 }
1195
1196 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1197 {
1198     /* Try to inject an interrupt if the guest can accept it */
1199     if (run->ready_for_interrupt_injection &&
1200         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1201         (env->eflags & IF_MASK)) {
1202         int irq;
1203
1204         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1205         irq = cpu_get_pic_interrupt(env);
1206         if (irq >= 0) {
1207             struct kvm_interrupt intr;
1208             intr.irq = irq;
1209             /* FIXME: errors */
1210             DPRINTF("injected interrupt %d\n", irq);
1211             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1212         }
1213     }
1214
1215     /* If we have an interrupt but the guest is not ready to receive an
1216      * interrupt, request an interrupt window exit.  This will
1217      * cause a return to userspace as soon as the guest is ready to
1218      * receive interrupts. */
1219     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1220         run->request_interrupt_window = 1;
1221     else
1222         run->request_interrupt_window = 0;
1223
1224     DPRINTF("setting tpr\n");
1225     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1226
1227     return 0;
1228 }
1229 #endif
1230
1231 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1232 {
1233     if (run->if_flag)
1234         env->eflags |= IF_MASK;
1235     else
1236         env->eflags &= ~IF_MASK;
1237
1238     cpu_set_apic_tpr(env->apic_state, run->cr8);
1239     cpu_set_apic_base(env->apic_state, run->apic_base);
1240
1241     return 0;
1242 }
1243
1244 #ifdef KVM_UPSTREAM
1245
1246 int kvm_arch_process_irqchip_events(CPUState *env)
1247 {
1248     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1249         kvm_cpu_synchronize_state(env);
1250         do_cpu_init(env);
1251         env->exception_index = EXCP_HALTED;
1252     }
1253
1254     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1255         kvm_cpu_synchronize_state(env);
1256         do_cpu_sipi(env);
1257     }
1258
1259     return env->halted;
1260 }
1261
1262 static int kvm_handle_halt(CPUState *env)
1263 {
1264     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1265           (env->eflags & IF_MASK)) &&
1266         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1267         env->halted = 1;
1268         env->exception_index = EXCP_HLT;
1269         return 0;
1270     }
1271
1272     return 1;
1273 }
1274
1275 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1276 {
1277     int ret = 0;
1278
1279     switch (run->exit_reason) {
1280     case KVM_EXIT_HLT:
1281         DPRINTF("handle_hlt\n");
1282         ret = kvm_handle_halt(env);
1283         break;
1284     }
1285
1286     return ret;
1287 }
1288 #endif
1289
1290 #ifdef KVM_CAP_SET_GUEST_DEBUG
1291 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1292 {
1293     static const uint8_t int3 = 0xcc;
1294
1295     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1296         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1297         return -EINVAL;
1298     return 0;
1299 }
1300
1301 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1302 {
1303     uint8_t int3;
1304
1305     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1306         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1307         return -EINVAL;
1308     return 0;
1309 }
1310
1311 static struct {
1312     target_ulong addr;
1313     int len;
1314     int type;
1315 } hw_breakpoint[4];
1316
1317 static int nb_hw_breakpoint;
1318
1319 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1320 {
1321     int n;
1322
1323     for (n = 0; n < nb_hw_breakpoint; n++)
1324         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1325             (hw_breakpoint[n].len == len || len == -1))
1326             return n;
1327     return -1;
1328 }
1329
1330 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1331                                   target_ulong len, int type)
1332 {
1333     switch (type) {
1334     case GDB_BREAKPOINT_HW:
1335         len = 1;
1336         break;
1337     case GDB_WATCHPOINT_WRITE:
1338     case GDB_WATCHPOINT_ACCESS:
1339         switch (len) {
1340         case 1:
1341             break;
1342         case 2:
1343         case 4:
1344         case 8:
1345             if (addr & (len - 1))
1346                 return -EINVAL;
1347             break;
1348         default:
1349             return -EINVAL;
1350         }
1351         break;
1352     default:
1353         return -ENOSYS;
1354     }
1355
1356     if (nb_hw_breakpoint == 4)
1357         return -ENOBUFS;
1358
1359     if (find_hw_breakpoint(addr, len, type) >= 0)
1360         return -EEXIST;
1361
1362     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1363     hw_breakpoint[nb_hw_breakpoint].len = len;
1364     hw_breakpoint[nb_hw_breakpoint].type = type;
1365     nb_hw_breakpoint++;
1366
1367     return 0;
1368 }
1369
1370 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1371                                   target_ulong len, int type)
1372 {
1373     int n;
1374
1375     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1376     if (n < 0)
1377         return -ENOENT;
1378
1379     nb_hw_breakpoint--;
1380     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1381
1382     return 0;
1383 }
1384
1385 void kvm_arch_remove_all_hw_breakpoints(void)
1386 {
1387     nb_hw_breakpoint = 0;
1388 }
1389
1390 static CPUWatchpoint hw_watchpoint;
1391
1392 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1393 {
1394     int handle = 0;
1395     int n;
1396
1397     if (arch_info->exception == 1) {
1398         if (arch_info->dr6 & (1 << 14)) {
1399             if (cpu_single_env->singlestep_enabled)
1400                 handle = 1;
1401         } else {
1402             for (n = 0; n < 4; n++)
1403                 if (arch_info->dr6 & (1 << n))
1404                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1405                     case 0x0:
1406                         handle = 1;
1407                         break;
1408                     case 0x1:
1409                         handle = 1;
1410                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1411                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1412                         hw_watchpoint.flags = BP_MEM_WRITE;
1413                         break;
1414                     case 0x3:
1415                         handle = 1;
1416                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1417                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1418                         hw_watchpoint.flags = BP_MEM_ACCESS;
1419                         break;
1420                     }
1421         }
1422     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1423         handle = 1;
1424
1425     if (!handle) {
1426         cpu_synchronize_state(cpu_single_env);
1427         assert(cpu_single_env->exception_injected == -1);
1428
1429         cpu_single_env->exception_injected = arch_info->exception;
1430         cpu_single_env->has_error_code = 0;
1431     }
1432
1433     return handle;
1434 }
1435
1436 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1437 {
1438     const uint8_t type_code[] = {
1439         [GDB_BREAKPOINT_HW] = 0x0,
1440         [GDB_WATCHPOINT_WRITE] = 0x1,
1441         [GDB_WATCHPOINT_ACCESS] = 0x3
1442     };
1443     const uint8_t len_code[] = {
1444         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1445     };
1446     int n;
1447
1448     if (kvm_sw_breakpoints_active(env))
1449         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1450
1451     if (nb_hw_breakpoint > 0) {
1452         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1453         dbg->arch.debugreg[7] = 0x0600;
1454         for (n = 0; n < nb_hw_breakpoint; n++) {
1455             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1456             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1457                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1458                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1459         }
1460     }
1461     /* Legal xcr0 for loading */
1462     env->xcr0 = 1;
1463 }
1464 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1465
1466 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1467 {
1468       return !(env->cr[0] & CR0_PE_MASK) ||
1469               ((env->segs[R_CS].selector  & 3) != 3);
1470 }
1471
1472 #include "qemu-kvm-x86.c"